JP3736046B2 - Semiconductor device substrate and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device substrate capable of high-density wiring using a build-up method and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, as represented by personal computers and the like, electronic devices are required to be smaller and thinner. For this reason, internal printed wiring boards are also required to be reduced in size and thickness. To achieve this, the width of the wiring pattern is narrow, the gap is small, the wiring layers are multi-layered, and the vias connecting the wiring layers are connected. There is a demand for so-called high-density wiring that is reduced in diameter.
In addition, when a thin insulating substrate or a thin copper foil is used to form a thin insulating layer and a thin wiring layer accompanying the reduction in thickness, the material cost increases.
A printed wiring board using a build-up method is known as a printed wiring board that solves these problems. In this method, a multilayer printed wiring board is formed by repeating a process of forming a wiring pattern on an insulating substrate, forming an insulating layer thereon, further forming a wiring pattern thereon, and further forming an insulating layer. Is to form.
[0003]
This printed wiring board is only used as a parent board, in which an IC package obtained by mounting a semiconductor chip on a lead frame and resin-sealing, and mounting electronic components such as resistance components and capacitor components. As a semiconductor device substrate mounted on a parent substrate as a semiconductor device in which a single or a plurality of semiconductor chips are mounted directly and in the form of a ball grid array (BGA), a pin grid array (PGA), etc. Are also used. These semiconductor devices are also called multi-chip modules (MCM) and single-chip modules (SCM).
An example of a printed wiring board using the build-up method will be described with reference to FIG. First, as shown in FIG. 4A, a first wiring layer 52 is formed on an insulating substrate (first insulating layer) 51 made of a rigid material such as a glass epoxy substrate. In this case, a method of forming a wiring pattern by etching using a double-sided copper-clad glass epoxy substrate may be simple. Subsequently, as shown in FIG. 4B, a photosensitive epoxy resin is applied, the second insulating layer 53 is formed, and the photosensitive epoxy resin in the portion 54 where the via hole is formed is removed by exposure and development. Thus, a fine via hole can be obtained by forming a via hole in the exposure and development steps.
[0004]
In forming the insulating layer, a method of applying a resin is preferable from the viewpoint that the insulating layer can be easily formed with a uniform thickness. Examples of the application method include screen printing, curtain coating, and spin coating. Has been applied. Other materials for the insulating layer include polyimide resin and acrylic resin. Note that via holes are formed in the insulating resin using a laser such as a carbon dioxide laser, YAG laser, or excimer laser instead of using a photosensitive resin as described above to form via holes in the exposure and development processes. You may adopt the method of doing. In this case, the insulating resin does not need to be a photosensitive material. Then, as shown in FIG. 4C, a second wiring layer is formed by forming a copper foil on the second insulating layer 53 by electroless plating and electrolytic plating, providing a via 55, and etching the formed copper foil. 56 is formed. At this time, the electroless plating is performed in order to impart conductivity to the insulating layer so that the electrolytic plating can be performed. Note that both the subtractive method and the additive method can be applied to the formation of the wiring pattern.
[0005]
Next, as shown in FIG. 4D, a third insulating layer 57 is formed on the entire surface, and the via hole portion is exposed and developed. The formation method may be the same as the method used in the step of FIG. Further, a through hole 58 for a through hole is formed using a drill. Then, plating is performed in the same process as in FIG. 4C to form the via 59 and the through hole 60 (FIG. 4E). In this case, it is preferable that the hole diameter of the through hole 60 is as small as possible so as not to hinder high density formation of the wiring pattern.
Subsequently, the third wiring layer 61 is formed by etching. At this time, the copper foil on the surface opposite to the side on which the surface wiring layer is formed is simultaneously etched to form a power supply layer pattern 62. And the soldering resist 63 which protects the pattern 62 of the 3rd wiring layer 61 and a power supply layer is provided, and a printed wiring board is completed (FIG.4 (f)).
[0006]
[Problems to be solved by the invention]
Here, FIG. 3 is an enlarged view of the vicinity of the via 55 in FIG. The insulating resin on the via land 41 of the first wiring layer is removed to form the second insulating layer 53, and a copper layer is formed by plating or the like. This copper layer is etched to form the second wiring layer 56.
However, if the via diameter is reduced due to the high density of the wiring, the peeling occurs at the portion 42 between the via land 41 and the second wiring layer 56 formed thereon, that is, at the broken line portion in FIG. There was a problem that was likely to occur.
[0007]
This is because the resin between the first wiring layer and the second wiring layer expands due to thermal history or the like, and a peeling force is applied between the upper surface of the first wiring layer and the lower surface of the via of the second wiring layer. This is probably because of this. When such a peeling force is applied, peeling occurs. This phenomenon is more likely to occur as the via diameter is reduced and the bottom area is reduced.
Further, when vias are formed by plating, it is preferable that the vias have a shape that gradually spreads upward, that is, a tapered shape, in order to facilitate uniform distribution of the plating solution during plating. By using the taper shape, the plating solution is difficult to flow around, and the plating solution is also spread over the portion 42 described above, and the connection reliability is improved. However, with such a tapered shape, as described above, when a peeling force is applied between the upper surface of the first wiring layer and the lower surface of the via of the second wiring layer, the first wiring layer Peeling tends to occur between the upper surface and the lower surface of the via of the second wiring layer.
[0008]
In the printed wiring board using the build-up method, the present invention solves the above problems, and even when the via is reduced in diameter and the connection area between the first wiring layer and the via is reduced, peeling occurs at the bottom of the via. Therefore, it is difficult to provide a printed wiring board having high connection reliability and a manufacturing method thereof.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, in the invention according to claim 1, a first wiring layer having a wiring pattern and a via land connected to the second wiring layer formed on the first insulating layer by a photoetching method. A second insulating layer formed by curing a liquid resin on the first wiring layer, a second wiring layer formed on the second insulating layer, and penetrating through the second insulating layer, the first wiring In a semiconductor device substrate having a via for connecting a layer and a second wiring layer and directly mounting a semiconductor chip, a via land connected to the second wiring layer of the first wiring layer is excluded. The wiring pattern is characterized in that unevenness having an average depth of 3 μm or more is formed only in the via land with the resist remaining .
[0010]
In such a means, when the recess is 3 μm or less, the recess is smoothed by subsequent processing, for example, soft etching or the like in the previous step when the second wiring layer is formed by plating or the like. Therefore, a sufficient effect can be obtained by setting the recesses to 3 μm or more, preferably 5 μm or more. In addition, a process for forming fine irregularities on the surface by an oxidation process or a reduction process after the oxidation process, which has been conventionally performed, is performed before the second wiring layer is formed as described above. As a result, the connection reliability of the via was not improved. Also, a method such as buffing has been proposed, but if a large concave portion of 3 μm or more is to be formed, there has been a problem that the wiring pattern is peeled off in the polishing step. Further, it is difficult to form a recess only in the land portion, and a recess is also formed in the wiring pattern portion, and the edge portion of the wiring pattern is lost, resulting in a problem that the electrical characteristics are deteriorated.
[0011]
The invention according to claim 2 technically limits the invention according to claim 1. That is, the invention according to claim 2 is the invention according to claim 1, wherein the via is formed by plating.
[0012]
The invention according to claim 3
A step of forming a first wiring layer having a wiring pattern and a via land connected to the second wiring layer by photoetching on the first insulating layer , and a liquid resin is cured on the first wiring layer Forming the second insulating layer from which the via portion has been removed, and forming the second wiring layer formed on the second insulating layer and the via connecting the second wiring layer and the first wiring layer. In the method for manufacturing a substrate for a semiconductor device, in which a semiconductor chip is directly mounted to form a semiconductor device, the wiring pattern excluding the via land connected to the second wiring layer before the via formation step A step of forming unevenness having a center line average roughness of 3 μm or more is performed only on a portion of the upper surface of the first wiring layer connected to the via with the resist remaining .
[0013]
The invention according to claim 4 technically limits the invention according to claim 3. That is, the invention according to claim 4 is the process according to claim 3, wherein the second wiring layer formed on the second insulating layer and the via connecting the second wiring layer and the first wiring layer are formed. Is performed by plating.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described based on examples.
[0015]
[Example 1]
A first embodiment of the present invention will be described with reference to FIG. FIG. 1 is an enlarged explanatory view of a via portion. First, a material in which a copper foil with a thickness of 18 μm is attached to an insulating substrate made of glass-epoxy (corresponding to the first insulating layer) is prepared, and a resist (trade name: manufactured by AZ-1300 Hoechst Japan) is applied. Then, temporary drying was performed.
A mask having a desired pattern was prepared, exposed, and developed to leave a portion of the resist where the copper foil was to remain. At this time, the size of the resist that was exposed and cured on the via land was 200 μmφ, but many black circles with a size of 15 μmφ should be formed in the land portion of the exposure mask. Thus, the resist of the portion was removed. Thus, by making a small hole in the resist, the etching solution enters appropriately when etching, and a recess is formed. By controlling the size of the hole by changing the pattern of the mask, a recess having a desired depth can be obtained. In addition, if the number of recesses is too large, adjacent recesses are bonded and flattened, and if it is too small, the purpose of forming the recesses cannot be achieved. It is desirable to provide it. Further, the shape is not round, and there is no particular limitation such as a rectangle or an ellipse.
[0016]
Then, etching was performed using ferric chloride to remove the copper foil exposed from the resist. The via land was formed with a diameter of 200 μm, and a recess was formed in the land by etching. In this way, a first wiring layer was formed. This state is shown in FIG. A via land 11 is formed on the first insulating layer 10, and a recess 12 is formed on the surface of the via land. FIG. 2 is a top view of this state. A large number of recesses 12 are formed on the via land 11.
At this time, when the depth of the recess 12 formed on the via land 11 was measured using a laser film thickness meter (model name: C6595 laser film thickness meter manufactured by Hamamatsu Photonics Co., Ltd.), the average depth was It was about 7.5 μm.
Next, by applying an insulating resin (trade name: Provicoat 5000 manufactured by Nippon Paint Co., Ltd.), exposing and developing, the second insulating layer 14 having a thickness of 20 μm having via holes 13 having a hole diameter of 120 μm. (FIG. 1B) was obtained.
[0017]
Electroless plating and electrolytic plating were performed on the insulating layer to form a copper layer having a thickness of 15 μm, and a via was formed. Thereafter, similarly, a second wiring layer 15 was formed by etching, and a via 16 was also formed (FIG. 1C).
Further, a second insulating layer was formed by the same process as described above, and a third wiring layer was further formed. Furthermore, a solder resist was formed to protect the third wiring layer.
A temperature cycle test was performed on the semiconductor device substrate thus obtained. That is, 100 cycles of a temperature cycle test in which 125 ° C. (holding for 30 minutes) → −65 ° C. (holding for 30 minutes) was set to one cycle was repeated 10 times. A continuity test between the measurement terminals at both ends was performed every 100 cycles. As a result, no poor conduction was observed. Also, no peeling was observed in the via cross-sectional observation.
[0018]
This continuity test will be described in more detail. A pattern for continuity test was formed at the time of manufacturing the semiconductor device substrate. The continuity test pattern is connected to a via that connects the third wiring layer and the second wiring layer in the third wiring layer. Connected repeatedly to the wiring pattern of the second wiring layer, to connect the third wiring layer and the second wiring layer again, to the other via, and to the wiring pattern of the third wiring layer. After passing through 1000 vias, it is connected to a measurement terminal, which is the other end of the continuity test, formed in the third wiring layer. That is, a wiring pattern in which the second wiring layer and the third wiring layer are alternately wired by 1000 vias is formed between the measurement terminals at both ends. Needless to say, conditions such as the land diameter and hole diameter of the via are formed as described above.
[0019]
Then, 10 semiconductor device substrates were prepared and the temperature cycle test was performed as described above. However, in both the continuity test every 100 cycles and the continuity test after 1000 cycles, continuity failure was observed. There wasn't.
In this embodiment, the method of forming a recess in the land by etching is not limited to this method. Methods such as laser processing and sandblasting are also possible. Further, instead of forming the recesses, a method may be used in which the projections are formed by performing uneven plating, and as a result, the depth of the recesses becomes 3 μm or more.
In addition, the method of forming a recess on the via land of the first wiring layer is described as an example. However, the recess may be formed in the second wiring layer or in the case of further multilayering after the third wiring layer. Needless to say, the wiring layers other than the uppermost layer may be formed.
[0020]
As a starting material, a material in which a copper foil having a thickness of 18 μm was adhered to an insulating substrate made of glass-epoxy was used. This was achieved by using a multilayer wiring board in which a wiring pattern was already formed. Also good.
Although the case where the buildup layer is formed on one side of the insulating substrate has been described, the present invention can be applied to a semiconductor device substrate in which the buildup layer is formed on both sides.
[0021]
[Example 2]
The size of the resist to be removed in the via land is 7 μmφ with respect to 15 μmφ of Example 1, and the formation site is formed only in the area of 120 μmφ which is the diameter of the via hole. Except for this, a semiconductor device substrate was prepared in the same manner as in Example 1.
At the same time as in Example 1, the depth of the recess formed on the via land was measured using a laser film thickness meter (model name: C6595 laser film thickness meter manufactured by Hamamatsu Photonics Co., Ltd.). The depth was about 3.1 μm.
Similarly to Example 1, ten semiconductor device substrates were prepared, a temperature cycle test was performed, and a continuity test was performed. In both the continuity test every 100 cycles and the continuity test after 1000 cycles, In any case, no conduction failure was observed.
No peeling was observed in the cross section of the via.
[0022]
[Example 3]
A substrate for a semiconductor device was produced in the same manner as in Example 2 except that the size of the resist to be removed was 20 μmφ with respect to 7 μmφ in Example 2 in the via land.
At the same time as Example 2, the depth of the recess formed on the via land was measured using a laser film thickness meter (model name: C6595 laser film thickness meter manufactured by Hamamatsu Photonics Co., Ltd.). The depth was about 10 μm.
Similarly to Example 1, ten semiconductor device substrates were prepared, a temperature cycle test was performed, and a continuity test was performed. In both the continuity test every 100 cycles and the continuity test after 1000 cycles, In any case, no conduction failure was observed.
No peeling was observed in the cross section of the via.
[0023]
[Comparative example]
A substrate for a semiconductor device was prepared in the same manner as in Example 1 except that no resist remained in the via land, and therefore no recess was formed on the via land.
Similarly to Example 1, ten semiconductor device substrates were prepared, a temperature cycle test was conducted, and a continuity test was performed. In the continuity test after 100 cycles, the two semiconductor device substrates were conducted. In the continuity test after 500 cycles, all 10 semiconductor device substrates were defective in continuity.
When the cross section of the via was observed after the end of the 500 cycles, a via in which the upper surface of the first wiring layer and the lower surface of the via of the second wiring layer were completely peeled was observed.
[0024]
【The invention's effect】
According to the present invention, since the wiring pattern of the first wiring layer has the resist remaining , unevenness having an average depth of 3 μm or more is formed only on the via land connected to the second wiring layer. In addition, even when the strength of the connection portion with the second wiring layer is increased, and therefore the via diameter is reduced, peeling at the bottom of the via hardly occurs, and a printed wiring board with high connection reliability and a method for manufacturing the same can be obtained. .
[0025]
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device substrate according to Embodiment 1 of the present invention. FIG. 2 is a top view of FIG. 1A. FIG. FIG. 4 is an explanatory diagram of a semiconductor device substrate according to the prior art.
DESCRIPTION OF SYMBOLS 10 1st insulating layer 11 Via land 12 Recess 13 Via hole 14 Second insulating layer 15 Second wiring layer 16 Via 41 Via land 51 First insulating layer 52 First wiring layer 53 Second insulating layer 55 Via 56 Second wiring layer 57 Third insulating layer 58 Through hole 59 Via 60 Through hole 61 Third wiring layer 63 Solder resist

Claims (4)

Formed by photoetching on the first insulating layer and having a wiring pattern and via lands connected to the second wiring layer, and curing the liquid resin on the first wiring layer A semiconductor chip having a second insulating layer, a second wiring layer formed on the second insulating layer, and a via that penetrates the second insulating layer and connects the first wiring layer and the second wiring layer In a semiconductor device substrate that is directly mounted as a semiconductor device,
Said first wiring layer, while the wiring pattern excluding the via land connected to the second wiring layer remaining resist, only the via land, the average depth to form a more uneven 3μm A substrate for a semiconductor device.   The semiconductor device substrate according to claim 1, wherein the via is formed by plating. A step of forming a first wiring layer having a wiring pattern and a via land connected to the second wiring layer by photoetching on the first insulating layer , and a liquid resin is cured on the first wiring layer Forming the second insulating layer from which the via portion has been removed, and forming the second wiring layer formed on the second insulating layer and the via connecting the second wiring layer and the first wiring layer. In a method for manufacturing a substrate for a semiconductor device, including a semiconductor device by directly mounting a semiconductor chip,
Prior to the via formation step, a center line is formed only on a portion of the upper surface of the first wiring layer connected to the via in a state where a resist remains in the wiring pattern excluding a via land connected to the second wiring layer. A method of manufacturing a substrate for a semiconductor device, comprising performing a step of forming irregularities having an average roughness of 3 μm or more.   4. The semiconductor device according to claim 3, wherein the step of forming a second wiring layer formed on the second insulating layer and a via for connecting the second wiring layer and the first wiring layer is performed by plating. A method for manufacturing a substrate.

Images