JP2000261141A - Multilayer wiring substrate and manufacture thereof and semiconductor device - Google Patents

Multilayer wiring substrate and manufacture thereof and semiconductor device

Info

Publication number
JP2000261141A
JP2000261141A JP6011599A JP6011599A JP2000261141A JP 2000261141 A JP2000261141 A JP 2000261141A JP 6011599 A JP6011599 A JP 6011599A JP 6011599 A JP6011599 A JP 6011599A JP 2000261141 A JP2000261141 A JP 2000261141A
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JP
Japan
Prior art keywords
insulating layer
wiring
step
formed
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6011599A
Other languages
Japanese (ja)
Other versions
JP3790063B2 (en
Inventor
Naohiro Mashino
直寛 真篠
Original Assignee
Shinko Electric Ind Co Ltd
新光電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Ind Co Ltd, 新光電気工業株式会社 filed Critical Shinko Electric Ind Co Ltd
Priority to JP6011599A priority Critical patent/JP3790063B2/en
Publication of JP2000261141A publication Critical patent/JP2000261141A/en
Application granted granted Critical
Publication of JP3790063B2 publication Critical patent/JP3790063B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To realize fine wiring at a level close to a full additive method without inconvenience such as side etching and electromigration in a multilayer wiring substrate, and to form a via hole having a high aspect ratio. The purpose is to contribute. SOLUTION: A core substrate 1 on which a first wiring 11 is formed.
0, insulating layers 12 and 13 are formed on this insulating layer.
A recess 16 corresponding to the shape of the wiring is formed, a via hole 17 reaching the first wiring 11 is formed in the recess, and an electrolytic panel plating film or a deposition film is formed so as to fill the via hole 17 and the recess 16. To form an interlayer connection 18
And the second wiring 19 are formed. Thereafter, the above processing is repeated until the required number of wiring layers is reached.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multilayer wiring board, a method for manufacturing the same, and a semiconductor device.
The present invention relates to a technique useful for realizing fine wiring in a build-up multilayer wiring board provided as a semiconductor package.

[0002]

2. Description of the Related Art In recent years, printed wiring boards have been required to be reduced in weight, and PGA (pin grid array) and BGA (ball grid array) have been reduced in size and increased in number of pins.
In order to mount such devices, miniaturization and high-density wiring are required. However, the conventional printed wiring board requires a large area for forming a via hole, which limits the degree of freedom of design and makes it difficult to miniaturize the wiring. Therefore, in recent years, practical use has progressed on printed wiring boards (build-up multilayer wiring boards) using the build-up method.
It is.

[0003] Many kinds of build-up multilayer wiring boards can be manufactured by combining the material of the interlayer insulating layer and the process of forming via holes. The formation of via holes in the layers and the formation of conductor patterns (wirings) including the insides of the via holes are sequentially and repeatedly accumulated.

In such a manufacturing process, when forming a wiring, a subtractive method, a semi-additive method or a full-additive method is mainly used. The subtractive method is a conventionally known method, and is generally a wiring (conductor film) formed on a flat insulating film.
This is a technique in which a photosensitive etching resist film or the like is formed thereon, and a wiring is formed by removing a conductor film other than the wiring portion by etching.

[0005] The semi-additive method generally refers to a method in which an electroless copper plating is performed on a perforated wiring substrate (insulating substrate), a wiring pattern is formed by a plating resist, and the exposed copper is exposed. In this method, wiring is formed by using a plating film as an electrode and growing electrolytic plating only on this portion. In addition, the full additive method is generally a method in which a wiring is formed by exposing and developing a plating resist to open only a wiring portion and growing electroless copper plating only in the opened portion.

[0006]

As described above, in the subtractive method, the conductive film other than the wiring portion is etched away using the resist film formed on the wiring (conductor film) as a mask. For example, when isotropic etching is performed, the portion of the conductor film closer to the edge portion of the resist film progresses faster than the portion farther away, so that portion is excessively etched, and the cross section of the conductor film is The shape becomes a trapezoidal shape (side etching)
There was a problem that occurs. This appears more conspicuously as the thickness of the conductor film increases, and is particularly likely to occur when the adhesion of the resist film to the conductor film is poor.

Further, if such a side-etched portion exists in the conductor film defining the wiring pattern, the portion is lost due to a shower pressure during a cleaning process performed in a later step ( That is, a part of the wiring layer is removed), which is a problem that a so-called “wiring jump” occurs. In addition, in the subtractive method, when the minimum line width of the wiring pattern is about 100 μm or less, the yield decreases, and mass production becomes difficult. Therefore, it has been difficult to realize fine wiring with the current technology.

On the other hand, in the case of the full additive method, for example, when a dry film is used as a plating resist,
Since the development accuracy of the dry film becomes the pattern accuracy as it is, fine wiring can be realized. However, in the full additive method, as in the semi-additive method, electroless plating is performed at the time of forming wiring (pattern), so that the type of plating remaining on the surface of the insulating film may adversely affect electromigration. there were.

The present invention has been made in view of the above-mentioned problems in the prior art, and realizes fine wiring at a level close to the full additive method without inconvenience such as side etching and electromigration, and thus has a high aspect ratio. It is an object of the present invention to provide a multilayer wiring board which can contribute to the formation of a via hole, a method of manufacturing the same, and a semiconductor device.

[0010]

According to one aspect of the present invention, a first surface is provided on a surface.
A first step of forming an insulating layer on the core substrate on which the wiring is formed, and forming a recess in the insulating layer in accordance with the shape of the second wiring to be formed on the insulating layer. A second step, a third step of forming a via hole reaching the first wiring in the recess, and forming a metal film on the insulating layer so as to fill the via hole and the recess. A fourth step of forming an interlayer connection portion and a second wiring by performing the same, and a fifth step of repeating the same steps as the first to fourth steps until the required number of wiring layers is reached. A method for manufacturing a multilayer wiring board is provided.

According to the method of manufacturing a multilayer wiring board according to the present invention, when forming a wiring (second wiring), the wiring is not formed on a flat insulating film as in the prior art, but is formed by insulating. Since the via holes and the concave portions formed in the layer are buried (that is, the wiring is buried in the insulating layer), the problems seen in the conventional pattern forming method can be solved. That is, since the etching treatment used in the subtractive method is not performed and the electroless plating used in the semi-additive method or the full additive method is not performed, disadvantages such as side etching and electromigration occur. Absent.

This makes it possible to realize fine wiring at a level close to the full additive method.
The diameter of the via hole included in the fine wiring can be reduced accordingly. That is, a via hole having a high aspect ratio can be formed. According to another aspect of the present invention, there is provided a multilayer wiring board manufactured by the above-described method for manufacturing a multilayer wiring board.

Further, according to another aspect of the present invention, a pin or ball is provided on a PGA type or BGA type wiring board formed using the multilayer wiring board manufactured by the above-described method for manufacturing a multilayer wiring board. A semiconductor device is provided in which electronic components, semiconductor devices, and the like are mounted on a surface opposite to the side on which the device is mounted.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A build-up multilayer wiring board according to an embodiment of the present invention will be described below with reference to FIGS. First, in the first step (see FIG. 1A), two layers are respectively formed on copper (Cu) wirings 11 patterned on both sides of a core base material (core substrate 10 in the present embodiment) serving as a base of the wiring board. The insulating layers 12 and 13 having the structure are formed. That is, the insulating layer 12 containing the nonwoven fabric is formed on the Cu wiring 11 on the core substrate 10 to a thickness of about 25 μm, and the thermosetting insulating layer 13 is further formed thereon to a thickness of about 30 μm.

In the example shown in the figure, for simplification, a cross-sectional structure of only one surface of the core substrate 10 is shown, and the same applies to FIG. 1B and thereafter. It is sufficient for the material of the upper thermosetting insulating layer 13 to have a property of being cured by a crosslinking reaction when heated in a later step and exhibiting a thermally stable state, for example, an epoxy resin,
A phenol resin or the like is used. On the other hand, it is desirable that the lower insulating layer 12 containing the nonwoven fabric is made of a material having a low dielectric constant, and that the film thickness can be controlled stably (film thickness control stability). For this purpose, for example, a liquid crystal polymer, an aramid fiber, or the like is used as the nonwoven fabric, and, for example, an epoxy resin, a polyimide resin, or the like is used as the insulating layer.

The core substrate 10 forms an insulating layer, and together with the Cu wiring 11 (conductor layer) formed thereon forms a core layer (first layer) of the build-up multilayer wiring substrate. As a material of the core substrate 10, for example, a glass-epoxy resin, a glass BT (bismaleimide-triazine) resin, or the like is used. The core layer is formed, for example, by applying a resist or etching to a copper-clad resin plate (such as a glass-epoxy resin composite plate) having a copper foil adhered to the surface thereof, thereby forming copper (C).
u) It can be manufactured by forming a wiring pattern.

In the next step (see FIG. 1B), a peelable resin film (a dry film in the present embodiment) used as a positive resist is formed on the thermosetting insulating layer 13 and a mask is further formed. (Not shown), the dry film is patterned so as to follow the shape of the second-layer wiring, and is exposed and developed with an alkaline solution. As a result, a dry film 14 patterned into the shape of the second-layer wiring is formed on the thermosetting insulating layer 13 as shown in the figure. Dry film 1 thus formed
The film thickness of No. 4 defines the film thickness of the second layer wiring, and is selected to be about 25 μm in this embodiment.

In the next step (see FIG. 1C), the Cu film on the core substrate 10 is not damaged so that the patterned dry film 14 is not broken (that is, the shape of the dry film 14 is accurately maintained). In order not to destroy the wiring 11, the insulating layer 13 is pressed while being pressed from both sides of the substrate by a press plate 15, while applying heat to melt the thermosetting insulating layer 13 while embedding the dry film 14 in the insulating layer 13. Let it cure.

In the next step (see FIG. 2 (a)), the dry film 14 (see FIG. 1 (c)) is peeled off using a weakly alkaline chemical solution (for example, an aqueous solution of sodium hydroxide (NaOH)) and removed. I do. As a result, a recess 16 is formed in the portion of the thermosetting insulating layer 13 where the dry film 14 was formed (the portion indicated by the broken line), as shown in the figure. The recess 16 has the same thickness as the thickness of the dry film 14, that is, the thickness of the second-layer wiring.

In the next step (see FIG. 2 (b)), the core substrate 1
The via holes 17 are formed in the thermosetting insulating layer 13 and the non-woven fabric-containing insulating layer 12 in the portion corresponding to the position of the Cu wiring 11 on
Is formed with a diameter of about 35 μm. YAG as laser
A laser, excimer laser or CO 2 laser is used.

Thereafter, a process (deburring, desmearing, etc.) for removing resin pieces, dirt and the like generated by the drilling process is performed. In the next step (see FIG. 2C), a copper (Cu) plating film or a vapor deposition film is formed on the entire substrate surface by electrolytic panel plating or vapor deposition so as to fill the via holes 17 and the concave portions 16. As a result, an interlayer connection portion (via hole conduction portion) 18 and a second-layer wiring portion 19 are formed. However, at this stage, since only the process of electrolytic panel plating or vapor deposition is performed, the unevenness portion remains on the substrate surface as shown in the figure.

In the next step (see FIG. 3A), the above-mentioned irregularities on the substrate surface are polished by mechanical polishing and flattened. In the figure, reference numeral 20 denotes fine abrasive grains used for polishing, and flattening is performed by processing the substrate surface by mechanically pushing and scratching the fine abrasive grains. In the next step (see FIG. 3B), 2
Leveling (removal of the surface portion of the metal film) is performed until the wiring portion 19 of the layer is exposed. In the figure, the part shown by the broken line is
It shows a portion removed by etching. At this stage, the final second-layer Cu wiring 21 is formed.

In the last step (see FIG. 3C), FIG.
In the same manner as in the step shown in FIG.
1 (conductor layer), a third insulating layer (nonwoven fabric-containing insulating layer 22 and thermosetting insulating layer 23) is formed in a two-layer structure, and further shown in FIGS. 1 (b) to 3 (b). The same steps as above are repeated. The above steps are repeated as needed until the required number of layers is reached, and the insulating layer including via holes and the conductor layer (C
u wiring) are alternately stacked.

As described above, according to the method of manufacturing a build-up multilayer wiring board according to the present embodiment, when forming wiring in each layer (except for the core layer), etching such as used in the subtractive method is performed. Since the wiring is buried in the insulating layer by electrolytic panel plating or vapor deposition without performing treatment or electroless plating as used in the semi-additive method or the full additive method, it can be seen in the conventional pattern forming method. Such problems (side etching, wiring jump, electromigration, etc.) can be solved.

As a result, it is possible to realize fine wiring at a level close to that of the full-additive method, and to reduce the diameter of via holes included in such fine wiring. This contributes to the formation of a high aspect ratio via hole. Each layer (excluding core layer)
Since the insulating layer has a two-layer structure (an insulating layer containing a nonwoven fabric and a thermosetting insulating layer), for example, in the case of the second layer, the insulating layer 12 containing a nonwoven fabric as a lower layer has a lower C side.
It can function as a buffer layer between the u wiring 11 and the upper thermosetting insulating layer 13. That is, when pressed by both sides of the substrate by the pressing process (see FIG. 1C), an extra force due to the pressing is prevented from spreading to the Cu wiring 11 so that the Cu wiring 11 is not broken (that is, the Cu wiring 11 is broken). The shape and the like of the wiring 11 can be accurately maintained).

FIG. 4 illustrates an application example of the build-up multilayer wiring board according to the above-described embodiment. In the illustrated example, the build-up multilayer wiring board according to the above-described embodiment is formed by using a PG in which a large number of pins serving as external connection terminals of a plastic type semiconductor package are erected on one surface of the board.
FIG. 4 schematically shows an example of a configuration in the case of realizing the configuration of an A-type wiring board, in which electronic components, semiconductor devices, and the like (shown in FIG. Shows the configuration of a semiconductor device on which the semiconductor chip 31) is mounted.

In the figure, hatched portions indicate wirings or interlayer connection portions (conductive portions of via holes) formed by a copper (Cu) plating film or a vapor deposition film. Reference numeral 24 denotes a third-layer Cu wiring (conductor layer), reference numeral 32 denotes a solder bump provided on the chip 31, reference numeral 33 denotes an underfill agent such as epoxy resin, and reference numeral 34 denotes a property of being cured by ultraviolet (UV) irradiation. Reference numeral 35 denotes a solder resist layer made of a resin, reference numeral 35 denotes solder, and reference numeral 36 denotes a through hole (not shown in FIGS. 1 to 3 for simplification of description) provided in the core substrate 10.

The joining of the pins 30 is performed, for example, as follows. First, the pin 3 of the solder resist layer 34
0 is the conductor layer to be joined (C defined as pad)
UV-irradiation is performed on the portion corresponding to the region of (u wiring), exposure and development are performed to form an opening, and then an appropriate amount of solder 35 is placed on the pad in this opening, and The head of a T-shaped pin 30 having a large-diameter head is arranged, and reflow is further performed to solidify the solder 35, and the pin 3
0 is fixed. On the other hand, the connection between the chip 31 and the wiring board
This is performed by pressing the solder bumps 32 against the pads (Cu wiring) of the wiring board by thermocompression bonding or the like.

In the configuration example shown in FIG. 4, the case where the build-up multilayer wiring board of the above-described embodiment is realized in the form of a PGA type wiring board has been described. It will be apparent to those skilled in the art that the same can be applied to a case where the present invention is implemented in a form. Further, in the above-described embodiment, the case where the insulating layer formed on the Cu wiring has a two-layer structure has been described, but the structure of the insulating layer is, of course, not limited to this. In short, if the insulating layer as a whole has a low dielectric constant, a stable film thickness control, and a thermosetting property as described above, a multilayer structure other than two layers or a single layer structure may be used. It is possible.

In the above-described embodiment, the core substrate 10 is used as the core base material serving as the base of the wiring substrate.
Instead, a film made of a polyimide resin or the like may be used. In this case, for the core layer, for example, a polyimide-based thermoplastic adhesive is applied to the surface of a polyimide resin film, and a copper (Cu) foil is hot-press-bonded thereon, and photo-etching or the like is performed to form a wiring pattern. Thereby, it can be produced.

[0031]

As described above, according to the present invention, by embedding wiring in a flat insulating layer by electrolytic panel plating or vapor deposition, it is possible to solve the problems seen in the conventional pattern forming method. In addition, it is possible to realize fine wiring at a level close to the full additive method, and to contribute to the formation of via holes having a high aspect ratio.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process (part 1) of a build-up multilayer wiring board according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing step (part 2) following the manufacturing step in FIG.

FIG. 3 is a cross-sectional view showing a manufacturing step (3) following the manufacturing step in FIG. 2;

FIG. 4 is a cross-sectional view showing one application example of a build-up multilayer wiring board according to one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Core board (core base material used as the base of a wiring board) 11,19,21,24 ... Cu wiring (conductor layer) 12,22 ... Insulating layer containing nonwoven fabric 13,23 ... Thermosetting insulating layer 14 ... Dry film DESCRIPTION OF SYMBOLS 16 ... Concave part 17 ... Via hole 18 ... Interlayer connection part (conductive part of via hole) 30 ... Pin 31 ... Semiconductor chip 32 ... Solder bump 33 ... Underfill agent 34 ... Solder resist layer 35 ... Solder

Claims (10)

    [Claims]
  1. A first step of forming an insulating layer on a core substrate having a first wiring formed on a surface thereof; and a second wiring to be formed on the insulating layer on the insulating layer. A second step of forming a concave portion corresponding to the shape of the above, a third step of forming a via hole reaching the first wiring in the concave portion, and filling the via hole and the concave portion. A fourth step of forming a metal film on the insulating layer to form an interlayer connection portion and a second wiring; and performing steps similar to the first to fourth steps until the required number of wiring layers is reached. A method of manufacturing a multilayer wiring board, comprising: repeating a fifth step.
  2. 2. The step of forming a metal film of a plating film or a vapor deposition film on the entire surface of the insulating layer so as to fill the via holes and the concave portions by electrolytic panel plating or vapor deposition. 2. The multi-layer wiring board according to claim 1, further comprising: flattening a surface of the metal film; and removing a surface portion of the metal film until the second wiring is exposed. Production method.
  3. 3. The method according to claim 1, wherein in the first step, the insulating layer is formed of a material having a low dielectric constant, a stable film thickness control, and a thermosetting property. Of manufacturing a multilayer wiring board.
  4. 4. The first step includes: forming a first insulating layer having a low dielectric constant and film thickness control stability on the core base material; and forming a first insulating layer on the first insulating layer. Forming a second insulating layer having thermosetting properties. 4. The method according to claim 3, further comprising the step of:
  5. 5. The method according to claim 5, wherein the second step includes forming a peelable resin film having a pattern patterned on the insulating layer so as to conform to a shape of the second wiring; 4. The multilayer wiring according to claim 3, further comprising a step of embedding the pattern forming side in the insulating layer until the upper end thereof coincides with the upper end of the insulating layer, and a step of peeling and removing the resin film. Substrate manufacturing method.
  6. 6. In the step of embedding the resin film in the insulating layer, the resin film is pressed from both sides by a press process,
    6. The resin film is buried in the insulating layer by applying heat to melt an upper end portion of the insulating layer.
    3. The method for manufacturing a multilayer wiring board according to item 1.
  7. 7. The method according to claim 5, wherein a dry film is used as the peelable resin film.
  8. 8. The method according to claim 1, wherein, in the third step, the via hole is formed by using a YAG laser, an excimer laser, or a CO 2 laser.
  9. 9. A multilayer wiring board manufactured by the method for manufacturing a multilayer wiring board according to claim 1. Description:
  10. 10. A semiconductor device, wherein a semiconductor element is mounted on a multilayer wiring board manufactured by the method for manufacturing a multilayer wiring board according to any one of claims 1 to 8.
JP6011599A 1999-03-08 1999-03-08 Multilayer wiring board, manufacturing method thereof, and semiconductor device Expired - Fee Related JP3790063B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6011599A JP3790063B2 (en) 1999-03-08 1999-03-08 Multilayer wiring board, manufacturing method thereof, and semiconductor device

Publications (2)

Publication Number Publication Date
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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002071818A1 (en) * 2001-02-23 2002-09-12 Sony Chemicals Corp. Method for producing flexible wiring board
WO2004006331A1 (en) * 2002-07-03 2004-01-15 Sony Corporation Multilayer wiring circuit module and method for fabricating the same
JP2006049804A (en) * 2004-07-07 2006-02-16 Shinko Electric Ind Co Ltd Manufacturing method of wiring board
JP2007520070A (en) * 2004-01-29 2007-07-19 アトーテヒ ドイッチュラント ゲゼルシャフト ミット ベシュレンクテル ハフツング Method of manufacturing a circuit carrier and use of the method
US7285867B2 (en) 2002-11-08 2007-10-23 Casio Computer Co., Ltd. Wiring structure on semiconductor substrate and method of fabricating the same
JP2008218494A (en) * 2007-02-28 2008-09-18 Casio Comput Co Ltd Semiconductor device and its manufacturing method
WO2010004841A1 (en) * 2008-07-07 2010-01-14 イビデン株式会社 Printed wiring board and method for manufacturing same
WO2010064467A1 (en) * 2008-12-05 2010-06-10 イビデン株式会社 Multilayer printed wiring board and method for manufacturing multilayer printed wiring board
JP2010129997A (en) * 2008-11-26 2010-06-10 Samsung Electro-Mechanics Co Ltd Printed-circuit board with embedded pattern, and its manufacturing method
JP2011035182A (en) * 2009-08-03 2011-02-17 Shinko Electric Ind Co Ltd Manufacturing method of wiring substrate
US20140123487A1 (en) * 2012-11-08 2014-05-08 Boardtek Electronics Corporation Printed circuit board manufacturing method
US20140124124A1 (en) * 2012-11-08 2014-05-08 Boardtek Electronics Corporation Printed circuit board manufacturing method

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002071818A1 (en) * 2001-02-23 2002-09-12 Sony Chemicals Corp. Method for producing flexible wiring board
US6912779B2 (en) 2001-02-23 2005-07-05 Sony Chemicals Corp. Method of manufacturing flexible wiring board
WO2004006331A1 (en) * 2002-07-03 2004-01-15 Sony Corporation Multilayer wiring circuit module and method for fabricating the same
KR101053419B1 (en) * 2002-07-03 2011-08-01 소니 주식회사 Multilayer wiring circuit module and manufacturing method thereof
US7235477B2 (en) 2002-07-03 2007-06-26 Sony Corporation Multi-layer interconnection circuit module and manufacturing method thereof
US7473992B2 (en) 2002-07-03 2009-01-06 Sony Corporation Multi-layer interconnection circuit module and manufacturing method thereof
US7285867B2 (en) 2002-11-08 2007-10-23 Casio Computer Co., Ltd. Wiring structure on semiconductor substrate and method of fabricating the same
JP2007520070A (en) * 2004-01-29 2007-07-19 アトーテヒ ドイッチュラント ゲゼルシャフト ミット ベシュレンクテル ハフツング Method of manufacturing a circuit carrier and use of the method
KR101156256B1 (en) * 2004-01-29 2012-06-13 아토테크더치랜드게엠베하 Method of manufacturing a circuit carrier and the use of the method
JP2013065874A (en) * 2004-01-29 2013-04-11 Atotech Deutsche Gmbh Method of manufacturing circuit carrier and use of the same
US8927899B2 (en) 2004-01-29 2015-01-06 Atotech Deutschland Gmbh Method of manufacturing a circuit carrier and the use of the method
JP2006049804A (en) * 2004-07-07 2006-02-16 Shinko Electric Ind Co Ltd Manufacturing method of wiring board
JP2008218494A (en) * 2007-02-28 2008-09-18 Casio Comput Co Ltd Semiconductor device and its manufacturing method
JP4506767B2 (en) * 2007-02-28 2010-07-21 カシオ計算機株式会社 Manufacturing method of semiconductor device
WO2010004841A1 (en) * 2008-07-07 2010-01-14 イビデン株式会社 Printed wiring board and method for manufacturing same
CN102084731B (en) * 2008-07-07 2013-04-03 揖斐电株式会社 Printed wiring board and method for manufacturing same
JP4944246B2 (en) * 2008-07-07 2012-05-30 イビデン株式会社 Printed wiring board and manufacturing method thereof
KR101022903B1 (en) * 2008-11-26 2011-03-16 삼성전기주식회사 A printed circuit board comprising a buried-pattern and a method of manufacturing the same
US8191249B2 (en) 2008-11-26 2012-06-05 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing a printed circuit board
JP2010129997A (en) * 2008-11-26 2010-06-10 Samsung Electro-Mechanics Co Ltd Printed-circuit board with embedded pattern, and its manufacturing method
JPWO2010064467A1 (en) * 2008-12-05 2012-05-10 イビデン株式会社 Multilayer printed wiring board and method for producing multilayer printed wiring board
US8156647B2 (en) 2008-12-05 2012-04-17 Ibiden Co., Ltd. Method for manufacturing a multilayer printed wiring board
WO2010064467A1 (en) * 2008-12-05 2010-06-10 イビデン株式会社 Multilayer printed wiring board and method for manufacturing multilayer printed wiring board
US8853552B2 (en) 2008-12-05 2014-10-07 Ibiden Co., Ltd. Multilayer printed wiring board and method for manufacturing multilayer printed wiring board
JP2011035182A (en) * 2009-08-03 2011-02-17 Shinko Electric Ind Co Ltd Manufacturing method of wiring substrate
US20140123487A1 (en) * 2012-11-08 2014-05-08 Boardtek Electronics Corporation Printed circuit board manufacturing method
US20140124124A1 (en) * 2012-11-08 2014-05-08 Boardtek Electronics Corporation Printed circuit board manufacturing method

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