JP3718392B2 - Oscillator circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an oscillation circuit used in, for example, a television receiver.
[0002]
[Prior art]
FIG. 4 shows a configuration of a conventional oscillation circuit. The control current I1 (101) from the power supply VDD is connected to the terminal 0 of the switch SW1 (103) and the terminal 0 of the switch SW2 (105), and the terminal 1 of the switch SW1 (103) and the terminal 1 of the switch SW2 (105) are grounded. It is connected to the potential GND.
[0003]
The switch SW1 (103) is controlled by the output of the first NAND 111. When the output of the first NAND 111 is high, the switch SW1 (103) falls to the terminal 1 side, and when the output of the first NAND 111 is low, the switch SW1 (103) falls to the terminal 0 side.
[0004]
The switch SW2 (105) is controlled by the output of the second NAND 113. When the output of the second NAND 113 is high, the switch SW (105) falls to the terminal 1 side, and when the output of the second NAND 113 is low, the switch SW2 (105) falls to the terminal 0.
[0005]
The selector of the switch SW1 (103) is connected to the negative input terminal of the first comparison circuit 107, and the capacitor C1 is connected to the GND. The selector of the switch SW2 (105) is connected to the negative input terminal of the second comparison circuit 109, and the capacitor C2 is connected to the GND.
[0006]
The + input terminals of the first comparison circuit 107 and the second comparison circuit 109 are connected to the reference voltage source V1, and the other end of the reference voltage source V1 is connected to GND.
[0007]
The output of the first comparison circuit 107 is supplied to the input terminal of the first NAND 111. The output of the second comparison circuit 109 is supplied to the input terminal of the second NAND 113.
[0008]
The output of the first NAND 111 is supplied to the other input terminal of the second NAND 113. The output of the second NAND 113 is supplied to the other input terminal of the first NAND 111.
[0009]
With the above configuration, the first and second NANDs 111 and 113 operate as RS flip-flops.
[0010]
Next, the circuit operation will be described.
[0011]
When the power supply VDD is on, since the capacitors C1 and C2 have no electric charge, the outputs of the first and second comparison circuits 107 and 109 are both high. Therefore, one of the outputs of the first NAND 111 and the second NAND 113 is high and the other is low.
[0012]
When the output of the first NAND 111 is high and the output of the second NAND 113 is low, the switch SW1 (103) falls to the terminal 1 side, and the switch SW2 (105) falls to the terminal 0 side.
[0013]
Then, the capacitor C2 is charged, and the voltage of the capacitor C2 at this time is set to VC2. When time elapses, VC2 rises, and when VC2> V1, the output of the second comparison circuit 109 switches to low.
[0014]
At this time, the output of the second NAND 113 changes to high, at the same time, the output of the first NAND 111 changes to low, the switch SW1 (103) falls to the terminal 0 side, and the switch SW2 (105) falls to the terminal 1 side.
[0015]
Then, the capacitor C1 is charged, and the voltage of the capacitor C1 at this time is set to VC1. The electric charge of the capacitor C2 is discharged to the GND potential, and VC2 <V1, so that the output of the second comparison circuit 109 is switched to high.
[0016]
When time elapses, VC1 rises, and when VC1> V1, the output of the first comparison circuit 107 switches to low. At this time, the output of the first NAND 111 changes to high, and at the same time, the output of the second NAND 113 changes to low.
[0017]
By repeating the above operation, an oscillation voltage signal is obtained at the output OUT.
[0018]
[Problems to be solved by the invention]
As described above, the conventional oscillation circuit has a problem that the linearity of the control characteristics is poor as shown in FIG. Further, as shown in FIG. 5, the waveforms during discharge of the capacitors C1 and C2 were not smooth. Furthermore, when the electric charges of the capacitors C1 and C2 are discharged, the through current flows directly to the GND, so that a noise that shakes the GND is generated, and the first NAND 111 and the second NAND 113 are affected by the noise. There was.
[0019]
Therefore, an object of the present invention is to provide an oscillation circuit that improves the linearity of control characteristics.
[0020]
It is another object of the present invention to provide an oscillation circuit that smoothes a waveform when a capacitor is discharged.
[0021]
Another object of the present invention is to provide an oscillation circuit that prevents generation of noise that shakes GND.
[0022]
[Means for Solving the Problems]
In an oscillation circuit that generates an oscillation output signal by switching charge / discharge of a first capacitor and a second capacitor,
A current source unit that is connected to a power source and maintains an output current so as to obtain the oscillation output signal having a desired oscillation frequency;
A first switch means connected to the first capacitor, wherein, based on the oscillation output signal, the output current of the current source unit is used as the charging current of the first capacitor during charging, and is discharged to the ground potential during discharging. When,
A second switch is connected to the second capacitor, and the oscillation output signal causes the output current of the current source unit to be the charging current of the second capacitor during charging and to the ground potential during discharging. Means,
A voltage source for supplying a reference potential;
First comparing means for comparing the potential of the first capacitor with the reference potential of the voltage source unit;
Second comparing means for comparing the potential of the second capacitor and the reference potential of the voltage source unit;
An RS flip-flop unit that receives the output signal of the first comparison unit and the output signal of the second comparison unit and generates the oscillation output signal;
The output current of the current source unit is used for the first comparison unit and the second comparison unit.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a circuit configuration diagram of an oscillation circuit of the present invention. Capacitor C1 and capacitor C2 are charge / discharge capacitors. The capacitor C1 corresponds to the capacitor C1 in FIG. 4, and the capacitor C2 corresponds to the capacitor C2 in FIG. The capacitor C3 is a phase compensation capacitor.
[0024]
The P-channel MOS transistor M6 and the N-channel MOS transistor M7 constitute the first inverter 11, and the charge / discharge of the capacitor C1 connected to the common drain of both the MOS transistors M6 and M7 is switched, and the switch SW1 in FIG. Corresponds to (103).
[0025]
The P-channel MOS transistor M11 and the N-channel MOS transistor M12 constitute the second inverter 13, and the charging / discharging of the capacitor C2 connected to the common drain of both the MOS transistors M11 and M12 is switched, and the switch SW2 in FIG. This corresponds to (105).
[0026]
The P-channel MOS transistors M13 and M18 and the N-channel MOS transistors M14 and M17 constitute the first comparison circuit 15, which corresponds to the first comparison circuit 107 in FIG. The gate of the MOS transistor M18 is connected to the reference voltage source V1, and the gate of the MOS transistor M13 is connected to the capacitor C1.
[0027]
The P-channel MOS transistors M19 and M24 and the N-channel MOS transistors M20 and M23 constitute the second comparison circuit 17, which corresponds to the second comparison circuit 109 in FIG. The gate of the MOS transistor M19 is connected to the reference voltage source V1, and the gate of the MOS transistor M24 is connected to the capacitor C2.
[0028]
The P-channel MOS transistors M25 and M26 and the N-channel MOS transistors M27 and M28 constitute the first NAND 19, which corresponds to the first NAND 111 in FIG. The common drain of the MOS transistors M13 and M14 is connected to the common gate of the MOS transistors M26 and M28. The common drains of the MOS transistors M25, M26, and M27 are connected to the common gates of the MOS transistors M6 and M7 in the first inverter 11 and the common gates of the MOS transistors M29 and M31 in the second NAND 21 described later.
[0029]
The P-channel MOS transistors M29 and M30 and the N-channel MOS transistors M31 and M32 constitute the second NAND 21, which corresponds to the second NAND 113 in FIG. The common drain of the MOS transistors M23 and M24 is connected to the common gate of the MOS transistors M30 and M32. The common drains of the MOS transistors M29, M30, and M31 are connected to the common gates of the MOS transistors M11 and M12 in the second inverter 13 and the common gates of the MOS transistors M25 and M27 in the first NAND 19.
[0030]
With the above configuration, the first and second NANDs 19 and 21 operate as RS flip-flops.
[0031]
P-channel MOS transistors M1, M2, M3, M4, M9, M10, M15, M16, M21, and M22 constitute a current mirror.
[0032]
N-channel MOS transistors M5 and M8 form a current mirror. The sources of the MOS transistors M7 and M12 are connected to the drain of the MOS transistor M8.
[0033]
The output oscillation voltage signal is extracted from the common drain of the MOS transistors M25, M26, and M27.
[0034]
Next, the operation will be described. The basic operation of the oscillation circuit is the same as the conventional one. Conventionally, the control current I1 is used only for charging the capacitors C1 and C2. However, in the present invention, the control current Iin is used as the charge / discharge of the capacitors C1 and C2 and the currents of the first and second comparison circuits 15 and 17. A MOS transistor M8 is inserted in the discharge path of the first and second inverters 11 and 13.
[0035]
Since the capacitors C1 and C2 have no electric charge when the power supply VDD is on, the output of the first comparison circuit 15 is high (M13 is on, M14 is off, M17 is off, and M18 is off). The output of 17 is high (M19 is off, M20 is off, M23 is off, and M24 is on).
[0036]
Therefore, one of the outputs of the first NAND 19 and the second NAND 21 is high and the other is low.
[0037]
When the output of the first NAND 19 is high (for example, M25 is on, M26 is off, M27 is off, M28 is on), and the output of the second NAND 21 is low (M29 is off, M30 is off, M31 is On, M32 is on), the MOS transistor M6 of the first inverter 11 is off, the MOS transistor M7 is on, the MOS transistor M11 of the second inverter 13 is on, and the MOS transistor M12 is off.
[0038]
Then, the capacitor C2 is charged, and the charging voltage of the capacitor C2 at this time is set to VC2. When time elapses, VC2 rises and when VC2> V1, the output of the second comparison circuit 17 switches to low (M19 is on, M20 is on, M23 is on, and M24 is off).
[0039]
At this time, the output of the second NAND 21 changes to high (M29 is off, M30 is on, M31 is on, and M32 is off). At the same time, the output of the first NAND 19 changes to low (M25 is off, M26 is off, M27 is on, M28 is on), the MOS transistor M6 of the first inverter 11 is on, the MOS transistor M7 is off, the MOS transistor M11 of the second inverter 13 is off, and the MOS transistor M12 is on.
[0040]
Then, the capacitor C1 is charged, and the charging voltage at this time is set to VC1. On the other hand, the charge of the capacitor C2 is discharged to become the drain potential of the MOS transistor M8, and VC2 <V1, so that the output of the second comparison circuit 17 is switched to high (M19 is off, M20 is off, M23 is off, M24 Is on).
[0041]
When time elapses, VC1 rises, and when VC1> V1, the output of the first comparison circuit 15 switches to low (M13 is off, M14 is on, M17 is on, and M18 is on).
[0042]
At this time, the output of the first NAND 19 changes to high (M25 is off, M26 is on, M27 is on, and M28 is off). At the same time, the output of the second NAND 21 changes to low (M29 is off, M30 is off, M31 is on and M32 is on).
[0043]
By repeating the above operation, an oscillation voltage signal is obtained as an output.
[0044]
Next, when the power supply VDD is on, the capacitors C1 and C2 have no charge, and the output of the first comparison circuit 15 is high (M13 is on, M14 is off, M17 is off, M18 is off), and the second comparison circuit 17 Output is high (M19 is off, M20 is off, M23 is off, M24 is on), the output of the second NAND 21 is high (for example, M29 is on, M30 is off, M31 is off, and M32 is off) ON), when the output of the first NAND 19 is low (M25 is OFF, M26 is OFF, M27 is ON, M28 is ON), the MOS transistor M11 of the second inverter 13 is OFF and the MOS transistor M12 is ON In the first inverter 11, the MOS transistor M6 is turned on and the MOS transistor M7 is turned off.
[0045]
Then, the capacitor C1 is charged, and the charging voltage of the capacitor C1 at this time is set to VC1. When time elapses, VC1 rises and when VC1> V1, the output of the first comparison circuit 15 switches to low (M13 is off, M14 is on, M17 is on, and M18 is on).
[0046]
At this time, the output of the first NAND 19 changes to high (M25 is off, M26 is on, M27 is on, and M28 is off). At the same time, the output of the second NAND 21 changes to low (M29 is off, M30 is off, M31 is on, M32 is on), the MOS transistor M11 of the second inverter 13 is on, the MOS transistor M12 is off, the MOS transistor M6 of the first inverter 11 is off, and the MOS transistor M7 is on.
[0047]
Then, the capacitor C2 is charged, and the voltage of the capacitor C2 at this time is set to VC2. On the other hand, the charge of the capacitor C1 is discharged to become the drain potential of the MOS transistor M8, and VC1 <V1, so that the output of the first comparison circuit 15 is switched to high (M13 is on, M14 is off, M17 is off, M18 Is off).
[0048]
When time elapses, VC2 rises, and when VC2> V1, the output of the second comparison circuit 17 switches to low (M19 is on, M20 is on, M23 is on, and M24 is off).
[0049]
At this time, the output of the second NAND 21 changes to high (M29 is off, M30 is on, M31 is on, and M32 is off). At the same time, the output of the first NAND 19 changes to low (M25 is off, M26 is off, M27 is on and M28 is on).
[0050]
By repeating the above operation, an oscillation voltage signal is obtained as an output.
[0051]
As shown in FIG. 1, the first comparison circuit 15 is supplied with current from current sources (M15, M16). The second comparison circuit 17 is supplied with current from current sources (M21, M22).
[0052]
As shown in FIG. 2, the oscillation circuit of the present invention has greatly improved linearity of control characteristics compared to the conventional oscillation circuit.
[0053]
Also, by pulling out the discharge currents of the capacitors C1 and C2 with the current of the current mirror composed of the MOS transistors M5 and M8, the MOS transistor M8 has an on-resistance and has a time constant. Therefore, the capacitors C1 and C2 The waveform at the time of discharging becomes smooth, and the GND is less likely to be shaken. As shown in FIG. 3, the waveforms during discharge of the capacitors C1 and C2 are smooth.
[0054]
【The invention's effect】
As described above, the oscillation circuit of the present invention has improved linearity of control characteristics. The waveform when the capacitor is discharged is smooth. Furthermore, it is possible to prevent the occurrence of noise that shakes GND.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram of an oscillation circuit of the present invention.
FIG. 2 is a control characteristic diagram of the oscillation circuit of the present invention and a conventional oscillation circuit.
FIG. 3 is a voltage waveform diagram at the terminals of capacitors C1 and C2 in FIG. 1;
FIG. 4 is a block diagram showing a configuration of a conventional oscillation circuit.
5 is a voltage waveform diagram at the ends of capacitors C1 and C2 in FIG. 4;
[Explanation of symbols]
11... First inverter, 13... Second inverter, 15... First comparison circuit, 17... Second comparison circuit, 19.

Claims (2)

In an oscillation circuit that generates an oscillation output signal by switching charge / discharge of a first capacitor and a second capacitor,
A current source unit that is connected to a power source and maintains an output current so as to obtain the oscillation output signal having a desired oscillation frequency;
A first switch means connected to the first capacitor, wherein, based on the oscillation output signal, the output current of the current source unit is used as the charging current of the first capacitor during charging, and is discharged to the ground potential during discharging. When,
A second switch is connected to the second capacitor, and the oscillation output signal causes the output current of the current source unit to be the charging current of the second capacitor during charging and to the ground potential during discharging. Means,
A voltage source for supplying a reference potential;
First comparing means for comparing the potential of the first capacitor with the reference potential of the voltage source unit;
Second comparing means for comparing the potential of the second capacitor and the reference potential of the voltage source unit;
An RS flip-flop unit that receives the output signal of the first comparison unit and the output signal of the second comparison unit and generates the oscillation output signal;
An oscillation circuit characterized in that the output current of the current source section is used for the first comparison means and the second comparison means. 2. The oscillation circuit according to claim 1, wherein a resistance component is inserted between the first switch means and the second switch means and the ground potential.

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