JP3715948B2 - Image display device - Google Patents

Description

として表される電流である。
【０１２０】
また、走査配線の両端の電位が同図（ａ）の例ではＶｓであるのに対し、同図（ｂ）ではＧＮＤ電位としているのは、縮退モデルでは、変調配線から選択した走査配線に流れ込む電流を上記電流源によりモデリングしたことにより、走査配線上の各部の電圧降下量は、その給電部を基準電位として各部の電圧（電位差）を算出することにより計算できるためである。
【０１２１】
また、表面伝導型放出素子を省略しているのは、選択された走査配線から見た場合に、列配線から同等の電流が流れ込めば、表面伝導型放出素子の有無によらず、発生する電圧降下自体は変わらないためである。従って、ここでは、各ブロックの電流源から流れ込む電流値を各ブロック内の素子電流の総和の電流値（式１）に設定することで表面伝導型放出素子を省略した。
【０１２２】
また、各ブロックの走査配線の配線抵抗は一区間の走査配線の配線抵抗ｒのｎ倍とした（ここで一区間とは走査配線の、ある列配線との交差部とその隣の列配線との交差部の間のことを指している。また本例では、一区間の走査配線の配線抵抗は均一であるものとした。）。
【０１２３】
このような縮退モデルにおいて、走査配線上の各ノードにおいて発生する電圧降下量ＤＶ０〜ＤＶ４は以下のような積和形式の式により、簡単に計算することができる。
【数２】

すなわち、
【数３】

ただし、ａｉｊは縮退モデルにおいてｊ番目のブロックだけに単位電流を注入したときに、ｉ番目のノードに発生する電圧である（以下、これをａｉｊの定義とする。）。
【０１２４】
上記のａｉｊはキルヒホフの法則により以下のように簡単に導出できる。
【０１２５】
即ち、図６（ｂ）において、ブロックｉの電流源からみた走査配線の左側の供給端子までの配線抵抗をｒｌｉ（ｉ＝０，１，２，３，４），右側の供給端子までの配線抵抗をｒｒｉ（ｉ＝０，１，２，３，４），ブロック０と左の供給端子との間の配線抵抗及びブロック４と右の供給端子との間の配線抵抗をいずれもｒｔと定義すれば、
【数４】

さらに、
【数５】

とおくと、ａｉｊは、
【数６】

のように簡単に導出できる。ただし式３において、Ａ／／Ｂは、抵抗Ａと抵抗Ｂの並列の抵抗値を表す記号であって、Ａ／／Ｂ＝Ａ×Ｂ／（Ａ＋Ｂ）である。
【０１２６】
式２はブロック数が４でない場合においても、ａｉｊの定義を顧みれば、キルヒホフの法則によって簡単に算出することができる。また本例のように走査配線の両側に給電端子を備えず片側のみに備える場合においても、ａｉｊの定義に従って計算することにより簡単に算出できる。
【０１２７】
なお、式３によって定義されるパラメータａｉｊは計算を行うたびに計算し直す必要はなく、一度計算してテーブルとして記憶しておけばよい。
【０１２８】
さらに、式１で定めた各ブロックの総和電流ＩＦ０〜ＩＦ３に対し、式４のような近似を行った。
【０１２９】
【数７】

ただし、上式においてＣｏｕｎｔｉは選択された走査線上のｉ番目のピクセルが点灯状態である場合には１をとり、消灯状態である場合には０をとる変数である。
【０１３０】
ＩＦＳは表面伝導型放出素子１素子の両端に電圧Ｖ_SELを印加したときに流れる素子電流ＩＦに対し、０〜１の間の値をとる係数αをかけた量である。
【０１３１】
すなわち、
【数８】

と定義した。
【０１３２】
式４は選択された走査配線に対し各ブロックの列配線から該ブロック内の点灯数に比例した素子電流が流れ込むものとしている。この際１素子の素子電流ＩＦに係数αをかけたものを１素子の素子電流ＩＦＳとしたのは、以下の理由のよる。
【０１３３】
本来、電圧降下量を計算するためには、電圧降下による走査配線の電圧上昇とそれによる素子電流の減少量とを繰り返し計算することが必要であるが、この収束計算をハードウエアで計算するのは現実的でない。そこで、本発明においては、ＩＦの収束値として近似的にαＩＦを用いる。具体的には、電圧降下量が最大となるとき（全白のとき）のＩＦの低下率（＝α１）と、電圧降下量が（最小＝０）となるときのＩＦの低下率（＝α２）を予め見積もっておいて、α１とα２の平均値または０．８×α１として求められる。
【０１３４】
図６（ｃ）は、ある点灯状態において、縮退モデルにより各ノードの電圧降下量ＤＶ０〜ＤＶ４を計算した結果の一例である。
【０１３５】
電圧降下は非常に滑らかなカーブとなるため、ノードとノードの間の電圧降下は近似的には図の点線に示したような値をとると想定される。
【０１３６】
このように本縮退モデルを用いれば、任意の画像データに対し所望の時点でのノードごとの電圧降下を計算することが可能である。
【０１３７】
以上、ある点灯状態における電圧降下量を、縮退モデルを用いて簡単に計算した。
【０１３８】
選択された走査配線上に発生する電圧降下は一水平走査期間内で時間的に変化するが、これについては前述したように一水平走査期間中のいくつかの時刻（基準時刻）に対して、その時の点灯状態を求め、その点灯状態に対し縮退モデルを用いて電圧降下を計算することにより予測した。
【０１３９】
なお、一水平走査期間のある時点での各ブロック内の点灯数は各ブロックの画像データを参照すれば簡単に求めることができる。
【０１４０】
いま、１つの例としてパルス幅変調回路への入力データのビット数が８ビットであるものとし、パルス幅変調回路は、入力データの大きさに対してリニアなパルス幅を出力するものとする。
【０１４１】
すなわち入力データが０のときは、出力は”Ｌ”となり、入力データが２５５のとき一水平走査期間の間は”Ｈ”を出力し、入力データが１２８のときには一水平走査期間のうち初めの半分の期間は”Ｈ”を出力し、後の半分の期間は”Ｌ”を出力するものとする。
【０１４２】
このような場合、パルス幅変調信号の立ち上がった時刻（開始時刻）の点灯数は、パルス幅変調回路への入力データが０よりも大きいものの数をカウントすれば簡単に検出できる。
【０１４３】
同様に一水平走査期間の中央の時刻の点灯数は、パルス幅変調回路への入力データが１２８よりも大きいものの数をカウントすれば簡単に検出できる。
【０１４４】
このように画像データをある閾値に対してコンパレートし、コンパレータの出力が真である数をカウントすれば、任意の時間における点灯数が簡単に計算することができる。
【０１４５】
ここで以降の説明を簡単化するため、タイムスロットという時間量を定義する。
【０１４６】
すなわち、タイムスロットとは一水平走査期間のなかのパルス幅変調信号の立ち上がりからの時間を表しており、タイムスロット＝０とはパルス幅変調信号の開始時刻（この場合は立ち上がり）直後の時刻を表すものと定義する。
【０１４７】
タイムスロット＝６４とは、パルス幅変調信号の開始時刻から、６４階調分の時間が経過した時刻を表すものと定義する。
【０１４８】
同様にタイムスロット＝１２８とは、パルス幅変調信号の開始時刻から、１２８階調分の時間が経過した時刻を表すものと定義する。
【０１４９】
なお、本例ではパルス幅変調は立ち上がり時刻を基準として、そこからのパルス幅を変調した例を示したが、同様に、パルスの立ち下がり時刻を基準として、パルス幅を変調する場合でも、時間軸の進む方向とタイムスロットの進む方向が逆となるが、同様に適用することができることはいうまでもない。
【０１５０】
（電圧降下量から補正データの計算）
上述したように、縮退モデルを用いて繰り返し計算を行うことで一水平走査期間中の電圧降下の時間変化を近似的かつ離散的に計算することができた。
【０１５１】
図７は、ある画像データに対して、電圧降下を繰り返し計算し、走査配線での電圧降下の時間変化を計算した例である
（ここに示されている電圧降下及びその時間変化は、ある画像データに対する一例であって、別の画像データに対する電圧降下は、また別の変化をすることは当然である。）。
【０１５２】
同図ではタイムスロット＝０，６４，１２８，１９２の４つの時点に対して、各々縮退モデルを適用して計算を行うことに、それぞれの時刻の電圧降下を離散的に計算した。
【０１５３】
図７では各ノードにおける電圧降下量を点線で結んでいるが、点線は図を見やすくするために記載したものであって、本縮退モデルにより計算された電圧降下は□、○、△で示した各ノードの位置において離散的に計算した。
【０１５４】
本発明者らは、電圧降下の大きさとその時間変化を計算可能となった次の段階として、電圧降下量から画像データを補正する補正データを算出する方法について検討を行った。
【０１５５】
図８は、選択した走査配線上に図７に示した電圧降下が発生した際に、点灯状態にある表面伝導型放出素子から放出される放出電流を見積もったグラフである。
【０１５６】
縦軸は電圧降下がないときに放出される放出電流の大きさを１００％として、各時間、各位置の放出電流の量を百分率で表しており、横軸は水平位置を表している。
【０１５７】
図８に示すように、ノード２の水平位置（基準点）において、
タイムスロット＝０の時の放出電流をＩｅ０、
タイムスロット＝６４の時の放出電流をＩｅ１、
タイムスロット＝１２８の時の放出電流をＩｅ２、
タイムスロットが１９２の時の放出電流をＩｅ３
とする。
【０１５８】
同図は図７の電圧降下量と図３の“駆動電圧対放出電流”のグラフから計算した。具体的には電圧Ｖ_SELから電圧降下量を引いた電圧が印加された際の放出電流の値を単に機械的にプロットしたものである。
【０１５９】
したがって、同図はあくまで点灯状態にある表面伝導型放出素子から放出される電流を意味しており、消灯状態にある表面伝導型放出素子が電流を放出することはない。
【０１６０】
以下に、電圧降下量から画像データを補正する補正データを算出する方法について説明する。
【０１６１】
図９（ａ），（ｂ），（ｃ）は図８の放出電流の時間変化から、電圧降下量の補正データを計算する方法を説明するための図である。同図は大きさが６４の画像データに対する補正データを算出した例である。
【０１６２】
輝度の発光量は、放出電流パルスによる放出電流を時間的に積分した、放出電荷量に他ならない。したがって以降では、電圧降下による輝度の変動を考えるのにあたって、放出電荷量をもとに説明を行う。
【０１６３】
いま、電圧降下の影響がない場合の放出電流をＩＥ、パルス幅変調の１階調に相当する時間をΔｔとするならば、画像データが６４のときの、放出電流パルスによって放出されるべき放出電荷量Ｑ０は放出電流パルスの振幅ＩＥにパルス幅（６４×Δｔ）をかけて、
【数９】

としてあらわすことができる。
【０１６４】
しかし、実際には、走査配線上の電圧降下によって放出電流が低下する現象が発生する。
【０１６５】
電圧降下の影響を考慮した放出電流パルスによる放出電荷量は、近似的には次のように計算できる。
【０１６６】
すなわち、ノード２のタイムスロット＝０、６４の放出電流をそれぞれＩｅ０、Ｉｅ１とし、０〜６４の間の放出電流はＩｅ０とＩｅ１の間を直線的に変化するものと近似すれば、この間の放出電荷量Ｑ１は図９（ｂ）の台形の面積、すなわち、
【数１０】

として計算できる。
【０１６７】
次に、図９（ｃ）に示すように、電圧降下による放出電流の低下分を補正するために、パルス幅をＤＣ１だけ伸ばしたとき、電圧降下の影響を除去できたとする。
【０１６８】
また、電圧降下の補正を行い、パルス幅を伸ばした場合には、各タイムスロットにおける放出電流量は変化すると考えられるが、ここでは簡単化のため、図９（ｃ）のように、タイムスロット＝０では、放出電流がＩｅ０、タイムスロット＝（６４＋ＤＣ１）における放出電流がＩｅ１になるものとする。
【０１６９】
また、タイムスロット０とタイムスロット（６４＋ＤＣ１）の間の放出電流は、２点の放出電流を直線で結んだ線上の値をとるものと近似する。
【０１７０】
すると、補正後の放出電流パルスによる放出電荷量Ｑ２は、
【数１１】

として計算できる。
【０１７１】
これが前述のＱ０と等しいとすれば、
【数１２】

これをＤＣ１について解けば、
【数１３】

となる。
【０１７２】
このようにして、画像データが６４の場合の補正データを算出した。
【０１７３】
すなわち、ノード２の位置の、大きさが６４の画像データに対しては式９に記載のように、ＣＤａｔａ ＝ＤＣ１だけ補正量を加算すればよい。
【０１７４】
図１０は計算された電圧降下量から、大きさが１２８の画像データに対する補正データを算出した例である。
【０１７５】
いま、電圧降下の影響がない場合、画像データが１２８のときに放出電流パルスによって放出される放出電荷量Ｑ３は、
【数１４】

一方、電圧降下の影響を受けた、実際の放出電流パルスによる投入電荷量は、近似的には次のように計算することができる。
【０１７６】
すなわち、ノード２のタイムスロット＝０、６４、１２８の放出電流量をそれぞれＩｅ０，Ｉｅ１，Ｉｅ２とする。また、０〜６４の間の放出電流はＩｅ０とＩｅ１の間を直線的に変化し、６４〜１２８の間はＩｅ１とＩｅ２の間を直線で結んだ線上を変化するものと近似すれば、０〜１２８までのタイムスロットの間の放出電荷量Ｑ４は図１０（ｂ）の２つの台形の面積の和、すなわち、
【数１５】

として計算できる。
【０１７７】
一方、電圧降下の補正量を以下のように計算した。
【０１７８】
タイムスロット０〜６４に相当する期間を期間１、６４〜１２８に相当する期間を期間２と定義する。
【０１７９】
補正を施した際に、期間１の部分がＤＣ１だけ伸びて期間１’に伸長され、期間２の部分がＤＣ２だけ伸びて、期間２’に伸長されるものと考える。
【０１８０】
この際におのおのの期間は補正を施されることにより、放出電荷量が前述のＱ０と同じになるものとする。
【０１８１】
また、各期間の初めと終わりの放出電流は、補正を行うことで変化することは言うまでもないが、ここでは計算を簡単化するため、変化しないものと仮定した。
【０１８２】
すなわち、期間１’の初めの放出電流はＩｅ０，期間１’の終わりの放出電流はＩｅ１，期間２’の初めの放出電流はＩｅ１、期間２’の終わりの放出電流は、Ｉｅ２であるものとする。
【０１８３】
すると、ＤＣ１は式９と同様にして計算することができる。
【０１８４】
また、ＤＣ２は、同様な考え方により、
【数１６】

として計算することができる。
【０１８５】
結果としてノード２の位置の大きさが１２８の画像データに対しては
【数１７】

だけ補正量ＣＤａｔａを加算すればよい。
【０１８６】
図１１は計算された電圧降下量から、大きさが１９２の画像データに対する補正データを算出した例である。
【０１８７】
いま、画像データが１９２のときに期待される放出電流パルスによる放出電荷量Ｑ５は、
【数１８】

一方、電圧降下の影響を受けた、実際の放出電流パルスによる放出電荷量は、近似的には次のように計算することができる。
【０１８８】
すなわち、ノード２のタイムスロット＝０の時の放出電流をＩｅ０、タイムスロット＝６４のときの放出電流をＩｅ１、タイムスロット＝１２８の時の放出電流をＩｅ２、タイムスロット＝１９２の時の放出電流をＩｅ３とし、０〜６４の間の放出電流はＩｅ０とＩｅ１の間を直線的に変化し、６４〜１２８の間はＩｅ１とＩｅ２の間を直線で結んだ線上を変化し、１２８〜１９２の間はＩｅ２とＩｅ３の間を直線で結んだ線上を変化するものと近似すれば、０〜１９２までのタイムスロットの間の投入電荷量Ｑ６は図１１（ｃ）の３つの台形の面積、すなわち、
【数１９】

として計算できる。
【０１８９】
一方、電圧降下の補正量を以下のように計算した。
【０１９０】
タイムスロット０〜６４に相当する期間を期間１、６４〜１２８に相当する期間を期間２、１２８〜１９２に相当する期間を期間３と定義する。
【０１９１】
先ほどと同様に、補正を施した後には、期間１の部分がＤＣ１だけ伸びて期間１’に伸長され、期間２の部分がＤＣ２だけ伸びて、期間２’に伸長され、期間３の部分がＤＣ３だけ伸びて期間３’に伸張されるものと考える。
【０１９２】
この際、おのおのの期間は補正を施されることにより、放出電荷量が前述のＱ０と同じになるものとする。
【０１９３】
また、各期間の初めと終わりの放出電流は、補正の前後で変わらないものと仮定した。
【０１９４】
すなわち、期間１’の初めの放出電流は、Ｉｅ０，期間１’の終わりの放出電流はＩｅ１，期間２’の初めの放出電流はＩｅ１、期間２’の終わりの放出電流は、Ｉｅ２、期間３’の初めの放出電流はＩｅ３、期間３’の終わりの放出電流はＩｅ４であるものとする。
【０１９５】
すると、ＤＣ１、ＤＣ２はそれぞれ式９，１２と同様に計算することができる。
【０１９６】
また、ＤＣ３については、
【数２０】

として計算することができる。
【０１９７】
結果としてノード２の位置の大きさが１９２の画像データに加算する補正データＣＤａｔａとしては、
【数２１】

を加算すればよい。
【０１９８】
以上のようにしてノード２の位置に対する画像データ６４、１２８、１９２の補正データＣＤａｔａを算出した。
【０１９９】
また、パルス幅が０の時には、当然ながら放出電流に対する電圧降下の影響はないため、補正データは０とし画像データに加算する補正データＣＤａｔａも０とした。
【０２００】
なお、このように０、６４、１２８、１９２というように、とびとびの画像データに対して補正データを計算しているのは、計算量を減らすことを狙ったものである。
【０２０１】
すなわち任意のすべての画像データに対して同様の計算を行っては、非常に計算量が大きくなり、計算を行うためのハードウエア量が非常に大きくなってしまう。
【０２０２】
一方、あるノードの位置においては、画像データが大きいほど、補正データも大きくなる傾向がある。これにより、任意の画像データに対する補正データを算出する際には、その画像データの近傍のすでに補正データが算出されている点と点を直線近似により補間すれば、計算量を大幅に減少させることができるためである。なお、この補間については離散補正データ補間部を説明する際に詳しく説明する。
【０２０３】
また、同様な考え方をすべてのノードの位置において適用すれば、すべてのノードの位置における、画像データ＝０、６４、１２８、１９２の補正データを算出できる。
【０２０４】
本例ではタイムスロットを０、６４，１２８，１９２の４点に対して縮退モデルを適用して、各時刻の電圧降下量を計算したことにより、０、６４，１２８，１９２の４つの画像データ基準値に対する補正データを求めることができた。
【０２０５】
しかし、好ましくは前述したように、縮退モデルにより電圧降下を計算する時間の間隔を細かく、画像データの基準値をさらに多くとることで、電圧降下の時間変化をより精密に扱うことができ、近似計算の誤差を低減することができる。
【０２０６】
なお、その際には同様な考え方に立って、式６〜式１６を変形して計算を行えばよい。
【０２０７】
上述の方法により、ある入力データに対し、各々のノードの位置における、画像データ＝０，６４，１２８，１９２に対する補正データを離散的に計算した。
【０２０８】
本方法により求めた、ある入力画像データに対する離散補正データの例を図１２（ａ）に示す。同図において横軸は水平表示位置に対応しており、各ノードの位置が記載されている。また、縦軸は補正データの大きさである。
【０２０９】
離散補正データは図の□、○、●、△で記載したノードの位置と画像データＤａｔａの大きさ（画像データ基準値＝０，６４，１２８，１９２）に対して計算がされているものである。
【０２１０】
（離散補正データの補間方法）
離散的に算出された補正データは、各ノードの位置に対する離散的なものであって、任意の水平位置（列配線番号）における補正データを与えるものではない。またそれと同時に、各ノード位置においていくつかの予め定められた画像データの基準値の大きさをもつ画像データに対する補正データであって実際の画像データの大きさに応じた補正データをあたえるものではない。
【０２１１】
そこで発明者らは、各列配線における入力画像データの大きさに適合した補正データを離散的に算出した補正データを補間することにより算出した。
【０２１２】
図１２（ｂ）はノードｎとノードｎ＋１の間に位置するｘという位置における、画像データＤａｔａに相当する補正データを算出する方法を示した図である。
【０２１３】
なお前提として、補正データはすでにノードｎ及びノードｎ＋１の位置Ｘｎ及びＸｎ＋１において離散的に計算されているものとする。
【０２１４】
また、入力画像データであるＤａｔａはすでに離散的に補正データが算出されている２つの画像データ基準値ＤｋとＤｋ＋１の間の値をとるものとする。
【０２１５】
いま、ノードｎのｋ番目の画像データの基準値Ｄｋに対する補正データをＣＤａｔａ［ｋ］［ｎ］と表記するならば、位置ｘにおける画像データＤｋに対する補正データＣＡは、ＣＤａｔａ［ｋ］［ｎ］とＣＤａｔａ［ｋ］［ｎ＋１］の値を用いて、直線近似により、以下のように計算できる。
【数２２】

【０２１６】
また、位置ｘにおける画像データＤｋ＋１の補正データＣＢは以下のように計算できる。
【数２３】

【０２１７】
ＣＡとＣＢの補正データを直線近似することにより、位置ｘにおける画像データＤａｔａに対する補正データＣＤは、以下のように計算できる。
【数２４】

【０２１８】
以上のように、離散補正データから実際の位置や画像データの大きさに適合した補正データを算出するためには、式１７〜式１９に記載した方法により簡単に計算できる。
【０２１９】
このようにして算出した補正データを画像データに加算して画像データを補正し、補正後の画像データに応じてパルス幅変調を行えば、従来からの課題であった電圧降下による画質の低下を低減することができ、画質を向上させることができる。
【０２２０】
また予てからの課題であった補正のためのハードウエアも、これまで説明してきたような縮退化などの近似を導入することにより、計算量を低減化することができるため非常に小規模なハードウエアで構成することができるというすぐれたメリットがあった。
【０２２１】
（システム全体と各部分の機能説明）
次に、補正データ算出手段を内蔵した画像表示装置のハードウエアについて説明する。
【０２２２】
図１３はその回路構成の概略を示すブロック図である。図において１は図１の表示パネル、Ｄｘ１〜ＤｘＭ及びＤｘ１’〜ＤｘＭ’は表示パネルの走査配線の電圧供給端子、Ｄｙ１〜ＤｙＮは表示パネルの変調配線の電圧供給端子、Ｈｖはフェースプレートとリアプレートの間に加速電圧を印加するための高圧供給端子、Ｖａは高圧電源、２は走査回路（走査手段）、３は同期信号分離回路、４はタイミング発生回路、７は同期分離回路３によりＹＰｂＰｒ信号をＲＧＢに変換するための変換回路、１７は逆γ処理部、５は画像データ１ライン分のシフトレジスタ、６は画像データ１ライン分のラッチ回路、８は表示パネルの変調配線に変調信号を出力するパルス幅変調手段（変調手段）、１２は加算器（演算処理手段，加算処理手段）、１４は補正データ算出手段である。
【０２２３】
また、同図においてＲ、Ｇ、ＢはＲＧＢパラレルの入力映像データ、Ｒａ，Ｇａ，Ｂａは後述する逆γ変換処理を施したＲＧＢパラレルの映像データ、Ｄａｔａはデータ配列変換部によりパラレル・シリアル変換された画像データ、ＣＤは補正データ算出手段により算出された補正データ、Ｄｏｕｔは加算器により画像データに補正データを加算することにより、補正された画像データである。
【０２２４】
（同期分離回路、タイミング発生回路）
本実施形態の画像表示装置は、ＮＴＳＣや、ＰＡＬ、ＳＥＣＡＭ、ＨＤＴＶなどのテレビジョン信号や、コンピュータの出力であるＶＧＡなどをともに表示することができる。
【０２２５】
図１３では図を簡単化するため、ＨＤＴＶ方式のみについて記載している。
【０２２６】
ＨＤＴＶ方式の映像信号は、まず３の同期分離回路により同期信号Ｖｓｙｎｃ，Ｈｓｙｎｃを分離し、タイミング発生回路に供給する。同期分離された映像信号は、ＲＧＢ変換手段に供給される。ＲＧＢ変換手段の内部には、ＹＰｂＰｒからＲＧＢへの変換回路の他に、不図示のローパスフィルタやＡ／Ｄ変換器などが設けられており、ＹＰｂＰｒをディジタルＲＧＢ信号へと変換し、逆γ処理部へと供給する。
【０２２７】
（タイミング発生回路）
タイミング発生回路は、ＰＬＬ回路を内蔵しており、様々な映像ソースの同期信号に同期したタイミング信号を発生し、各部の動作タイミング信号を発生する回路である。
【０２２８】
タイミング発生回路４が発生するタイミング信号としては、シフトレジスタ５の動作タイミングを制御するＴｓｆｔ、シフトレジスタから、ラッチ回路６へデータをラッチするための制御信号Ｄａｔａｌｏａｄ、変調手段８のパルス幅変調開始信号Ｐｗｍｓｔａｒｔ，パルス幅変調のためのクロックＰｗｍｃｌｋ、走査回路２の動作を制御するＴｓｃａｎなどがある。
【０２２９】
（走査回路）
走査回路２及び２’は、表示パネルを一水平走査期間に１行ずつ順次走査するために、接続端子Ｄｘ１〜ＤｘＭに対して選択電位Ｖｓまたは非選択電位Ｖｎｓを出力する回路である（図１４）。
【０２３０】
走査回路２及び２’はタイミング発生回路４からのタイミング信号Ｔｓｃａｎに同期して、一水平期間ごとに、選択している走査配線を順次切り替え、走査を行う回路である。
【０２３１】
なお、Ｔｓｃａｎは垂直同期信号及び水平同期信号などから作られるタイミング信号群である。
【０２３２】
走査回路２及び２’は、図１４に示すようにそれぞれＭ個のスイッチとシフトレジスタなどから構成される。これらのスイッチはトランジスタやＦＥＴにより構成するのが好ましい。
【０２３３】
なお、走査配線での電圧降下を低減するためには、走査回路は図１３に示したように、表示パネルの走査配線の両端に接続され、両端からドライブされることが好ましい。
【０２３４】
一方、本発明は、走査回路が走査配線の両端に接続されていない場合でも有効であり、式３のパラメータを変更するだけで適用できる。
【０２３５】
（逆γ処理部）
ＣＲＴは入力に対しほぼ２．２乗の発光特性（以降逆γ特性とよぶ）を備えている。
【０２３６】
入力映像信号はＣＲＴのこのような特性が考慮されており、ＣＲＴに表示した際にリニアな発光特性となるように一般に０．４５乗のγ特性にしたがって変換される。
【０２３７】
一方、本実施形態の画像表示装置の表示パネルは駆動電圧の印加時間により変調を施す場合、印加時間の長さに対しほぼリニアな発光特性を有しているため、入力映像信号を逆γ特性にもとづいて変換（以降逆γ変換とよぶ）する必要がある。
【０２３８】
図１３に記載した逆γ処理部は、入力映像信号を逆γ変換するためのブロックである。
【０２３９】
本実施形態の逆γ処理部は、上記逆γ変換処理をメモリによって構成した。
【０２４０】
逆γ処理部は映像信号Ｒ、Ｇ、Ｂのビット数を８ビットとし、逆γ処理部の出力である映像信号Ｒａ、Ｇａ、Ｂａのビット数を同じく８ビットとして、アドレス８ビット、データ８ビットのメモリを各色ごと用いることにより構成した（図１５）。
【０２４１】
各メモリには図１６に記載した逆γ特性を記憶させた。なお同図（ａ）は本変換テーブルの入力映像信号が０〜２５５の範囲の該テーブルに記載したデータである。また、同図（ｂ）は入力画像データが０〜４８の範囲を拡大して表示したものである。
【０２４２】
（データ配列変換部）
データ配列変換部９はＲＧＢパラレルな映像信号であるＲａ，Ｇａ，Ｂａを表示パネルの画素配列に合わせてパラレル・シリアル変換する回路である。データ配列変換部９の構成は図１７に示したようにＲＧＢ各色ごとのＦＩＦＯ（ＦｉｒｓｔＩｎＦｉｒｓｔＯｕｔ）メモリ２０２１Ｒ，２０２１Ｇ、２０２１Ｂとセレクタ２０２２から構成される。
【０２４３】
同図では図示していないが、ＦＩＦＯメモリは水平画素数ワードのメモリを奇数ライン用と偶数ライン用の２本備えている。奇数行目の映像データが入力された際には、奇数ライン用のＦＩＦＯにデータが書き込まれる一方、偶数ライン用のＦＩＦＯメモリから一つ前の水平走査期間に蓄積された画像データが読み出される。偶数行目の映像データが入力された際には偶数ライン用のＦＩＦＯにデータが書き込まれる一方、奇数ライン用ＦＩＦＯメモリから一つ前の水平期間に蓄積された画像データが読み出される。
【０２４４】
ＦＩＦＯメモリから読み出されたデータは、セレクタにより表示パネルの画素配列にしたがって、パラレル・シリアル変換され、ＲＧＢのシリアル画像データＳＤａｔａとして出力される。詳細については記載しないが、タイミング発生回路４からのタイミング制御信号に基づいて動作する。
【０２４５】
（加算器１２）
加算器１２は補正データ算出手段からの補正データＣＤと画像データＤａｔｂ・チ算する手段である。加算を行うことにより画像データＤａｔａは補正が施され、画像データＤｏｕｔとしてシフトレジスタへ転送される。
【０２４６】
なお、画像データＤａｔａと補正データＣＤを加算する際に、加算器でオーバーフローが起きる可能性があるが、
これに対し、本例ではオーバーフローを起こさないための構成として、画像データＤａｔａと補正データＣＤを加算した際の最大値に応じて、加算器のビット幅と、その後の変調手段のビット幅を決定した。
【０２４７】
より具体的には、本例の画像表示装置の場合、画像データがすべて２５５の画面の際に補正データが最大１２０になったため、
加算器の出力の最大値＝２５５＋１２０＝３７５
となったため、加算器の出力ビット数を９ビット、変調手段のビット数も９ビットとして各部のビット数を決定した。
【０２４８】
また、オーバーフローがおきないようにするための別の構成としては、加算される補正データの最大値をあらかじめ見積もり、該最大値が加算されたときにオーバーフローがおきないように、画像データの取りえる範囲を予め小さくしておいてもよい。
【０２４９】
画像データの取りえる大きさを小さくするためには、たとえば、入力画像データをＡ／Ｄ変換する際に制限してもよいし、乗算器を設けて、入力された画像データに０以上１以下のゲインを乗算し、その大きさを制限してもよい。
【０２５０】
（遅延回路１９）
データ配列変換部により並び替えが行われた画像データＳＤａｔａは補正データ算出手段と遅延回路（遅延手段）１９に入力される。補正データ算出手段の補正データ補間部はタイミング制御回路からの水平位置情報ｘと画像データＳＤｂ狽≠フ値を参照して、それらにあった補正データＣＤを算出する。
【０２５１】
遅延回路１９は、補正データ算出にかかる時間を吸収するために設けられており、加算器で画像データに補正データが加算される際に、画像データにそれに対応した補正データが正しく加算されるよう遅延を行う手段である。同手段はフリップフロップを用いることにより構成できる。
【０２５２】
（シフトレジスタ、ラッチ回路）
補正データ補間部の出力である画像データＤｏｕｔは、シフトレジスタ５により、シリアルなデータフォーマットから、各変調配線毎のパラレルな画像データＩＤ１〜ＩＤＮへとシリアル／パラレル変換されラッチ回路へ出力される。ラッチ回路では１水平期間が開始される直前にタイミング信号Ｄａｔａｌｏａｄにより、シフトレジスタからのデータをラッチする。ラッチ回路６の出力は、パラレルな画像データＤ１〜ＤＮとして変調手段へと供給される。
【０２５３】
なお本実施形態では画像データＩＤ１〜ＩＤＮ、Ｄ１〜ＤＮはそれぞれ８ビットの画像データとした。これらの動作タイミングはタイミング発生回路４（図１３）からのタイミング制御信号ＴＳＦＴ及びＤａｔａｌｏａｄに基づいて動作する。
【０２５４】
（変調手段の詳細）
ラッチ回路６の出力であるパラレル画像データＤ１〜ＤＮは変調手段８へと供給される。
【０２５５】
変調手段は、図１８（ａ）に示したように、ＰＷＭカウンタと、各変調配線ごとにコンパレータとスイッチ（同図ではＦＥＴ）を備えたパルス幅変調回路（ＰＷＭ回路）である。
【０２５６】
画像データＤ１〜ＤＮと変調手段の出力パルス幅の関係は、図１８（ｂ）のようなリニアな関係にある。
【０２５７】
同図（ｃ）に変調手段の出力波形の例を３つ示す。
【０２５８】
同図において上側の波形は、変調手段への入力データが０の時の波形、
中央の波形は、変調手段への入力データが２５６の時の波形、
下側の波形は、変調手段への入力データが５１１の時の波形である。
【０２５９】
なお本例では変調手段への入力データＤ１〜ＤＮのビット数は前述のように、オーバーフローしないことを考慮して、９ビットとした。
【０２６０】
なお、前述の説明では、変調手段の入力データが５１１のときは、一水平走査期間に相当するパルス幅の変調信号が出力されると記載した箇所があるが、詳細には同図（ｃ）のように非常に短い時間ではあるがパルスの立ち上がる前と、立ち下がった後に駆動しない期間を設けタイミング的な余裕を持たせている。
【０２６１】
図１９は、本発明の変調手段の動作を示すタイミングチャートである。
【０２６２】
同図において、Ｈｓｙｎｃ水平同期信号、Ｄａｔａｌｏａｄはラッチ回路６へのロード信号、Ｄ１〜ＤＮは前述の変調手段の列１〜Ｎへの入力信号、ＰｗｍｓｔａｒｔはＰＷＭカウンタの同期クリア信号、ＰｗｍｃｌｋはＰＷＭカウンタのクロックである。また、ＸＤ１〜ＸＤＮは変調手段の第１〜第Ｎ列の出力を表している。
【０２６３】
同図にあるように１水平走査期間が始まると、ラッチ回路６は画像データをラッチするとともに変調手段へデータを転送する。
【０２６４】
ＰＷＭカウンタは、同図に示したように、Ｐｗｍｓｔａｒｔ、Ｐｗｍｃｌｋに基づいてカウントを開始し、カウント値が５１１になるとカウンタをストップしカウント値５１１を保持する。
【０２６５】
各列毎に設けられているコンパレータは、ＰＷＭカウンタのカウント値と各列の画像データを比較し、ＰＷＭカウンタの値が画像データ以上のときＨｉｇｈを出力し、それ以外の期間はＬｏｗを出力する。
【０２６６】
コンパレータの出力は、各列のスイッチのゲートに接続されており、コンパレータの出力がＬｏｗの期間は同図の上側（ＶＰＷＭ側）のスイッチがＯＮ、下側（ＧＮＤ側）のスイッチがＯＦＦとなり、変調配線を電圧ＶＰＷＭに接続する。
【０２６７】
逆にコンパレータの出力がＨｉｇｈの期間は、同図の上側のスイッチがＯＦＦし、下側のスイッチがＯＮするとともに、変調配線の電圧をＧＮＤ電位に接続する。
【０２６８】
各部が以上のように動作することで、変調手段が出力するパルス幅変調信号は、図１９のＤ１、Ｄ２、ＤＮに示したような、パルスの立ち上がりが同期した波形となる。
【０２６９】
（補正データ算出手段）
補正データ算出手段は前述した補正データ算出方法により、電圧降下の補正データを算出する回路である。補正データ算出手段は図２０に示すように離散補正データ算出部と補正データ補間部の２つのブロックから構成される。
【０２７０】
離散補正データ算出部では入力された映像信号から電圧降下量を算出し、電圧降下量から補正データを離散的に計算する手段である。同手段は計算量やハードウエア量を減少させるために、前述の縮退モデルの概念を導入して、補正データを離散的に算出する。
【０２７１】
離散的に算出された補正データは補正データ補間部（補正データ補間手段）により補間され、画像データの大きさやその水平表示位置ｘに適合した補正データＣＤが算出される。
【０２７２】
（離散補正データ算出部）
図２１は本発明の離散補正データを算出するための離散補正データ算出部である。
【０２７３】
離散補正データ算出部は、以下に述べるように、画像データをブロックわけし、ブロックごとの統計量（点灯数）を算出するとともに、統計量から各ノードの位置における、電圧降下量の時間変化を計算する電圧降下量算出部としての機能と、各時間ごとの電圧降下量を発光輝度量に変換する機能、および発光輝度量を時間方向に積分して、発光輝度総量を算出する機能、およびそれらから離散的な基準点における、画像データの基準値に対する補正データを算出する手段である。
【０２７４】
同図において１００ａ〜１００ｃは点灯数カウント手段、１０１ａ〜１０１ｃは各ブロックごとの、各時刻における点灯数を格納するレジスタ群、１０２はＣＰＵ、１０３は式２及び３で記載したパラメータａｉｊを記憶するためのテーブルメモリ（電圧降下量記憶手段）、１０４は計算結果を一時記憶するためのテンポラリレジスタ、１０５はＣＰＵのプログラムが格納されているプログラムメモリ、１１１は、電圧降下量を放出電流量に変換する変換データが記載されたテーブルメモリ、１０６は、前述した離散補正データの計算結果を格納するためのレジスタ群である。
【０２７５】
点灯数カウント手段１００ａ〜１００ｃは、同図（ｂ）に記載したようなコンパレータと加算器などから構成されている。映像信号Ｒａ，Ｇａ，Ｂａはそれぞれコンパレータ１０７ａ〜ｃに入力され、逐次Ｃｖａｌの値と比較される。
【０２７６】
なお、Ｃｖａｌは前述してきた画像データに対して設定した、基準値に相当する。
【０２７７】
コンパレータ１０７ａ〜ｃはＣｖａｌと画像データの比較を行い画像データの方が大きければＨｉｇｈを出力し小さければＬｏｗを出力する。
【０２７８】
コンパレータの出力は加算器１０８及び１０９により互いに足し算され、さらに加算器１１０によりブロックごとに加算をおこない、ブロックごとの加算結果を各々のブロックごとの点灯数としてレジスタ群１０１ａ〜ｃへと格納する。
【０２７９】
点灯数カウント手段１００ａ〜ｃにはコンパレータの比較値Ｃｖａｌとしてそれぞれ０、６４、１２８、１９２が入力されている。
【０２８０】
結果として、点灯数カウント手段１００ａは画像データのうち、０より大きい画像データの個数をカウントしそのブロックごとの総計をレジスタ１０１ａに格納する。
【０２８１】
同様に、点灯数カウント手段１００ｂは画像データのうち、６４より大きい画像データの個数をカウントし、そのブロックごとの総計をレジスタ１０１ｂに格納する。
【０２８２】
同様に、点灯数カウント手段１００ｃは画像データのうち、１２８より大きい画像データの個数をカウントし、そのブロックごとの総計をレジスタ１０１ｃに格納する。
【０２８３】
同様に、点灯数カウント手段１００ｄは画像データのうち、１９２より大きい画像データの個数をカウントし、そのブロックごとの総計をレジスタ１０１ｄ格納する。
【０２８４】
ブロックごと、時間ごとの点灯数カウントされると、ＣＰＵはテーブルメモリ１０３に格納されたパラメータテーブルａｉｊを随時読み出して、式２〜５に従い、電圧降下量を計算し、計算結果をテンポラリレジスタ１０４に格納する。
【０２８５】
本例ではＣＰＵに式２の計算を円滑におこなうための積和演算機能を設けた。
【０２８６】
式２に挙げた演算を実現する手段としては、ＣＰＵで積和演算を行わないでもよく、例えば、その計算結果をメモリに入れておいてもよい。
【０２８７】
すなわち、各ブロックの点灯数を入力とし、考えられるすべての入力パターンに対し、各ノード位置の電圧降下量をメモリに記憶させておいても構わない。
【０２８８】
電圧降下量の計算が完了するとともに、ＣＰＵはテンポラリレジスタ１０４から、各時間、各ブロックごとの電圧降下量をよみだし、テーブルメモリ２（１１１）を参照して、電圧降下量を放出電流量に変換し、式６〜１６に従って、離散補正データを算出した。
【０２８９】
計算した離散補正データは、レジスタ群１０６に格納した。
【０２９０】
（補正データ補間部）
補正データ補間部は画像データの表示される位置（水平位置）及び、画像データの大きさに適合した補正データを算出するための手段である。同手段は離散的に算出された補正データを補間することにより、画像データの表示位置（水平位置）及び、画像データの大きさに応じた補正データを算出する。
【０２９１】
図２２は補正データ補間部を説明するための図である。
【０２９２】
同図において１２３は画像データの表示位置（水平位置）ｘから、補間に用いる離散補正データのノード番号ｎ及びｎ＋１を決定するためのデコーダであり、１２４は画像データの大きさから、式１７〜式１９のｋおよびｋ＋１を決定するためのデコーダである。
【０２９３】
また、セレクタ１２５〜１２８は、離散補正データを選択して、直線近似手段に供給するためのセレクタである。
【０２９４】
また、１２１〜１２３は、それぞれ式１７〜１９の直線近似を行うための直線近似手段である。
【０２９５】
図２３に直線近似手段１２１の構成例を示す。一般に直線近似手段は式１７〜１９の演算子にあらわされるように、減算器、積算器、加算器、割り算器などによって構成可能である。
【０２９６】
しかし、望ましくは離散補正データを算出するノードのノードの間の列配線本数や、離散補正データを算出する画像データ基準値の間隔（すなわち電圧降下を算出する時間間隔）が２のべき乗になるように構成するとハードウエアを非常に簡単に構成できるというメリットがある。それらを２のべき乗に設定すれば、図２３に示した割り算器において、Ｘｎ＋１−Ｘｎは２のべき乗の値となり、ビットシフトすればよい。
【０２９７】
Ｘｎ＋１−Ｘｎの値がいつも一定の値であって、２のべき乗で表される値であるならば、加算器の加算結果をべき乗の乗数分だけシフトして出力すればよく、あえて割り算器を作製する必要がない。
【０２９８】
またこれ以外の箇所でも離散補正データを算出するノードの間隔や、画像データの間隔を２のべき乗とすることにより、たとえばデコーダ１２３〜１２４を簡単に作製することが可能となるとともに、図２３の減算器で行っている演算を簡単なビット演算に置き換えることができるなど、非常にメリットが多い。
【０２９９】
（各部の動作タイミング）
図２４に各部の動作タイミングのタイミングチャートを示す。
【０３００】
なお、同図においてＨｓｙｎｃは水平同期信号、ＤｏｔＣＬＫはタイミング発生回路の中のＰＬＬ回路により水平同期信号Ｈｓｙｎｃから作成したクロック、Ｒ、Ｇ、Ｂは入力切り替え回路からのディジタル画像データ、Ｄａｔａはデータ配列変換後の画像データ、Ｄｏｕｔは電圧降下補正を施された画像データ、ＴＳＦＴはシフトレジスタ５へ画像データＤｏｕｔを転送するためのシフトクロック、Ｄａｔａｌｏａｄはラッチ回路６へデータをラッチするためのロードパルス、Ｐｗｍｓｔａｒｔは前述のパルス幅変調の開始信号、変調信号ＸＤ１は変調配線１へ供給されるパルス幅変調信号の一例である。
【０３０１】
１水平期間の開始とともに、入力切り替え回路からディジタル画像データＲＧＢが転送される。同図では水平走査期間Ｉにおいて、入力される画像データをＲ＿Ｉ、Ｇ＿Ｉ、Ｂ＿Ｉで表すと、それらは、データ配列変換回路９では１水平期間の間、画像データを蓄えられ、水平走査期間Ｉ＋１において、表示パネルの画素配置に合わせてディジタル画像データＤａｔａ＿Ｉとして出力される。
【０３０２】
Ｒ＿Ｉ，Ｇ＿Ｉ，Ｂ＿Ｉは、水平走査期間Ｉにおいて補正データ算出手段に入力される。同手段では、前述した点灯数をカウントし、カウントの終了とともに、電圧降下量が算出される。
【０３０３】
電圧降下量が算出されるのにつづいて、離散補正データが算出され、算出結果がレジスタに格納される。
【０３０４】
走査期間Ｉ＋１に移り、データ配列変換部から、１水平走査期間前の画像データＤａｔａ＿Ｉが出力されるのに同期して、補正データ補間部では離散補正データが補間され、補正データが算出される。補間された補正データは、階調数変換部１５で直ちに階調数変換を施され、加算器１２に供給される。
【０３０５】
加算器１２では、画像データＤａｔａと補正データＣＤｚを順次加算し、補正された画像データＤｏｕｔをシフトレジスタへ転送する。シフトレジスタはＴｓｆｔにしたがって、一水平期間分の画像データＤｏｕｔを記憶するとともにシリアル・パラレル変換をおこなってパラレルな画像データＩＤ１〜ＩＤＮをラッチ回路６に出力する。ラッチ回路６はＤａｔａｌｏａｄの立ち上がりにしたがってシフトレジスタからのパラレル画像データＩＤ１〜ＩＤＮをラッチし、ラッチされた画像データＤ１〜ＤＮをパルス幅変調手段８へと転送する。
【０３０６】
パルス幅変調手段８は、ラッチされた画像データに応じたパルス幅のパルス幅変調信号を出力する。本実施形態の画像表示装置では、結果として、変調手段が出力するパルス幅は、入力された画像データに対し、２水平走査期間分おくれて表示される。
【０３０７】
このような画像表示装置により画像の表示を行ったところ、従来からの課題であった走査配線における電圧降下量を補正することができ、それに起因する表示画像の劣化を改善することができ、非常に良好な画像を表示することができた。
【０３０８】
また、離散的に補正データを算出し、離散的に計算した点と点の間はそれを補間して求めることにより、補正データを非常に簡単に計算させることができ、さらに非常に簡単なハードウエアでそれを実現できるなど、非常に優れた効果があった。
【０３０９】
（ノードの位置及び、画像データ基準値の好ましい設定間隔について）
上述の例では、説明を簡単化する意味もあり、ブロックを４つとした例を示してきた。電圧降下量や離散補正データを算出する位置であるノードはブロックの境界位置の５つの点で表される。しかし補正データを精度よく計算するためには、ブロックやノードの数としては、多ければ多いほど前述した直線近似による誤差が少なくなるため、好ましいが、その一方で計算量が増加することは言うまでもない。
【０３１０】
一方、限られたブロック数、ノード数で、誤差を少なくするための手法としては、電圧降下量や補正データの変化の大きい箇所はブロックや、ノードの間隔を細かく設定し、逆に電圧降下量や補正データの変化の小さい箇所は、ブロックや、ノードを設定する間隔を荒くすることが好ましい。このようにノードやブロックを設定すれば、前述した直線近似を行っても誤差を少なく、かつ少ない計算量で計算ができるという点で非常に好ましい。
【０３１１】
図２５（ａ）は走査配線の両側に走査回路を備えた場合に画面に全白を表示した際の補正画像データを計算した計算結果の例である。
【０３１２】
理想的な計算結果としては同図の点線にあるような曲線として計算されることが好ましいが、本発明では縮退化を行って計算しているため、実際には、図中○マークで記載した、ノードの位置において離散補正画像データが算出されており、その中間の位置に置いては、隣接するノードとノードの補正画像データを直線近似して計算していることについては先に述べた。
【０３１３】
この場合、ノードの位置としては図２５（ａ）の点線の勾配の大きい、画面の左右両端に近いほど、ノードの設定間隔を細かくし、画面の中央ほどノードの設定間隔を荒くすれば、限られた計算量のなかで直線補間を行うことによる計算誤差を低減することができ、好ましかった。
【０３１４】
図２５（ｂ）は走査配線の片側にのみ、走査回路を備えた場合に、画面に全白を表示した際の補正画像データを計算した計算結果の例である。
【０３１５】
このような場合でも、変化の大きい画面の左側（走査回路のある側）ほどノードの設定間隔を細かくし、画面の右側（走査回路のない側）ほどブロックや、ノードの設定間隔を荒くすることで、少ない計算量で精度のよい計算を行うことができるなど、好ましかった。
【０３１６】
なおこの場合も、隣接するノードとノードの間隔は２のべき乗に選択したほうが補間回路でのハードウエア量を少なくできるため、好ましいことはいうまでもない。
【０３１７】
また、前述した、画像データ基準値を設定する間隔においては、画像データの大きさによって、以下のように設定することが好ましかった。
【０３１８】
とくに画像データの小さい箇所では、画像データ自体の大きさが小さいため、補正データを算出した際の誤差により受ける影響が目立ちやすいという特徴がある。またこれと逆に、画像データの大きさが大きい箇所では、画像データの大きさ自体が大きいため、補正データを算出した際の誤差による影響は目立ちにくい。
【０３１９】
このような特徴を鑑みて、補正の誤差を減らすという観点では、画像データの小さい領域において、画像データ基準値を設定する間隔を細かく設定し、逆に、画像データの大きさの大きい領域においては、画像データ基準値を設定する間隔を荒く設定することが好ましかった。
【０３２０】
より具体的には、本発明者らは、画像データ基準値として、０、２、４、６、８、１６、３２、４８、６４、９６、１２８、１９２、２５６を選択して計算を行ったところ、非常に好ましかった。
【０３２１】
なおこの場合も隣接する画像データ基準値との間の間隔は、２のべき乗に選択することで計算を行うための補間回路のハードウエアを小さくできるため（割り算器などをビットシフト回路に置き換えることが可能。）非常に好ましかった。
【０３２２】
（第２の実施形態）
第１の実施形態では、入力画像データに対し、離散的な画像データの基準値を設定するとともに、行配線上に基準点を設定し、該基準点における、画像データ基準値の大きさの画像データに対する補正データを算出していた。
【０３２３】
さらに離散的に算出された補正データを補間することにより、入力された画像データの水平表示位置と、その大きさに応じた補正データを算出し、画像データと加算することにより、補正を実現していた。
【０３２４】
一方、上述の構成とは別に下記の構成によっても同様な補正が行える。
【０３２５】
離散的な水平位置と、画像データ基準値に対する、画像データの補正結果（すなわち前記離散補正データと画像データ基準値の和：すなわち補正画像データ）を算出し、
さらに離散的に算出された補正結果を補間し、入力された画像データの水平表示位置と、その大きさに応じた補正結果を算出し、その補正結果に応じて変調を行ってもよい。
【０３２６】
この構成では、離散的な計算の際に、画像データと補正データの加算された結果として算出されるため、補間後に画像データと補正データの加算を行う必要はない。
【０３２７】
【発明の効果】
以上説明したように、本発明の画像表示装置によれば、従来からの課題であった、走査配線上の電圧降下による表示画像の劣化を改善することができた。
【０３２８】
また、いくつかの近似を導入したことにより、電圧降下を補正するための、画像データの補正量を簡単に計算することができ、非常に簡単なハードウエアでそれを実現することができるなど、非常に優れた効果があった。
【０３２９】
また、表示画像の違和感についても低減することができるなどの優れた効果があった。
【図面の簡単な説明】
【図１】本発明の実施形態に係る画像表示装置の概観を示す図である。
【図２】表示パネルの電気的な接続を示す図である。
【図３】表面伝導型放出素子の特性を示す図である。
【図４】表示パネルの駆動方法を示す図である。
【図５】電圧降下の影響を説明する図である。
【図６】本発明の実施形態の縮退モデルを説明する図である。
【図７】離散的に算出した電圧降下量を示すグラフである。
【図８】離散的に算出した放出電流の変化量を示すグラフである。
【図９】本発明の実施形態の補正データの算出方法を説明するための図である。
【図１０】画像データの大きさが１２８の場合の補正データの算出例を示す図である。
【図１１】画像データの大きさが１９２の場合の補正データの算出例を示す図である。
【図１２】本発明の実施形態の補正データの補間方法を説明するための図である。
【図１３】本発明の実施形態の補正回路を内蔵した画像表示装置の概略構成を示すブロック図である。
【図１４】本発明の実施形態に係る画像表示装置の走査回路の構成を示すブロック図である。
【図１５】本発明の実施形態に係る画像表示装置の逆γ処理部の構成を示すブロック図である。
【図１６】本発明の実施形態に係る画像表示装置の逆γ処理部の入出力特性を示す図である。
【図１７】本発明の実施形態に係る画像表示装置のデータ配列変換部の構成を示すブロック図である。
【図１８】本発明の実施形態に係る画像表示装置の変調手段の構成及び動作を説明する図である。
【図１９】本発明の実施形態に係る画像表示装置の変調手段のタイミングチャートである。
【図２０】本発明の実施形態に係る画像表示装置の補正データ算出手段の構成を示すブロック図である。
【図２１】本発明の実施形態に係る画像表示装置の離散補正データ算出部の構成を示すブロック図である。
【図２２】本発明の実施形態の補正データ補間部の構成を示すブロック図である。
【図２３】本発明の実施形態の直線近似手段の構成を示すブロック図である。
【図２４】本発明の実施形態に係る画像表示装置のタイミングチャートである。
【図２５】本発明の実施形態のノードの設定する間隔について説明するための図である。
【図２６】従来の画像表示装置の構成を示すブロック図である。
【符号の説明】
１ 表示パネル
２ 走査回路
８ パルス幅変調手段
１２ 加算器
１４ 補正データ算出手段
１７ 逆γ処理部
１９ 遅延回路
１００ａ〜１００ｃ 点灯数カウント手段
１０１ａ〜１０１ｃ レジスタ群
１０３ テーブルメモリ
１１１ テーブルメモリ２
１０７ａ〜１０７ｃ コンパレータ
１２３〜１２４ デコーダ
１００１ 基板
１００２ 冷陰極素子
１００３ 行配線（走査配線）
１００４ 列配線（変調配線）
１００７ フェースプレート
１００８ 蛍光膜
２１２２ 加算器[0001]
BACKGROUND OF THE INVENTION
The present invention is an image display device provided with an element for forming an image such as an electron-emitting device wired in a matrix, and in particular, a fluorescent screen that emits light upon irradiation with an electron beam emitted from the image-forming device. The present invention relates to an image display device such as a television receiver or a display device that receives a television signal or a display signal from a computer or the like and displays an image by providing or emitting light by itself.
[0002]
[Prior art]
In order to correct the brightness drop due to voltage drop due to wiring resistance such as electrical connection wiring to the cold cathode element, the correction data is calculated by statistical calculation, and the electron beam required value and correction An image display apparatus having a configuration for combining values is disclosed in Japanese Patent Laid-Open No. 8-248920.
[0003]
The configuration of the image display device described in this publication is shown in FIG.
[0004]
The configuration related to the correction of data in this apparatus is roughly as follows.
[0005]
First, luminance data for one line of the digital image signal is added by the adder 208, and correction rate data corresponding to the added value is read from the memory 207.
[0006]
On the other hand, the digital image signal is serial / parallel converted in the shift register 204, held in the latch circuit 205 for a predetermined time, and then input to a multiplier 208 provided for each column wiring at a predetermined timing.
[0007]
The multiplier 208 multiplies the luminance data by the correction data read from the memory 207 for each column wiring, and the corrected data obtained is transferred to the modulation signal generator 209 and modulated corresponding to the corrected data. A signal is generated in the modulation signal generator 209, and an image is displayed on the display panel based on the modulation signal.
[0008]
Here, a statistical calculation process such as calculating the sum or average is performed on the digital image signal as in the summation process of luminance data for one line of the digital image signal in the adder 208, and this value is obtained. Based on the correction.
[0009]
[Problems to be solved by the invention]
However, the conventional configuration described above requires large-scale hardware such as a multiplier for each column wiring, a memory for outputting correction data, and a summer for supplying an address signal to the memory.
[0010]
The present invention has been made to solve the problems of the prior art, and the object of the present invention is to change the driving conditions due to the electric resistance of the matrix wiring of the display panel with less hardware than the conventional one. An object of the present invention is to provide an image display device capable of correcting the above.
[0011]
[Means for Solving the Problems]
  In order to achieve the above object, the present invention provides:The following configuration is adopted. An image display device comprising an image forming element arranged in a matrix, driven through a plurality of row wirings and column wirings and used for image formation, and scanning means for sequentially selecting and scanning the row wirings, Corresponding to the image data, corrected image data calculating means for calculating corrected image data for reducing at least the influence of voltage drop due to the resistance of the row wiring, and modulating means for outputting a modulation signal applied to the column wiring; The corrected image data calculation means uses a plurality of discrete values among the values of the image data as image data reference values, and a plurality of positions along the row wiring as reference positions. A corrected image data calculation unit corresponding to each reference position and calculating corrected image data for each image data reference value, and corresponding to a position other than the reference position. Corrected image data that is corrected image data and that is other than the image data reference value is calculated by interpolating corrected image data that is the corrected image data corresponding to the reference position and that corresponds to the image data reference value. A correction image data interpolating unit that performs the discrete correction image data calculation unit, a comparator that compares the image data and the image data reference value, and outputs the comparator to each of the reference positions. An adder for accumulating for each of a plurality of regions associated with each other, and the modulation means outputs the modulation signal based on the corrected image data calculated by the corrected image data interpolation unit An image display device characterized by that.
  An image display device comprising an image forming element arranged in a matrix, driven through a plurality of row wirings and column wirings and used for image formation, and scanning means for sequentially selecting and scanning the row wirings, Correction image data calculating means for calculating correction image data by performing correction to compensate for a decrease in luminance caused by a voltage drop due to a resistance of the row wiring, and a modulation signal applied to the column wiring Modulation means for outputting, wherein the corrected image data calculating means uses a plurality of discrete values among the values of the image data as image data reference values, and a plurality of values along the row wiring. A discrete corrected image data calculating unit that calculates corrected image data corresponding to each reference position and that is corrected image data corresponding to each reference position with the position as a reference position, and the reference position Corrected image data corresponding to an external position and corrected image data for image data other than the image data reference value is corrected image data corresponding to the reference position and corrected image for the image data reference value A corrected image data interpolation unit that calculates and interpolates data, and the discrete corrected image data calculation unit compares the image data with the image data reference value, and outputs the comparator An adder for integrating each of the plurality of regions associated with each of the reference positions, and the modulation means is based on the corrected image data calculated by the corrected image data interpolation unit. An image display device that outputs the modulation signal.
  The reference position is preferably located at a boundary between the plurality of regions or at a center of the plurality of regions.
  An image display device comprising an image forming element arranged in a matrix, driven through a plurality of row wirings and column wirings and used for image formation, and scanning means for sequentially selecting and scanning the row wirings, Corresponding to the image data, corrected image data calculating means for calculating corrected image data for reducing at least the influence of voltage drop due to the resistance of the row wiring, and modulating means for outputting a modulation signal applied to the column wiring; The corrected image data calculating means calculates discrete corrected image data by calculating a plurality of discrete values of the image data values as image data reference values and calculating corrected image data for the image data reference values. And corrected image data for calculating corrected image data for image data other than the image data reference value by interpolating the corrected image data for the image data reference value The discrete correction image data calculation unit includes a sum of light emission luminance amounts in each time region of one horizontal scanning period divided based on the image data reference value. Each time region is expanded so as to be the same as in the case where there is not, and the corrected image data is calculated by adding the expanded time, and the modulation means includes the corrected image data interpolation unit. The modulation signal is based on the calculated corrected image data. An image display device characterized by outputting a signal.
  An image display device comprising an image forming element arranged in a matrix, driven through a plurality of row wirings and column wirings and used for image formation, and scanning means for sequentially selecting and scanning the row wirings, Corresponding to the image data, corrected image data calculating means for calculating corrected image data for reducing at least the influence of voltage drop due to the resistance of the row wiring, and modulating means for outputting a modulation signal applied to the column wiring; The corrected image data calculating means calculates discrete corrected image data by calculating a plurality of discrete values of the image data values as image data reference values and calculating corrected image data for the image data reference values. And corrected image data for calculating corrected image data for image data other than the image data reference value by interpolating the corrected image data for the image data reference value The discrete corrected image data calculation unit emits light emission luminance amount emitted by the image forming element in a plurality of regions of the image data divided based on the image data reference value. Each area is expanded so as to be the same as the case where there is no voltage drop, and the corrected image data is calculated by adding the expanded data. An image display device that outputs the modulation signal based on the corrected image data calculated by an interpolation unit.
  An image display device comprising an image forming element arranged in a matrix, driven through a plurality of row wirings and column wirings and used for image formation, and scanning means for sequentially selecting and scanning the row wirings, Corresponding to the image data, at least correction data calculation means for calculating correction data for reducing the influence of a voltage drop due to the resistance of the row wiring, calculation means, and the column wiring based on the output of the calculation means Modulation means for outputting a modulation signal to be applied, wherein the correction data calculation means uses a plurality of discrete values among the values of the image data as image data reference values and follows the row wiring. A plurality of positions as reference positions, a discrete correction data calculation unit for calculating discrete correction data for each image data reference value at each reference position, and a position other than the reference position Correction data interpolation which is positive data and correction data for image data other than the image data reference value is correction data corresponding to the reference position and is calculated by interpolating the correction data for the image data reference value And the discrete correction data calculation unit includes a comparator that compares the image data with the image data reference value, and a plurality of outputs that are associated with each of the reference positions. And an adder for accumulating each area, wherein the calculation means calculates image data and the correction data calculated by the correction data interpolation unit.
  An image display device comprising an image forming element arranged in a matrix, driven through a plurality of row wirings and column wirings and used for image formation, and scanning means for sequentially selecting and scanning the row wirings, Correction data calculation means for calculating a correction data for compensating for a decrease in luminance caused by a voltage drop due to a resistance of the row wiring, calculation means corresponding to image data, calculation means, and the column based on the output of the calculation means Modulation means for outputting a modulation signal applied to the wiring, wherein the correction data calculation means uses a plurality of discrete values among the values of the image data as image data reference values, and the row wiring A discrete correction data calculation unit that calculates discrete correction data for each image data reference value at each reference position with a plurality of positions along the reference position as a reference position, and a position other than the reference position Correction data corresponding to the reference position, and correction data corresponding to the reference position and correction data calculated by interpolating the correction data for the image data reference value A data interpolation unit, and the discrete correction data calculation unit associates the image data with the image data reference value, and associates the output of the comparator with each of the reference positions. And an adder for accumulating for each of a plurality of regions, wherein the calculation means calculates image data and the correction data calculated by the correction data interpolation unit. .
  The arithmetic means is preferably an adder.
  The modulated signal is preferably a signal whose pulse width is modulated based on the image data.
  The image forming element is preferably an electron emitting element that emits electrons in accordance with the modulation signal.
  The electron-emitting device is preferably a surface conduction electron-emitting device.
  A control method for an image display device, which is arranged in a matrix and is driven through a plurality of row wirings and column wirings, and includes image forming elements used for image formation, and scanning means that sequentially selects and scans the row wirings. In accordance with the image data, a corrected image data calculating step for calculating corrected image data for reducing at least the influence of a voltage drop due to the resistance of the row wiring, and a modulation signal applied to the column wiring are output. A correction step, wherein the correction image data calculation step uses a plurality of discrete values among the values of the image data as image data reference values, and sets a plurality of positions along the row wiring. As a reference position, based on a value obtained by integrating the result of comparing the image data and the image data reference value for each of a plurality of regions associated with each of the reference positions, Calculating corrected image data for each image data reference value at the quasi-position, corrected image data corresponding to a position other than the reference position, and corrected image data for image data other than the image data reference value; Interpolating and calculating corrected image data corresponding to the reference position and the image data reference value, and in the modulating step, the step of calculating by interpolation A control method for an image display device, comprising: outputting the modulation signal based on the calculated corrected image data.
  A control method for an image display device, which is arranged in a matrix and is driven through a plurality of row wirings and column wirings, and includes image forming elements used for image formation, and scanning means that sequentially selects and scans the row wirings. A correction data calculating step for calculating correction data for reducing at least an influence of a voltage drop due to the resistance of the row wiring corresponding to the image data; a calculation step; and the output based on the output of the calculation step. A modulation step of outputting a modulation signal to be applied to the column wiring, wherein the correction data calculation step uses a plurality of discrete values among the values of the image data as image data reference values, and the row Using a plurality of positions along the wiring as reference positions, a result of comparing the image data and the image data reference value is associated with each of the reference positions. A step of calculating discrete correction data for each image data reference value at each reference position based on a value integrated for each area; correction data corresponding to a position other than the reference position; and the image data Calculating correction data for image data other than a reference value by correcting the correction data corresponding to the reference position and interpolating the correction data for the image data reference value. A method for controlling an image display device, comprising: calculating the image data and the correction data calculated in the interpolation calculation step.
[0047]
DETAILED DESCRIPTION OF THE INVENTION
Exemplary embodiments of the present invention will be described in detail below with reference to the drawings. However, the dimensions, materials, shapes, and relative arrangements of the components described in this embodiment should be appropriately changed according to the configuration of the apparatus to which the invention is applied and various conditions. It is not intended to limit the scope to the following embodiments.
[0048]
(First embodiment)
In the display device in which the electron-emitting devices are arranged in a simple matrix, in view of the phenomenon that a voltage drop occurs due to the current flowing into the scanning wiring and the wiring resistance of the scanning wiring, and the display image is deteriorated. The present invention relates to an image display apparatus including a processing circuit that corrects the influence of a voltage drop on a scanning wiring on a display image, and particularly realizes it with a relatively small circuit scale.
[0049]
The correction circuit according to the present embodiment calculates deterioration of a display image caused by a voltage drop according to input image data, obtains correction data for correcting the deterioration, and corrects the image data.
[0050]
As an image display device incorporating such a correction circuit, the present inventors have intensively studied an image display device of the following type.
[0051]
Hereinafter, in describing the present invention, an overview of a display panel of an image display device according to an embodiment of the present invention, electrical connection of the display panel, characteristics of a surface conduction electron-emitting device, a driving method of the display panel, and such After describing the mechanism for reducing the drive voltage due to the electrical resistance of the scanning wiring when displaying an image on a simple display panel, a correction method and apparatus for the influence of the voltage drop, which is a feature of the present invention, will be described.
[0052]
(Overview of image display device)
FIG. 1 is a perspective view of a display panel used in the image display apparatus according to the present embodiment, and a part of the panel is cut away to show the internal structure. In the figure, 1005 is a rear plate, 1006 is a side wall, and 1007 is a face plate, and 1005 to 1007 form an airtight container for maintaining the inside of the display panel in a vacuum.
[0053]
A substrate 1001 is fixed to the rear plate 1005, and N × M cold cathode devices 1002 are formed on the substrate. Row wiring (scanning wiring) 1003, column wiring (modulation wiring) 1004, and cold cathode elements (image forming elements) are connected as shown in FIG.
[0054]
Such a connection structure is called a simple matrix.
[0055]
A fluorescent film 1008 is formed on the lower surface of the face plate 1007. Since the image display device according to the present embodiment is a color display device, the phosphor film 1008 is coated with phosphors of three primary colors red, green, and blue used in the field of CRT. The phosphor is formed in a matrix corresponding to each pixel (picture element) on the rear plate so as to form a pixel at a position irradiated with emitted electrons (emitted current) from the cold cathode element. It is configured.
[0056]
A metal back 1009 is formed on the lower surface of the fluorescent film 1008.
[0057]
Hv is a high-voltage terminal and is electrically connected to the metal back. By applying a high voltage to the Hv terminal, a high voltage is applied between the rear plate and the face plate.
[0058]
In this embodiment, a surface conduction electron-emitting device was produced as a cold cathode device in the display panel as described above. A field emission type element can also be used as the cold cathode element. The present invention can also be applied to an image display device that is driven by connecting an element that emits light such as an EL element other than a cold cathode element to a matrix wiring.
[0059]
(Characteristics of surface conduction electron-emitting devices)
The surface conduction electron-emitting device has (emitter current Ie) vs. (device applied voltage Vf) characteristics and (device current If) vs. (device applied voltage Vf) characteristics as shown in FIG. Since the emission current Ie is remarkably smaller than the device current If and it is difficult to illustrate on the same scale, the two graphs are illustrated on different scales.
[0060]
The surface conduction electron-emitting device has the following three characteristics with respect to the emission current Ie.
[0061]
First, when a voltage higher than a certain voltage (referred to as a threshold voltage Vth) is applied to the device, the emission current Ie increases rapidly. On the other hand, the emission current Ie is hardly detected at a voltage lower than the threshold voltage Vth.
[0062]
That is, it is a nonlinear element having a clear threshold voltage Vth with respect to the emission current Ie.
[0063]
Second, since the emission current Ie changes depending on the voltage Vf applied to the element, the magnitude of the emission current Ie can be controlled by varying the voltage Vf.
[0064]
Thirdly, since the cold cathode device has high-speed response, the emission time of the emission current Ie can be controlled by the application time of the voltage Vf.
[0065]
By utilizing the above characteristics, the surface conduction electron-emitting device can be suitably used for a display device.
[0066]
For example, in the image display apparatus using the display panel shown in FIG. 1, if the first characteristic is used, it is possible to display by sequentially scanning the display screen. That is, a voltage equal to or higher than the threshold voltage Vth is appropriately applied to the driven element according to the desired light emission luminance, and a voltage lower than the threshold voltage Vth is applied to the non-selected element. By sequentially switching the elements to be driven, it is possible to perform display by sequentially scanning the display screen.
[0067]
Further, by utilizing the second characteristic, the light emission luminance of the phosphor can be controlled by the voltage Vf applied to the element, and image display can be performed.
[0068]
Further, by utilizing the third characteristic, the light emission time of the phosphor can be controlled by the time during which the voltage Vf is applied to the element, and an image can be displayed.
[0069]
In the image display device of this embodiment, the amount of the electron beam of the display panel is modulated using the third characteristic.
[0070]
(Display panel drive method)
The method for driving the display panel of the present invention will be specifically described with reference to FIG.
[0071]
FIG. 4 shows an example of voltages applied to the voltage supply terminals of the scanning wiring and the modulation wiring when the display panel of the present invention is driven.
[0072]
Now, the horizontal scanning period I is a period during which the pixels in the i-th row emit light.
[0073]
In order to cause the pixels in the i-th row to emit light, the scanning wiring in the i-th row is set in a selected state, and the selection potential Vs is applied to the voltage supply terminal Dxi. Further, the voltage supply terminals Dxk (k = 1, 2,... N, where k ≠ i) of the other scanning wirings are set in a non-selected state, and a non-selection potential Vns is applied.
[0074]
In this example, the selection potential Vs is set to the voltage V shown in FIG._SELHalf of -0.5V_SELThe non-selection potential Vns was set to the GND potential.
[0075]
A pulse width modulation signal having a voltage amplitude Vpwm was supplied to the voltage supply terminal of the modulation wiring. Conventionally, the pulse width of the pulse width modulation signal supplied to the j-th modulation wiring is determined according to the size of the image data of the pixel in the i-th row and j-th column of the image to be displayed unless correction is performed, A pulse width modulation signal corresponding to the size of image data of each pixel is supplied to all the modulation wirings.
[0076]
In this embodiment, as will be described later, the pulse width of the pulse width modulation signal supplied to the j-th modulation wiring in order to correct the decrease in luminance due to the influence of the voltage drop is the first of the image to be displayed. The pulse width modulation signal is supplied to all the modulation wirings according to the size of the image data of the pixel in the i-th row and the j-th column and the correction amount.
[0077]
In this embodiment, the voltage Vpwm is + 0.5V._SELSet to.
[0078]
The surface conduction electron-emitting device has a voltage V V across the device as shown in FIG._SELIs applied, electrons are emitted, but no electrons are emitted when the applied voltage is lower than Vth.
[0079]
The voltage Vth is 0.5 V as shown in FIG._SELThere is a feature that is larger than.
[0080]
For this reason, electrons are not emitted from the surface conduction electron-emitting device connected to the scanning wiring to which the non-selection potential Vns is applied.
[0081]
Similarly, a period in which the output of the pulse width modulation means is a ground potential (hereinafter referred to as an “L” period) is applied to both ends of the surface conduction electron-emitting device on the selected scanning wiring. Since the voltage is Vs, no electrons are emitted.
[0082]
Electrons are emitted from the surface conduction electron-emitting devices on the scanning wiring to which the selection potential Vs is applied in accordance with a period in which the output of the pulse width modulation means is Vpwm (hereinafter referred to as an “H” period). The When electrons are emitted, the above-described phosphor emits light according to the amount of the emitted electron beam, so that it is possible to emit luminance corresponding to the emitted time.
[0083]
The image display apparatus according to the present embodiment also displays an image by line-sequential scanning and pulse width modulation of such a display panel.
[0084]
(Voltage drop in scanning wiring)
As described above, the fundamental problem of the present invention is that the voltage applied to the surface conduction electron-emitting device decreases because the potential on the scan line increases due to the voltage drop in the scan line of the display panel. The emission current from the surface conduction electron-emitting device is reduced. Hereinafter, this voltage drop mechanism will be described.
[0085]
Although it depends on the design specifications and manufacturing method of the surface conduction electron-emitting device, the device current for one element of the surface conduction electron-emitting device is the voltage V_SELIs about several hundreds of μA.
[0086]
For this reason, when only one pixel on the selected scanning line is caused to emit light during a certain horizontal scanning period and the other pixels are not allowed to emit light, the element current flowing from the modulation wiring into the scanning wiring of the selected row is equivalent to one pixel. Since there is only a current (that is, the above-mentioned several hundreds of μA), a voltage drop hardly occurs and the light emission luminance does not decrease.
[0087]
However, when all the pixels in the selected row are caused to emit light in a certain horizontal scanning period, the current for all pixels flows from all the modulation wirings to the scanning wiring in the selected state. 100 mA to several A, and a voltage drop occurred on the scanning wiring due to the wiring resistance of the scanning wiring.
[0088]
If a voltage drop occurs on the scanning wiring, the voltage applied to both ends of the surface conduction electron-emitting device decreases. For this reason, the emission current emitted from the surface conduction electron-emitting device is lowered, and as a result, the light emission luminance is lowered.
[0089]
Specifically, consider a case where a white cross-shaped pattern is displayed on a black background as shown in FIG.
[0090]
Then, when driving the row L in the figure, since the number of lit pixels is small, almost no voltage drop occurs on the scanning wiring of the row. As a result, a desired amount of emission current is emitted from the surface conduction electron-emitting device of each pixel, and light can be emitted with a desired luminance.
[0091]
On the other hand, when driving the row L 'in the figure, since all the pixels are turned on at the same time, a voltage drop occurs on the scanning wiring, and the emission current from the surface conduction electron-emitting device of each pixel decreases. As a result, the luminance is reduced in the line L ′.
[0092]
As described above, since the influence of the voltage drop changes due to the difference in the image data for each horizontal line, when displaying the cross pattern as shown in FIG. 5A, the image as shown in FIG. Has been displayed.
[0093]
Note that this phenomenon is not limited to the cross pattern, and also occurs when, for example, a window pattern or a natural image is displayed.
[0094]
Further, more complicatedly, the magnitude of the voltage drop has a property of changing even during one horizontal scanning period by performing modulation by pulse width modulation.
[0095]
When the pulse width modulation signal supplied to each column outputs a pulse width modulation signal whose rise is synchronized with the input data as shown in FIG. Depending on the input image data, in general, the number of pixels that are lit is large at the beginning of one horizontal scanning period, and then the pixels are turned off in order from the lower luminance. In one horizontal scanning period, it decreases with time.
[0096]
Therefore, the magnitude of the voltage drop generated on the scanning wiring also tends to decrease gradually as the beginning of one horizontal scanning period.
[0097]
Since the output of the pulse width modulation signal changes every time corresponding to one gradation of modulation, the temporal change in voltage drop also changes every time corresponding to one gradation of the pulse width modulation signal.
[0098]
The voltage drop in the scanning wiring, which is the fundamental problem of the present invention, has been described above.
[0099]
Next, how to correct the influence of the voltage drop, which is a feature of the present invention, will be described in detail.
[0100]
(Voltage drop calculation method)
In order to obtain a correction amount for reducing the influence of the voltage drop, the present inventors first develop hardware that predicts the magnitude of the voltage drop and its time change in real time as the first step. I thought it was necessary.
[0101]
However, a display panel of an image display apparatus such as the present invention generally has thousands of modulation wirings, and it is very difficult to calculate the voltage drop at the intersection of all the modulation wirings and the scanning wiring. It was difficult to make hardware that calculates it in real time.
[0102]
On the other hand, as a result of investigation of the voltage drop by the present inventors, it has been found that there are the following characteristics.
[0103]
i) At a certain point in one horizontal scanning period, the voltage drop generated on the scanning wiring is a spatially continuous amount on the scanning wiring and is a very smooth curve.
[0104]
ii) Although the magnitude of the voltage drop varies depending on the display image, it varies with time corresponding to one gradation of pulse width modulation, but is roughly larger at the rising edge of the pulse and gradually smaller in time. Either, or keep its size. That is, in the driving method as shown in FIG. 4, the magnitude of the voltage drop does not increase in one horizontal scanning period.
[0105]
In view of the above-described characteristics, the present inventors have examined whether the amount of calculation can be reduced by performing calculation by simplifying the following approximate model.
[0106]
First, from the feature of i), when calculating the magnitude of the voltage drop at a certain time, it is approximately simplified by a degenerate model in which thousands of modulation wirings are concentrated on several to tens of modulation wirings. (This will be explained in detail in the calculation of the voltage drop using the degenerate model below).
[0107]
In addition, from the characteristics listed in ii), a plurality of times are provided in one horizontal scanning period, and the time change of the voltage drop is roughly predicted by calculating the voltage drop for each time.
[0108]
More specifically, the voltage change over time was roughly predicted by calculating the voltage drop based on the degenerate model described below for a plurality of times.
[0109]
(Calculation of voltage drop by degenerate model)
FIG. 6A is a diagram for explaining blocks and nodes when performing degeneration according to the present invention.
[0110]
In order to simplify the drawing, only the selected scanning wiring, each modulation wiring, and the surface conduction electron-emitting device connected to the intersection thereof are shown in FIG.
[0111]
Now, at a certain time in one horizontal scanning period, the lighting state of each pixel on the selected scanning wiring (that is, whether the output of the modulation means is “H” or “L”) is known. It shall be.
[0112]
In this lighting state, an element current flowing from each modulation wiring to the selected scanning wiring is defined as Ifi (i = 1, 2,... N, i is a column number).
[0113]
Further, as shown in the figure, a block is defined with a group of n-conducting wiring lines and a portion of the selected scanning wiring line that intersects with the surface conduction electron-emitting devices arranged at the intersections. In this example, the block is divided into four blocks.
[0114]
In addition, a position called a node is set at the boundary position of each block. The node is a horizontal position (reference point) for discretely calculating a voltage drop amount generated on the scanning wiring in the degenerate model. Here, the divided blocks are constituted by surface conduction electron-emitting devices connected to the region of the scanning wiring divided by the nodes (reference points).
[0115]
In this example, five nodes of node 0 to node 4 are set at the block boundary positions.
[0116]
FIG. 6B is a diagram for explaining the degenerate model.
[0117]
In the degenerate model, n modulation wirings included in one block in FIG. 1A are reduced to one and connected so that they are located at the center of the scanning wiring block.
[0118]
In addition, a current source is connected to the centralized modulation wiring of each block, and the total current (statistics) IF0 to IF3 in each block flows from each current source.
[0119]
That is, IFj (j = 0, 1,... 3) is
[Expression 1]

Is expressed as
[0120]
In addition, the potential at both ends of the scanning wiring is Vs in the example of FIG. 9A, whereas the GND potential in FIG. 10B is the GND potential. In the degenerate model, it flows into the scanning wiring selected from the modulation wiring. This is because the voltage drop amount of each part on the scanning wiring can be calculated by calculating the voltage (potential difference) of each part using the power supply part as a reference potential by modeling the current with the current source.
[0121]
In addition, the surface conduction electron-emitting device is omitted if the equivalent current flows from the column wiring when viewed from the selected scanning wiring, regardless of the presence of the surface conduction electron-emitting device. This is because the voltage drop itself does not change. Therefore, here, the surface conduction electron-emitting device is omitted by setting the current value flowing from the current source of each block to the total current value (Equation 1) of the device currents in each block.
[0122]
In addition, the wiring resistance of the scanning wiring of each block is set to n times the wiring resistance r of the scanning wiring in one section (here, one section is the intersection of the scanning wiring with a certain column wiring and the adjacent column wiring. (In this example, the wiring resistance of the scanning wiring in one section is assumed to be uniform.)
[0123]
In such a degenerate model, the voltage drop amounts DV0 to DV4 generated at each node on the scanning wiring can be easily calculated by the following product-sum formula.
[Expression 2]

That is,
[Equation 3]

However, aij is a voltage generated at the i-th node when a unit current is injected only into the j-th block in the degenerate model (hereinafter, this is defined as aij).
[0124]
The above aij can be easily derived from Kirchhoff's law as follows.
[0125]
That is, in FIG. 6B, the wiring resistance to the left supply terminal of the scanning wiring viewed from the current source of the block i is rli (i = 0, 1, 2, 3, 4), and the wiring to the right supply terminal. The resistance is defined as ri (i = 0, 1, 2, 3, 4), the wiring resistance between block 0 and the left supply terminal, and the wiring resistance between block 4 and the right supply terminal are all defined as rt. if,
[Expression 4]

further,
[Equation 5]

Aij is
[Formula 6]

It can be easily derived as follows. However, in Expression 3, A // B is a symbol representing the parallel resistance value of the resistor A and the resistor B, and A // B = A × B / (A + B).
[0126]
Even if the number of blocks is not 4, Equation 2 can be easily calculated according to Kirchhoff's law, taking into account the definition of aij. Even in the case where only one side is not provided on both sides of the scanning wiring as in this example, it can be easily calculated by calculating according to the definition of aij.
[0127]
Note that the parameter aij defined by Equation 3 does not need to be recalculated every time it is calculated, but may be calculated once and stored as a table.
[0128]
Further, approximation as in Expression 4 was performed on the total current IF0 to IF3 of each block defined in Expression 1.
[0129]
[Expression 7]

However, in the above equation, “County” is a variable that takes 1 when the i-th pixel on the selected scanning line is in a lighting state, and takes 0 when it is in a light-off state.
[0130]
The IFS has a voltage V across the surface conduction electron-emitting device._SELIs an amount obtained by multiplying the element current IF flowing when a current is applied by a coefficient α taking a value between 0 and 1.
[0131]
That is,
[Equation 8]

It was defined as
[0132]
Equation 4 assumes that an element current proportional to the number of lighting in the block flows from the column wiring of each block into the selected scanning wiring. At this time, the element current IF of one element multiplied by the coefficient α is used as the element current IFS of one element for the following reason.
[0133]
Originally, in order to calculate the voltage drop amount, it is necessary to repeatedly calculate the voltage rise of the scanning wiring due to the voltage drop and the decrease amount of the element current due to this, but this convergence calculation is calculated by hardware. Is not realistic. Therefore, in the present invention, αIF is approximately used as the convergence value of IF. Specifically, the IF reduction rate (= α1) when the voltage drop amount is the maximum (when all white), and the IF reduction rate (= α2) when the voltage drop amount is (minimum = 0). ) Is estimated in advance, and is obtained as an average value of α1 and α2 or 0.8 × α1.
[0134]
FIG. 6C is an example of a result of calculating the voltage drop amounts DV0 to DV4 of each node using a degenerate model in a certain lighting state.
[0135]
Since the voltage drop becomes a very smooth curve, it is assumed that the voltage drop between the nodes is approximately the value shown by the dotted line in the figure.
[0136]
In this way, by using this degenerate model, it is possible to calculate a voltage drop for each node at a desired time point for arbitrary image data.
[0137]
As described above, the voltage drop amount in a certain lighting state is simply calculated using the degenerate model.
[0138]
The voltage drop generated on the selected scanning wiring changes with time within one horizontal scanning period, and as described above, with respect to several times (reference time) during one horizontal scanning period, The lighting state at that time was obtained and predicted by calculating the voltage drop for the lighting state using a degenerate model.
[0139]
Note that the number of lighting in each block at a certain point in one horizontal scanning period can be easily obtained by referring to the image data of each block.
[0140]
As an example, assume that the number of bits of input data to the pulse width modulation circuit is 8 bits, and the pulse width modulation circuit outputs a pulse width linear with respect to the size of the input data.
[0141]
That is, when the input data is 0, the output is “L”, when the input data is 255, “H” is output during one horizontal scanning period, and when the input data is 128, the output is the first in one horizontal scanning period. It is assumed that “H” is output during the half period and “L” is output during the latter half period.
[0142]
In such a case, the number of lighting at the time (start time) when the pulse width modulation signal rises can be easily detected by counting the number of input data larger than 0 to the pulse width modulation circuit.
[0143]
Similarly, the number of lighting at the center of one horizontal scanning period can be easily detected by counting the number of input data to the pulse width modulation circuit that is greater than 128.
[0144]
Thus, if the image data is compared with respect to a certain threshold and the number of outputs of the comparator being true is counted, the number of lightings at an arbitrary time can be easily calculated.
[0145]
Here, in order to simplify the following explanation, an amount of time called a time slot is defined.
[0146]
That is, the time slot represents the time from the rising edge of the pulse width modulation signal in one horizontal scanning period, and the time slot = 0 represents the time immediately after the start time (rising edge in this case) of the pulse width modulation signal. It is defined to represent.
[0147]
Time slot = 64 is defined as representing the time when 64 gradations have elapsed from the start time of the pulse width modulation signal.
[0148]
Similarly, time slot = 128 is defined as representing the time when 128 gradations have elapsed from the start time of the pulse width modulation signal.
[0149]
In this example, the pulse width modulation is shown by using the rise time as a reference, and the pulse width is modulated from the rise time, but similarly, even when the pulse width is modulated using the pulse fall time as a reference, The direction in which the axis advances and the direction in which the time slot advances are opposite, but it goes without saying that the same applies.
[0150]
(Calculation of correction data from voltage drop)
As described above, the time change of the voltage drop during one horizontal scanning period can be calculated approximately and discretely by repeatedly calculating using the degenerate model.
[0151]
FIG. 7 shows an example in which the voltage drop is repeatedly calculated for a certain image data, and the time change of the voltage drop in the scanning wiring is calculated.
(The voltage drop and its time change shown here are examples for one image data, and it is natural that the voltage drop for another image data will make another change.)
[0152]
In the figure, the voltage drop at each time is discretely calculated by applying the degenerate model to each of the four time points of time slots = 0, 64, 128, and 192.
[0153]
In FIG. 7, the amount of voltage drop at each node is connected by a dotted line, but the dotted line is shown for easy understanding of the figure, and the voltage drop calculated by this degenerate model is indicated by □, ○, △. It was calculated discretely at the position of each node.
[0154]
The present inventors examined a method for calculating correction data for correcting image data from a voltage drop amount as the next stage in which the magnitude of the voltage drop and its time change can be calculated.
[0155]
FIG. 8 is a graph in which the emission current emitted from the surface conduction electron-emitting device in the lighting state is estimated when the voltage drop shown in FIG. 7 occurs on the selected scanning wiring.
[0156]
The vertical axis represents the amount of emission current at each position in percentage with the magnitude of the emission current emitted when there is no voltage drop as 100%, and the horizontal axis represents the horizontal position.
[0157]
As shown in FIG. 8, at the horizontal position (reference point) of node 2,
The emission current when time slot = 0 is Ie0,
The emission current at time slot = 64 is Ie1,
The emission current at time slot = 128 is Ie2,
The emission current when the time slot is 192 is Ie3
And
[0158]
This figure was calculated from the voltage drop amount of FIG. 7 and the graph of “driving voltage versus emission current” of FIG. Specifically, voltage V_SELThe value of the emission current when a voltage obtained by subtracting the amount of voltage drop from is applied is simply mechanically plotted.
[0159]
Therefore, this figure only means the current emitted from the surface conduction electron-emitting device in the lit state, and the surface conduction electron-emitting device in the unlit state does not emit current.
[0160]
A method for calculating correction data for correcting image data from the voltage drop amount will be described below.
[0161]
FIGS. 9A, 9B, and 9C are diagrams for explaining a method for calculating correction data of the voltage drop amount from the time change of the emission current of FIG. The figure shows an example of calculating correction data for image data having a size of 64.
[0162]
The amount of light emission with brightness is nothing but the amount of emitted charge obtained by temporally integrating the emission current caused by the emission current pulse. Therefore, in the following, the description will be made based on the amount of emitted charges when considering the variation in luminance due to the voltage drop.
[0163]
If the emission current when there is no voltage drop effect is IE and the time corresponding to one gradation of the pulse width modulation is Δt, the emission to be emitted by the emission current pulse when the image data is 64 The charge amount Q0 is obtained by multiplying the amplitude IE of the emission current pulse by the pulse width (64 × Δt),
[Equation 9]

Can be represented as:
[0164]
However, in practice, a phenomenon occurs in which the emission current decreases due to a voltage drop on the scanning wiring.
[0165]
The amount of charge emitted by the emission current pulse considering the influence of the voltage drop can be approximately calculated as follows.
[0166]
That is, if the emission currents at time slot = 0 and 64 of node 2 are set to Ie0 and Ie1, respectively, and the emission current between 0 and 64 is approximated to change linearly between Ie0 and Ie1, the emission during this period The amount of charge Q1 is the area of the trapezoid in FIG.
[Expression 10]

Can be calculated as
[0167]
Next, as shown in FIG. 9C, it is assumed that the influence of the voltage drop can be removed when the pulse width is increased by DC1 in order to correct the decrease in the emission current due to the voltage drop.
[0168]
Further, when the voltage drop is corrected and the pulse width is increased, the amount of emission current in each time slot is considered to change, but here, for simplicity, as shown in FIG. When = 0, the emission current is Ie0, and the emission current at time slot = (64 + DC1) is Ie1.
[0169]
Further, the emission current between the time slot 0 and the time slot (64 + DC1) is approximated to take a value on a line obtained by connecting two emission currents with a straight line.
[0170]
Then, the emission charge amount Q2 due to the emission current pulse after correction is
## EQU11 ##

Can be calculated as
[0171]
If this is equal to the aforementioned Q0,
[Expression 12]

Solving this for DC1,
[Formula 13]

It becomes.
[0172]
In this way, correction data when the image data is 64 was calculated.
[0173]
That is, the correction amount may be added by CData = DC1 for the image data at the position of the node 2 having a size of 64 as described in Expression 9.
[0174]
FIG. 10 shows an example in which correction data for image data having a size of 128 is calculated from the calculated voltage drop amount.
[0175]
Now, when there is no influence of the voltage drop, when the image data is 128, the emission charge amount Q3 released by the emission current pulse is
[Expression 14]

On the other hand, the input charge amount due to the actual emission current pulse affected by the voltage drop can be approximately calculated as follows.
[0176]
That is, the emission current amounts of time slot = 0, 64, and 128 of node 2 are Ie0, Ie1, and Ie2, respectively. Further, the emission current between 0 and 64 changes linearly between Ie0 and Ie1, and between 64 and 128 is 0 when approximated to change on a line connecting Ie1 and Ie2 with a straight line. The amount of charge Q4 emitted during the time slots from ˜128 is the sum of the areas of the two trapezoids in FIG.
[Expression 15]

Can be calculated as
[0177]
On the other hand, the correction amount of the voltage drop was calculated as follows.
[0178]
A period corresponding to time slots 0 to 64 is defined as period 1, and a period corresponding to 64 to 128 is defined as period 2.
[0179]
When correction is performed, it is considered that the period 1 portion is extended by DC1 and extended to the period 1 ', and the period 2 portion is extended by DC2 and extended to the period 2'.
[0180]
At this time, it is assumed that the amount of emitted charges becomes the same as the above-described Q0 by performing correction during each period.
[0181]
In addition, it goes without saying that the emission current at the beginning and end of each period changes as a result of correction, but here it is assumed that it does not change in order to simplify the calculation.
[0182]
That is, the emission current at the beginning of period 1 ′ is Ie0, the emission current at the end of period 1 ′ is Ie1, the emission current at the beginning of period 2 ′ is Ie1, and the emission current at the end of period 2 ′ is Ie2. To do.
[0183]
Then, DC1 can be calculated in the same manner as Equation 9.
[0184]
DC2 is based on the same concept.
[Expression 16]

Can be calculated as
[0185]
As a result, for image data with a node 2 position size of 128,
[Expression 17]

It is sufficient to add the correction amount CData.
[0186]
FIG. 11 shows an example in which correction data for image data having a size of 192 is calculated from the calculated voltage drop amount.
[0187]
Now, the emission charge amount Q5 due to the emission current pulse expected when the image data is 192 is
[Expression 18]

On the other hand, the amount of charge emitted by the actual emission current pulse affected by the voltage drop can be approximately calculated as follows.
[0188]
That is, the emission current at node 2 time slot = 0 is Ie0, the emission current at time slot = 64 is Ie1, the emission current at time slot = 128 is Ie2, and the emission current at time slot = 192. Ie3, the emission current between 0 and 64 changes linearly between Ie0 and Ie1, between 64 and 128 changes on the line connecting Ie1 and Ie2 with a straight line, and between 128 and 192 If the interval is approximated to change on a line connecting Ie2 and Ie3 with a straight line, the input charge amount Q6 during the time slot from 0 to 192 is the area of the three trapezoids in FIG. ,
[Equation 19]

Can be calculated as
[0189]
On the other hand, the correction amount of the voltage drop was calculated as follows.
[0190]
A period corresponding to time slots 0 to 64 is defined as period 1, a period corresponding to 64 to 128 is defined as period 2, and a period corresponding to 128 to 192 is defined as period 3.
[0191]
As before, after the correction, the period 1 part is extended by DC1 and extended to period 1 ', the period 2 part is extended by DC2 and extended to period 2', and the period 3 part is It is assumed that it extends by DC3 and is extended to period 3 ′.
[0192]
At this time, it is assumed that the amount of emitted charges becomes the same as the above-described Q0 by performing correction during each period.
[0193]
It was also assumed that the emission current at the beginning and end of each period did not change before and after correction.
[0194]
That is, the emission current at the beginning of period 1 ′ is Ie0, the emission current at the end of period 1 ′ is Ie1, the emission current at the beginning of period 2 ′ is Ie1, the emission current at the end of period 2 ′ is Ie2, and period 3 It is assumed that the first emission current of “Ie3” and the emission current at the end of period 3 ′ are Ie4.
[0195]
Then, DC1 and DC2 can be calculated in the same manner as Equations 9 and 12, respectively.
[0196]
For DC3,
[Expression 20]

Can be calculated as
[0197]
As a result, the correction data CData to be added to the image data having the position of the node 2 of 192 is as follows:
[Expression 21]

Should be added.
[0198]
As described above, the correction data CDdata of the image data 64, 128, and 192 with respect to the position of the node 2 was calculated.
[0199]
When the pulse width is 0, naturally, there is no influence of the voltage drop on the emission current, so that the correction data is 0 and the correction data CData added to the image data is also 0.
[0200]
In this way, the correction data is calculated for the discrete image data such as 0, 64, 128, and 192 in order to reduce the calculation amount.
[0201]
That is, if the same calculation is performed for all arbitrary image data, the amount of calculation becomes very large, and the amount of hardware for performing the calculation becomes very large.
[0202]
On the other hand, at a certain node position, the correction data tends to increase as the image data increases. As a result, when calculating correction data for arbitrary image data, the amount of calculation can be greatly reduced by interpolating the points where correction data has already been calculated in the vicinity of the image data by linear approximation. It is because it can do. This interpolation will be described in detail when the discrete correction data interpolation unit is described.
[0203]
Further, if the same idea is applied to the positions of all nodes, correction data of image data = 0, 64, 128, and 192 at the positions of all nodes can be calculated.
[0204]
In this example, four image data of 0, 64, 128, and 192 are calculated by applying the degeneracy model to four points of time slots of 0, 64, 128, and 192 and calculating the voltage drop amount at each time. Correction data for the reference value could be obtained.
[0205]
However, preferably, as described above, the time interval for calculating the voltage drop is reduced by the degenerate model, and by taking more reference values of the image data, the time change of the voltage drop can be handled more precisely, and the approximation Calculation errors can be reduced.
[0206]
In this case, calculation may be performed by transforming Equations 6 to 16 based on the same concept.
[0207]
According to the above-described method, correction data for image data = 0, 64, 128, and 192 at each node position was discretely calculated for certain input data.
[0208]
An example of discrete correction data for a certain input image data obtained by this method is shown in FIG. In the figure, the horizontal axis corresponds to the horizontal display position, and the position of each node is described. The vertical axis represents the size of the correction data.
[0209]
The discrete correction data is calculated with respect to the position of the node and the size of the image data Data (image data reference value = 0, 64, 128, 192) indicated by □, ○, ●, △ in the figure. is there.
[0210]
(Interpolation method for discrete correction data)
The correction data calculated discretely is discrete with respect to the position of each node, and does not give correction data at an arbitrary horizontal position (column wiring number). At the same time, it is correction data for image data having a predetermined reference value size of image data at each node position, and does not provide correction data according to the actual image data size. .
[0211]
Therefore, the inventors calculated correction data obtained by discretely calculating correction data suitable for the size of input image data in each column wiring by interpolating the correction data.
[0212]
FIG. 12B is a diagram showing a method for calculating correction data corresponding to the image data Data at a position x located between the node n and the node n + 1.
[0213]
As a premise, it is assumed that the correction data has already been discretely calculated at the positions Xn and Xn + 1 of the nodes n and n + 1.
[0214]
Data that is input image data takes a value between two image data reference values Dk and Dk + 1 for which correction data has already been calculated discretely.
[0215]
Now, if the correction data for the reference value Dk of the k-th image data of the node n is expressed as CDdata [k] [n], the correction data CA for the image data Dk at the position x is CDdata [k] [n]. And the value of CData [k] [n + 1] can be calculated as follows by linear approximation.
[Expression 22]

[0216]
Further, the correction data CB of the image data Dk + 1 at the position x can be calculated as follows.
[Expression 23]

[0217]
By linearly approximating the correction data of CA and CB, the correction data CD for the image data Data at the position x can be calculated as follows.
[Expression 24]

[0218]
As described above, in order to calculate the correction data suitable for the actual position and the size of the image data from the discrete correction data, it can be easily calculated by the method described in Expression 17 to Expression 19.
[0219]
If the correction data calculated in this way is added to the image data to correct the image data, and pulse width modulation is performed according to the corrected image data, the image quality degradation due to the voltage drop, which has been a problem in the past, has been reduced. The image quality can be reduced and the image quality can be improved.
[0220]
In addition, the hardware for correction, which has been a problem for some time, can be reduced by introducing the approximation such as degeneration as explained so far. There was an excellent merit that it can be configured with.
[0221]
(Explanation of functions of the entire system and each part)
Next, the hardware of an image display device incorporating correction data calculation means will be described.
[0222]
FIG. 13 is a block diagram showing an outline of the circuit configuration. In the figure, 1 is the display panel of FIG. 1, Dx1 to DxM and Dx1 ′ to DxM ′ are voltage supply terminals of the scanning wiring of the display panel, Dy1 to DyN are voltage supply terminals of the modulation wiring of the display panel, and Hv is the face plate and the rear. A high voltage supply terminal for applying an acceleration voltage between the plates, Va is a high voltage power source, 2 is a scanning circuit (scanning means), 3 is a synchronization signal separation circuit, 4 is a timing generation circuit, 7 is YPbPr by the synchronization separation circuit 3 A conversion circuit for converting the signal into RGB, 17 is an inverse γ processing unit, 5 is a shift register for one line of image data, 6 is a latch circuit for one line of image data, and 8 is a modulation signal on the modulation wiring of the display panel. Is a pulse width modulation means (modulation means), 12 is an adder (arithmetic processing means, addition processing means), and 14 is a correction data calculation means.
[0223]
In the same figure, R, G, and B are RGB parallel input video data, Ra, Ga, and Ba are RGB parallel video data that has been subjected to inverse γ conversion processing to be described later, and Data is parallel / serial converted by a data array conversion unit. The corrected image data, CD is the correction data calculated by the correction data calculation means, and Dout is the image data corrected by adding the correction data to the image data by the adder.
[0224]
(Synchronous separation circuit, timing generation circuit)
The image display apparatus according to the present embodiment can display both television signals such as NTSC, PAL, SECAM, and HDTV, and VGA that is an output of a computer.
[0225]
In FIG. 13, only the HDTV system is described to simplify the drawing.
[0226]
For the HDTV video signal, first, the synchronization signals Vsync and Hsync are separated by the three synchronization separation circuits and supplied to the timing generation circuit. The synchronized and separated video signal is supplied to the RGB conversion means. In addition to the conversion circuit from YPbPr to RGB, a low-pass filter (not shown), an A / D converter, and the like are provided inside the RGB conversion means, which converts YPbPr into a digital RGB signal and performs inverse γ processing. Supply to the department.
[0227]
(Timing generation circuit)
The timing generation circuit includes a PLL circuit, generates a timing signal synchronized with a synchronization signal of various video sources, and generates an operation timing signal for each unit.
[0228]
The timing signal generated by the timing generation circuit 4 includes Tsft for controlling the operation timing of the shift register 5, a control signal Dataload for latching data from the shift register to the latch circuit 6, and a pulse width modulation start signal for the modulation means 8. Pwmstart, clock Pwmclk for pulse width modulation, Tscan for controlling the operation of the scanning circuit 2, and the like.
[0229]
(Scanning circuit)
The scanning circuits 2 and 2 ′ are circuits that output the selection potential Vs or the non-selection potential Vns to the connection terminals Dx1 to DxM in order to sequentially scan the display panel row by row in one horizontal scanning period (FIG. 14). ).
[0230]
The scanning circuits 2 and 2 ′ are circuits that perform scanning by sequentially switching the selected scanning wiring for each horizontal period in synchronization with the timing signal Tscan from the timing generation circuit 4.
[0231]
Tscan is a timing signal group generated from a vertical synchronization signal, a horizontal synchronization signal, and the like.
[0232]
Each of the scanning circuits 2 and 2 'includes M switches and a shift register as shown in FIG. These switches are preferably composed of transistors and FETs.
[0233]
In order to reduce a voltage drop in the scanning wiring, the scanning circuit is preferably connected to both ends of the scanning wiring of the display panel and driven from both ends as shown in FIG.
[0234]
On the other hand, the present invention is effective even when the scanning circuit is not connected to both ends of the scanning wiring, and can be applied only by changing the parameter of Equation 3.
[0235]
(Reverse γ processing part)
The CRT has a light emission characteristic (hereinafter referred to as an inverse γ characteristic) of approximately 2.2 to the input.
[0236]
The input video signal considers such characteristics of the CRT, and is generally converted in accordance with a γ characteristic of the power of 0.45 so as to have a linear light emission characteristic when displayed on the CRT.
[0237]
On the other hand, when the display panel of the image display apparatus according to the present embodiment modulates according to the application time of the drive voltage, the display panel has a light emission characteristic that is almost linear with respect to the length of the application time. It is necessary to perform conversion based on the above (hereinafter referred to as inverse γ conversion).
[0238]
The inverse γ processing unit described in FIG. 13 is a block for performing inverse γ conversion on an input video signal.
[0239]
The inverse γ processing unit of the present embodiment configured the inverse γ conversion process using a memory.
[0240]
The inverse γ processing unit sets the number of bits of the video signals R, G, and B to 8 bits, sets the number of bits of the video signals Ra, Ga, and Ba, which are the outputs of the inverse γ processing unit, to 8 bits, addresses 8 bits, data 8 A bit memory is used for each color (FIG. 15).
[0241]
In each memory, the inverse γ characteristic shown in FIG. 16 was stored. FIG. 5A shows data described in the table in which the input video signal of this conversion table is in the range of 0 to 255. FIG. 4B shows the input image data in an enlarged range of 0 to 48.
[0242]
(Data array converter)
The data array conversion unit 9 is a circuit that performs parallel-serial conversion of Ra, Ga, Ba, which are RGB parallel video signals, in accordance with the pixel array of the display panel. As shown in FIG. 17, the data array conversion unit 9 includes FIFO (FirstInFirstOut) memories 2021R, 2021G, 2021B and selectors 2022 for each RGB color.
[0243]
Although not shown in the figure, the FIFO memory includes two memories each having a horizontal pixel number for odd lines and even lines. When odd-numbered video data is input, data is written to the odd-line FIFO, while image data stored in the previous horizontal scanning period is read from the even-line FIFO memory. When the even-numbered video data is input, the data is written in the even-line FIFO, while the image data stored in the previous horizontal period is read from the odd-line FIFO memory.
[0244]
The data read from the FIFO memory is parallel-serial converted by the selector according to the pixel arrangement of the display panel, and output as RGB serial image data SData. Although not described in detail, it operates based on a timing control signal from the timing generation circuit 4.
[0245]
(Adder 12)
The adder 12 is a means for calculating the correction data CD from the correction data calculation means and the image data Datb. By performing addition, the image data Data is corrected and transferred to the shift register as image data Dout.
[0246]
Note that when the image data Data and the correction data CD are added, an overflow may occur in the adder.
On the other hand, in this example, as a configuration for preventing overflow, the bit width of the adder and the bit width of the subsequent modulation means are determined according to the maximum value when the image data Data and the correction data CD are added. did.
[0247]
More specifically, in the case of the image display apparatus of this example, the correction data reaches a maximum of 120 when the image data is all 255 screens.
Maximum value of adder output = 255 + 120 = 375
Therefore, the number of output bits of the adder is 9 bits, the number of bits of the modulation means is 9 bits, and the number of bits of each part is determined.
[0248]
Further, as another configuration for preventing overflow, the maximum value of correction data to be added is estimated in advance, and image data can be obtained so that overflow does not occur when the maximum value is added. The range may be reduced in advance.
[0249]
In order to reduce the size of image data, the input image data may be limited when A / D conversion is performed, or a multiplier is provided so that the input image data is 0 or more and 1 or less. The gain may be multiplied to limit the size.
[0250]
(Delay circuit 19)
The image data SData rearranged by the data array conversion unit is input to the correction data calculation means and the delay circuit (delay means) 19. The correction data interpolation unit of the correction data calculation means refers to the horizontal position information x from the timing control circuit and the image data SDb 狽 ≠ f value, and calculates correction data CD corresponding to them.
[0251]
The delay circuit 19 is provided to absorb the time required for calculating correction data. When the correction data is added to the image data by the adder, the correction data corresponding thereto is correctly added to the image data. It is a means for performing a delay. This means can be configured by using a flip-flop.
[0252]
(Shift register, latch circuit)
The image data Dout, which is the output of the correction data interpolation unit, is serial / parallel converted from the serial data format to the parallel image data ID1 to IDN for each modulation wiring by the shift register 5, and is output to the latch circuit. In the latch circuit, the data from the shift register is latched by the timing signal Dataload immediately before one horizontal period is started. The output of the latch circuit 6 is supplied to the modulation means as parallel image data D1 to DN.
[0253]
In this embodiment, the image data ID1 to IDN and D1 to DN are each 8-bit image data. These operation timings operate based on the timing control signals TSFT and Dataload from the timing generation circuit 4 (FIG. 13).
[0254]
(Details of modulation means)
Parallel image data D <b> 1 to DN as outputs of the latch circuit 6 are supplied to the modulation means 8.
[0255]
As shown in FIG. 18A, the modulation means is a pulse width modulation circuit (PWM circuit) including a PWM counter and a comparator and a switch (FET in the figure) for each modulation wiring.
[0256]
The relationship between the image data D1 to DN and the output pulse width of the modulation means is linear as shown in FIG.
[0257]
FIG. 3C shows three examples of output waveforms of the modulation means.
[0258]
In the figure, the upper waveform is the waveform when the input data to the modulation means is 0,
The center waveform is the waveform when the input data to the modulation means is 256,
The lower waveform is a waveform when the input data to the modulation means is 511.
[0259]
In this example, the number of bits of input data D1 to DN to the modulation means is set to 9 bits in consideration of the fact that overflow does not occur as described above.
[0260]
In the above description, there is a place where a modulation signal having a pulse width corresponding to one horizontal scanning period is output when the input data of the modulation means is 511. However, FIG. As described above, although there is a very short time, a period in which the pulse is not driven after the rising of the pulse and after the falling is provided to provide a timing margin.
[0261]
FIG. 19 is a timing chart showing the operation of the modulating means of the present invention.
[0262]
In the figure, the Hsync horizontal synchronization signal, Dataload is the load signal to the latch circuit 6, D1 to DN are the input signals to the above-mentioned modulation means columns 1 to N, Pwmstart is the PWM counter synchronization clear signal, and Pwmclk is the PWM counter Is the clock. XD1 to XDN represent outputs of the first to Nth columns of the modulation means.
[0263]
As shown in the figure, when one horizontal scanning period starts, the latch circuit 6 latches image data and transfers the data to the modulation means.
[0264]
As shown in the figure, the PWM counter starts counting based on Pwmstart and Pwmclk. When the count value reaches 511, the counter stops and holds the count value 511.
[0265]
The comparator provided for each column compares the count value of the PWM counter with the image data of each column, and outputs High when the value of the PWM counter is equal to or greater than the image data, and outputs Low during other periods. .
[0266]
The output of the comparator is connected to the gate of the switch in each column. During the period when the output of the comparator is low, the switch on the upper side (VPWM side) in the figure is ON, and the switch on the lower side (GND side) is OFF. The modulation wiring is connected to the voltage VPWM.
[0267]
On the contrary, during the period when the output of the comparator is High, the upper switch in the figure is turned OFF, the lower switch is turned ON, and the voltage of the modulation wiring is connected to the GND potential.
[0268]
As each unit operates as described above, the pulse width modulation signal output from the modulation means has a waveform in which the rising edges of the pulses are synchronized as shown by D1, D2, and DN in FIG.
[0269]
(Correction data calculation means)
The correction data calculation means is a circuit that calculates correction data for the voltage drop by the correction data calculation method described above. As shown in FIG. 20, the correction data calculation means is composed of two blocks, a discrete correction data calculation unit and a correction data interpolation unit.
[0270]
The discrete correction data calculation unit is means for calculating a voltage drop amount from the input video signal and calculating correction data discretely from the voltage drop amount. In order to reduce the amount of calculation and the amount of hardware, this means introduces the concept of the above-mentioned degenerate model and calculates correction data discretely.
[0271]
The correction data calculated discretely is interpolated by a correction data interpolation unit (correction data interpolation means), and correction data CD suitable for the size of the image data and the horizontal display position x is calculated.
[0272]
(Discrete correction data calculation unit)
FIG. 21 shows a discrete correction data calculation unit for calculating discrete correction data according to the present invention.
[0273]
As described below, the discrete correction data calculation unit divides the image data into blocks, calculates the statistic (number of lightings) for each block, and calculates the time change of the voltage drop at each node position from the statistic. A function as a voltage drop amount calculation unit to calculate, a function to convert the voltage drop amount for each time into a light emission luminance amount, a function to calculate the light emission luminance total amount by integrating the light emission luminance amount in the time direction, and those To correction data for a reference value of image data at discrete reference points.
[0274]
In the figure, 100a to 100c are lighting number counting means, 101a to 101c are register groups for storing the number of lighting at each time for each block, 102 is a CPU, 103 is a parameter aij described in equations 2 and 3. Table memory (voltage drop amount storage means) 104, a temporary register 104 for temporarily storing calculation results, 105 a program memory storing a CPU program, 111 a voltage drop amount converted into an emission current amount A table memory 106 in which conversion data to be written is described is a group of registers for storing the calculation results of the discrete correction data described above.
[0275]
The lighting number counting means 100a to 100c are composed of a comparator and an adder as shown in FIG. The video signals Ra, Ga, Ba are respectively input to the comparators 107a to 107c and are sequentially compared with the value of Cval.
[0276]
Cval corresponds to a reference value set for the image data described above.
[0277]
The comparators 107a to 107c compare Cval and image data, and output High when the image data is larger, and output Low when the image data is smaller.
[0278]
The outputs of the comparators are added to each other by the adders 108 and 109, and addition is performed for each block by the adder 110, and the addition result for each block is stored in the register groups 101a to 101c as the number of lighting for each block.
[0279]
0, 64, 128, and 192 are input to the lighting number counting means 100a to 100c as comparison values Cval of the comparators, respectively.
[0280]
As a result, the lighting number counting means 100a counts the number of image data larger than 0 among the image data, and stores the total for each block in the register 101a.
[0281]
Similarly, the lighting number counting means 100b counts the number of image data larger than 64 of the image data, and stores the total for each block in the register 101b.
[0282]
Similarly, the lighting number counting means 100c counts the number of image data larger than 128 among the image data, and stores the total for each block in the register 101c.
[0283]
Similarly, the lighting number counting means 100d counts the number of image data larger than 192 in the image data, and stores the total for each block in the register 101d.
[0284]
When the number of lightings for each block and time is counted, the CPU reads the parameter table aij stored in the table memory 103 at any time, calculates the voltage drop amount according to Equations 2 to 5, and stores the calculation result in the temporary register 104. Store.
[0285]
In this example, the CPU is provided with a product-sum operation function for smoothly performing the calculation of Equation 2.
[0286]
As a means for realizing the calculation shown in Equation 2, the CPU does not have to perform the product-sum operation. For example, the calculation result may be stored in a memory.
[0287]
That is, the number of lighting of each block may be used as an input, and the voltage drop amount at each node position may be stored in the memory for all possible input patterns.
[0288]
When the calculation of the voltage drop amount is completed, the CPU reads out the voltage drop amount for each block for each time from the temporary register 104, and refers to the table memory 2 (111) to determine the voltage drop amount as the emission current amount. After conversion, discrete correction data was calculated according to equations 6-16.
[0289]
The calculated discrete correction data was stored in the register group 106.
[0290]
(Correction data interpolation unit)
The correction data interpolation unit is a means for calculating correction data suitable for the position (horizontal position) where the image data is displayed and the size of the image data. The means interpolates discretely calculated correction data, thereby calculating correction data corresponding to the display position (horizontal position) of the image data and the size of the image data.
[0291]
FIG. 22 is a diagram for explaining the correction data interpolation unit.
[0292]
In the figure, reference numeral 123 denotes a decoder for determining the node numbers n and n + 1 of the discrete correction data used for the interpolation from the display position (horizontal position) x of the image data. It is a decoder for determining k and k + 1 in Equation 19.
[0293]
Further, the selectors 125 to 128 are selectors for selecting discrete correction data and supplying it to the linear approximation means.
[0294]
Reference numerals 121 to 123 are linear approximation means for performing linear approximation of equations 17 to 19, respectively.
[0295]
FIG. 23 shows a configuration example of the straight line approximation means 121. In general, the linear approximation means can be constituted by a subtractor, an integrator, an adder, a divider, etc., as represented by the operators of equations 17-19.
[0296]
However, preferably, the number of column wirings between the nodes for calculating the discrete correction data and the interval between the image data reference values for calculating the discrete correction data (that is, the time interval for calculating the voltage drop) are a power of 2. This configuration has the advantage that the hardware can be configured very easily. If they are set to a power of 2, in the divider shown in FIG. 23, Xn + 1−Xn becomes a power of 2 and may be bit-shifted.
[0297]
If the value of Xn + 1−Xn is always a constant value and is a value represented by a power of 2, the addition result of the adder may be shifted by the power of the power and output. There is no need to make it.
[0298]
Further, by making the interval between the nodes for calculating the discrete correction data and the interval between the image data powers of 2 in other places, for example, the decoders 123 to 124 can be easily manufactured, and FIG. There are many merits such as the operation performed by the subtracter can be replaced with a simple bit operation.
[0299]
(Operation timing of each part)
FIG. 24 shows a timing chart of the operation timing of each part.
[0300]
In the figure, Hsync is a horizontal synchronization signal, DotCLK is a clock generated from the horizontal synchronization signal Hsync by a PLL circuit in the timing generation circuit, R, G and B are digital image data from the input switching circuit, and Data is a data array. Image data after conversion, Dout is image data subjected to voltage drop correction, TSFT is a shift clock for transferring the image data Dout to the shift register 5, Dataload is a load pulse for latching data to the latch circuit 6, Pwmstart is an example of the pulse width modulation start signal, and the modulation signal XD1 is an example of a pulse width modulation signal supplied to the modulation wiring 1.
[0301]
With the start of one horizontal period, digital image data RGB is transferred from the input switching circuit. In the figure, when the input image data is represented by R_I, G_I, and B_I in the horizontal scanning period I, they are stored in the data array conversion circuit 9 for one horizontal period, and in the horizontal scanning period I + 1. The digital image data Data_I is output in accordance with the pixel arrangement of the display panel.
[0302]
R_I, G_I, and B_I are input to the correction data calculation means in the horizontal scanning period I. In this means, the number of lighting described above is counted, and the voltage drop amount is calculated as the count ends.
[0303]
Following the calculation of the voltage drop amount, discrete correction data is calculated, and the calculation result is stored in the register.
[0304]
In the scanning period I + 1, the correction data interpolation unit interpolates the discrete correction data and calculates correction data in synchronization with the output of the image data Data_I one horizontal scanning period before from the data array conversion unit. The interpolated correction data is immediately subjected to gradation number conversion by the gradation number conversion unit 15 and supplied to the adder 12.
[0305]
The adder 12 sequentially adds the image data Data and the correction data CDz, and transfers the corrected image data Dout to the shift register. The shift register stores image data Dout for one horizontal period according to Tsft, performs serial-parallel conversion, and outputs parallel image data ID1 to IDN to the latch circuit 6. The latch circuit 6 latches the parallel image data ID1 to IDN from the shift register in accordance with the rising edge of Dataload, and transfers the latched image data D1 to DN to the pulse width modulation means 8.
[0306]
The pulse width modulation means 8 outputs a pulse width modulation signal having a pulse width corresponding to the latched image data. In the image display apparatus of the present embodiment, as a result, the pulse width output by the modulation means is displayed with a delay of two horizontal scanning periods with respect to the input image data.
[0307]
When an image is displayed using such an image display device, it is possible to correct the amount of voltage drop in the scanning wiring, which has been a problem in the past, and to improve the deterioration of the display image caused by that. A good image could be displayed.
[0308]
Also, correction data can be calculated discretely, and correction data can be calculated very easily by interpolating between the points calculated discretely. There were very good effects such as being able to realize it with wear.
[0309]
(Preferred setting interval of node position and image data reference value)
In the above example, there is also a meaning for simplifying the explanation, and an example in which four blocks are provided has been shown. A node that is a position for calculating a voltage drop amount or discrete correction data is represented by five points at the boundary position of the block. However, in order to calculate the correction data with high accuracy, the larger the number of blocks and nodes, the smaller the error due to the above-mentioned linear approximation, which is preferable, but it goes without saying that the amount of calculation increases. .
[0310]
On the other hand, as a technique to reduce the error with a limited number of blocks and nodes, the block and node intervals are set finely in areas where the voltage drop amount or correction data changes greatly, and conversely the voltage drop amount It is preferable to set a rough interval for setting blocks and nodes at locations where the change in correction data is small. Setting nodes and blocks in this way is very preferable in that the error can be reduced and the calculation can be performed with a small amount of calculation even if the above-described linear approximation is performed.
[0311]
FIG. 25A shows an example of a calculation result obtained by calculating corrected image data when all white is displayed on the screen when the scanning circuits are provided on both sides of the scanning wiring.
[0312]
The ideal calculation result is preferably calculated as a curve as shown by the dotted line in the figure. However, in the present invention, since the calculation is performed by degeneration, the actual calculation is indicated by a circle in the figure. As described above, the discrete corrected image data is calculated at the position of the node, and the corrected image data of the adjacent node and the node is calculated by linear approximation at an intermediate position.
[0313]
In this case, as the position of the node, if the gradient of the dotted line in FIG. 25 (a) is large, the closer to the left and right ends of the screen, the narrower the node setting interval, and the rougher the node setting interval toward the center of the screen, It was preferable because the calculation error due to linear interpolation could be reduced in the calculated amount.
[0314]
FIG. 25B is an example of a calculation result obtained by calculating the corrected image data when all white is displayed on the screen when the scanning circuit is provided only on one side of the scanning wiring.
[0315]
Even in this case, the left side of the screen (the side with the scanning circuit) with a large change is finer in the node setting interval, and the right side of the screen (the side without the scanning circuit) is to make the block or node setting interval rougher. Therefore, it was preferable because it was possible to perform highly accurate calculations with a small amount of calculation.
[0316]
In this case as well, it is needless to say that it is preferable to select the interval between adjacent nodes to a power of 2 because the amount of hardware in the interpolation circuit can be reduced.
[0317]
Further, the interval for setting the image data reference value is preferably set as follows depending on the size of the image data.
[0318]
In particular, in a portion where the image data is small, since the size of the image data itself is small, there is a feature that the influence of the error when calculating the correction data is easily noticeable. On the other hand, since the size of the image data itself is large at a location where the size of the image data is large, the influence of the error when calculating the correction data is not noticeable.
[0319]
In view of such characteristics, from the viewpoint of reducing correction errors, the interval for setting the image data reference value is set finely in a small area of the image data, and conversely in the area where the size of the image data is large. It was preferable to set a rough interval for setting the image data reference value.
[0320]
More specifically, the inventors select 0, 2, 4, 6, 8, 16, 32, 48, 64, 96, 128, 192, 256 as the image data reference value and perform the calculation. I was very pleased.
[0321]
In this case as well, the interval between adjacent image data reference values can be reduced by selecting a power of 2 so that the hardware of the interpolation circuit for performing the calculation can be reduced (replace the divider or the like with a bit shift circuit). Was possible.) Very good.
[0322]
(Second Embodiment)
In the first embodiment, a reference value of discrete image data is set for input image data, a reference point is set on the row wiring, and an image having a size of the image data reference value at the reference point is set. Correction data for the data was calculated.
[0323]
In addition, the correction data calculated according to the horizontal display position of the input image data and its size is calculated by interpolating the correction data calculated discretely, and the correction is realized by adding the correction data to the image data. It was.
[0324]
On the other hand, the same correction can be performed by the following configuration in addition to the above configuration.
[0325]
Calculate a correction result of the image data with respect to the discrete horizontal position and the image data reference value (that is, the sum of the discrete correction data and the image data reference value: that is, the corrected image data),
Further, the correction results calculated discretely may be interpolated to calculate a correction result according to the horizontal display position of the input image data and its size, and modulation may be performed according to the correction result.
[0326]
In this configuration, since the calculation is performed as a result of adding the image data and the correction data in the discrete calculation, it is not necessary to add the image data and the correction data after the interpolation.
[0327]
【The invention's effect】
As described above, according to the image display device of the present invention, it has been possible to improve the degradation of the display image due to the voltage drop on the scanning wiring, which has been a conventional problem.
[0328]
In addition, by introducing several approximations, it is possible to easily calculate the correction amount of the image data to correct the voltage drop, and to realize it with very simple hardware, etc. There was a very good effect.
[0329]
In addition, there was an excellent effect that the discomfort of the display image can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram showing an overview of an image display apparatus according to an embodiment of the present invention.
FIG. 2 is a diagram showing an electrical connection of a display panel.
FIG. 3 is a diagram showing characteristics of a surface conduction electron-emitting device.
FIG. 4 is a diagram showing a display panel driving method.
FIG. 5 is a diagram illustrating the influence of a voltage drop.
FIG. 6 is a diagram illustrating a degenerate model according to the embodiment of this invention.
FIG. 7 is a graph showing voltage drop amounts calculated discretely.
FIG. 8 is a graph showing changes in emission current calculated discretely.
FIG. 9 is a diagram for explaining a correction data calculation method according to the embodiment of the present invention.
FIG. 10 is a diagram illustrating an example of calculating correction data when the size of image data is 128;
11 is a diagram illustrating an example of calculation of correction data when the size of image data is 192. FIG.
FIG. 12 is a diagram for explaining a correction data interpolation method according to the embodiment of the present invention;
FIG. 13 is a block diagram illustrating a schematic configuration of an image display device including a correction circuit according to an embodiment of the present invention.
FIG. 14 is a block diagram showing a configuration of a scanning circuit of the image display apparatus according to the embodiment of the present invention.
FIG. 15 is a block diagram illustrating a configuration of an inverse γ processing unit of the image display apparatus according to the embodiment of the present invention.
FIG. 16 is a diagram illustrating input / output characteristics of an inverse γ processing unit of the image display apparatus according to the embodiment of the present invention;
FIG. 17 is a block diagram showing a configuration of a data array conversion unit of the image display apparatus according to the embodiment of the present invention.
FIG. 18 is a diagram illustrating the configuration and operation of a modulation unit of the image display apparatus according to the embodiment of the present invention.
FIG. 19 is a timing chart of the modulation means of the image display apparatus according to the embodiment of the present invention.
FIG. 20 is a block diagram showing a configuration of correction data calculation means of the image display apparatus according to the embodiment of the present invention.
FIG. 21 is a block diagram illustrating a configuration of a discrete correction data calculation unit of the image display device according to the embodiment of the present invention.
FIG. 22 is a block diagram illustrating a configuration of a correction data interpolation unit according to the embodiment of this invention.
FIG. 23 is a block diagram showing a configuration of a straight line approximating unit according to the embodiment of the present invention.
FIG. 24 is a timing chart of the image display device according to the embodiment of the present invention.
FIG. 25 is a diagram illustrating an interval set by a node according to the embodiment of this invention.
FIG. 26 is a block diagram illustrating a configuration of a conventional image display device.
[Explanation of symbols]
1 Display panel
2 Scanning circuit
8 Pulse width modulation means
12 Adder
14 Correction data calculation means
17 Reverse γ processing section
19 Delay circuit
100a to 100c lighting number counting means
101a to 101c register group
103 Table memory
111 Table memory 2
107a-107c comparator
123-124 decoder
1001 Substrate
1002 Cold cathode devices
1003 Row wiring (scanning wiring)
1004 Column wiring (modulation wiring)
1007 Face plate
1008 Fluorescent film
2122 Adder

Claims (13)

An image display device comprising an image forming element arranged in a matrix, driven through a plurality of row wirings and column wirings and used for image formation, and scanning means for sequentially selecting and scanning the row wirings,
Corresponding to the image data, corrected image data calculating means for calculating corrected image data for reducing at least the influence of the voltage drop due to the resistance of the row wiring,
Modulation means for outputting a modulation signal applied to the column wiring, and
The corrected image data calculating means includes
Correction image data corresponding to each reference position, with a plurality of discrete values among the values of the image data as image data reference values and a plurality of positions along the row wiring as reference positions, and A discrete corrected image data calculation unit for calculating corrected image data for the image data reference value;
Corrected image data corresponding to a position other than the reference position, and corrected image data for image data other than the image data reference value is corrected image data corresponding to the reference position, and the image data reference value A corrected image data interpolation unit that calculates and corrects the corrected image data for
The discrete correction image data calculation unit includes a comparator for comparing the image data with the image data reference value, and an addition for integrating the output of the comparator for each of a plurality of regions associated with each of the reference positions. And
The image display device characterized in that the modulation means outputs the modulation signal based on the corrected image data calculated by the corrected image data interpolation unit. An image display device comprising an image forming element arranged in a matrix, driven through a plurality of row wirings and column wirings and used for image formation, and scanning means for sequentially selecting and scanning the row wirings,
Correction image data calculating means for performing correction for compensating for a decrease in luminance caused by a voltage drop due to the resistance of the row wiring on image data to calculate corrected image data;
Modulation means for outputting a modulation signal applied to the column wiring, and
The corrected image data calculating means includes
Correction image data corresponding to each reference position, with a plurality of discrete values among the values of the image data as image data reference values and a plurality of positions along the row wiring as reference positions, and A discrete corrected image data calculation unit for calculating corrected image data for the image data reference value;
Corrected image data corresponding to a position other than the reference position, and corrected image data for image data other than the image data reference value is corrected image data corresponding to the reference position, and the image data reference value A corrected image data interpolation unit that calculates and corrects the corrected image data for
The discrete correction image data calculation unit includes a comparator for comparing the image data with the image data reference value, and an addition for integrating the output of the comparator for each of a plurality of regions associated with each of the reference positions. And
The image display device characterized in that the modulation means outputs the modulation signal based on the corrected image data calculated by the corrected image data interpolation unit. The image display device according to claim 1, wherein the reference position is located at a boundary between the plurality of regions or at a center of the plurality of regions. An image display device comprising an image forming element arranged in a matrix, driven through a plurality of row wirings and column wirings and used for image formation, and scanning means for sequentially selecting and scanning the row wirings,
Corresponding to the image data, corrected image data calculating means for calculating corrected image data for reducing at least the influence of the voltage drop due to the resistance of the row wiring,
Modulation means for outputting a modulation signal applied to the column wiring,
The corrected image data calculating means includes
A discrete corrected image data calculation unit that calculates a plurality of discrete values among the values of the image data as image data reference values and calculates corrected image data for the image data reference values;
A correction image data interpolation unit that calculates correction image data for image data other than the image data reference value by interpolating correction image data for the image data reference value, and
The discrete correction image data calculation unit is configured so that the total amount of light emission luminances in each time region of one horizontal scanning period divided based on the image data reference value is the same as that in the case where there is no voltage drop. Each time region is expanded, the expanded time is integrated, and the corrected image data is calculated.
The image display apparatus characterized in that the modulation means outputs the modulation signal based on the corrected image data calculated by the corrected image data interpolation unit. An image display device comprising an image forming element arranged in a matrix, driven through a plurality of row wirings and column wirings and used for image formation, and scanning means for sequentially selecting and scanning the row wirings,
Corresponding to the image data, corrected image data calculating means for calculating corrected image data for reducing at least the influence of the voltage drop due to the resistance of the row wiring,
Modulation means for outputting a modulation signal applied to the column wiring,
The corrected image data calculating means includes
A discrete corrected image data calculation unit that calculates a plurality of discrete values among the values of the image data as image data reference values and calculates corrected image data for the image data reference values;
A correction image data interpolation unit that calculates correction image data for image data other than the image data reference value by interpolating correction image data for the image data reference value, and
The discrete corrected image data calculation unit is the same as the case where there is no voltage drop in the total amount of light emission luminance emitted by the image forming element in a plurality of regions of the image data divided based on the image data reference value. Each area is expanded so as to be, and the expanded data is integrated to calculate the corrected image data,
The image display device characterized in that the modulation means outputs the modulation signal based on the corrected image data calculated by the corrected image data interpolation unit. An image display device comprising an image forming element arranged in a matrix, driven through a plurality of row wirings and column wirings and used for image formation, and scanning means for sequentially selecting and scanning the row wirings,
Corresponding to the image data, correction data calculating means for calculating correction data for reducing at least the influence of the voltage drop due to the resistance of the row wiring,
Computing means;
Modulation means for outputting a modulation signal applied to the column wiring based on the output of the arithmetic means,
The correction data calculation means includes
Discrete correction for each image data reference value at each reference position with a plurality of discrete values of the image data values as image data reference values and a plurality of positions along the row wiring as reference positions A discrete correction data calculation unit for calculating data;
Correction data corresponding to a position other than the reference position and correction data for image data other than the image data reference value is correction data corresponding to the reference position and correction data for the image data reference value. A correction data interpolation unit that calculates by interpolating
The discrete correction data calculation unit includes a comparator for comparing the image data with the image data reference value, and an adder for integrating the output of the comparator for each of a plurality of regions associated with each of the reference positions. And
The image display device characterized in that the calculation means calculates image data and the correction data calculated by the correction data interpolation unit. An image display device comprising an image forming element arranged in a matrix, driven through a plurality of row wirings and column wirings and used for image formation, and scanning means for sequentially selecting and scanning the row wirings,
Correction data calculating means for calculating correction data for compensating for a decrease in luminance caused by a voltage drop due to the resistance of the row wiring, corresponding to the image data;
Computing means;
Modulation means for outputting a modulation signal applied to the column wiring based on the output of the arithmetic means,
The correction data calculation means includes
Discrete correction for each image data reference value at each reference position with a plurality of discrete values of the image data values as image data reference values and a plurality of positions along the row wiring as reference positions A discrete correction data calculation unit for calculating data;
Correction data corresponding to a position other than the reference position and correction data for image data other than the image data reference value is correction data corresponding to the reference position and correction data for the image data reference value. A correction data interpolation unit that calculates by interpolating
The discrete correction data calculation unit includes a comparator for comparing the image data and the image data reference value, and an adder for integrating the output of the comparator for each of a plurality of regions associated with the reference positions. And
The image display device characterized in that the calculation means calculates image data and the correction data calculated by the correction data interpolation unit. The image display device according to claim 6, wherein the calculation unit is an adder. 9. The image display device according to claim 1, wherein the modulation signal is a signal whose pulse width is modulated based on the image data. The image display device according to claim 1, wherein the image forming element is an electron emitting element that emits electrons according to the modulation signal. The image display apparatus according to claim 10, wherein the electron-emitting device is a surface conduction electron-emitting device. A control method for an image display device, which is arranged in a matrix and is driven through a plurality of row wirings and column wirings, and includes image forming elements used for image formation, and scanning means that sequentially selects and scans the row wirings. There,
Corresponding to the image data, a corrected image data calculating step for calculating corrected image data for reducing at least the influence of the voltage drop due to the resistance of the row wiring;
And a modulation step for outputting a modulation signal applied to the column wiring, and
The corrected image data calculating step includes:
A result of comparing the image data and the image data reference value with a plurality of discrete values among the values of the image data as image data reference values and a plurality of positions along the row wiring as reference positions Calculating corrected image data for each image data reference value at each reference position based on a value accumulated for each of a plurality of regions associated with each of the reference positions;
Correction image data corresponding to a position other than the reference position, and the image data reference value The correction image data for the image data other than is corrected image data corresponding to the reference position and interpolating the correction image data for the image data reference value to calculate,
In the modulation step, the modulation signal is output based on the corrected image data calculated in the interpolation calculation step. A control method for an image display device, which is arranged in a matrix and is driven through a plurality of row wirings and column wirings, and includes image forming elements used for image formation, and scanning means that sequentially selects and scans the row wirings. There,
Corresponding to the image data, a correction data calculating step for calculating correction data for reducing at least the influence of the voltage drop due to the resistance of the row wiring;
A calculation step;
A modulation step for outputting a modulation signal to be applied to the column wiring based on the output of the calculation step;
The correction data calculation step includes:
A result of comparing the image data and the image data reference value with a plurality of discrete values among the values of the image data as image data reference values and a plurality of positions along the row wiring as reference positions Calculating discrete correction data for each image data reference value at each reference position based on a value obtained by integrating each of the plurality of regions associated with each of the reference positions;
Correction data corresponding to a position other than the reference position and correction data for image data other than the image data reference value is correction data corresponding to the reference position and correction data for the image data reference value. Interpolating and calculating, and
In the calculation step, the image data and the correction data calculated in the interpolation calculation step are calculated.

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