JP2003223131A - Image display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image display apparatus in which a change of a drive condition resulting from an electrical resistance of a matrix wiring of a display panel can be adjusted by a small number of hardware. <P>SOLUTION: An adjusted image data calculating means for calculating adjusted image data for reducing an influence of a voltage drop caused by the resistance of a row wiring for image data is provided with a discrete adjusted image data calculating part for setting a plurality of discrete image data reference values to the image data and calculating discrete adjusted image data for the image data reference values, and an adjusted image data interpolating part for interpolating the output of the discrete adjusted image data calculating part and calculating the adjusted image data corresponding to the size of the data of images. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device provided with elements for forming an image, such as electron-emitting elements arranged in a matrix, and particularly, irradiation of an electron beam emitted from the image-forming element. The present invention relates to an image display device such as a television receiver or a display device that receives a television signal or a display signal of a computer or the like to display an image by providing a fluorescent screen that receives and emits light.

[0002]

2. Description of the Related Art In order to correct a decrease in brightness due to a voltage drop due to a wiring resistance of a wiring for electrically connecting to a cold cathode element, the correction data is calculated by a statistical calculation, An image display device having a configuration for combining a line request value and a correction value is disclosed in Japanese Patent Laid-Open No. 8-248920.

The structure of the image display device described in this publication is shown in FIG.
6 shows.

The structure relating to the correction of data in this apparatus is roughly as follows.

First, the luminance data for one line of the digital image signal is added up by the adder 208, and the correction rate data corresponding to this added value is read from the memory 207.

On the other hand, the digital image signal is serial / parallel converted in the shift register 204, held in the latch circuit 205 for a predetermined time, and then input to a multiplier 208 provided for each column wiring at a predetermined timing.

The multiplier 208 multiplies the brightness data for each column wiring by the correction data read from the memory 207, and the obtained corrected data is transferred to the modulation signal generator 209 to be converted into corrected data. A corresponding modulation signal is generated in the modulation signal generator 209, and an image is displayed on the display panel based on this modulation signal.

Here, a statistical calculation process such as calculating a sum or an average is performed on the digital image signals, like the summing process of the luminance data for one line of the digital image signals in the adder 208, Correction is performed based on this value.

[0009]

However, in the above-mentioned conventional structure, a large-scale device such as a multiplier for each column wiring, a memory for outputting correction data, and a summing device for giving an address signal to the memory is required. I needed hardware.

The present invention has been made in order to solve the problems of the prior art, and an object thereof is to drive by the electric resistance of the matrix wiring of the display panel with less hardware than before. An object of the present invention is to provide an image display device capable of correcting fluctuations in conditions.

[0011]

In order to achieve the above object, according to the present invention, an image forming element arranged in a matrix and driven through a plurality of row wirings and column wirings and used for image formation. A scanning unit that sequentially selects and scans the row wirings; a correction image data calculation unit that calculates correction image data for reducing at least the influence of a voltage drop due to the resistance of the row wirings on the image data; An image display device comprising: a modulator that outputs a modulation signal to be applied to the column wiring based on the corrected image data.
The correction image data calculation means sets a plurality of discrete image data reference values for the image data, and calculates discrete correction image data for the image data reference values, and a discrete correction image data And a corrected image data interpolating unit that interpolates the output of the data calculation unit and calculates corrected image data corresponding to the size of the image data.

The discrete corrected image data calculation unit sets a plurality of reference points in the horizontal direction along the selected row wiring, calculates the corrected image data at the reference points, and performs the corrected image data interpolation. It is also preferable that the unit interpolates the output of the discrete corrected image data calculation unit in the horizontal direction to calculate corrected image data according to the horizontal display position of the image data.

The discrete corrected image data calculation unit divides the selected row wiring into a plurality of areas, calculates a statistic of the image data for each of the divided areas, and further calculates a statistic from the statistic. It is also preferable to calculate the corrected image data.

The statistic is an amount obtained by integrating, for each region, the result of comparing the image data with the discrete image data reference value set for the image data for each region. It is also preferable that there is.

It is also preferable that the reference point is located at a boundary between the plurality of areas.

It is also preferable that the reference point is located at the center of the area.

The discrete corrected image data calculation unit predicts and calculates a voltage drop amount when the image data is modulated at a plurality of times in one horizontal scanning period corresponding to the image data reference value. Is also suitable.

It is also preferable that the discrete corrected image data calculation unit predictively calculates a voltage drop amount at the reference point.

The discrete corrected image data calculation unit predicts the light emission luminance of the image forming element when the image data is modulated at a plurality of times in one horizontal scanning period corresponding to the image data reference value. It is also preferable to calculate.

It is also preferable that the discrete corrected image data calculation unit predictively calculates the light emission luminance amount of the image forming element at the reference point when the image data is modulated.

The discrete corrected image data calculation unit divides one horizontal scanning period into a plurality of time regions corresponding to the image data reference value, and the total amount of light emission luminance emitted in each time region is a voltage. It is also preferable to extend each time domain so as to be the same as when there is no influence of the descent, and further integrate the extended results of each time domain to calculate the discrete corrected image data.

When the time domain is expanded, the discrete corrected image data calculation unit approximates that the amount of light emission luminance at the boundary of the time domain does not change by the expansion, and the expansion amount of each time domain is approximated. It is also preferable to calculate

The discrete corrected image data calculation unit divides the data range of the image data into a plurality of areas corresponding to the image data reference value, and determines the total amount of emission luminance emitted to each area. It is also preferable to expand each area so that it becomes the same as when there is no influence of the voltage drop, and further integrate the expanded results of each area to calculate the discrete corrected image data.

When the area is expanded, the discrete corrected image data calculation unit approximates that the amount of light emission luminance at the boundary of the area does not change due to the expansion, and calculates the expansion amount of each area. Is also suitable.

It is also preferable that the number of image forming elements in the horizontal direction between the reference points set in the horizontal direction along the row wiring and the adjacent reference points can be expressed as an integer power of two.

It is also preferable that the interval between the image data reference values set for the image data can be expressed as an integer power of 2.

Image forming elements arranged in a matrix and driven through a plurality of row wirings and column wirings and used for image formation, scanning means for sequentially selecting and scanning the row wirings, and image data, At least correction data calculation means for calculating correction data for reducing the effect of voltage drop due to the resistance of the row wiring, calculation means for calculating the correction data and the image data, and the correction data calculation means according to the output of the calculation means. An image display device comprising: a modulation unit that outputs a modulation signal to be applied to a column wiring, wherein the correction data calculation unit sets a plurality of discrete image data reference values for the image data. A discrete correction data calculation unit that calculates discrete correction data with respect to a reference value, and a correction that interpolates the output of the discrete correction data calculation unit and that corresponds to the data size of the image Characterized in that it comprises a correction data interpolation unit for calculating the over data, the.

The discrete correction data calculation unit sets a plurality of reference points in the horizontal direction along the selected row wiring, calculates the correction data at the reference points, and the correction data interpolation unit sets the It is also preferable to interpolate the output of the discrete correction data calculation unit in the horizontal direction to calculate the correction data according to the horizontal display position.

The discrete correction data calculation unit divides the row wiring into a plurality of areas, and for each of the divided areas,
It is also preferable to calculate the statistical amount of the input image data and further calculate the discrete correction data from the statistical amount.

It is also preferable that the statistic is a result obtained by integrating, for each region, a comparison result of image data and a discrete image data reference value set for the image data.

It is also preferable that the reference point is located at a boundary between the plurality of areas.

It is also preferable that the reference point is located at the center of the area.

The discrete correction data calculation unit may predictively calculate the voltage drop amount when the image data is modulated at a plurality of times in one horizontal scanning period corresponding to the image data reference value. It is suitable.

It is also preferable that the discrete correction data calculation unit predictively calculates the voltage drop amount at the reference point.

The discrete corrected image data calculation unit predicts the light emission brightness of the image forming element when the image data is modulated at a plurality of times in one horizontal scanning period corresponding to the image data reference value. It is also preferable to calculate.

It is also preferable that the discrete correction data calculation unit predictively calculates the light emission luminance amount of the image forming element at the reference point when the image data is modulated.

The discrete correction data calculation unit divides one horizontal scanning period into a plurality of time regions in accordance with the image data reference value, and the total amount of light emission luminance emitted in each time region drops as a voltage. It is also preferable to expand each time domain so as to be the same as when there is no influence of, and further integrate the expanded results of each time domain to calculate the discrete correction data.

When the time domain is expanded, the discrete correction data calculation unit approximates that the amount of light emission luminance at the boundary of the time domain does not change by the expansion, and determines the expansion amount of each time domain. It is also preferable to calculate.

The discrete correction data calculation unit divides the data range of the image data into a plurality of areas corresponding to the image data reference value, and the total amount of light emission luminance emitted to each area is a voltage. It is also preferable to expand each area so that it becomes the same as when there is no influence of descent, and further integrate the expanded results of each area to calculate the discrete correction data.

When the area is expanded, the discrete correction data calculation unit approximates that the amount of emission luminance at the boundary of the area does not change due to expansion, and calculates the expansion amount of each area. Is also suitable.

It is also preferable that the number of image forming elements in the horizontal direction between the reference points set in the horizontal direction along the row wiring and the adjacent reference points can be expressed as an integer power of two.

It is also preferable that the interval between the image data reference values set for the image data can be expressed as an integer power of 2.

It is also preferable that the arithmetic means is an adder for adding the image data and the correction data.

It is also preferable that the modulating means modulates the pulse width of the modulation signal waveform applied to each column wiring based on the corrected image data.

It is also preferable that the image forming element is an electron emitting element that emits electrons in response to an applied modulation signal.

It is also preferable that the electron emitting device is a surface conduction type emitting device.

[0047]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be illustratively described in detail below with reference to the drawings. However, the dimensions of the components described in this embodiment,
The material, the shape, and the relative arrangement of them should be appropriately changed depending on the configuration of the device to which the invention is applied and various conditions, and the scope of the invention is not limited to the following embodiments.

(First Embodiment) In the present invention, in a display device in which electron-emitting devices are arranged in a simple matrix, a voltage drop occurs due to a current flowing into a scanning wiring and a wiring resistance of the scanning wiring, and a display image is displayed. In view of the phenomenon of deterioration, the present invention relates to an image display device provided with a processing circuit that corrects the influence of such a voltage drop in the scanning wiring on the display image, and in particular, it is realized with a relatively small circuit scale.

The correction circuit of the present embodiment calculates deterioration of a display image caused by a voltage drop according to input image data, obtains correction data for correcting the deterioration, and corrects the image data. .

As an image display device having such a correction circuit built-in, the present inventors have conducted extensive studies on an image display device of the following system.

In describing the present invention below,
Overview of a display panel of an image display device according to an embodiment of the present invention, electrical connection of the display panel, characteristics of a surface conduction electron-emitting device, a method of driving the display panel, and when displaying an image by such a display panel. After the mechanism of the reduction of the driving voltage due to the electric resistance of the scanning wiring is described, the correction method and apparatus for the influence of the voltage drop, which is the feature of the present invention, will be described.

(Overview of Image Display Device) FIG. 1 is a perspective view of a display panel used in the image display device according to the present embodiment, in which a part of the panel is cut away to show the internal structure. . In the figure, 1005 is a rear plate, 1006 is a side wall, 1007 is a face plate, and 1005-
1007 forms an airtight container for maintaining a vacuum inside the display panel.

The rear plate 1005 has a substrate 1001.
, But the cold cathode device 1002 is fixed on the substrate.
Are formed by N × M. Row wiring (scan wiring) 100
3, the column wiring (modulation wiring) 1004 and the cold cathode element (image forming element) are connected as shown in FIG.

Such a connection structure is called a simple matrix.

A fluorescent film 1008 is formed on the lower surface of the face plate 1007. Since the image display device according to the present embodiment is a color display device, the fluorescent film 1
Red, green, which is used in the field of CRT
Phosphors of three primary colors of blue are painted separately. The phosphor is formed in a matrix corresponding to each pixel (picture element) on the rear plate, and forms a pixel at a position irradiated with emitted electrons (emission current) from the cold cathode element. It is configured.

A metal back 1 is formed on the lower surface of the fluorescent film 1008.
009 is formed.

Hv is a high-voltage terminal, which is electrically connected to the metal back. By applying a high voltage to the Hv terminal, a high voltage is applied between the rear plate and the face plate.

In this embodiment, a surface conduction electron-emitting device was prepared as a cold cathode device in the above display panel. A field emission type element can also be used as the cold cathode element. The present invention can also be applied to an image display device in which an element that emits light by itself such as an EL element other than the cold cathode element is connected to a matrix wiring and driven.

(Characteristics of Surface Conduction Type Emitting Element) In the surface conduction type emitting element, as shown in FIG. 3, (emission current Ie) vs. (element applied voltage Vf) characteristics and (element current If) vs. (element applied voltage Vf). ) Has characteristics. Since the emission current Ie is significantly smaller than the device current If and it is difficult to draw the same current scale, the two graphs are shown on different scales.

The surface conduction electron-emitting device has the following three characteristics regarding the emission current Ie.

First, a certain voltage (this is the threshold voltage Vth
When the above voltage is applied to the element, the emission current Ie rapidly increases, while the emission current Ie is hardly detected at a voltage lower than the threshold voltage Vth.

That is, it is a nonlinear element having a clear threshold voltage Vth with respect to the emission current Ie.

Secondly, since the emission current Ie changes depending on the voltage Vf applied to the element, the magnitude of the emission current Ie can be controlled by changing the voltage Vf.

Thirdly, since the cold cathode element has a high-speed response, the emission current I depends on the application time of the voltage Vf.
The release time of e can be controlled.

By utilizing the above characteristics, the surface conduction electron-emitting device can be preferably used in a display device.

For example, in the image display device using the display panel shown in FIG. 1, if the first characteristic is utilized, it is possible to sequentially scan the display screen for display. That is, a voltage equal to or higher than the threshold voltage Vth is appropriately applied to the driven element according to the desired light emission luminance, and a voltage lower than the threshold voltage Vth is applied to the non-selected element. By sequentially switching the elements to be driven, it is possible to sequentially scan the display screen for display.

By utilizing the second characteristic,
By the voltage Vf applied to the element, the emission brightness of the phosphor can be controlled and an image can be displayed.

By utilizing the third characteristic,
The light emission time of the phosphor can be controlled by the time for which the voltage Vf is applied to the element, and an image can be displayed.

In the image display device of this embodiment, the amount of the electron beam on the display panel is modulated using the third characteristic.

(Display Panel Driving Method) The display panel driving method of the present invention will be described in detail with reference to FIG.

FIG. 4 shows an example of voltages applied to the voltage supply terminals of the scanning wiring and the modulation wiring when the display panel of the present invention is driven.

Now, the horizontal scanning period I is a period in which the pixels in the i-th row emit light.

In order to cause the pixel on the i-th row to emit light,
The scanning wiring of the i-th row is selected and its voltage supply terminal D
The selection potential Vs is applied to xi. Further, the voltage supply terminals Dxk (k = 1, 2, ... N, where k ≠ i) of the other scanning wirings are set in the non-selected state and the non-selection potential Vns is applied.

In this example, the selection potential Vs is set to -0.5V _SEL, which is half the voltage V _SEL shown in FIG. 3, and the non-selection potential Vs is set.
ns is the GND potential.

A pulse width modulation signal having a voltage amplitude Vpwm was supplied to the voltage supply terminal of the modulation wiring. Conventionally, the pulse width of the pulse width modulation signal supplied to the j-th modulation wiring is conventionally i-th row, j-th
The pulse width modulation signal according to the size of the image data of each pixel is supplied to all the modulation wirings, which is determined according to the size of the image data of the pixel of the column.

In the present embodiment, as will be described later, the pulse width of the pulse width modulation signal supplied to the j-th modulation wiring in order to correct the decrease in luminance due to the influence of the voltage drop is displayed. The pulse width modulation signal is supplied to all the modulation wirings, which is determined according to the size of the image data of the pixel at the i-th row and the j-th column of the image and the correction amount thereof.

In this embodiment, the voltage Vpwm is +
It was set to 0.5V _SEL .

As shown in FIG. 3, the surface conduction electron-emitting device emits electrons when a voltage V _SEL is applied across the device, but does not emit electrons at a voltage lower than Vth.

Further, the voltage Vth is as shown in FIG.
It is characterized by being larger than 0.5V _SEL .

Therefore, no electrons are emitted from the surface conduction electron-emitting device connected to the scanning wiring to which the non-selection potential Vns is applied.

Similarly, during a period in which the output of the pulse width modulation means is at the ground potential (hereinafter, referred to as a period in which the output is "L"), both ends of the surface conduction electron-emitting device on the selected scanning wiring are connected. Since the applied voltage is Vs, no electrons are emitted.

From the surface conduction electron-emitting device on the scanning wiring to which the selection potential Vs is applied, the output of the pulse width modulation means is V.
Pwm period (hereinafter referred to as "H" period of output)
The electrons are emitted according to the. When the electrons are emitted, the above-mentioned phosphor emits light in accordance with the amount of the emitted electron beam, so that it is possible to emit the brightness corresponding to the emitted time.

The image display apparatus according to the present embodiment also displays an image by line-sequential scanning and pulse width modulation of such a display panel.

(Regarding Voltage Drop in Scan Wiring) As described above, the fundamental problem of the present invention is that the potential on the scan wiring increases due to the voltage drop in the scan wiring of the display panel, and thus the surface conduction type This means that the voltage applied to the emission element is reduced, so that the emission current from the surface conduction type emission element is reduced. The mechanism of this voltage drop will be described below.

The device current for one device of the surface conduction electron-emitting device is about several hundred μA when the voltage V _SEL is applied, although it depends on the design specifications and manufacturing method of the surface conduction electron-emitting device.

Therefore, when only one pixel on the selected scanning line is made to emit light and the other pixels are not made to emit light in a certain horizontal scanning period, the device current flowing from the modulation wiring to the scanning wiring of the selected row is 1. Since it is only the current for the pixel (that is, the above-mentioned several 100 μA), there is almost no voltage drop, and the emission brightness does not decrease.

However, in the case where all the pixels in the selected row are made to emit light in a certain horizontal scanning period, the current for all the pixels flows from all the modulation wirings to the scanning wirings in the selected state, so that the current The sum is several hundred mA
The number was several A, and a voltage drop occurred on the scanning wiring due to the wiring resistance of the scanning wiring.

If a voltage drop occurs on the scanning wiring, the voltage applied across the surface conduction electron-emitting device will decrease. For this reason, the emission current emitted from the surface conduction electron-emitting device is reduced, and as a result, the emission brightness is reduced.

Specifically, let us consider a case where a white cross pattern is displayed on a black background as shown in FIG. 5A as a display image.

Then, when the row L in the figure is driven, since the number of lit pixels is small, almost no voltage drop occurs on the scanning wiring in that row. As a result, a desired amount of emission current is emitted from the surface conduction electron-emitting device of each pixel, and light can be emitted with a desired brightness.

On the other hand, when driving the row L ′ in the figure, all the pixels are turned on at the same time, so that a voltage drop occurs on the scanning wiring, and the emission current from the surface conduction electron-emitting device of each pixel is generated. Decrease. As a result, the luminance of the line of row L'is reduced.

As described above, the influence of the voltage drop changes due to the difference in the image data for each horizontal line. Therefore, when displaying the cross pattern as shown in FIG. An image like this had been displayed.

This phenomenon is not limited to the cross pattern, but also occurs when a window pattern or a natural image is displayed.

Further, more complicatedly, the magnitude of the voltage drop has the property of changing within one horizontal scanning period by performing modulation by pulse width modulation.

The pulse width modulation signal supplied to each column is shown in FIG.
In the case of outputting a pulse width modulation signal whose pulse width depends on the size of the input data and whose rising edge is synchronized with respect to the input data as shown in, it depends on the input image data Since the number of pixels that are lit is large at the beginning of one horizontal scanning period and then the pixels are turned off in order from a place with low brightness, the number of lit pixels decreases with time in one horizontal scanning period. .

Therefore, the magnitude of the voltage drop generated on the scan wiring also tends to decrease gradually toward the beginning of one horizontal scanning period.

Since the output of the pulse width modulated signal changes at each time corresponding to one gradation of modulation, the temporal change of the voltage drop also changes at each time corresponding to one gradation of the pulse width modulated signal.

The voltage drop in the scanning wiring, which is the fundamental problem of the present invention, has been described above.

Next, a method of correcting the influence of the voltage drop, which is a feature of the present invention, will be described in detail.

(Calculation Method of Voltage Drop) In order to obtain the correction amount for reducing the influence of the voltage drop, the present inventors first predict the magnitude of the voltage drop and its change with time as the first step. We thought it necessary to develop hardware that predicts in real time.

However, a display panel of an image display device such as the present invention is generally provided with thousands of modulation wirings, and the voltage drop at the intersection of all the modulation wirings and the scanning wirings is calculated. Is very difficult and
It was not realistic to create hardware that calculates it in real time.

On the other hand, as a result of the examination of the voltage drop by the present inventors, it has been found that the following features are provided.

I) At a certain point in one horizontal scanning period, the voltage drop generated on the scan wiring is a spatially continuous amount on the scan wiring, which is a very smooth curve.

Ii) Although the magnitude of the voltage drop varies depending on the display image, it changes at each time corresponding to one gradation of pulse width modulation. Either becomes smaller or maintains its size. That is, the driving method as shown in FIG. 4 does not increase the magnitude of the voltage drop in one horizontal scanning period.

In view of the above-mentioned characteristics, the present inventors have examined whether or not the calculation amount can be reduced by simplifying the calculation with the following approximate model.

First, from the characteristic of i), when calculating the magnitude of the voltage drop at a certain time, it is approximated by a degenerate model in which thousands of modulation wirings are concentrated into several to several tens of modulation wirings. We examined whether it could be simplified and calculated (this will be explained in detail in the calculation of the voltage drop by the following degenerate model).

Further, from the characteristics mentioned in ii), it is possible to roughly predict the time change of the voltage drop by providing a plurality of times in one horizontal scanning period and calculating the voltage drop at each time. did.

Specifically, the time change of the voltage drop was roughly predicted by calculating the voltage drop by the degeneration model described below for a plurality of times.

(Calculation of voltage drop by degenerate model) FIG. 6
(A) is a figure for demonstrating the block and node at the time of performing degeneration of this invention.

In the figure, for simplification of the drawing, only the selected scanning wiring, each modulation wiring, and the surface conduction electron-emitting device connected to the intersection thereof are shown.

At a certain time in one horizontal scanning period, the lighting state of each pixel on the selected scanning wiring (that is, whether the output of the modulating means is "H" or "L"). Is known.

In this lighting state, the element current flowing from each modulation wiring to the selected scanning wiring is set to Ifi (i =
1, 2 ,. ． ． N and i are defined as column numbers).

Further, as shown in the figure, a block is defined by grouping the n modulation wirings, the intersections of the selected scanning wirings and the surface conduction electron-emitting devices arranged at the intersections thereof. . In this example, the blocks are divided into four blocks.

A position called a node is set at the boundary position of each block. A node is a horizontal position (reference point) for discretely calculating the amount of voltage drop that occurs on the scan wiring in the degenerate model. Here, the divided blocks are constituted by surface conduction electron-emitting devices connected to the regions of the scanning wiring divided by the nodes (reference points).

In this example, node 0 is placed at the block boundary position.
~ 5 nodes of node 4 were set.

FIG. 6B is a diagram for explaining the degenerate model.

In the degenerate model, n modulation wirings included in one block in FIG. 9A were degenerated into one, and they were connected so as to be located at the center of the scanning wiring block.

Further, a current source is connected to the modulation wiring of each centralized block, and the total sum (statistical amount) IF0 to IF3 of the current in each block flows from each current source.

That is, IFj (j = 0, 1, ... 3) is

[Equation 1] Is the current expressed as

Further, the potentials at both ends of the scanning wiring are shown in FIG.
However, in the degenerate model, the current flowing into the scanning wiring selected from the modulation wiring is modeled by the above-mentioned current source. The voltage drop amount of each part is the voltage of each part (potential difference) with the feeding part as the reference potential.
This is because it can be calculated by calculating

The surface-conduction type electron-emitting device is omitted regardless of the presence or absence of the surface-conduction type electron-emitting device as long as an equivalent current flows from the column line when viewed from the selected scanning line. This is because the generated voltage drop itself does not change. Therefore, here, the surface conduction electron-emitting device is omitted by setting the current value flowing from the current source of each block to the total current value of the device currents in each block (Equation 1).

Further, the wiring resistance of the scanning wiring of each block is set to n times the wiring resistance r of the scanning wiring in one section (here, one section is the intersection of the scanning wiring with a certain column wiring and its adjacent portion. In this example, the wiring resistance of the scanning wiring in one section is assumed to be uniform.

In such a degenerate model, the voltage drop amounts DV0 to DV generated at each node on the scanning wiring.
4 can be easily calculated by the following product-sum formula.

[Equation 2] That is,

[Equation 3] However, aij is a voltage generated at the i-th node when a unit current is injected only into the j-th block in the degenerate model (hereinafter, this is defined as aij).

The above aij can be easily derived as follows according to Kirchhoff's law.

That is, in FIG. 6B, the wiring resistance from the current source of the block i to the supply terminal on the left side of the scanning wiring is rli (i = 0, 1, 2, 3, 4), and the supply terminal on the right side. Wiring resistance up to rri (i = 0, 1, 2, 3,
4), if the wiring resistance between the block 0 and the left supply terminal and the wiring resistance between the block 4 and the right supply terminal are both defined as rt,

[Equation 4] further,

[Equation 5] Then, aij is

[Equation 6] Can be derived easily. However, in Equation 3, A /
/ B is a symbol indicating the resistance value of the resistance A and the resistance B in parallel, and is A // B = A × B / (A + B).

Even when the number of blocks is not 4, the expression 2 can be easily calculated by Kirchhoff's law, considering the definition of aij. Further, even in the case where the power supply terminals are not provided on both sides of the scanning wiring as in this example and only one side is provided, the calculation can be easily performed by performing calculation according to the definition of aij.

The parameter aij defined by the equation 3 does not need to be recalculated each time the calculation is performed, but may be calculated once and stored as a table.

Further, the summation currents IF0 to IF3 of each block defined by the equation 1 are approximated by the equation 4.

[0129]

[Equation 7] However, in the above formula, Counti is a variable that takes 1 when the i-th pixel on the selected scanning line is in the lighting state and takes 0 when it is in the unlit state.

IFS is an amount obtained by multiplying a device current IF flowing when a voltage V _SEL is applied across one surface conduction electron-emitting device by a coefficient α having a value between 0 and 1.

That is,

[Equation 8] Was defined.

Equation 4 assumes that an element current proportional to the number of lighting in each block flows into the selected scanning wiring from the column wiring of each block. At this time, the element current IF of one element is obtained by multiplying the element current IF of one element by the coefficient α for the following reason.

Originally, in order to calculate the amount of voltage drop, it is necessary to repeatedly calculate the voltage increase of the scanning wiring due to the voltage drop and the decrease amount of the device current due to it, but this convergence calculation is performed by hardware. It is not realistic to calculate. Therefore, in the present invention, αIF is approximately used as the convergence value of IF. Specifically, the IF decrease rate (= α1) when the voltage drop amount is the maximum (when all white)
Then, the IF reduction rate (= α2) when the voltage drop amount becomes (minimum = 0) is estimated in advance, and is calculated as the average value of α1 and α2 or 0.8 × α1.

FIG. 6C shows an example of the result of calculation of the voltage drop amounts DV0 to DV4 of each node by the degeneration model in a certain lighting state.

Since the voltage drop has a very smooth curve, it is assumed that the voltage drop between the nodes approximately takes the value shown by the dotted line in the figure.

By using this degenerate model as described above, it is possible to calculate the voltage drop for each node at a desired time point with respect to arbitrary image data.

As described above, the amount of voltage drop in a certain lighting state was simply calculated using the degeneration model.

The voltage drop generated on the selected scanning wiring changes with time within one horizontal scanning period. As described above, this may occur at some time (reference time) during one horizontal scanning period. On the other hand, the lighting state at that time was obtained, and it was predicted by calculating the voltage drop using the degeneration model for the lighting state.

The number of lights in each block at a certain point in one horizontal scanning period can be easily obtained by referring to the image data of each block.

As an example, assume that the number of bits of input data to the pulse width modulation circuit is 8 bits, and the pulse width modulation circuit outputs a linear pulse width with respect to the size of the input data. And

That is, when the input data is 0, the output is "L", when the input data is 255, "H" is output during one horizontal scanning period, and when the input data is 128, the one horizontal scanning period is output. It is assumed that "H" is output in the first half period and "L" is output in the second half period.

In such a case, the number of lights at the rise time (start time) of the pulse width modulation signal can be easily detected by counting the number of input data to the pulse width modulation circuit which is larger than zero.

Similarly, the number of lights at the center time of one horizontal scanning period can be easily detected by counting the number of input data to the pulse width modulation circuit which is larger than 128.

In this way, by comparing the image data with a certain threshold value and counting the number of true outputs of the comparator, the number of lightings at any time can be easily calculated.

Here, in order to simplify the following description, a time amount called a time slot is defined.

That is, the time slot represents the time from the rise of the pulse width modulation signal in one horizontal scanning period, and the time slot = 0 means immediately after the start time (rise in this case) of the pulse width modulation signal. Is defined as representing the time of day.

The time slot = 64 is defined as a time when 64 gradations have elapsed from the start time of the pulse width modulation signal.

Similarly, the time slot = 128 is defined as a time when 128 gradations have elapsed from the start time of the pulse width modulation signal.

In the present example, the pulse width modulation is an example in which the pulse width from the rising time is used as the reference, and the pulse width is modulated based on the falling time of the pulse. However, it goes without saying that the same can be applied, although the advancing direction of the time axis is opposite to the advancing direction of the time slot.

(Calculation of Correction Data from Voltage Drop Amount) As described above, the time change of the voltage drop during one horizontal scanning period is approximately and discretely calculated by repeating the calculation using the degenerate model. I was able to.

FIG. 7 is an example in which the voltage drop is repeatedly calculated for a certain image data and the time change of the voltage drop in the scanning wiring is calculated (the voltage drop shown here and its time change are , An example for one image data, and it is natural that the voltage drop for another image data has another change.

In the figure, time slots = 0, 64, 12
The voltage drop at each time was calculated discretely by applying the degenerate model to each of the four time points of 8, 192.

In FIG. 7, the voltage drop amount at each node is connected by a dotted line, but the dotted line is shown to make the diagram easy to see, and the voltage drop calculated by this degenerate model is □, ○, Δ. It was calculated discretely at the position of each node shown in.

The present inventors examined the method of calculating the correction data for correcting the image data from the voltage drop amount as the next step after the magnitude of the voltage drop and its change over time can be calculated.

FIG. 8 is a graph showing an estimated emission current emitted from the surface conduction electron-emitting device in the lighting state when the voltage drop shown in FIG. 7 occurs on the selected scanning wiring.

The vertical axis represents the amount of the emission current at each position at each time in percentage, with the magnitude of the emission current emitted when there is no voltage drop being 100%, and the horizontal axis represents the horizontal position. There is.

As shown in FIG. 8, at the horizontal position (reference point) of node 2, the emission current at time slot = 0 is Ie0, the emission current at time slot = 64 is Ie1, and time slot = 128. The emission current at time is Ie2, and the emission current at time slot 192 is Ie3.

The same figure was calculated from the graph of the voltage drop amount of FIG. 7 and the “driving voltage vs. emission current” of FIG. Specifically, it is simply a mechanical plot of the value of the emission current when a voltage obtained by subtracting the voltage drop amount from the voltage V _SEL is applied.

Therefore, the figure only means the current emitted from the surface conduction electron-emitting device in the lighting state, and the surface conduction electron-emitting device in the off state does not emit current.

A method of calculating correction data for correcting image data from the amount of voltage drop will be described below.

FIGS. 9A, 9B, and 9C are diagrams for explaining a method of calculating correction data of the voltage drop amount from the time change of the emission current of FIG. The figure is 64
It is an example of calculating the correction data for the image data.

The emission amount of luminance is nothing but the emitted charge amount obtained by temporally integrating the emission current by the emission current pulse.
Therefore, in the following, when considering the variation of the brightness due to the voltage drop, the description will be given based on the amount of the emitted charges.

Now, when there is no influence of the voltage drop, the emission current is IE, and the time corresponding to one gradation of the pulse width modulation is Δt.
Then, when the image data is 64, the emission charge amount Q0 to be emitted by the emission current pulse is obtained by multiplying the amplitude IE of the emission current pulse by the pulse width (64 × Δt).

[Equation 9] Can be represented as

However, in reality, a phenomenon occurs in which the emission current decreases due to the voltage drop on the scanning wiring.

The amount of charge emitted by the emission current pulse considering the influence of the voltage drop can be calculated approximately as follows.

That is, the time slot of node 2 =
The emission currents of 0 and 64 are Ie0 and Ie1, respectively, and 0
If it is approximated that the emission current between ˜64 changes linearly between Ie0 and Ie1, the emission charge amount Q1 during this period is the trapezoidal area of FIG. 9B, that is,

[Equation 10] Can be calculated as

Next, as shown in FIG. 9C, when the pulse width is extended by DC1 in order to correct the decrease in the emission current due to the voltage drop, it is assumed that the effect of the voltage drop can be eliminated.

When the voltage drop is corrected and the pulse width is extended, the amount of emission current in each time slot is considered to change. However, for simplification, here,
As shown in FIG. 9C, it is assumed that the emission current is Ie0 at time slot = 0 and the emission current is Ie1 at time slot = (64 + DC1).

Further, the emission current between the time slot 0 and the time slot (64 + DC1) is approximated to take a value on a line connecting the emission currents at two points with a straight line.

Then, the amount of emitted charge Q2 due to the corrected emission current pulse is

[Equation 11] Can be calculated as

If this is equal to Q0, then

[Equation 12] If you solve this for DC1,

[Equation 13] Becomes

In this way, the correction data when the image data was 64 was calculated.

That is, the size of the position of node 2 is 6
For the image data of No. 4, as shown in Expression 9, CDa
It suffices to add the correction amount by ta = DC1.

FIG. 10 is an example in which correction data for image data of size 128 is calculated from the calculated voltage drop amount.

Now, when there is no influence of the voltage drop, when the image data is 128, the emission charge amount Q3 emitted by the emission current pulse is

[Equation 14] On the other hand, the input charge amount due to the actual emission current pulse, which is affected by the voltage drop, can be approximately calculated as follows.

That is, the time slot of node 2 =
Emission current amounts of 0, 64, and 128 are Ie0 and Ie, respectively.
1 and Ie2. The emission current between 0 and 64 is I
If it is approximated to change linearly between e0 and Ie1 and change on a line connecting Ie1 and Ie2 with a straight line between 64 and 128, the emitted charge during the time slot from 0 to 128 is approximated. The quantity Q4 is the sum of the areas of the two trapezoids in FIG.

[Equation 15] Can be calculated as

On the other hand, the correction amount of the voltage drop was calculated as follows.

The period corresponding to time slots 0 to 64 is defined as period 1, and the period corresponding to 64 to 128 is defined as period 2.

When the correction is applied, the portion of the period 1 is DC1.
Is extended to period 1'and the portion of period 2 is DC2
I think that it will be extended only in the period 2 '.

At this time, it is assumed that the amount of emitted charges becomes the same as Q0 described above by performing the correction in each period.

It is needless to say that the emission currents at the beginning and the end of each period change due to the correction, but here it is assumed that they do not change in order to simplify the calculation.

That is, the emission current at the beginning of the period 1'is I
e0, the emission current at the end of period 1'is Ie1, period 2 '
The emission current at the beginning of the period is Ie1 and the emission current at the end of the period 2'is Ie2.

Then, DC1 can be calculated in the same manner as the equation 9.

DC2 uses the same concept as above.

[Equation 16] Can be calculated as

As a result, the size of the position of node 2 is 12
For the image data of 8

[Equation 17] Only the correction amount CData should be added.

FIG. 11 is an example in which correction data for image data of size 192 is calculated from the calculated voltage drop amount.

Now, when the image data is 192, the amount of emitted charge Q5 expected by the emission current pulse is

[Equation 18] On the other hand, the amount of electric charge emitted by the actual emission current pulse, which is affected by the voltage drop, can be approximately calculated as follows.

That is, the time slot of node 2 = 0
Let Ie0 be the emission current at the time of, Ie1 be the emission current at the time slot = 64, Ie2 be the emission current at the time slot = 128, and Ie3 be the emission current at the time slot = 192. Emission currents of Ie0 and Ie
It changes linearly between e1 and Ie1 between 64 and 128
And Ie2 change on a straight line connecting 128 to 1
If 92 is approximated to change on a line connecting Ie2 and Ie3 with a straight line, the input charge amount Q6 during the time slot from 0 to 192 is the area of the three trapezoids of FIG. 11C. , That is,

[Formula 19] Can be calculated as

On the other hand, the correction amount of the voltage drop was calculated as follows.

The period corresponding to the time slots 0 to 64 is the period 1, and the period corresponding to the time slots 64 to 128 is the period 2,128.
The period corresponding to 192 is defined as period 3.

Similarly to the above, after the correction, the portion of the period 1 is extended by DC1 and extended to the period 1 ', the portion of the period 2 is extended by DC2 and extended to the period 2',
It is considered that the portion of the period 3 is extended by DC3 and then extended to the period 3 ′.

At this time, it is assumed that the amount of emitted charge becomes the same as Q0 described above by performing the correction during each period.

Further, it is assumed that the emission currents at the beginning and the end of each period do not change before and after the correction.

That is, the emission current at the beginning of the period 1'is
Ie0, the emission current at the end of the period 1'is Ie1, the emission current at the beginning of the period 2'is Ie1, the emission current at the end of the period 2'is Ie2, and the emission current at the beginning of the period 3'is Ie.
3, the emission current at the end of the period 3'is assumed to be Ie4.

Then, DC1 and DC2 are respectively expressed by equation 9,
It can be calculated similarly to 12.

For DC3,

[Equation 20] Can be calculated as

As a result, the size of the position of node 2 is 19
As the correction data CData to be added to the image data of 2,

[Equation 21] Should be added.

As described above, the correction data CDat of the image data 64, 128, 192 for the position of the node 2 is obtained.
a was calculated.

When the pulse width is 0, of course, there is no influence of the voltage drop on the emission current, so the correction data is set to 0 and the correction data CData is added to the image data.
Is also 0.

[0200] In this way, 0, 64, 128, 19
The reason why correction data is calculated for discrete image data as in 2 is to reduce the amount of calculation.

That is, if the same calculation is performed for all arbitrary image data, the calculation amount becomes very large.
The amount of hardware for calculation becomes very large.

On the other hand, at a certain node position, the larger the image data, the larger the correction data tends to be. As a result, when calculating correction data for arbitrary image data, if the points near the image data for which correction data has already been calculated and the points are interpolated by linear approximation, the amount of calculation will be greatly reduced. This is because you can The interpolation will be described in detail when the discrete correction data interpolation unit is described.

If the same idea is applied to the positions of all the nodes, the correction data of image data = 0, 64, 128, 192 can be calculated at the positions of all the nodes.

In this example, the time slots are 0, 64, 12
By applying the degenerate model to the four points of 8, 192 and calculating the voltage drop amount at each time, 0, 64, 12
The correction data for the four image data reference values of 8,192 could be obtained.

However, as described above, preferably, the time interval for calculating the voltage drop by the degenerate model is made fine,
By increasing the reference value of the image data, the time change of the voltage drop can be handled more accurately, and the error in the approximation calculation can be reduced.

At that time, based on the same idea,
It suffices to modify Equations 6 to 16 and perform the calculation.

According to the above-mentioned method, image data = 0,6 at the position of each node with respect to certain input data.
The correction data for 4,128,192 were calculated discretely.

FIG. 12A shows an example of discrete correction data for certain input image data obtained by this method. In the figure, the horizontal axis corresponds to the horizontal display position, and the position of each node is described. The vertical axis represents the size of the correction data.

The discrete correction data is calculated for the positions of the nodes indicated by □, ○, ●, and Δ in the figure and the size of the image data Data (image data reference value = 0, 64, 128, 192). There is something.

(Interpolation Method of Discrete Correction Data) The correction data calculated discretely is discrete with respect to the position of each node, and correction data at an arbitrary horizontal position (column wiring number) is not given. Absent. At the same time, it is correction data for image data having some predetermined reference image data size at each node position, and does not give correction data according to the actual image data size. .

Therefore, the inventors calculated the correction data suitable for the size of the input image data in each column wiring by interpolating the correction data calculated discretely.

FIG. 12B shows the image data Dat at the position x located between the node n and the node n + 1.
It is the figure which showed the method of calculating the correction data equivalent to a.

As a premise, it is assumed that the correction data has already been discretely calculated at the positions Xn and Xn + 1 of the nodes n and n + 1.

Further, it is assumed that the input image data Data takes a value between two image data reference values Dk and Dk + 1 for which correction data has already been calculated discretely.

Now, the correction data for the reference value Dk of the kth image data of the node n is set to CData [k] [n].
The correction data CA for the image data Dk at the position x is CData [k] [n] and CD
The value of ata [k] [n + 1] can be used to calculate as follows by linear approximation.

[Equation 22]

Also, the image data Dk + 1 at the position x
The correction data CB of can be calculated as follows.

[Equation 23]

The correction data CD for the image data Data at the position x can be calculated as follows by linearly approximating the correction data for CA and CB.

[Equation 24]

As described above, in order to calculate the correction data suitable for the actual position or the size of the image data from the discrete correction data, the calculation can be easily performed by the method described in Expressions 17 to 19.

If the correction data thus calculated is added to the image data to correct the image data and the pulse width modulation is performed according to the corrected image data, the image quality due to the voltage drop, which has been a problem in the past, has been solved. Can be reduced and the image quality can be improved.

Further, the hardware for correction, which has been a problem from the beginning, can be reduced in a very small scale by introducing an approximation such as degeneracy described above so that the calculation amount can be reduced. It has the excellent merit that it can be configured with various hardware.

(Explanation of Function of Entire System and Each Part) Next, the hardware of the image display device incorporating the correction data calculating means will be explained.

FIG. 13 is a block diagram showing an outline of the circuit configuration. In the figure, 1 is the display panel of FIG. 1, Dx1
˜DxM and Dx1 ′ to DxM ′ are voltage supply terminals of the scanning wiring of the display panel, Dy1 to DyN are voltage supply terminals of the modulation wiring of the display panel, and Hv is for applying an acceleration voltage between the face plate and the rear plate. High voltage supply terminal,
Va is a high voltage power supply, 2 is a scanning circuit (scanning means), 3 is a synchronization signal separation circuit, 4 is a timing generation circuit, 7 is a conversion circuit for converting the YPbPr signal into RGB by the synchronization separation circuit 3, and 17 is a reverse γ. A processing unit, 5 is a shift register for one line of image data, 6 is a latch circuit for one line of image data, 8 is pulse width modulation means (modulation means) for outputting a modulation signal to the modulation wiring of the display panel, and 12 is addition. Reference numeral 14 denotes a correction data calculation means (calculation processing means, addition processing means).

In the figure, R, G, and B are RGB parallel input video data, Ra, Ga, and Ba are RGB parallel video data subjected to inverse γ conversion processing, which will be described later, and D.
ata is image data subjected to parallel / serial conversion by the data array conversion unit, CD is correction data calculated by the correction data calculating unit, and Dout is image data corrected by adding the correction data to the image data by the adder. Is.

(Synchronous Separation Circuit, Timing Generation Circuit) The image display device according to the present embodiment is NTSC, PAL, SE.
Television signals such as CAM and HDTV, and VGA output from a computer can be displayed together.

In FIG. 13, the HDTV is shown in order to simplify the drawing.
Only the method is described.

In the HDTV system video signal, the synchronization signals Vsync and Hsync are first separated by the synchronization separation circuit 3 and supplied to the timing generation circuit. The video signals separated by synchronization are supplied to the RGB conversion means. Inside the RGB conversion means, a YPbPr-to-RGB conversion circuit, a low-pass filter (not shown), an A / D converter, and the like are provided. The YPbPr is converted into a digital RGB signal, and the inverse γ processing is performed. Supply to the department.

(Timing Generation Circuit) The timing generation circuit is a circuit which has a built-in PLL circuit, generates timing signals synchronized with the synchronization signals of various video sources, and generates operation timing signals for each section.

The timing signal generated by the timing generation circuit 4 includes Tsft for controlling the operation timing of the shift register 5, the shift register, and the latch circuit 6.
Control signal Dataalo for latching data to
d, pulse width modulation start signal Pwmstar of the modulation means 8
t, a clock Pwmclk for pulse width modulation, Tscan for controlling the operation of the scanning circuit 2, and the like.

(Scanning Circuit) The scanning circuits 2 and 2'output the selection potential Vs or the non-selection potential Vns to the connection terminals Dx1 to DxM in order to sequentially scan the display panel row by row in one horizontal scanning period. Circuit (FIG. 14).

The scanning circuits 2 and 2 ′ are circuits that perform scanning by sequentially switching the selected scanning wiring in every horizontal period in synchronization with the timing signal Tscan from the timing generation circuit 4.

Incidentally, Tscan is a timing signal group made up of a vertical synchronizing signal and a horizontal synchronizing signal.

The scanning circuits 2 and 2'are each composed of M switches and shift registers as shown in FIG. These switches are preferably composed of transistors or FETs.

In order to reduce the voltage drop in the scanning wiring, it is preferable that the scanning circuit is connected to both ends of the scanning wiring of the display panel and driven from both ends as shown in FIG.

On the other hand, the present invention is effective even when the scanning circuit is not connected to both ends of the scanning wiring, and can be applied only by changing the parameter of Expression 3.

(Inverse γ Processing Section) The CRT has a light emission characteristic of approximately 2.2 to the input (hereinafter referred to as an inverse γ characteristic).

Such characteristics of the CRT are taken into consideration in the input video signal, and the input video signal is generally converted according to the .gamma. Characteristic of 0.45 so as to have a linear emission characteristic when displayed on the CRT.

On the other hand, when the display panel of the image display device of the present embodiment has a light emission characteristic which is substantially linear with respect to the length of the application time when the drive voltage is applied for modulation, the input video signal is It is necessary to perform conversion (hereinafter referred to as inverse γ conversion) based on the inverse γ characteristic.

The inverse γ processing section shown in FIG. 13 is a block for performing inverse γ conversion on the input video signal.

The inverse γ processing section of this embodiment is configured by a memory for the above inverse γ conversion processing.

The inverse γ processing unit sets the number of bits of the video signals R, G and B to 8 bits, and the video signal R output from the inverse γ processing unit.
The number of bits of a, Ga, and Ba is also set to 8 bits, and a memory of 8 bits for address and 8 bits for data is used for each color (FIG. 15).

The inverse γ characteristic shown in FIG. 16 was stored in each memory. It should be noted that FIG. 9A shows the data described in the table in which the input video signal of this conversion table is in the range of 0 to 255. Further, in the same figure (b), the input image data is 0-4.
The range of 8 is enlarged and displayed.

(Data Array Converter) Data Array Converter 9
Is a circuit for performing parallel / serial conversion of RGB parallel video signals Ra, Ga, Ba according to the pixel array of the display panel. The configuration of the data array converter 9 is shown in FIG.
As shown in, the FIFO (First
InFirstOut) memories 2021R and 2021
G, 2021B and selector 2022.

Although not shown in the figure, the FIFO memory includes two horizontal pixel memory words for odd lines and even lines. When the video data of the odd line is input, the data is written in the FIFO for the odd line, while the image data accumulated in the previous horizontal scanning period is read from the FIFO memory for the even line. When the video data of the even-numbered lines is input, the data is written in the FIFO for the even-numbered lines, while the image data accumulated in the previous horizontal period is read from the FIFO memory for the odd-numbered lines.

The data read from the FIFO memory is parallel-serial converted by the selector according to the pixel array of the display panel and output as RGB serial image data SData. Although not described in detail, it operates based on the timing control signal from the timing generation circuit 4.

(Adder 12) The adder 12 is means for calculating the correction data CD from the correction data calculating means and the image data Datb. Image data D can be obtained by adding
ata is corrected and transferred to the shift register as image data Dout.

It should be noted that the image data Data and the correction data C
Although overflow may occur in the adder when D is added, in contrast to this, in this example, as a configuration for preventing overflow, the maximum value when the image data Data and the correction data CD are added is set. Accordingly, the bit width of the adder and the bit width of the subsequent modulation means were determined.

More specifically, in the case of the image display apparatus of this example, since the maximum correction data is 120 when the image data is all 255 screens, the maximum value of the output of the adder is 255 + 120 = 375. Therefore, the number of bits output from the adder is set to 9 bits, and the number of bits output from the modulator is also set to 9 bits to determine the number of bits in each unit.

As another configuration for preventing overflow, the maximum value of the correction data to be added is estimated in advance and image data is set so that overflow does not occur when the maximum value is added. The range that can be taken may be made small in advance.

In order to reduce the size of the image data, for example, the input image data may be limited when it is A / D converted, or a multiplier may be provided to reduce the input image data to 0. The magnitude may be limited by multiplying the gain by 1 or more.

(Delay Circuit 19) The image data SData rearranged by the data array converter is input to the correction data calculation means and the delay circuit (delay means) 19. The correction data interpolating section of the correction data calculating means refers to the horizontal position information x and the image data SDb.noteq.value from the timing control circuit and calculates the correction data CD suitable for them.

The delay circuit 19 is provided to absorb the time required to calculate the correction data, and when the correction data is added to the image data by the adder, the correction data corresponding to the correction data is correctly added to the image data. It is a means to delay so that it is done. The same means can be configured by using a flip-flop.

(Shift Register, Latch Circuit) The image data Dout output from the correction data interpolating unit is transferred from the serial data format by the shift register 5 to
The parallel image data ID1 to IDN for each modulation wiring are serial / parallel converted and output to the latch circuit. The latch circuit latches the data from the shift register by the timing signal Dataload immediately before the start of one horizontal period. The output of the latch circuit 6 is supplied to the modulation means as parallel image data D1 to DN.

In this embodiment, the image data ID1 to I
Each of DN and D1 to DN is 8-bit image data. These operation timings are the timing generation circuit 4
Timing control signals TSFT and Da from (FIG. 13)
It operates based on taload.

(Details of Modulating Means) The parallel image data D1 to DN output from the latch circuit 6 are supplied to the modulating means 8.

As shown in FIG. 18A, the modulation means is a pulse width modulation circuit (PWM circuit) including a PWM counter, a comparator and a switch (FET in the figure) for each modulation wiring.

The relationship between the image data D1 to DN and the output pulse width of the modulating means has a linear relationship as shown in FIG. 18 (b).

FIG. 3C shows an example of the output waveform of the modulator 3
Show one.

In the figure, the upper waveform is the waveform when the input data to the modulating means is 0, the central waveform is the waveform when the input data to the modulating means is 256, and the lower waveform is the modulating means. This is a waveform when the input data to 511 is 511.

In this example, the input data D1 to the modulation means is
As described above, the number of bits of DN is set to 9 in consideration of not overflowing.

In the above description, when the input data of the modulating means is 511, there is a part that the modulated signal having the pulse width corresponding to one horizontal scanning period is output.
More specifically, as shown in FIG. 6C, although it is a very short time, a period in which the pulse is not driven and before the pulse is driven is provided to provide a timing margin.

FIG. 19 is a timing chart showing the operation of the modulation means of the present invention.

In the figure, the Hsync horizontal sync signal,
Dataload is a load signal to the latch circuit 6, D1
-DN are the input signals to the columns 1-N of the aforementioned modulation means, Pw
mstart is a PWM counter synchronization clear signal, Pw
mclk is the clock of the PWM counter. Also, X
D1 to XDN represent outputs of the first to Nth columns of the modulation means.

When one horizontal scanning period starts as shown in the figure, the latch circuit 6 latches the image data and transfers the data to the modulating means.

The PWM counter, as shown in FIG.
Counting is started based on Pwmstart and Pwmclk, and when the count value reaches 511, the counter is stopped and the count value 511 is held.

The comparator provided for each column is
The count value of the PWM counter is compared with the image data of each column, and when the value of the PWM counter is greater than or equal to the image data, High
h is output, and Low is output during the other periods.

The output of the comparator is connected to the gates of the switches in each column, and the output of the comparator is Low.
During the period, the switch on the upper side (VPWM side) in the figure is ON,
The lower (GND side) switch is turned off, and the modulation wiring is connected to the voltage VPWM.

On the contrary, while the output of the comparator is High, the upper switch in the figure is turned off and the lower switch is turned on, and the voltage of the modulation wiring is connected to the GND potential.

The pulse width modulation signal output from the modulating means is D1 and D in FIG. 19 as a result of the operation of each section as described above.
2, a waveform in which the rising edges of the pulses are synchronized as shown by DN.

(Correction Data Calculation Means) The correction data calculation means is a circuit for calculating the correction data of the voltage drop by the above-mentioned correction data calculation method. As shown in FIG. 20, the correction data calculation means is composed of two blocks, a discrete correction data calculation unit and a correction data interpolation unit.

The discrete correction data calculation unit is means for calculating the amount of voltage drop from the input video signal and discretely calculating the correction data from the amount of voltage drop. In order to reduce the amount of calculation and the amount of hardware, the means introduces the concept of the above-mentioned degenerate model and calculates correction data discretely.

The correction data calculated discretely is interpolated by the correction data interpolating section (correction data interpolating means), and the correction data CD suitable for the size of the image data and its horizontal display position x is calculated.

(Discrete Correction Data Calculation Unit) FIG. 21 shows a discrete correction data calculation unit for calculating the discrete correction data of the present invention.

As will be described below, the discrete correction data calculation unit divides the image data into blocks, calculates a statistic amount (number of lights) for each block, and calculates the voltage drop amount at each node position from the statistic amount. Function as a voltage drop amount calculation unit that calculates changes over time, a function that converts the voltage drop amount for each time into a light emission brightness amount, and a function that integrates the light emission brightness amount in the time direction to calculate a total light emission brightness amount , And the correction data for the reference value of the image data at the discrete reference points.

In the figure, 100a to 100c are lighting number counting means, 101a to 101c are a group of registers for storing the number of lighting at each time for each block, and 10
2 is a CPU, 103 is a table memory (voltage drop amount storage means) for storing the parameters aij described in equations 2 and 3, 104 is a temporary register for temporarily storing the calculation result, and 105 is a program for the CPU. The program memory 111 is a table memory in which conversion data for converting a voltage drop amount into an emission current amount is described, and 106 is a register group for storing the calculation result of the discrete correction data described above.

Lighting number counting means 100a to 100c
Is composed of a comparator and an adder as shown in FIG. The video signals Ra, Ga, and Ba are input to the comparators 107a to 107c, respectively, and sequentially C
It is compared with the value of val.

Note that Cval corresponds to the reference value set for the image data described above.

The comparators 107a to 107c compare Cval with the image data, and if the image data is larger, Hi.
gh is output, and Low is output if it is small.

The output of the comparator is the adders 108 and 1
09, and the addition is performed for each block by the adder 110, and the addition result for each block is set as the lighting number for each block in the register group 1
01a-c are stored.

The number-of-lights counting means 100a to 100c respectively have 0, 64 and 1 as the comparison value Cval of the comparator.
28 and 192 are input.

As a result, the lighting number counting means 100a
Counts the number of image data larger than 0 among the image data, and totals each block by the register 101a.
To store.

Similarly, the lighting number counting means 100b counts the number of image data larger than 64 among the image data, and the total for each block is registered in the register 101b.
To store.

Similarly, the lighting number counting means 100c counts the number of image data larger than 128 among the image data, and the total for each block is registered in the register 101.
Store in c.

Similarly, the lighting number counting means 100d counts the number of image data larger than 192 among the image data, and the total for each block is registered in the register 101.
d Store.

When the number of lights for each block and for each time is counted, the CPU reads the parameter table aij stored in the table memory 103 at any time, and formulas 2-5 are used.
Then, the amount of voltage drop is calculated, and the calculation result is stored in the temporary register 104.

In this example, the CPU is provided with a product-sum operation function for smoothly performing the calculation of the equation 2.

As a means for realizing the operation shown in the equation 2, the product sum operation may not be performed by the CPU, and for example, the calculation result may be stored in the memory.

That is, the number of lighting of each block may be used as an input and the voltage drop amount at each node position may be stored in the memory for all possible input patterns.

When the calculation of the voltage drop amount is completed, C
The PU reads the voltage drop amount for each block from the temporary register 104 at each time, and the table memory 2
With reference to (111), the amount of voltage drop was converted into the amount of emission current, and the discrete correction data was calculated according to equations 6 to 16.

The calculated discrete correction data is stored in the register group 1
It was stored in 06.

(Correction Data Interpolation Unit) The correction data interpolation unit is means for calculating the correction position data (horizontal position) where the image data is displayed and the correction data suitable for the size of the image data. This means interpolates the correction data calculated discretely to display the image data (horizontal position).
Also, correction data corresponding to the size of the image data is calculated.

FIG. 22 is a diagram for explaining the correction data interpolation unit.

In the figure, reference numeral 123 is a decoder for determining the node numbers n and n + 1 of the discrete correction data used for interpolation from the display position (horizontal position) x of the image data, and 124 is the size of the image data. Formula 17 to Formula 19
Is a decoder for determining k and k + 1.

Further, the selectors 125 to 128 are selectors for selecting the discrete correction data and supplying it to the linear approximation means.

Further, 121 to 123 are respectively the expressions 17
The linear approximation means for performing the linear approximation of 19 to 19.

FIG. 23 shows a configuration example of the linear approximation means 121. Generally, the linear approximation means can be configured by a subtractor, an integrator, an adder, a divider, etc., as represented by the operators of Expressions 17 to 19.

However, it is desirable that the number of column wirings between the nodes for calculating the discrete correction data and the interval of the image data reference value for calculating the discrete correction data (that is, the time interval for calculating the voltage drop) be a power of two. There is a merit that the hardware can be configured very easily if it is configured as follows. If you set them to a power of 2,
In the divider shown in FIG. 3, Xn + 1-Xn becomes a power of 2 and bit shift is required.

If the value of Xn + 1-Xn is always a constant value and a value represented by a power of 2, it suffices to shift the addition result of the adder by the multiplier of the power and output the result. There is no need to make a divider.

Also at other locations, the intervals between the nodes for calculating the discrete correction data and the intervals between the image data are set to be powers of 2, for example, the decoders 123 to 124.
Can be easily manufactured, and the calculation performed by the subtractor in FIG. 23 can be replaced with a simple bit calculation, which is very advantageous.

(Operation Timing of Each Part) FIG. 24 shows a timing chart of the operation timing of each part.

In the figure, Hsync is a horizontal synchronizing signal and DotCLK is a PLL in the timing generation circuit.
A clock generated by the circuit from the horizontal synchronizing signal Hsync, R, G, B are digital image data from the input switching circuit, Data is image data after data array conversion,
Dout is image data that has been subjected to voltage drop correction, TSF
T is a shift clock for transferring the image data Dout to the shift register 5, Dataload is a load pulse for latching data in the latch circuit 6, and Pwms
start is the start signal of the above-mentioned pulse width modulation, the modulation signal X
D1 is an example of a pulse width modulation signal supplied to the modulation wiring 1.

With the start of one horizontal period, the digital image data RGB is transferred from the input switching circuit. In the figure, in the horizontal scanning period I, when the input image data is represented by R_I, G_I, and B_I, the image data is stored in the data array conversion circuit 9 for one horizontal period, and in the horizontal scanning period I + 1. , Is output as digital image data Data_I according to the pixel arrangement of the display panel.

R_I, G_I and B_I are input to the correction data calculating means in the horizontal scanning period I. With this means, the number of times of lighting described above is counted, and at the end of counting, the voltage drop amount is calculated.

Subsequent to the calculation of the voltage drop amount, the discrete correction data is calculated, and the calculation result is stored in the register.

In the scanning period I + 1, the correction data interpolating unit interpolates the discrete correction data in synchronization with the output of the image data Data_I one horizontal scanning period before from the data array converting unit, and the correction data is calculated. To be done. The interpolated correction data is immediately subjected to gradation number conversion by the gradation number conversion unit 15 and supplied to the adder 12.

The adder 12 sequentially adds the image data Data and the correction data CDz to obtain the corrected image data D.
Transfer out to the shift register. The shift register sets the image data Do for one horizontal period according to Tsft.
ut is stored, serial-parallel conversion is performed, and parallel image data ID1 to IDN are output to the latch circuit 6. The latch circuit 6 latches the parallel image data ID1 to IDN from the shift register according to the rising edge of Dataload, and transfers the latched image data D1 to DN to the pulse width modulation means 8.

The pulse width modulation means 8 outputs a pulse width modulation signal having a pulse width corresponding to the latched image data. In the image display device of the present embodiment, as a result, the pulse width output by the modulation means is displayed with a delay of two horizontal scanning periods with respect to the input image data.

When an image is displayed by such an image display device, it is possible to correct the amount of voltage drop in the scanning wiring, which has been a problem in the past, and it is possible to improve the deterioration of the displayed image due to the correction. It was possible to display a very good image.

Further, the correction data can be calculated very easily by calculating the correction data discretely and interpolating between the points calculated discretely to obtain the correction data. It was very effective, as it could be achieved with simple hardware.

(Regarding Node Position and Preferable Interval of Setting Image Data Reference Value) In the above example, there are four blocks for the purpose of simplifying the description. The node, which is the position where the voltage drop amount and the discrete correction data are calculated, is represented by five points at the block boundary position. However, in order to accurately calculate the correction data, the larger the number of blocks and nodes, the smaller the error due to the above-described linear approximation, which is preferable. However, it goes without saying that the amount of calculation increases. .

On the other hand, with a limited number of blocks and a limited number of nodes,
As a method for reducing the error, a block or a node is set finely in a portion where the voltage drop amount or the correction data changes largely, and conversely, a block is set in the portion where the voltage drop amount or the correction data change is small. It is preferable to make the intervals for setting the nodes rough. Setting the nodes and blocks in this way is very preferable in that the error can be reduced and the calculation can be performed with a small calculation amount even if the above-described linear approximation is performed.

FIG. 25 (a) shows an example of the calculation result of the corrected image data when all white is displayed on the screen when the scanning circuits are provided on both sides of the scanning wiring.

As an ideal calculation result, it is preferable to calculate as a curve as shown by the dotted line in the figure, but in the present invention, since the calculation is performed by degeneracy, in reality, a circle mark in the figure Discrete correction image data is calculated at the position of the node described in, and the correction image data of the adjacent node and the node is linearly approximated and calculated at the intermediate position. Stated.

In this case, the position of the node is shown in FIG.
By making the node setting interval finer the closer to the left and right ends of the screen where the slope of the dotted line in (a) is large, and making the node setting interval rougher toward the center of the screen, linear interpolation can be performed within a limited calculation amount. The calculation error due to the execution can be reduced, which is preferable.

FIG. 25 (b) shows an example of the calculation result of the corrected image data when all white is displayed on the screen when the scanning circuit is provided on only one side of the scanning wiring.

Even in such a case, the setting intervals of nodes are made finer on the left side of the screen (the side with the scanning circuit) where the change is large, and the setting intervals of blocks and nodes are increased on the right side of the screen (the side without the scanning circuit). By making it rough, it was possible to perform accurate calculations with a small amount of calculation, which was desirable.

In this case as well, it is needless to say that it is preferable to select an interval between adjacent nodes to be a power of 2 because the amount of hardware in the interpolation circuit can be reduced.

Further, it is preferable that the above-mentioned interval for setting the image data reference value is set as follows depending on the size of the image data.

In particular, in a portion where the image data is small, since the size of the image data itself is small, there is a feature that the influence of an error when the correction data is calculated is conspicuous. On the contrary, in the area where the size of the image data is large, the size of the image data itself is large, so that the influence of the error when the correction data is calculated is not noticeable.

In view of such characteristics, from the viewpoint of reducing the correction error, the interval for setting the image data reference value is set finely in a small area of the image data,
On the contrary, in the area where the size of the image data is large, it is preferable to set a rough interval for setting the image data reference value.

More specifically, the present inventors set 0, 2, 4, 6, 8, 16, 32, 4 as the image data reference value.
The calculation was performed by selecting 8, 64, 96, 128, 192, and 256, and it was very favorable.

In this case as well, the interval between adjacent image data reference values can be reduced to the power of 2 to reduce the hardware of the interpolation circuit (calculation of the divider and the bit shift circuit). It can be replaced with.) Very liked.

(Second Embodiment) In the first embodiment,
With respect to the input image data, the reference value of the discrete image data is set, the reference point is set on the row wiring, and the correction data for the image data having the size of the image data reference value at the reference point is calculated. Was there.

Further, by interpolating the correction data calculated discretely, the correction data corresponding to the horizontal display position of the input image data and its size is calculated, and the correction data is added to the image data to correct the correction data. Was realized.

On the other hand, similar correction can be performed by the following configuration in addition to the above configuration.

The correction result of the image data with respect to the discrete horizontal position and the image data reference value (that is, the sum of the discrete correction data and the image data reference value: that is, the corrected image data) is calculated, and further calculated discretely. The correction result may be interpolated, the correction result corresponding to the horizontal display position of the input image data and its size may be calculated, and the modulation may be performed according to the correction result.

In this configuration, since it is calculated as a result of addition of image data and correction data in discrete calculation, it is not necessary to add image data and correction data after interpolation.

[0327]

As described above, according to the image display device of the present invention, the deterioration of the displayed image due to the voltage drop on the scanning wiring, which has been a conventional problem, can be improved.

Further, by introducing some approximations, the correction amount of the image data for correcting the voltage drop can be easily calculated, and it can be realized by very simple hardware. It had a very good effect.

Further, there is an excellent effect that the discomfort of the displayed image can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing an overview of an image display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an electrical connection of a display panel.

FIG. 3 is a diagram showing characteristics of a surface conduction electron-emitting device.

FIG. 4 is a diagram showing a driving method of a display panel.

FIG. 5 is a diagram illustrating an influence of a voltage drop.

FIG. 6 is a diagram illustrating a degenerate model according to the embodiment of this invention.

FIG. 7 is a graph showing a discretely calculated voltage drop amount.

FIG. 8 is a graph showing the amount of change in emission current calculated discretely.

FIG. 9 is a diagram for explaining a method of calculating correction data according to the embodiment of the present invention.

FIG. 10 is a diagram showing an example of calculation of correction data when the size of image data is 128.

FIG. 11 is a diagram showing an example of calculation of correction data when the size of image data is 192.

FIG. 12 is a diagram for explaining a correction data interpolation method according to the embodiment of the present invention.

FIG. 13 is a block diagram showing a schematic configuration of an image display device including a correction circuit according to an embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of a scanning circuit of the image display device according to the embodiment of the present invention.

FIG. 15 is an inverse γ of the image display device according to the embodiment of the present invention.
It is a block diagram which shows the structure of a process part.

FIG. 16 is an inverse γ of the image display device according to the embodiment of the present invention.
It is a figure which shows the input-output characteristic of a process part.

FIG. 17 is a block diagram showing a configuration of a data array conversion unit of the image display device according to the embodiment of the present invention.

FIG. 18 is a diagram illustrating the configuration and operation of the modulation means of the image display device according to the embodiment of the present invention.

FIG. 19 is a timing chart of the modulation means of the image display device according to the embodiment of the present invention.

FIG. 20 is a block diagram showing a configuration of correction data calculation means of the image display device according to the embodiment of the present invention.

FIG. 21 is a block diagram showing a configuration of a discrete correction data calculation unit of the image display device according to the embodiment of the present invention.

FIG. 22 is a block diagram showing a configuration of a correction data interpolation unit according to the embodiment of the present invention.

FIG. 23 is a block diagram showing a configuration of a linear approximation unit according to the embodiment of the present invention.

FIG. 24 is a timing chart of the image display device according to the embodiment of the present invention.

FIG. 25 is a diagram for explaining an interval set by a node according to the embodiment of this invention.

FIG. 26 is a block diagram showing a configuration of a conventional image display device.

[Explanation of symbols]

1 Display panel 2 scanning circuit 8 Pulse width modulation means 12 adder 14 Correction data calculation means 17 Reverse γ processing unit 19 Delay circuit 100a to 100c Lighting number counting means 101a to 101c register group 103 table memory 111 table memory 2 107a-107c comparator 123-124 decoder 1001 substrate 1002 cold cathode device 1003 row wiring (scan wiring) 1004 Column wiring (modulation wiring) 1007 face plate 1008 fluorescent film 2122 adder

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 642 G09G 3/20 642A (72) Inventor Hiroshi Saito 3-30-2 Shimomaruko, Ota-ku, Tokyo No. Canon Inc. (72) Inventor Kohei Inamura 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Takeshi Ikeda 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. In-house F-term (reference) 5C080 AA08 AA18 BB05 CC03 DD05 DD22 EE19 EE29 EE30 FF12 GG08 GG11 GG12 HH17 JJ01 JJ02 JJ03 JJ04 JJ05 JJ06 KK02 KK43

Claims (36)

[Claims] 1. An image forming element which is arranged in a matrix and is driven through a plurality of row wirings and column wirings and which is used for image formation, a scanning unit which sequentially selects and scans the row wirings, and image data. On the other hand, a correction image data calculating unit for calculating correction image data for reducing at least the voltage drop due to the resistance of the row wiring, and a modulation signal applied to the column wiring based on the correction image data are output. An image display device comprising a modulating means, wherein the corrected image data calculating means sets a plurality of discrete image data reference values for the image data and calculates discrete corrected image data for the image data reference values. A correction image for calculating the correction image data corresponding to the size of the image data by interpolating the output of the discrete correction image data calculation unit and the output of the discrete correction image data calculation unit An image display device comprising: a data interpolator. 2. The discrete corrected image data calculation unit sets a plurality of reference points in a horizontal direction along a selected row wiring, calculates corrected image data at the reference points, and The image display according to claim 1, wherein the data interpolation unit interpolates the output of the discrete corrected image data calculation unit in the horizontal direction to calculate corrected image data according to the horizontal display position of the image data. apparatus. 3. The discrete corrected image data calculation unit divides the selected row wiring into a plurality of regions, calculates a statistical amount of the image data for each divided region, and further calculates the statistical amount. The image display device according to claim 2, wherein the discrete corrected image data is calculated from 4. The statistic is obtained by, for each area, accumulating a result of comparing the image data for each area with a discrete image data reference value set for the image data. The image display device according to claim 3, wherein the image display device is a quantity. 5. The image display device according to claim 3, wherein the reference point is located at a boundary between the plurality of areas. 6. The image display device according to claim 3, wherein the reference point is located at the center of the area. 7. The discrete corrected image data calculation unit predictively calculates a voltage drop amount when the image data is modulated at a plurality of times in one horizontal scanning period corresponding to the image data reference value. The image display device according to claim 1, wherein the image display device comprises: 8. The image display device according to claim 7, wherein the discrete corrected image data calculation unit predictively calculates a voltage drop amount at the reference point. 9. The discrete corrected image data calculation unit is configured to modulate the image data at a plurality of times in one horizontal scanning period corresponding to the image data reference value, and then to the emission brightness of the image forming element. The image display device according to claim 1 or 2, wherein the image display device is used for predictive calculation. 10. The discrete corrected image data calculation unit predictively calculates a light emission luminance amount of an image forming element at the reference point when the image data is modulated. Image display device. 11. The discrete corrected image data calculation unit divides one horizontal scanning period into a plurality of time regions corresponding to the image data reference value, and a total amount of light emission luminance emitted in each time region. Is extended in the same manner as when there is no influence of the voltage drop, and the extended results of the respective time regions are integrated to calculate the discrete corrected image data. The image display device according to claim 1. 12. The discrete corrected image data calculation unit approximates that the amount of light emission luminance at the boundary of the time domain does not change when the time domain is extended, and the discrete corrected image data calculation unit The image display device according to claim 11, wherein an expansion amount is calculated. 13. The discrete corrected image data calculation unit divides the data range of the image data into a plurality of areas corresponding to the image data reference value, and determines the amount of light emission luminance emitted to each area. The discrete corrected image data is calculated by expanding each area so that the total amount is the same as when there is no influence of the voltage drop, and further integrating the expanded results of each area. The image display device according to item 1 or 2. 14. The discrete corrected image data calculation unit approximates that when the area is expanded, the amount of light emission luminance at the boundary of the area does not change due to the expansion,
14. The expansion amount of each area is calculated.
The image display device according to. 15. The number of image forming elements in the horizontal direction between a reference point set in the horizontal direction along the row wiring and an adjacent reference point can be expressed as an integer power of two. The image display device according to. 16. The image display device according to claim 1, wherein the interval between the image data reference values set for the image data can be expressed as an integer power of 2. 17. An image forming element arranged in a matrix, driven through a plurality of row wirings and column wirings, and used for image formation, a scanning means for sequentially selecting and scanning the row wirings, and image data. On the other hand, at least the correction data calculation means for calculating the correction data for reducing the influence of the voltage drop due to the resistance of the row wiring, the calculation means for calculating the correction data and the image data, and the output of the calculation means. An image display device including a modulation unit that outputs a modulation signal to be applied to the column wiring according to the correction data calculation unit, wherein the correction data calculation unit sets a plurality of discrete image data reference values for the image data, A discrete correction data calculation unit that calculates discrete correction data with respect to the image data reference value and an output of the discrete correction data calculation unit are interpolated to correspond to the data size of the image. The image display apparatus characterized by comprising: a correction data interpolation unit for calculating the correction data. 18. The discrete correction data calculation unit sets a plurality of reference points in the horizontal direction along a selected row wiring, calculates correction data at the reference points, and the correction data interpolation unit 18. The image display device according to claim 17, wherein the output of the discrete correction data calculation unit is interpolated in the horizontal direction to calculate the correction data according to the horizontal display position. 19. The discrete correction data calculation unit divides the row wiring into a plurality of regions, calculates a statistical amount of input image data for each of the divided regions, and further performs a discrete correction from the statistical amount. The image display device according to claim 18, wherein data is calculated. 20. The statistic is a result obtained by accumulating, for each area, a comparison result of image data and a discrete image data reference value set for the image data. 19. The image display device according to item 19. 21. The image display device according to claim 19, wherein the reference point is located at a boundary between the plurality of areas. 22. The image display device according to claim 19, wherein the reference point is located at the center of the area. 23. The discrete correction data calculation unit predictively calculates a voltage drop amount when the image data is modulated at a plurality of times in one horizontal scanning period corresponding to the image data reference value. The method according to claim 17 or 18, characterized in that
The image display device according to. 24. The image display device according to claim 23, wherein the discrete correction data calculation unit predictively calculates a voltage drop amount at the reference point. 25. The discrete correction image data calculation unit emits luminance of an image forming element when image data is modulated at a plurality of times in one horizontal scanning period corresponding to the image data reference value. The image display device according to claim 17 or 18, wherein the image display device predicts and calculates. 26. The discrete correction data calculation unit predictively calculates a light emission luminance amount of the image forming element at the reference point when the image data is modulated.
The image display device according to. 27. The discrete correction data calculation unit divides one horizontal scanning period into a plurality of time regions corresponding to the image data reference value, and a total amount of light emission luminance emitted in each time region is calculated. The discrete correction data is calculated by extending each time domain so as to be the same as when there is no influence of a voltage drop, and further integrating the extended results of each time domain. The image display device according to 17 or 18. 28. When expanding the time domain, the discrete correction data calculation unit approximates that the amount of light emission luminance at the boundary of the time domain does not change by the expansion, and expands each time domain. The image display device according to claim 27, wherein an amount is calculated. 29. The discrete correction data calculation unit divides a data range of image data into a plurality of areas corresponding to the image data reference value, and a total amount of emission luminance emitted to each area. 18. The discrete correction data is calculated by expanding each area so that the same as when there is no influence of voltage drop, and further integrating the expanded results of each area. Or the image display device according to item 18. 30. The discrete correction data calculation unit calculates the expansion amount of each area by approximating that the amount of light emission luminance at the boundary of the area does not change when the area is expanded. The image display device according to claim 29, wherein: 31. The number of image forming elements in the horizontal direction between a reference point set in the horizontal direction along the row wiring and an adjacent reference point can be expressed as an integer power of 2. The image display device according to. 32. The image display device according to claim 17, wherein the interval between the image data reference values set for the image data can be expressed as an integer power of 2. 33. The image display device according to claim 17, wherein the arithmetic means is an adder for adding the image data and the correction data. 34. The modulating means modulates the pulse width of a modulation signal waveform applied to each column wiring based on the corrected image data, according to any one of claims 1 to 33. Image display device. 35. The image display device according to claim 1, wherein the image forming element is an electron emitting element that emits electrons according to an applied modulation signal. 36. The image display device according to claim 35, wherein the electron-emitting device is a surface conduction electron-emitting device.