JP2003195797A - Device and method for displaying picture - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a picture display device capable of suitably correcting variation in driving conditions due to electric resistance in the matrix wiring of a display panel by using lesser hardware. <P>SOLUTION: The picture display device comprises a correction picture data calculation means for calculating correction picture data correcting an influence by a voltage drop caused by a resistance portion of the row wiring according to input picture data, an amplitude adjustment means having a function for adjusting the amplitude of the corrected picture data so that the corrected picture data calculated correspond to the input range of a modulation means, and the modulation means for modulating a driving waveform to be applied to the column wiring to the corrected picture data with the amplitude adjustment. Further, the amplitude adjustment means comprise a smoothing means provided with a filter in each row in order to prevent the display from being decreased in brightness when there are some rows having projectingly large corrected picture data in the display. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a display panel having a plurality of matrix-wired display elements to receive a television signal or a display signal from a computer or the like to display an image and a television receiver or display device. The present invention relates to an image display device and an image display method.

[0002]

2. Description of the Related Art Conventionally, there are n × m display elements arranged in a matrix in which m row wirings and n column wirings are arranged, and the row wirings are sequentially scanned. ,
By performing the modulation in the column direction, the element groups for one row are simultaneously driven.

In the case of driving in this way, there is a problem in the row wiring due to the voltage drop between the power feeding portions at both ends due to the electric resistance of the wiring.

Therefore, in order to correct the decrease in brightness due to the voltage drop due to the wiring resistance of the electric connection wiring to the display element, the correction data is calculated by a statistical calculation to obtain the electron beam required value. An image display device having a configuration for combining correction values is disclosed in Japanese Patent Laid-Open No. 8-248920.

The configuration of the image display device described in this publication is shown in FIG.
6 shows. The structure relating to the correction of data in this device is roughly as follows. First, 1 of the digital image signal
The luminance data for the lines is added up by the adder 206, and the correction rate data corresponding to this added value is read from the memory 207.

On the other hand, the digital image signal is serial / parallel converted in the shift register 204, held in the latch circuit 205 for a predetermined time, and then input to a multiplier 208 provided for each column wiring at a predetermined timing. In the multiplier 208, the luminance data is multiplied by the correction data read from the memory 207 for each column wiring, and the obtained corrected data is transferred to the modulation signal generator 209, and the modulated data corresponding to the corrected data is modulated. A signal is generated in the modulation signal generator 209, and an image is displayed on the display panel 201 based on this modulation signal.

Here, like the summing process of the luminance data for one line of the digital image signal in the summing device 206, statistical calculation processing such as calculating the sum or average of the digital image signals is performed. Correction is performed based on this value.

[0008]

However, in the above-mentioned conventional structure, a large-scale device such as a multiplier for each column wiring, a memory for outputting correction data, and a summing device for giving an address signal to the memory is required. I needed hardware.

The present invention has been made in order to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a drive condition based on electric resistance of a matrix wiring of a display panel with hardware having a simple structure. An object of the present invention is to provide an image display device and an image display method capable of suitably correcting fluctuation.

[0010]

In order to achieve the above object, in an image display device according to the present invention, the image display devices are arranged in a matrix and driven through a plurality of row wirings and column wirings to form an image. An image forming element to be used, a scanning means for sequentially selecting and scanning the row wirings, a modulation means connected to the column wirings, and a voltage drop caused by a resistance component of the row wirings with respect to input image data. Correction image data calculation means for calculating the correction image data in which the influence of the correction image data is corrected, and amplitude adjustment means for adjusting the amplitude of the correction image data so that the correction image data corresponds to the input range of the modulation means. The modulation means is an image display device for modulating a drive waveform applied to the column wiring in accordance with the corrected image data adjusted by the amplitude adjustment means, Is a row-direction maximum value detection function that detects the maximum in-row value of the corrected image data for each row wiring, a maximum value smoothing function that smoothes the detected maximum in-row value with a filter, and a smoothed value with a filter. And a smoothing maximum value detection function for detecting an in-frame maximum value from the in-row maximum value, and adjusting the amplitude of the corrected image data so that the in-frame maximum value corresponds to the maximum value of the input range of the modulating means. And a function of performing.

As another aspect of the image display device according to the present invention, an image forming element arranged in a matrix and driven through a plurality of row wirings and column wirings and used for image formation, and the row wirings. An image display device comprising a scanning means for sequentially selecting and scanning, and a modulation means connected to the column wiring, wherein the voltage drop of the voltage drop generated by the resistance component of the row wiring with respect to the input image data. Correction image data calculation means for calculating the correction image data with the influence corrected, and amplitude adjustment means for adjusting the amplitude of the correction image data so that the correction image data corresponds to the input range of the modulation means. The modulation means is an image display device that modulates a drive waveform applied to the column wiring in accordance with the corrected image data adjusted by the amplitude adjustment means, and the amplitude adjustment means The means has a row direction maximum value detection function for detecting the maximum in-row value of the corrected image data for each row wiring, and the detected maximum in-row value in each row so that the detected maximum in-row value falls within the maximum value of the input range of the modulation means. A row coefficient calculation function for calculating a row coefficient, a row coefficient smoothing function for smoothing the row coefficient by a filter, and a row coefficient minimum value detection for detecting a row coefficient minimum value in a frame from the row coefficient smoothed by the filter It has a function and a function of calculating a coefficient for amplitude adjustment based on the minimum value of the in-frame coefficient and adjusting the amplitude of the corrected image data.

It is preferable that the amplitude adjusting means calculates a coefficient for performing amplitude adjustment from the maximum value in the frame and multiplies the output of the corrected image data by the coefficient.

The amplitude adjusting means calculates a coefficient for performing amplitude adjustment from the maximum value in the frame, multiplies the input image data by the coefficient for performing amplitude adjustment, and the corrected image data calculating means. Preferably calculates corrected image data for the image data that has been multiplied.

It is preferable that the amplitude adjusting means multiplies the output of the corrected image data calculating means by a coefficient for adjusting the amplitude.

The amplitude adjusting means multiplies the input image data by a coefficient for adjusting the amplitude, and the corrected image data calculating means calculates corrected image data for the multiplied image data. Is preferred.

The filter is preferably a low pass filter.

The filter is preferably a logical filter.

The corrected image data calculating means predicts and calculates, in the spatial direction and the time direction, the amount of voltage drop that should occur on the row wiring during one horizontal scanning period with respect to the input image data. And a means for calculating corrected image data obtained by correcting the input image data based on the amount of voltage drop.

The correction image data calculating means discretely predicts and calculates the amount of voltage drop that should occur on the row wiring in one horizontal scanning period in the spatial direction and the time direction with respect to the input image data. And means for calculating corrected image data obtained by correcting the input image data from the calculated discrete voltage drop amount.

The coefficient G for adjusting the amplitude is preferably G = INMAX / MAX, where MAX is the maximum value in the frame for each frame and INMAX is the maximum value in the input range of the modulating means. Is.

The coefficient G for adjusting the amplitude is MAX for the maximum value in the frame for each frame, INMAX for the maximum value of the input range of the modulation means, and the coefficient for the frame one frame before the current frame. When Go, it is preferable that G = INMAX / MAX × Go.

As the coefficient G for performing the amplitude adjustment, a row coefficient for each row calculated from the maximum value in the previous term is G1, a maximum value in the row for each row is MAX1, and a maximum value in the input range of the modulating means is a maximum value. If INMAX, Gl = INMAX / MAX1 and the row coefficient Gl is smoothed by the filter, the frame inner coefficient minimum value sGl is detected from the smoothed output for each frame, and the frame inner coefficient minimum value sGl is detected. It is preferable that the coefficient G is obtained.

As the coefficient G for adjusting the amplitude of the input image data, the row coefficient for each row calculated from the maximum value in the row is Gl ', and the maximum value in the row is MAX.
l, the maximum value of the input range of the modulating means is INMAX, and the coefficient in the frame immediately before the current frame is G
If it is o, Gl ′ = INMAX / MAX1 × Go, the row coefficient Gl ′ is smoothed by the filter, and the frame inner coefficient minimum value sGl ′ is detected for each frame from the smoothed output, and the frame inner row is detected. It is preferable that the coefficient minimum value sGl ′ be the coefficient G.

As the coefficient G for adjusting the amplitude of the input image data, the row coefficient for each row calculated from the maximum value in the previous row is Gl, and the maximum value in the row for each row is MAX.
l, where the maximum value of the input range of the modulating means is INMAX, then Gl = INMAX / MAXl, and the row coefficient Gl is smoothed by the filter, and the smoothed frame output coefficient minimum value sGl for each frame from the smoothed output. Is detected, and when the coefficient in the frame immediately before the current frame is Go, it is preferable that G = sGl x Go.

It is preferable that the coefficient for adjusting the amplitude is a coefficient of the current frame in the amplitude adjusting means obtained by calculating the coefficient for each of a plurality of frames before the current frame.

As the coefficient for adjusting the amplitude, a value calculated by calculating the coefficient for each of a plurality of frames before the current frame and smoothing each coefficient by a low-pass filter in the frame direction is used. , The coefficient of the current frame is preferable.

The amplitude adjusting means preferably includes a limiter for limiting the maximum value of the input data to the modulating means.

The limiter includes a preset limit value and a comparator for comparing the output data whose amplitude is adjusted by the amplitude adjusting means with the output data and the limit value. If the limit value is smaller than the adjusted output data,
If the limit value is output and the limit value is larger than the amplitude-adjusted output data of the corrected image data, the amplitude-adjusted output data of the corrected image data is preferably output.

It is preferable that the modulating means is a pulse width modulating means for performing modulation by varying the pulse width of the voltage pulse waveform applied to each column wiring according to the input of the modulating means.

The image forming element may be a cold cathode element.

The cold cathode device may be a surface conduction electron-emitting device.

Further, in the image display method according to the present application, the image forming elements used for image formation, which are arranged in a matrix and driven through a plurality of row wirings and column wirings, and the row wirings are provided. Scanning means for sequentially selecting and scanning, modulation means connected to the column wiring, and correction image data in which the influence of voltage drop caused by the resistance of the row wiring is corrected with respect to the input image data is calculated. The image display device includes a correction image data calculating unit and an amplitude adjusting unit that adjusts the amplitude of the correction image data so that the correction image data corresponds to the input range of the modulating unit. In accordance with the corrected image data adjusted by the amplitude adjusting means, the drive waveform applied to the column wiring is modulated, and the amplitude adjusting means, for each row wiring, in the row of the corrected image data. A large value is detected, the detected maximum value in the row is smoothed by a filter, the maximum value in the frame is detected from the maximum value in the row smoothed by the filter, and the maximum value in the frame is the input range of the modulation means. The amplitude of the corrected image data is adjusted so as to correspond to the maximum value of, and the image is displayed.

Image forming elements arranged in a matrix and driven through a plurality of row wirings and column wirings and used for image formation, scanning means for sequentially selecting and scanning the row wirings, and connection to the column wirings. And a correction image data calculation unit for calculating the correction image data for correcting the influence of the voltage drop caused by the resistance of the row wiring with respect to the input image data. An amplitude adjusting means for adjusting the amplitude of the corrected image data so as to correspond to the input range of the means, and the modulating means responds to the corrected image data adjusted by the amplitude adjusting means. And modulates the drive waveform applied to the column wiring, and the amplitude adjusting unit detects the maximum in-row value of the corrected image data for each row wiring. The row coefficient is calculated for each row so that it falls within the maximum value of the input range of the modulation means, the row coefficient is smoothed by a filter, and the frame inner row coefficient minimum value is detected from the row coefficient smoothed by the filter, It is characterized in that a coefficient for performing amplitude adjustment is calculated based on the minimum value of the in-frame coefficient and the amplitude of the corrected image data is adjusted to display an image.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be illustratively described in detail below with reference to the drawings. However,
The dimensions, materials, and components of the components described in this embodiment
The shape and the relative arrangement thereof are not intended to limit the scope of the present invention thereto unless otherwise specified.

(First Embodiment) First, a first embodiment of the present invention will be described.

(Overall Outline) In a display device in which cold cathode elements are arranged in a simple matrix, there is a phenomenon that a voltage drop occurs due to a current flowing into a scanning wiring and a wiring resistance of the scanning wiring, and a display image is deteriorated. Therefore, the image display device according to the embodiment of the present invention is provided with a processing circuit that appropriately corrects the influence of the voltage drop in the scanning wiring on the display image, and realizes it with a relatively small circuit scale. Configured.

The correction circuit predicts and calculates deterioration of a display image caused by a voltage drop according to input image data, obtains correction data for correcting the deterioration, and corrects the input image data.

As an image display device having such a correction circuit built-in, the inventors have intensively studied an image display device of the type described below.

In describing the present invention below,
First, the appearance of the display panel of the image display device according to the embodiment of the present invention, the electrical connection of the display panel, the characteristics of the surface conduction electron-emitting device, the driving method of the display panel, when displaying an image by such a display panel. The mechanism of the reduction of the drive voltage due to the electric resistance of the scan wiring, and the correction method and apparatus for the influence of the voltage drop will be described.

(Overview of Image Display Device) FIG. 1 is a perspective view of a display panel used in the image display device according to the present embodiment, in which a part of the panel is cut away to show the internal structure. . In the figure, 1005 is a rear plate, 1006 is a side wall, 1007 is a face plate, and 1005-
1007 forms an airtight container for maintaining a vacuum inside the display panel.

The rear plate 1005 has a substrate 1001.
, But the cold cathode device 1002 is fixed on the substrate.
Are formed by N × M. Row wiring (scan wiring) 100
3, the column wiring (modulation wiring) 1004 and the cold cathode device are shown in FIG.
Are connected like.

Such a connection structure is called a simple matrix.

A fluorescent film 1008 is formed on the lower surface of the face plate 1007. Since the image display device according to the present embodiment is a color display device, the fluorescent film 1
Red, green, which is used in the field of CRT
Phosphors of three primary colors of blue are painted separately.

The fluorescent material is formed in a matrix corresponding to each pixel (picture element) on the rear plate 1005, and the pixel is arranged with respect to the position where the emitted electrons (emission current) from the cold cathode element are irradiated. Configured to form.

A metal back 1 is formed on the lower surface of the fluorescent film 1008.
009 is formed.

Hv is a high voltage terminal and is a metal back 100.
9 is electrically connected. By applying a high voltage to the Hv terminal, a high voltage is applied between the rear plate 1005 and the face plate 1007.

In this embodiment, a surface conduction electron-emitting device was manufactured as a cold cathode device in the above display panel. A field emission type element can also be used as the cold cathode element. The present invention can also be applied to an image display device in which an element that emits light by itself such as an EL element other than the cold cathode element is connected to a matrix wiring and driven.

(Characteristics of Surface Conduction Type Emitting Element) In the surface conduction type emitting element, as shown in FIG. 3, (emission current Ie) vs. (element applied voltage Vf) characteristics, and (element current If) vs. (element applied voltage). Vf) characteristic. Since the emission current Ie is significantly smaller than the device current If and it is difficult to draw the same current scale, the two graphs are shown on different scales.

That is, the emission current Ie has the following three characteristics.

First, a certain voltage (this is the threshold voltage Vth
When the above voltage is applied to the element, the emission current Ie rapidly increases, while the emission current Ie is hardly detected at a voltage lower than the threshold voltage Vth.

That is, it is a nonlinear element having a clear threshold voltage Vth with respect to the emission current Ie.

Secondly, since the emission current Ie changes depending on the voltage Vf applied to the element, the magnitude of the emission current Ie can be controlled by changing the voltage Vf.

Thirdly, since the cold cathode element has a high-speed response, the emission current I depends on the application time of the voltage Vf.
The release time of e can be controlled.

By utilizing the above characteristics, the surface conduction electron-emitting device can be preferably used in a display device. For example, in the image display device using the display panel shown in FIG. 1, if the first characteristic is used, it is possible to sequentially scan the display screen for display. That is, a voltage equal to or higher than the threshold voltage Vth is appropriately applied to the driven element according to the desired light emission luminance, and the threshold voltage Vt is applied to the non-selected element.
A voltage less than h is applied. By sequentially switching the elements to be driven, it is possible to sequentially scan the display screen for display.

By utilizing the second characteristic,
By the voltage Vf applied to the element, the emission brightness of the phosphor can be controlled and an image can be displayed.

By utilizing the third characteristic,
The light emission time of the phosphor can be controlled by the time for which the voltage Vf is applied to the element, and an image can be displayed.

In the image display device of the present invention, the amount of the electron beam of the display panel is modulated by using the above third characteristic.

(Display Panel Driving Method) The display panel driving method of the present invention will be specifically described with reference to FIG.

FIG. 4 shows an example of voltages applied to the voltage supply terminals of the scanning wiring and the modulation wiring when the display panel of the image display device according to the embodiment of the present invention is driven.

Now, the horizontal scanning period I is a period in which the pixels in the i-th row emit light.

In order to cause the pixel in the i-th row to emit light,
The scanning wiring of the i-th row is selected and its voltage supply terminal D
The selection potential Vs is applied to xi. Further, the voltage supply terminals Dxk (k = 1, 2, ... N, where k ≠ i) of the other scanning lines are set in the non-selected state and the non-selection potential Vns is applied.

In this example, the selection potential Vs is set to -0.5V _SEL which is half the voltage V _SEL shown in FIG. 3, and the non-selection potential Vs is set.
ns is the GND potential.

A pulse width modulation signal having a voltage amplitude Vpwm was supplied to the voltage supply terminal of the modulation wiring. Conventionally, the pulse width of the pulse width modulation signal supplied to the j-th modulation wiring is conventionally i-th row, j-th
The pulse width modulation signal according to the size of the image data of each pixel is supplied to all the modulation wirings, which is determined according to the size of the image data of the pixel of the column.

In the present invention, as will be described later, the pulse width of the pulse width modulation signal supplied to the j-th modulation wiring is the image to be displayed in order to correct the decrease in brightness due to the influence of the voltage drop. Is determined according to the size of the image data of the pixel at the i-th row and the j-th column and the correction amount thereof, and the pulse width modulation signal is supplied to all the modulation wirings. In this embodiment, the voltage Vpwm is set to + 0.5V _SEL .

As shown in FIG. 3, the surface conduction electron-emitting device emits electrons when the voltage V _SEL is applied across the device, but does not emit electrons at a voltage lower than Vth.

Further, the voltage Vth is, as shown in FIG.
It is characterized by being larger than 0.5V _SEL .

Therefore, no electrons are emitted from the surface conduction electron-emitting device connected to the scanning wiring to which the non-selection potential Vns is applied.

Similarly, during a period in which the output of the pulse width modulation means is at the ground potential (hereinafter, referred to as a period in which the output is "L"), both ends of the surface conduction electron-emitting device on the selected scan wiring are detected. Since the voltage applied to Vs is Vs, no electrons are emitted.

From the surface conduction electron-emitting device on the scanning wiring to which the selection potential Vs is applied, the output of the pulse width modulation means is V.
Pwm period (hereinafter referred to as "H" period of output)
The electrons are emitted according to the. When the electrons are emitted, the above-mentioned phosphor emits light in accordance with the amount of the emitted electron beam, so that it is possible to emit the brightness corresponding to the emitted time.

The image display device according to the embodiment of the present invention also includes
An image is displayed by line-sequential scanning and pulse width modulation of such a display panel.

(Regarding Voltage Drop in Scanning Wiring) As described above, the fundamental problem faced by the image display device is that the voltage drop in the scanning wiring of the display panel causes the potential on the scanning wiring to rise, and This means that the voltage applied to the conduction type emission element is reduced, so that the emission current from the surface conduction type emission element is reduced. The mechanism of this voltage drop will be described below.

The device current for one device of the surface conduction electron-emitting device is about several hundred μA when the voltage V _SEL is applied, although it depends on the design specifications and manufacturing method of the surface conduction electron-emitting device.

Therefore, when only one pixel on the selected scanning line is made to emit light and the other pixels are not made to emit light in a certain horizontal scanning period, the device current flowing from the modulation wiring to the scanning wiring of the selected row is 1 Since it is only the current for the pixel (that is, the above-mentioned several 100 μA), there is almost no voltage drop, and the emission brightness does not decrease.

However, in the case where all the pixels in the selected row are made to emit light in a certain horizontal scanning period, the current for all the pixels flows from all the modulation wirings to the scanning wirings in the selected state. The sum is several hundred mA
The number was several A, and a voltage drop occurred on the scanning wiring due to the wiring resistance of the scanning wiring.

If a voltage drop occurs on the scanning wiring, the voltage applied across the surface conduction electron-emitting device will decrease. For this reason, the emission current emitted from the surface conduction electron-emitting device is reduced, and as a result, the emission brightness is reduced.

Specifically, consider a case where a white cross pattern is displayed on a black background as shown in FIG. 5A as a display image.

Then, when the row L in the same drawing is driven, since the number of lit pixels is small, almost no voltage drop occurs on the scanning wiring of that row. As a result, a desired amount of emission current is emitted from the surface conduction electron-emitting device of each pixel, and light can be emitted with a desired brightness.

On the other hand, when driving the row L'in the figure, since all the pixels are turned on at the same time, a voltage drop occurs on the scanning wiring, and the emission current from the surface conduction type emission element of each pixel is generated. Decrease. As a result, the luminance of the line of row L'is reduced.

As described above, the influence of the voltage drop changes due to the difference in the image data for each horizontal line. Therefore, when displaying the cross pattern as shown in FIG. An image like this had been displayed.

This phenomenon is not limited to the cross pattern, but occurs even when a window pattern or a natural image is displayed, for example.

Further, more complicatedly, the magnitude of the voltage drop has the property of changing within one horizontal scanning period by performing modulation by pulse width modulation.

The pulse width modulation signal supplied to each column is shown in FIG.
In the case of outputting a pulse width modulation signal whose pulse width depends on the size of the input data and whose rising edge is synchronized with respect to the input data as shown in, it depends on the input image data In one horizontal scanning period, the number of pixels that are lit is large immediately after the rising of the pulse, and then the lights are turned off in order from a place with low brightness.
The number of lit pixels decreases with time in one horizontal scanning period.

Therefore, the magnitude of the voltage drop generated on the scanning wiring also tends to decrease gradually toward the beginning of one horizontal scanning period.

Since the output of the pulse width modulation signal changes at each time corresponding to one gradation of modulation, the temporal change of the voltage drop also changes at each time corresponding to one gradation of the pulse width modulated signal.

The voltage drop in the scanning wiring has been described above.

(Calculation Method of Voltage Drop) Next, a method of correcting the influence of the voltage drop will be described in detail.

In order to obtain the correction amount for reducing the influence of the voltage drop, the inventors first of all develop the hardware for predicting the magnitude of the voltage drop and its change with time in the first step. Thought necessary.

However, the display panel of the image display device according to the embodiment of the present invention is generally provided with thousands of modulation wirings, and the voltage drop at the intersection of all the modulation wirings and the scanning wirings is reduced. It was very difficult to calculate, and it was not realistic to make hardware to calculate it in real time.

On the other hand, as a result of the investigation of the voltage drop by the inventors, it has been found that the following features are provided.

I) At a certain point in one horizontal scanning period, the voltage drop generated on the scan wiring is a spatially continuous amount on the scan wiring, which is a very smooth curve.

Ii) Although the magnitude of the voltage drop varies depending on the display image, it changes at each time corresponding to one gradation of pulse width modulation, and is generally larger at the rising portion of the pulse and temporally. It either becomes smaller or maintains its size. That is, the driving method as shown in FIG. 4 does not increase the magnitude of the voltage drop in one horizontal scanning period.

Therefore, in view of the above-mentioned characteristics, the inventors examined whether the calculation amount can be reduced by performing the calculation in a simplified manner by the following approximate model.

First, from the feature of i), when calculating the magnitude of the voltage drop at a certain time, it is approximated by a degenerate model in which thousands of modulation wirings are concentrated into several to several tens of modulation wirings. We examined whether it can be simplified and calculated.

This will be described in detail in the calculation of the voltage drop by the following degenerate model.

Further, from the characteristics mentioned in ii), it is possible to roughly predict the time change of the voltage drop by providing a plurality of times in one horizontal scanning period and calculating the voltage drop at each time. did.

Specifically, the time change of the voltage drop was roughly predicted by calculating the voltage drop by the degenerate model described below for a plurality of times.

(Calculation of voltage drop by degenerate model) FIG. 6
(A) is a figure for demonstrating the block and node at the time of performing degeneration.

In the figure, for simplification of the drawing, only the selected scanning wiring, each modulation wiring, and the surface conduction electron-emitting device connected to the intersections thereof are shown.

At a certain time in one horizontal scanning period, the lighting state of each pixel on the selected scanning wiring (that is, whether the output of the modulating means is "H" or "L"). Is known.

In this lighting state, the element current flowing from each modulation wiring to the selected scanning wiring is set to Ifi (i =
1, 2 ,. ． ． N and i are defined as column numbers).

Further, as shown in the figure, a block is defined by grouping the n modulation wirings, the intersections of the selected scanning wirings and the surface conduction electron-emitting devices arranged at the intersections thereof. . In this example, the blocks are divided into four blocks.

A position called a node is set at the boundary position of each block. A node is a horizontal position (reference point) for discretely calculating the amount of voltage drop that occurs on the scanning wiring in the degenerate model.

In this example, node 0 is placed at the block boundary position.
~ 5 nodes of node 4 were set.

FIG. 6B is a diagram for explaining the degenerate model.

In the degenerate model, n modulation wirings included in one block in FIG. 10A are degenerated to one, and one degenerated modulation wiring is positioned at the center of the block of the scanning wirings. Connected to.

A current source is connected to the modulation wiring of each degenerated block, and the sum total IF0 to IF3 of the current in each block flows from each current source.

That is, IFj (j = 0, 1, ... 3)
Is

[Equation 1] Is a current (Equation 1) expressed as

Further, the potentials at both ends of the scanning wiring are shown in FIG.
However, in the degenerate model, the current flowing into the scanning wiring selected from the modulation wiring is modeled by the above current source, and Vs is Vs in the scanning wiring on the scanning wiring. This is because the voltage drop amount of each part can be calculated by calculating the voltage (potential difference) of each part using the power supply part as a reference (GND) potential. That is, it is defined as the reference potential for calculating the voltage drop.

The surface conduction electron-emitting device is omitted regardless of the presence or absence of the surface conduction electron-emitting device as long as an equivalent current flows from the column wiring when viewed from the selected scanning wiring. This is because the generated voltage drop itself does not change. Therefore, here, the surface conduction electron-emitting device is omitted by setting the current value flowing from the current source of each block to the total current value of the device currents in each block (Equation 1).

Further, the wiring resistance of the scanning wiring of each block is set to n times the wiring resistance r of the scanning wiring of one section (here, one section is the intersection of the scanning wiring with a certain column wiring and its adjacent area. In this example, the wiring resistance of the scanning wiring in one section is assumed to be uniform.

In such a degenerate model, the voltage drop amounts DV0 to DV generated at each node on the scanning wiring.
4 can be easily calculated by the following product-sum formula.

[0112]

[Equation 2] Becomes

That is,

[Equation 3] Is established.

However, aij is a voltage generated at the i-th node when a unit current is injected into only the j-th block in the degenerate model (hereinafter, this is defined as aij).

The above aij can be easily derived as follows according to Kirchhoff's law.

That is, in FIG. 6B, the wiring resistance from the current source of the block i to the supply terminal on the left side of the scanning wiring is rli (i = 0,1,2,3), to the supply terminal on the right side. The wiring resistance is defined as rri (i = 0, 1, 2, 3), and the wiring resistance between the block 0 and the left supply terminal and the wiring resistance between the block 3 and the right supply terminal are both defined as rt. If

[Equation 4] Is established.

Furthermore,

[Equation 5] far.

Then, aij is

[Equation 6] As described above, it can be easily derived as in (Equation 3). However, in (Equation 3), A // B is a symbol representing the resistance value of the resistance A and the resistance B in parallel, and A // B = A × B / (A +
B).

Even if the number of blocks is not 4, (Equation 2) can be easily calculated according to Kirchhoff's law by considering the definition of aij. Further, even in the case where the power supply terminals are not provided on both sides of the scanning wiring and only one side is provided as in this example, the calculation can be easily performed by performing the calculation according to the definition of aij.

The parameter aij defined by (Equation 3) does not need to be recalculated each time the calculation is performed.
It should be calculated once and stored as a table.

Further, with respect to the total currents IF0 to IF3 of each block defined by (Equation 1),

[Equation 7] The approximation shown in was performed.

However, in the above equation, Count i is a variable that takes 1 when the i-th pixel on the selected scanning line is in the lighting state and takes 0 when it is in the unlit state.

IFS is an amount obtained by multiplying the element current IF flowing when the voltage V _SEL is applied across both ends of one surface conduction electron-emitting device by a coefficient α having a value between 0 and 1.

That is,

[Equation 8] Was defined.

According to (Equation 4), the element current proportional to the number of lighting in each block flows into the selected scanning line from the column wiring of each block. At this time, the element current IF of one element is multiplied by the coefficient α to obtain the element current IF of one element.
The reason for setting S is that the amount of the device current is reduced due to the increase in the voltage of the scanning wiring due to the voltage drop.

FIG. 6C shows an example of the result of calculating the voltage drop amounts DV0 to DV4 of each node by the degeneration model in a certain lighting state.

Since the voltage drop has a very smooth curve, it is assumed that the voltage drop between the nodes approximately takes the value shown by the dotted line in the figure.

As described above, by using this degenerate model, it is possible to calculate the voltage drop at the node position at a desired time point with respect to the input image data.

As described above, the voltage drop amount in a certain lighting state was simply calculated using the degeneration model.

The voltage drop generated on the selected scanning wiring changes with time within one horizontal scanning period. As described above, with respect to some times during one horizontal scanning period, the voltage drop occurs at that time. The lighting state was calculated and the voltage drop was calculated using the degeneration model for the lighting state.

The number of lights in each block at a certain point in one horizontal scanning period can be easily obtained by referring to the image data of each block.

As an example, assume that the number of bits of input data to the pulse width modulation circuit is 8 bits, and the pulse width modulation circuit outputs a linear pulse width with respect to the size of the input data. And

That is, when the input data is 0, the output becomes "L", when the input data is 255, "H" is output during one horizontal scanning period, and when the input data is 128, the one horizontal scanning period is output. It is assumed that "H" is output in the first half period and "L" is output in the second half period.

In such a case, the number of lights at the start time of the pulse width modulation signal (the rising time in the example of the modulation signal of this example) is counted when the input data to the pulse width modulation circuit is larger than 0. It can be easily detected.

Similarly, the number of lights at the central time of one horizontal scanning period can be easily detected by counting the number of input data to the pulse width modulation circuit which is larger than 128.

In this way, by comparing the image data with a certain threshold value and counting the number of true outputs of the comparator, the number of lightings at any time can be easily calculated.

Here, in order to simplify the following description, a time amount called a time slot is defined.

That is, the time slot represents the time from the rise of the pulse width modulated signal in one horizontal scanning period, and the time slot = 0 represents the time immediately after the start time of the pulse width modulated signal. Define as a thing.

Time slot = 64 is defined as a time when 64 gradations have elapsed from the start time of the pulse width modulation signal.

Similarly, time slot = 128 is defined as a time when 128 gradations have elapsed from the start time of the pulse width modulation signal.

In this example, the pulse width modulation has been described in which the pulse width from the rising time is used as the reference, and the pulse width is modulated based on the falling time of the pulse. However, it goes without saying that the same can be applied, although the advancing direction of the time axis is opposite to the advancing direction of the time slot.

(Calculation of Correction Data from Voltage Drop Amount) As described above, the time change of the voltage drop during one horizontal scanning period is approximately and discretely calculated by repeatedly performing the degeneracy model. I was able to.

FIG. 7 shows an example in which the voltage drop is repeatedly calculated for certain image data, and the time change of the voltage drop in the scanning wiring is calculated (the voltage drop shown here and its time change are , An example for one image data, and it is natural that the voltage drop for another image data has another change.

In the figure, time slots = 0, 64, 12
The voltage drop at each time was calculated discretely by applying the degenerate model to each of the four time points of 8, 192.

In FIG. 7, the voltage drop amount at each node is connected by a dotted line, but the dotted line is shown to make the diagram easy to see, and the voltage drop calculated by this degenerate model is □, ○, ●. , Δ were calculated discretely at the positions of the nodes.

The inventors examined the method of calculating the correction data for correcting the image data from the voltage drop amount, as the next step after the magnitude of the voltage drop and its change over time can be calculated.

FIG. 8 is a graph in which the emission current emitted from the surface conduction electron-emitting device in the lighting state is estimated when the voltage drop shown in FIG. 7 occurs on the selected scanning wiring.

The vertical axis represents the amount of the emission current at each position for each time in percentage, with the magnitude of the emission current emitted when there is no voltage drop being 100%, and the horizontal axis represents the horizontal position. There is.

As shown in FIG. 8, the horizontal position of node 2
At (reference point), the emission current at time slot = 0 is Ie0, the emission current at time slot = 64 is Ie1, the emission current at time slot = 128 is Ie2, and the emission current at time slot = 192 is emission Let the current be Ie3.

The figure is calculated from the graph of the voltage drop amount of FIG. 7 and the “driving voltage vs. emission current” of FIG. Specifically, it is simply a mechanical plot of the value of the emission current when a voltage obtained by subtracting the voltage drop amount from the voltage V _SEL is applied.

Therefore, the figure only means the current emitted from the surface conduction electron-emitting device in the lighting state,
The surface conduction electron-emitting device in the off state does not emit current.

A method of calculating correction data for correcting image data from the amount of voltage drop will be described below.

(Correction data calculation method) FIG. 9 (a),
8B and 8C are diagrams for explaining a method for calculating correction data of the voltage drop amount from the time change of the emission current of FIG. The figure shows an example of calculating correction data for image data of size 64.

The emission amount of luminance is nothing but the emitted charge amount obtained by temporally integrating the emission current by the emission current pulse.
Therefore, in the following, a description will be given based on the amount of emitted charges when considering the change in luminance due to the voltage drop.

Now, assuming that the emission current when there is no influence of the voltage drop is IE and the time corresponding to one gradation of the pulse width modulation is Δt, the emission current pulse when the image data is 64 is emitted by the emission current pulse. The amount of emitted charge Q0 to be performed is obtained by multiplying the amplitude IE of the emitted current pulse by the pulse width (64 × Δt),

[Equation 9] Can be expressed as

However, in reality, a phenomenon occurs in which the emission current decreases due to the voltage drop on the scan wiring.

The amount of electric charge emitted by the emission current pulse considering the influence of the voltage drop can be calculated approximately as follows. That is, if the emission currents of the time slots = 0 and 64 of the node 2 are Ie0 and Ie1, respectively, and the emission current between 0 and 64 is approximated to change linearly between Ie0 and Ie1, the emission during this period is approximated. The charge amount Q1 is shown in FIG.
The area of the trapezoid.

That is,

[Equation 10] Can be calculated as

Next, as shown in FIG. 9C, when the pulse width is extended by DC1 in order to correct the decrease in the emission current due to the voltage drop, it is assumed that the effect of the voltage drop can be removed.

When the voltage drop is corrected and the pulse width is extended, the amount of emission current in each time slot is considered to change, but for simplification, here,
As shown in FIG. 9C, it is assumed that the emission current is Ie0 at time slot = 0 and the emission current is Ie1 at time slot = (64 + DC1).

Further, the emission current between the time slot 0 and the time slot (64 + DC1) is approximated to take a value on a line connecting the emission currents at two points with a straight line.

Then, the amount of emitted charge Q2 due to the corrected emission current pulse is

[Equation 11] Can be calculated as

If this is equal to Q0, then

[Equation 12] Becomes

If this is solved for DC1,

[Equation 13] Becomes

In this way, the correction data when the image data is 64 was calculated.

That is, the size of the position of node 2 is 64
For the image data of, as described in (Equation 9), the CD
The correction amount CData only needs to be added by ata = DC1.

FIG. 10 shows an example in which correction data for image data having a size of 128 is calculated from the calculated voltage drop amount.

Now, when there is no influence of the voltage drop, the amount of emitted charge Q3 to be emitted by the emission current pulse when the image data is 128 is

[Equation 14] On the other hand, the input charge amount due to the actual emission current pulse, which is affected by the voltage drop, can be approximately calculated as follows.

That is, the time slot of node 2 =
The emission current amounts of 0, 64, and 128 are Ie0 and Ie, respectively.
1 and Ie2. The emission current between 0 and 64 is I
If it is approximated to change linearly between e0 and Ie1 and change on a line connecting Ie1 and Ie2 with a straight line between 64 and 128, the emission charge during the time slot from 0 to 128 is approximated. The quantity Q4 is the sum of the areas of the two trapezoids in FIG.

That is,

[Equation 15] Can be calculated as

On the other hand, the correction amount of the voltage drop was calculated as follows.

The period corresponding to time slots 0 to 64 is defined as period 1, and the period corresponding to 64 to 128 is defined as period 2.

When the correction is applied, the portion of the period 1 is DC1.
Is extended to period 1'and the portion of period 2 is DC2
I think that it will be extended only in the period 2 '.

At this time, it is assumed that the amount of emitted charges becomes the same as Q0 described above by being corrected in each period.

It is needless to say that the emission currents at the beginning and the end of each period change due to the correction, but here it is assumed that they do not change in order to simplify the calculation.

That is, the emission current at the beginning of the period 1'is I
e0, the emission current at the end of period 1'is Ie1, period 2 '
The emission current at the beginning of the period is Ie1 and the emission current at the end of the period 2'is Ie2.

Then, DC1 can be calculated in the same manner as (Equation 9).

DC2 uses the same concept as above.

[Equation 16] Can be calculated as

As a result, the size of the position of node 2 is 12
For the image data of 8,

[Equation 17] Only the correction amount CData should be added.

FIG. 11 shows an example in which correction data for image data of size 192 is calculated from the calculated voltage drop amount.

Now, when the image data is 192, the emission charge amount Q5 expected by the emission current pulse is

[Equation 18] Becomes

On the other hand, the amount of charge emitted by the actual pulse of the emission current, which is affected by the voltage drop, can be approximately calculated as follows.

That is, the time slot of node 2 = 0
Let Ie0 be the emission current at time, Ie1 be the emission current at time slot = 64, Ie2 be the emission current at time slot = 128, and Ie3 be the emission current at time slot = 192. Emission currents of Ie0 and Ie
1 linearly changes, and between 64 and 128 changes on a line connecting Ie1 and Ie2 with a straight line, 128 to 19
2 can be approximated as changing on a line connecting Ie2 and Ie3 with a straight line, the input charge amount Q6 during the time slot from 0 to 192 is the area of the three trapezoids in FIG. Becomes

That is,

[Formula 19] On the other hand, the correction amount of the voltage drop was calculated as follows.

The period corresponding to time slots 0 to 64 is period 1, and the period corresponding to time slots 64 to 128 is period 2, 128.
The period corresponding to 192 is defined as period 3.

Similarly to the above, after the correction, the portion of the period 1 is extended by DC1 and extended to the period 1 ', the portion of the period 2 is extended by DC2 and extended to the period 2', and the portion of the period 3 is expanded. It is assumed that the portion is extended by DC3 and extended in the period 3 '.

At this time, it is assumed that the amount of emitted charges becomes the same as Q0 described above by performing the correction during each period.

Further, it is assumed that the emission currents at the beginning and the end of each period do not change before and after the correction.

That is, the emission current at the beginning of the period 1'is I
e0, the emission current at the end of period 1'is Ie1, period 2 '
The emission current at the beginning of the period is Ie1, the emission current at the end of the period 2'is Ie2, the emission current at the beginning of the period 3'is Ie2, and the emission current at the end of the period 3'is Ie3.

Then, DC1 and DC2 can be calculated similarly to (Equation 9) and (Equation 12), respectively.

As for DC3,

[Equation 20] Can be calculated as

As a result, the size of the position of node 2 is 19
As the correction data CData to be added to the image data of 2,

[Equation 21] Should be added.

As described above, the correction data CDat of the image data 64, 128, 192 for the position of the node 2 is obtained.
a was calculated.

When the pulse width is 0, of course, there is no effect of the voltage drop on the emission current, so the correction data is set to 0 and the correction data CData is added to the image data.
Is also 0.

Note that 0, 64, 128, 19
The reason why correction data is calculated for discrete image data as in 2 is to reduce the amount of calculation.

That is, if the same calculation is performed for all image data, the amount of calculation becomes very large, and the amount of hardware for performing the calculation becomes very large.

On the other hand, at a certain node position, the larger the image data, the larger the correction data tends to be. As a result, when calculating correction data for arbitrary image data, if the points near the image data for which correction data has already been calculated and the points are interpolated by linear approximation, the amount of calculation will be greatly reduced. This is because you can This interpolation will be described in detail when the discrete correction data interpolation means is described.

If the same idea is applied to the positions of all the nodes, the correction data of image data = 0, 64, 128, 192 can be calculated at the positions of all the nodes.

The discrete image data for which the correction data is calculated in this way is called an image data reference value.

In this example, the time slots are 0, 64, 12
By applying the degeneration model to the four points of 8 and 192 and calculating the amount of voltage drop at each time, the correction data is also corrected with respect to the four image data reference values of the image data of 0, 64, 128, and 192. I was able to request the data.

However, it is preferable to make the time interval for calculating the voltage drop fine by the degenerate model, so that the time change of the voltage drop can be handled more accurately, and the number of discrete image data reference values increases. On the other hand, the error in the approximate calculation can be reduced.

Specifically, in FIGS. 9 to 11, calculation is performed only at four points of time slots 0, 64, 128, and 192 in order to simplify the drawings, but in reality, time slots 0 to 255 are calculated. Of these, calculation was performed every 16 time slots (that is, the reference value of the image data was set for every 16 by the size of the image data), which was preferable.
At that time, based on the same idea, (Equation 6)-
Calculation may be performed by modifying (Expression 16).

FIG. 12A shows, by the above-described method, for a certain input image data, at each node position,
It is an example of a result of discretely calculating the correction data CData for image data = 0, 64, 128, 192.
In the figure, the discrete correction data for the same image data is shown by connecting with a dotted curve in order to make the figure easier to see.

(Interpolation Method of Discrete Correction Data) The correction data calculated discretely is discrete with respect to the position of each node and gives correction data at an arbitrary horizontal position (column wiring number). is not. At the same time, the correction data for the image data having the size of the reference value of some predetermined image data at each node position and for providing the correction data for the size of the actual image data is not provided. Absent.

Therefore, the inventors calculated the correction data suitable for the size of the input image data in each column wiring by interpolating the correction data calculated discretely.

FIG. 12B shows the image data Dat at the position x between the node n and the node n + 1.
It is the figure which showed the method of calculating the correction data equivalent to a.

As a premise, it is assumed that the correction data has already been discretely calculated at the positions Xn and Xn + 1 of the nodes n and n + 1.

The input image data Data is
It is assumed that the image data has a value between Dk and Dk + 1 of the image data reference value, which is image data for which correction data has already been calculated discretely.

Now, the discrete correction data for the reference value of the k-th image data of the node n is set to CData [k].
If expressed as [n], the pulse width Dk at the position x
Of the correction data CA of CData [k] [n] and CDa
Using the value of ta [k] [n + 1], by linear approximation,
It can be calculated as follows.

That is,

[Equation 22] However, Xn and Xn + 1 are nodes n and (n +
It is the horizontal display position of 1) and is a constant determined when the above-mentioned block is determined.

Also, the image data Dk + 1 at the position x
The correction data CB of can be calculated as follows.

That is,

[Equation 23] Becomes

By linearly approximating the correction data of CA and CB, the correction data CD for the image data Data at the position x can be calculated as follows.

That is,

[Equation 24] Becomes

As described above, in order to calculate the correction data suitable for the actual position and the size of the image data from the discrete correction data, the method described in (Equation 17) to (Equation 19) can be simply used. Can be calculated.

The correction data thus calculated is added to the image data to correct the image data, and pulse width modulation is performed according to the corrected image data (referred to as corrected image data). It is possible to reduce the influence of the voltage drop on the displayed image, and it is possible to improve the image quality.

Further, the hardware for correction, which has been a problem in the future, is extremely small because the amount of calculation can be reduced by introducing an approximation such as degeneracy described above. It had an excellent merit that it could be configured with large-scale hardware.

(Explanation of Function of Entire System and Each Part) Next, the hardware of the image display device incorporating the correction data calculating means will be explained.

Further, in the figure, R, G and B are RGB parallel input video data, Ra, Ga and Ba are RGB parallel video data subjected to an inverse γ conversion process, which will be described later, and D.
ata is image data subjected to parallel / serial conversion by the data array conversion unit, CD is correction data calculated by the correction data calculating unit, and Dout is image data corrected by adding the correction data to the image data by the adder. (Corrected image data).

(Synchronous Separation Circuit, Timing Generation Circuit) The image display device according to the present embodiment is NTSC, PAL, SE.
Television signals such as CAM and HDTV, and VGA output from a computer can be displayed together.

In FIG. 13, an HDTV is used for simplification of the drawing.
Only the method is described.

In the HDTV system video signal, the sync separation circuit 3 first separates the sync signals Vsync and Hsync and supplies them to the timing generation circuit 4. The video signals separated in synchronization are supplied to the RGB conversion means 7. Inside the RGB conversion means 7, in addition to a conversion circuit for converting YPbPr to RGB, a low-pass filter and an A / D converter (not shown) are provided, which converts YPbPr into a digital RGB signal and inverse γ. It is supplied to the processing unit 17.

(Timing Generation Circuit) The timing generation circuit 4 is a circuit which has a built-in PLL circuit, generates timing signals synchronized with the synchronization signals of various video sources, and generates operation timing signals for each section.

The timing signal generated by the timing generation circuit 4 is Tsft for controlling the operation timing of the shift register 5, and the control signal Dataalo for latching data from the shift register 5 to the latch circuit 6.
d, pulse width modulation start signal Pwmstar of the modulation means 8
t, a clock Pwmclk for pulse width modulation, Tscan for controlling the operation of the scanning circuit 2, and the like.

(Scanning Circuit) As shown in FIG. 14, the scanning circuits 2 and 2'are arranged to sequentially scan the display panel row by row in one horizontal scanning period, so that the selection potential Vs is applied to the connection terminals Dx1 to DxM. Alternatively, it is a circuit which outputs the non-selection potential Vns.

The scanning circuits 2 and 2 ′ are circuits that perform scanning by sequentially switching the selected scanning wiring every horizontal period in synchronization with the timing signal Tscan from the timing generation circuit 4.

Incidentally, Tscan is a timing signal group made up of a vertical synchronizing signal and a horizontal synchronizing signal.

The scanning circuits 2 and 2'are each composed of M switches and shift registers as shown in FIG. These switches are preferably composed of transistors or FETs.

In order to reduce the voltage drop in the scanning wiring, it is preferable that the scanning circuit is connected to both ends of the scanning wiring of the display panel and driven from both ends as shown in FIG.

On the other hand, the embodiment of the present invention is effective even when the scanning circuit is not connected to both ends of the scanning wiring, and can be applied only by changing the parameter of (Equation 3).

(Inverse γ Processing Unit) The CRT has a light emission characteristic of approximately 2.2 to the input (hereinafter referred to as an inverse γ characteristic).

Such characteristics of the CRT are taken into consideration in the input video signal, and the input video signal is generally converted according to the γ characteristic of 0.45 power so as to have a linear emission characteristic when displayed on the CRT.

On the other hand, when the display panel of the image display device according to the embodiment of the present invention has a light emission characteristic which is substantially linear with respect to the length of the application time when modulation is performed by the application time of the drive voltage, It is necessary to convert the input video signal based on the inverse γ characteristic (hereinafter referred to as inverse γ conversion).

The inverse γ processing section 17 shown in FIG. 13 is a block for performing inverse γ conversion on the input video signal.

The inverse γ processing section 17 of this embodiment uses the inverse γ
The conversion process is composed of memory.

The inverse γ processing unit sets the number of bits of the video signals R, G and B to 8 bits, and the number of bits of the video signals Ra, Ga and Ba output from the inverse γ processing unit is also 8 bits.
It is configured by using a memory having an address of 8 bits and a data of 8 bits for each color (FIG. 15).

(Data Array Converter) Data Array Converter 9
Is a circuit for performing parallel / serial conversion of RGB parallel video signals Ra, Ga, Ba according to the pixel array of the display panel. The configuration of the data array converter 9 is shown in FIG.
As shown in, the FIFO (First
In First Out) memory 2021R, 20
21G, 2021B and a selector 2022.

Although not shown in the figure, the FIFO memory is provided with two horizontal pixel memory words for odd lines and even lines. When the video data of the odd line is input, the data is written in the FIFO for the odd line, while the image data accumulated in the previous horizontal scanning period is read from the FIFO memory for the even line. When the video data of the even-numbered lines is input, the data is written in the FIFO for the even-numbered lines, while the image data accumulated in the previous horizontal period is read from the FIFO memory for the odd-numbered lines.

The data read from the FIFO memory is parallel-serial converted by the selector according to the pixel array of the display panel and output as RGB serial image data SData. Although not described in detail, it operates based on the timing control signal from the timing generation circuit 4.

(Delay Circuit 19) The image data SData rearranged by the data array converter 9 are input to the correction data calculator 14 and the delay circuit 19. The correction data interpolating unit of the correction data calculating means 14 which will be described later uses the horizontal position information x and the image data SDat from the timing control circuit.
The correction data CD suitable for them is calculated with reference to the value of a.

The delay circuit 19 is provided to absorb the time required for the correction data calculation (the above-mentioned correction data interpolation processing), and when the correction data is added to the image data by the adder, the image data It is a means for delaying so that the correction data corresponding to that is correctly added. The same means can be configured by using a flip-flop.

(Adder 12) The adder 12 receives the correction data CD and the image data Dat from the correction data calculating means 14.
It is a means for adding a. The image data Data is corrected by adding the corrected image data Dout.
Is transferred to the maximum value detection circuit 901 and the multiplier 904.

The number of bits of the corrected image data Dout output from the adder 12 is preferably determined so that overflow does not occur when the correction data CD is added to the image data Data.

More specifically, the image data Data is 8
It has a data width of bits, the maximum value is 255, the correction data CD has a data width of 7 bits, and the maximum value is 1
Suppose it was 20. At this time, the maximum value of the addition result is 2
55 + 120 = 375.

On the other hand, the corrected image data Dout output from the adder 12 preferably has an output bit width of 9 bits so that overflow does not occur.

(Overflow Processing) The correction is realized by adding the calculated correction data CD to the image data Data as described above.

Now, the number of bits of the modulation means 8 is 8 bits, and the corrected image data Dou which is the output of the adder 12 is output.
It is assumed that the number of bits of t is 9 bits.

Then, if the corrected image data Dout is directly connected to the input of the modulation means 8, an overflow will occur.

Therefore, overflow processing is performed to adjust the amplitude so that the corrected image data Dout corresponds to the input range of the modulating means.

As a structure for preventing the overflow, an all-white pattern (image data of 8 bits, all pixel data is a white screen of 255 in all pixels) which is image data having the maximum average luminance is input. Alternatively, the maximum value of the corrected image data may be estimated in advance, and the corrected image data may be always multiplied by a gain such that the maximum value is within the input range of the modulation means 8.

On the other hand, with the fixed gain as described above,
Although an overflow does not occur, an image with low average brightness is displayed with a larger gain, but is multiplied by a small gain, so that the brightness of the displayed image becomes dark.

Therefore, as will be described later, the maximum value detecting means 90 for detecting the maximum value of the corrected image data for each frame.
1 and a gain calculating means 902 for calculating a gain such that the output of the adder 12 falls within the input range of the modulating means 8, and a multiplier 904 for multiplying the calculated gain by the output of the adder 12 for each frame. The overflow is prevented by calculating the gain. Further, the brightness is held by adaptively calculating the gain.

The gain for preventing such overflow is preferably calculated in units of frames.

For example, the gain can be calculated for each horizontal line to prevent the overflow, but in this case, a difference in gain for each horizontal line causes an uncomfortable feeling in the displayed image.

In FIG. 13, a portion surrounded by a dotted line is an overflow processing section configured to faithfully prevent overflow.

The faithful overflow processing is composed of the following maximum value detecting means and gain calculating means. The configuration is shown below.

(Maximum value detecting means) The maximum value detecting means 901 of the present invention is in the overflow processing section of FIG.
As shown in the figure, each part is connected.

The maximum value detecting means 901 is a means for detecting the maximum value in the corrected image data Dout for one frame.

The maximum value detecting means 901 is a circuit which can be easily constructed by a comparator and a register. The maximum value detecting means 901 compares the value stored in the register with the size of the correction image data sequentially transferred. If the correction image data is larger than the register value, the maximum value detection unit 901 changes the value of the register to that value. It is a circuit that updates with a data value.

If the register value is cleared to 0 at the beginning of the frame, at the end of the frame, the maximum value of the corrected image data in the frame (also called maximum corrected image data) is stored in the register.

The maximum value of the corrected image data thus detected (maximum corrected image data) is transferred to the gain calculating means 902.

(Gain Calculation Means) Gain Calculation Means 902
Is a means for calculating the gain so that the corrected image data Dout falls within the input range of the modulating means 8.

The method of determining the gain is that the maximum value of the output data of the adder 12 detected by the maximum value detecting section is MAX and the maximum value of the input range of the modulating means 8 is INMAX within one frame.
Then,

[Equation 25] It may be determined such that (first method).

In the gain calculating means 902, the gain is updated in the vertical blanking period to change the gain value for each frame.

In the structure of the image display device of the present invention,
The maximum value of the corrected image data of the previous frame is used to calculate the gain by which the corrected image data of the current frame is multiplied.

Therefore, strictly speaking, an overflow may occur due to the difference in the corrected image data for each frame.

To address such a problem, a limiter means 905 described later is provided for the output of the multiplier that multiplies the corrected image data and the gain, and a circuit is provided so that the output of the multiplier 12 falls within the input range of the modulating means 8. Designed

Further, the present inventors have confirmed that, in addition to the above-described gain determination method, the gain may be calculated by another method as described below.

That is, as the gain to be applied to the corrected image data of the current frame, the maximum values of the corrected image data detected in the frames before the current frame are averaged, and the average value AMAX is

[Equation 26] It may be determined so that (2nd method).

In the third method, the current gain may be calculated by calculating the gain G for each frame by (Equation 20) and averaging it.

The inventors have confirmed that any of these three methods is preferable in the sense of preventing overflow, but on the other hand, it is more preferable than the first method.
It has been confirmed that the second and third methods have another effect that flicker in the display image is significantly reduced.

The inventors examined the number of frames to be averaged with respect to the second method and the third method. For example, averaging 16 to 64 frames has less flicker, which is preferable. An image was obtained.

Even in the cases of the second and third methods, the rate of occurrence of overflow can be considerably reduced, but more preferably it is preferable to provide a limiter to completely prevent overflow. Needless to say.

It was preferable that the gain calculated in this manner be set within the following range with respect to the maximum value of the corrected image data detected for each frame.

That is, the maximum value of the combined data detected by the maximum value detecting means 901 is MAX for each frame.
If the maximum value of the input range of the modulation means 8 is INMAX,

[Equation 27] Is preferred,

[Equation 28] It was particularly preferable to determine the gain G so that

In the overflow process, the above-mentioned overflow process is faithfully performed, and a filter is provided for each row to calculate the gain for the configuration of the amplitude adjustment that does not allow the overflow, and a means for dealing with the overflow is devised.

(Smoothing means) As a result of further research conducted by the inventors on means for calculating the gain of overflow processing, if the overflow processing is faithfully performed, in-line correction image data of one frame is obtained. It has been found that if there is a protruding line even if the maximum value is one line, the value of the gain becomes small due to the overflow process, and the entire screen of the frame is crushed by the gain and becomes dark.

An example for the above is shown in FIG. FIG. 17
(A) is an image with a gray background. Figure 17
When one white line is horizontally inserted as shown in (b), the maximum value of the corrected image data of the frame is remarkably increased as shown in FIG. 18 (a), and as a result, the gain value is decreased. The entire screen becomes dark.

With respect to such one horizontal line, the display image was better when the brightness was increased even if the overflow was allowed.

Therefore, when there is a line in which the corrected image data is prominently large, the inventors of the present invention alleviate the effect of the prominent corrected image data so that the brightness of the entire screen can be maintained. A means has been devised to provide a filter for overflow processing to smooth the corrected image data against changes in each row.

FIG. 18B is an example in which the maximum value of the corrected image data for each row is smoothed by using a low pass filter.

When smoothing is performed to determine the gain,
As shown in FIG. 18B, even if there is one large row in which the corrected image data is prominent and is large, the corrected image data in one row is cut by performing smoothing through the low-pass filter.

When the value of a large row of the corrected image data is smoothed, the fluctuation of the maximum value is smaller than that of the preceding and succeeding rows, the fluctuation of the gain is also small, and the deterioration of the screen brightness can be prevented.

On the other hand, as shown in FIG. 17C, when a plurality of lines having large correction image data continue, the maximum correction image data for each line is as shown in FIG.
The change is as shown in (c).

In the case of FIG. 17 (c), since the proportion of large lines in which the corrected image data occupies the entire screen is so large that it cannot be ignored, it is better to perform the overflow processing faithfully.

If the smoothing means is an image in which the corrected image data is large in a plurality of lines as shown in FIG. 18C, the corrected image data is as shown in FIG. Since it is not cut, the maximum value of the corrected image data of that frame does not change.

As a result, even if the smoothing means is performed, the gain value will be the same as when the overflow processing is performed faithfully.

In this way, the smoothing means is inserted in the overflow processing in the case where it is not necessary to execute the overflow processing faithfully such that the corrected image data is protruded by one row and a large row exists. It is effective and very effective in preventing the reduction of the brightness of the entire screen.

The embodiment will be described below.

(First Method of Smoothing Means) In the present invention, the following means was devised as the method of the first smoothing means.

The first smoothing means is a row-direction maximum value detecting means for detecting the maximum value for each row, a maximum value smoothing means for smoothing changes in the maximum value in the row direction, and smoothing for one frame. The maximum value detection means for detecting the maximum value among the maximum values for each row, and the gain calculation means for calculating the gain so that the output of the adder corresponds to the input range of the modulation means. .

The first method of smoothing means will be described below.
The circuit configuration will be described.

(Row-Direction Maximum Value Detection Means) The row-direction maximum value detection means 906 of the present invention is connected to each section as shown in FIG. FIG. 19 is a block diagram showing an outline of the circuit configuration.

FIG. 19 shows a circuit configuration in which the maximum value detection circuit 901 to the multiplication circuit 904 and the limiter 905 of the overflow processing unit in the circuit configuration of FIG. 13 are replaced with a circuit for smoothing means. The same reference numerals and configurations as those described with reference to FIG. 13 in FIG.

The row-direction maximum value detecting means 906 is means for performing the processing for detecting the maximum value from the corrected image data for one row for each horizontal scanning period.

The row-direction maximum value detecting means 906 is a circuit which can be simply constructed by a comparator and a register.

The row-direction maximum value detecting means 906 compares the sizes of the current data and the previous data in the sequentially transferred corrected image data Dout, and if the data before the current data is larger, , Is a circuit for updating the value of the register with the data.

If the register value is cleared to 0 at the beginning of each horizontal scanning period, the maximum value of the corrected image data of that row is stored in the register at the end of each horizontal scanning period.

The maximum value Lpwmax of the corrected image data for each row detected in this way is the maximum value smoothing means 9
It is transferred to 07.

(Maximum value smoothing means) Maximum value smoothing means 9
In 07, the low-pass filter is applied to the corrected image data for each row, and even if there is one row with large corrected image data,
This is a means to make the change smoother than the values of the preceding and following rows by the filter.

For example, as shown in FIG. 20, this means uses a latch which is a delay circuit which will be described later and a correction data of 1/4.
It can be composed of a multiplying circuit for multiplying, and an adding circuit, which serves as a low-pass filter.

In FIG. 20, the maximum value Lpwmax for each row of one frame that is sequentially transferred is input for four rows, each of which is multiplied by 1/4 in the multiplication circuit, and all the multiplication values in the addition circuit. Is a circuit for taking the sum of the above and outputting it to the next maximum value detecting means.

The latch circuit described later can delay the data by one horizontal period, which allows the circuit to accumulate and add data for up to four rows.

Since the multiplication circuit multiplies by 1/4 and finally four rows are added, the average value of Lpwmax of four rows can be output as the maximum value of the corrected image data for one row. Even if there is one line with large corrected image data, its value can be made smoother than the previous and next values.

In this way, the maximum value Spwmax of the smoothed corrected image data for each row is transferred to the smoothed maximum value detecting means 908.

(Smoothing Maximum Value Detecting Means) The smoothing maximum value detecting means 908 is means for detecting the maximum value among the maximum values Spwmax of each smoothed row in one frame.

The smoothed maximum value detecting means 908 is a circuit which can be simply constructed by a comparator and a register. The smoothed maximum value detection means 908 is a maximum value Spwm for each row, which is sequentially transferred with the value of the register.
The magnitudes of ax are compared, and if Spwmax is larger than the value of the register, the value of the register is updated with the data value.

If the value of the register is cleared to 0 at the first row of the frame, the maximum value of the smoothed corrected image data of the frame is stored in the register after the comparison with the last row of the frame is completed. It

The maximum value of the smoothed corrected image data detected in this way is transferred to the gain calculating means 909.

(Gain calculation means) Gain calculation means 909
Is a means for calculating the gain so that the corrected image data Dout corresponds to the input range of the modulating means, like the gain calculating means in the overflow processing.

The method of determining the gain is the same in the gain calculating means in the above-described overflow processing except that the input is different, and the description is omitted.

The above is the configuration of the first method of the smoothing means.

(Second Method of Smoothing Means) Further, as a second method of the smoothing means using the above-described low-pass filter, the present inventors may perform smoothing by another method as described below. I'm sure it's good.

The second smoothing means is a row-direction maximum value detecting means for detecting the maximum value for each row, a row-direction gain calculating means for calculating a gain for each row, and a change in the gain in the row direction. And a gain smoothing means for detecting a minimum gain value, and a minimum gain value detecting means for detecting a minimum gain value.

FIG. 21 shows a schematic circuit configuration of the second smoothing means method.

FIG. 21 shows a circuit configuration of FIG. 13 in which the maximum value detection circuit of the overflow processing unit, the multiplication circuit and the limiter are replaced with a circuit for smoothing means. In FIG. 21, the same reference numerals and configurations as those described with reference to FIG.

(Row-direction maximum value detecting means) The construction is exactly the same as the row-direction maximum value detecting means in the first method of the smoothing means described above, and therefore description thereof will be omitted.

(Row Direction Gain Calculation Means) The row direction gain calculation means 910 is the row direction maximum value detection circuit 906 described above.
The maximum value L of the corrected image data transferred by each line
This is an example of a row coefficient calculation means for calculating the row coefficient for each row so that the pwmax value falls within the input range of the modulation means 8. In the present embodiment, it is a means for calculating the gain for each row.

The gain determination method is as follows: MAXl is the maximum value of the corrected image data for each row detected by the row-direction maximum value detection circuit 906, and INMA is the maximum value of the input range of the modulator 8.
If you say X,

[Equation 29] It may be determined so that

The gain value Gl for each row determined in this way is transferred to the gain smoothing means 911.

(Gain Smoothing Means) Gain smoothing means 9
Reference numeral 11 denotes a row-direction low-pass filter for the gain value for each row transferred from the row-direction gain calculation unit 910 described above, and a certain row has a small row coefficient, in the present embodiment, a gain value Gl. Even so, it is an example of a row coefficient smoothing unit that smoothes the row coefficient so that a smooth change is obtained when compared with the values of the rows before and after by the filter. In the present embodiment, the gain is smoothed. Is a means to do.

The gain smoothing means 911 is, for example, as shown in FIG.
The circuit can be configured as shown in. The circuit shown in FIG. 22 has a latch which is a delay circuit described later and a gain value Gl of 1/4.
It is composed of a multiplication circuit for multiplying by and an addition circuit, and plays the role of a low-pass filter.

The gain smoothing means 911 inputs the gain values Gl for each row of one frame which are sequentially transferred, inputs the gain values Gl for four rows, multiplies each by 1/4 by the multiplication circuit, and adds all by the addition circuit. It is a circuit that takes the sum of the multiplication values and outputs it to the next minimum gain value detection means 912.

The latch circuit which will be described later can delay the data by one horizontal period, which allows the gain value of up to four rows to be accumulated and added in this circuit.

By multiplying by ¼ in the multiplication circuit and finally adding four rows, the average value of the gain values of four rows can be output as the gain value sGl of one row, and one row can be output. Even if there is a low gain value Gl, it can be made a smooth gain value compared with the values in the preceding and following rows.

The gain value sGl smoothed for each row in this way is transferred to the minimum gain value detecting means 912.

(Minimum Gain Value Detecting Means) The minimum gain value detecting means 912 is one frame among the row coefficients smoothed by the gain smoothing means 911 for each row, which is the gain value sGl in this embodiment. It is an example of a row coefficient minimum value detecting means for detecting the minimum row coefficient among the above, and in the present embodiment, it is a means for detecting the minimum gain value within one frame.

The minimum gain value detecting means 912 is a circuit which can be easily constructed by a comparator and a register. The minimum gain value detection means 912 compares the value of the register with the magnitude of the smoothed gain value for each row that is sequentially transferred, and if the transferred gain value is smaller than the gain value of the register. For example, it is a circuit that updates the register value with the gain value.

If the value of the register is cleared to 0 at the first row of the frame, the minimum value aG of the smoothed gain value of the frame after the end of the comparison with the last row of the frame is completed.
l is stored in the register.

The minimum value of the smoothed gain values thus detected is the gain applied to the corrected image data,
Forwarded to the multiplier (second method of smoothing means).

Further, the inventors of the present invention, as the gain to be applied to the corrected image data of the current frame, have the smoothing means No. 1 or No.
It has been confirmed that the average value of the gain values calculated using the above method may be calculated and the average value may be transferred to the multiplier as the gain of the current frame.

20 and 22, smoothing processing is performed as a low-pass filter by taking the maximum value of four rows and the average value of gains, but the low-pass filter is not limited to this configuration.

(Smoothing means using logical filter) Although all of the above three smoothing methods use a low-pass filter, as a smoothing means filter,
We devised a smoothing method by using a logical filter instead of a low-pass filter.

The logical filter is a filter for smoothing the maximum value and gain of the corrected image data for each row by combining a logical comparison such as a discriminant and a multiplier.

FIG. 23 shows a circuit configuration using a logic filter.

FIG. 23 shows the circuit configuration of FIG. 19 in which only the maximum value smoothing means section of the smoothing means is replaced with the low pass filter circuit by the logic filter circuit shown in FIG. 19 are the same as those in FIG. 19, the description thereof will be omitted.

FIG. 24 shows the maximum value smoothing means 913 constructed by a logical filter. Note that the logical filter is not limited to the circuit configuration in FIG. 24, and may be any filter that logically smoothes the maximum value of each row of corrected image data and the gain.

FIG. 24 shows a logical filter for smoothing the maximum value of the corrected image data for each row.

In FIG. 24, the discriminant g is L of a plurality of lines.
This is an expression for comparing pwmax with each other and determining and outputting the maximum value Z1 and the minimum value Z2.

Then, the function f subtracts the maximum value and the minimum value of the four values which are the output values of the discriminant g from the sum of the four values, and further divides the value by 2 to obtain the four values. The average of two intermediate values of is output.

Therefore, even if a line having a large value or a small value in the corrected image data is outstanding, that value is ignored and is not affected by the outstanding line.

FIG. 17B (in the graph, FIG. 18A)
As shown in, even if there is one line with the highest maximum value,
As shown in FIG. 25A, the maximum value of the row is ignored, and the average values of the rows before and after the row are inserted, so that smoothing is performed.

On the other hand, as shown in FIG. 17 (c) (in the graph of FIG. 18 (c)), when a plurality of large lines of corrected image data continue, a logical filter is used as shown in FIG. 25 (b). Also, since the maximum value is not cut,
It is possible to detect the maximum value of the same frame as when the overflow processing is performed faithfully.

As described above, even when the logical filter is used for the smoothing process, it is only necessary to execute the overflow process faithfully so that there is only one line in which the corrected image data is large. It becomes effective,
And it is very effective in preventing the decrease in the brightness of the entire screen (the third method of smoothing means).

In the above logical filter, the smoothing process is performed on the maximum value Lpwmax of the corrected image data for each row. However, the gain for each row is calculated, and the gain for each row is calculated using the logical filter. The inventors have confirmed that the same effect can be sufficiently obtained by performing smoothing.

A detailed circuit configuration is almost the same as that of the above-described logic filter, so that the description is omitted. However, in the case of the gain logic filter, in the circuit of FIG. 24, when compared with FIG. Also, the output destination is replaced with the minimum gain value detecting means (smoothing means fourth method).

Further, the logic filter is not limited to the above-mentioned circuit, and smoothing may be performed by using a structure including a logical circuit.

Further, the inventors of the present invention use the smoothing means third or fourth from the current frame to the previous frame as the gain to be applied to the corrected image data of the current frame calculated by smoothing with the logical filter. It has been confirmed that the average value of the gains calculated by using the method may be calculated and that value may be transferred to the multiplier as the gain of the current frame.

(Multiplier) The gain calculating means 909,
The gain calculated in the first to fourth methods of the smoothing means and the corrected image data Dout which is the output of the adder
Is multiplied by the multiplier of FIG. 14 (FIG. 19 or 21 when the smoothing means is used) to obtain the corrected image data Dm.
It is transferred to the limiter circuit as ult. The multiplier may be configured by a so-called logic circuit, or the multiplication result is stored in a table memory (ROM or RAM) and two parameters to be multiplied are input to an address,
The multiplication result may be output from the data.

Further, since the limiter means to which the output of the multiplier is connected can also be constituted by the table memory, the limiter means and the multiplier can be constituted by one table memory.

In this case, the contents to be stored in the table memory need only describe the data that limits the multiplication result.

The characteristics of the preferable limiter will be described below.

(Limiter Means) There is no problem if the gain can be determined so that overflow does not occur. However, according to some of the above-described gain determination methods, the overflow is allowed and the gain is determined.
er) must be provided.

The limiter has a preset limit value and compares the output data Dmulti input to the limiter with the limit value. If the limit value is smaller than the output data, the limit value is output and the limit value is output. If the limit value is large, the output data is output (the signal name in FIG. 13 is the corrected image data Dlim).

The limiter may have a characteristic of a broken line which is a straight line having a constant slope up to the maximum value as shown in FIG. 26 (a), or may be saturated at the maximum value as shown in FIG. 26 (b). It may be one showing a characteristic of a curve such as a characteristic.
The limiter with the characteristics shown in FIG. 26A can be realized by a comparator, and the limiter with the characteristics shown in FIG. 26B can be realized by a table memory or the like.

The corrected image data Dlim completely limited to the input range of the modulating means by the limiter means is supplied to the modulating means via the shift register and the latch.

As described above, the amplitude adjusting means is constituted by the overflow processing, the multiplier and the limiter.

(Shift Register, Latch Circuit) The corrected image data Dlim, which is the output of the limiter circuit, is transferred from the serial data format by the shift register 5 to
The parallel image data ID1 to IDN for each modulation wiring are serial / parallel converted and output to the latch circuit. The latch circuit latches the data from the shift register by the timing signal Dataload immediately before the start of one horizontal period. The output of the latch circuit 6 is supplied to the modulation means 8 as parallel image data D1 to DN.

In this embodiment, the image data ID1 to I
Each of DN and D1 to DN is 8-bit image data. These operation timings are the timing generation circuit 4
Timing control signals T _SFT and Dat from (FIG. 13)
It operates based on aload.

(Details of Modulating Means) The parallel image data D1 to DN output from the latch circuit 6 are supplied to the modulating means 8.

As shown in FIG. 27A, the modulation means 8 is a pulse width modulation circuit (PWM circuit) provided with a PWM counter, a comparator and a switch (FET in the figure) for each modulation wiring. .

The relationship between the image data D1 to DN and the output pulse width of the modulating means has a linear relationship as shown in FIG. 27 (b).

FIG. 13C shows three examples of output waveforms of the modulation means 8.

In the figure, the upper waveform is the waveform when the input data to the modulating means 8 is 0, the central waveform is the waveform when the input data to the modulating means 8 is 128, and the lower waveform is
This is a waveform when the input data to the modulation means 8 is 255.

In this example, the input data D to the modulation means 8 is
The number of bits 1 to DN is 8 bits.

In the above description, when the input data of the modulation means 8 is 255, there is a description that a modulation signal having a pulse width corresponding to one horizontal scanning period is output, but the details are the same. Although it is a very short time as shown in FIG. 6C, a period in which the pulse is not driven before and after the pulse rises is provided to allow a timing margin.

FIG. 28 is a timing chart showing the operation of the modulation means 8 of the present invention.

In the figure, the Hsync horizontal synchronizing signal,
Dataload is a load signal to the latch circuit 6, D1
-DN are the input signals to the columns 1-N of the aforementioned modulation means, Pw
mstart is a PWM counter synchronization clear signal, Pw
mclk is the clock of the PWM counter. Also, X
D1 to XDN represent outputs of the first to Nth columns of the modulation means.

When one horizontal scanning period starts as shown in the figure, the latch circuit 6 latches the image data and transfers the data to the modulation means 8.

The PWM counter, as shown in FIG.
Counting is started based on Pwmstart and Pwmclk, and when the count value reaches 255, the counter is stopped and the count value 255 is held.

The comparator provided for each column is
The count value of the PWM counter is compared with the image data of each column, and when the value of the PWM counter is greater than or equal to the image data, High
h is output, and Low is output during the other periods.

The output of the comparator is connected to the gates of the switches in each column, and the output of the comparator is Low.
During the period, the switch on the upper side (VPWM side) in the figure is ON,
The lower (GND side) switch is turned off, and the modulation wiring is connected to the voltage VPWM.

On the contrary, while the output of the comparator is High, the upper switch in the figure is turned off and the lower switch is turned on, and the voltage of the modulation wiring is connected to the GND potential.

The pulse width modulated signal output from the modulating means is D1 and D in FIG.
2, a waveform in which the rising edges of the pulses are synchronized as shown by DN.

(Correction Data Calculation Means) The correction data calculation means 14 is a circuit for calculating the voltage drop correction data by the above-mentioned correction data calculation method. As shown in FIG. 29, the correction data calculation means 14 is composed of two blocks, a discrete correction data calculation unit and a correction data interpolation unit.

The discrete correction data calculation unit calculates the voltage drop amount from the input video signal, and calculates the correction data discretely from the voltage drop amount. The calculation unit discretely calculates the correction data by introducing the concept of the above-described degenerate model in order to reduce the calculation amount and the hardware amount.

The correction data calculated discretely is interpolated by the correction data interpolation section, and the correction data CD suitable for the size of the image data and its horizontal display position x is calculated.

(Discrete Correction Data Calculation Unit) FIG. 30 shows a discrete correction data calculation unit for calculating correction data discretely according to the present invention.

As will be described below, the discrete correction data calculation unit divides the image data into blocks, calculates a statistic (number of lights) for each block, and calculates the voltage drop amount at each node position from the statistic. The function as a voltage drop amount calculation unit for calculating the time change of, the function of converting the voltage drop amount for each time into the light emission brightness amount, and the light emission brightness amount are integrated in the time direction to calculate the total light emission brightness amount. It is a function and means for calculating correction data for a reference value of image data at discrete reference points from the functions.

In the figure, 100a to 100d are lighting number counting means, 101a to 101d are a group of registers for storing the number of lighting at each time for each block, and 10
2 is a CPU, 103 is a table memory for storing the parameters aij described in (Equation 2) and (Equation 3), 1
Reference numeral 04 is a temporary register for temporarily storing the calculation result, 105 is a program memory in which the program of the CPU is stored, 110 is a table memory in which conversion data for converting the voltage drop amount into the emission current amount is written, 106
Is a register group for storing the calculation result of the discrete correction data described above.

Lighting number counting means 100a to 100d
Is composed of a comparator and an adder as shown in FIG. The video signals Ra, Ga and Ba are input to the comparators 107a to 107c, respectively,
Sequentially compared with the value of Cval. Note that Cval corresponds to the image data reference value set for the image data described above.

The comparators 107a to 107c are Cva
The image data is compared with l and High is output if the image data is larger, and Low is output if the image data is smaller.

The output of the comparator is the adders 108 and 1
09, they are added to each other, and addition is performed for each block by the adder 110, and the addition result for each block is set as the lighting number for each block in the register group 101
a to 101d.

In the lighting number counting means 100a to 100d, 0 and 6 are respectively set as the comparison value Cval of the comparator.
4, 128, and 192 have been input.

As a result, the lighting number counting means 100a
Counts the number of image data larger than 0 among the image data, and totals each block by the register 101a.
To store.

Similarly, the lighting number counting means 100b counts the number of image data larger than 64 among the image data, and the total for each block is registered in the register 101b.
To store.

Similarly, the lighting number counting means 100c counts the number of image data larger than 128 among the image data, and the total number for each block is registered in the register 101.
Store in c.

Similarly, the lighting number counting means 100d counts the number of image data larger than 192 out of the image data, and the total for each block is registered in the register 101.
Store in d.

When the number of times of lighting for each block is counted, the CPU reads the parameter table aij stored in the table memory 103 at any time and calculates the voltage drop amount according to (Equation 2) to (Equation 5). Then, the calculation result is stored in the temporary register 104.

In this example, the CPU is provided with a product-sum operation function for smoothly performing the calculation of (Equation 2).

As a means for realizing the operation given in (Equation 2), the CPU does not have to perform the product-sum operation.
The calculation result may be stored in the memory.

That is, the number of lights in each block may be used as an input and the voltage drop amount at each node position may be stored in the memory for all possible input patterns.

When the calculation of the amount of voltage drop is completed, C
The PU reads out the voltage drop amount for each block from the temporary register 104 at each time, and outputs the table memory 2
With reference to (111), the voltage drop amount was converted into the emission current amount, and the discrete correction data was calculated according to (Equation 6) to (Equation 16).

The calculated discrete correction data was stored in the register group 106.

(Correction Data Interpolation Unit) The correction data interpolation unit is a means for calculating the correction data suitable for the position (horizontal position) where the image data is displayed and the size of the image data. This means interpolates the correction data calculated discretely to display the image data (horizontal position).
Also, correction data corresponding to the size of the image data is calculated.

FIG. 31 is a diagram for explaining the correction data interpolation unit.

In the figure, 123 is a decoder for determining the node numbers n and n + 1 of the discrete correction data used for interpolation from the display position (horizontal position) x of the image data, and 124 is the size of the image data. , (Equation 17) ~
This is a decoder for determining k and k + 1 in (Equation 19).

Further, the selectors 125 to 128 are selectors for selecting the discrete correction data and supplying it to the linear approximation means.

Further, 121 to 123 are respectively expressed by (Equation 1
7) to (Equation 19) are linear approximation means for performing linear approximation.

FIG. 32 shows an example of the structure of the linear approximation means 121. In general, the linear approximation means is represented by the operators of (Equation 17) to (Equation 19), as shown by a subtracter, an integrator, an adder,
It can be configured by a divider or the like.

However, it is desirable that the number of column wirings between the nodes for calculating the discrete correction data and the interval of the image data reference value for calculating the discrete correction data (that is, the time interval for calculating the voltage drop) be 2. There is an advantage that the hardware can be configured very easily if it is configured to be a power of. If you set them to a power of 2,
In the divider shown in FIG. 32, Xn + 1-Xn is 2
It becomes a power of value and can be bit-shifted.

If the value of Xn + 1-Xn is always a constant value and a value represented by a power of 2, it is sufficient to shift the addition result of the adder by a multiplier of the power and output the result. There is no need to make a divider.

Also, by setting the intervals of the nodes for calculating the discrete correction data and the intervals of the image data to the powers of 2 at other locations, for example, the decoders 123 to 12 can be used.
4 can be easily manufactured, and FIG.
There are many advantages, such as the fact that the operation performed by the subtractor can be replaced with a simple bit operation.

(Operation Timing of Each Part) FIG. 33 shows a timing chart of the operation timing of each part.

In the figure, Hsync is a horizontal synchronizing signal and DotCLK is a PLL in the timing generation circuit.
A clock generated by the circuit from the horizontal synchronizing signal Hsync, R, G, B are digital image data from the input switching circuit, Data is image data after data array conversion,
Dlim is the output of the limiter means, correction image data subjected to voltage drop correction, TSFT is a shift clock for transferring the correction image data Dlim to the shift register 5, and Dataload is for latching data to the latch circuit 6. Load pulse, Pwmstart is an example of the pulse width modulation start signal described above, and modulation signal XD1 is an example of the pulse width modulation signal supplied to the modulation wiring 1.

At the start of one horizontal period, the digital image data RGB is transferred from the input switching circuit. In the drawing, in the horizontal scanning period I, when the input image data is represented by R_I, G_I, and B_I, the image data is stored in the data array conversion circuit 9 for one horizontal period, and in the horizontal scanning period I + 1. , Is output as digital image data Data_I according to the pixel arrangement of the display panel.

R_I, G_I and B_I are input to the correction data calculating means in the horizontal scanning period I. With this means, the number of times of lighting described above is counted, and at the end of counting, the voltage drop amount is calculated.

Subsequent to the calculation of the voltage drop amount, the discrete correction data is calculated, and the calculation result is stored in the register.

In the scanning period I + 1, in synchronization with the output of the image data Data_I one horizontal scanning period before from the data array conversion unit, the correction data interpolating means interpolates the discrete correction data and outputs the correction data. It is calculated. The interpolated correction data is supplied to the adder 12.

The adder 12 sequentially adds the image data Data and the correction data CD and transfers the corrected correction image data Dlim to the shift register. The shift register stores the corrected image data Dlim for one horizontal period according to Tsft, performs serial / parallel conversion, and outputs parallel image data ID1 to IDN to the latch circuit 6.

The latch circuit 6 latches the parallel image data ID1 to IDN from the shift register at the rising edge of Dataload, and transfers the latched image data D1 to DN to the pulse width modulation means 8.

The pulse width modulation means 8 outputs a pulse width modulation signal having a pulse width corresponding to the latched image data. In the image display device of the present embodiment, as a result, the pulse width output by the modulation means is displayed with a delay of two horizontal scanning periods with respect to the input image data.

When an image is displayed by such an image display device, it is possible to correct the amount of voltage drop in the scanning wiring, which has been a problem in the past, and it is possible to improve the deterioration of the displayed image due to the correction. It was possible to display a very good image.

Further, the correction data can be calculated very easily by calculating the correction data discretely and interpolating between the points calculated discretely. It was very effective, as it could be achieved with simple hardware.

(Other Examples of Application Target of Correction Data Calculation Means) In the above description, the correction data calculation means is RG.
The case where the correction data is calculated from the B-parallel image data is shown, but the present invention is not particularly limited to this.

That is, the data array converter converts RGB
It goes without saying that the correction data can be obtained by using the image data converted from parallel to RGB serial.

In this case, a register or memory for delaying the RGB serial image data is necessary to secure the time required to calculate the correction data, but similar correction can be performed. Needless to say.

Further, in the above description, the example in which the result of the correction data calculating means is applied to the RGB serial image data whose data array has been converted has been shown, but the present invention is not particularly limited to this.

That is, the data array conversion unit is replaced with a simple line memory, parallel image data is input,
Even if the parallel image data is output, it goes without saying that the correction can be performed by a simple modification of the hardware.

Of course, the above-mentioned configuration positively utilizes the line memory and the delay time thereat required for the data array conversion (parallel / serial conversion) of the image data, and corrects during the delay time. Needless to say, the amount of hardware can be reduced by calculating the data and correcting the serial image data.

As described above, according to the image display device configured as described above, it is very possible to suitably improve the deterioration of the display image due to the voltage drop on the scanning wiring, which has been a problem in the past. We were able to do that with simple hardware.

Furthermore, by using the smoothing means for each line for overflow processing, simple hardware
It was possible to prevent the brightness of the screen from being lowered due to the influence of a row having a significantly large amount of corrected image data.

(Second Embodiment) On the other hand, in the second embodiment of the present image display device, the same effect as in the first embodiment can be obtained by the configuration shown below.

FIG. 34 shows its configuration.

In FIG. 34, the difference from FIG. 19 is 14
The correction data calculation means and the adder 12 are deleted, and instead, a discrete correction image data calculation unit 14a and a correction image data interpolation circuit (means) 14b are newly provided.

Further, in FIG. 34, the parts other than the above-mentioned changed parts have the same structure as that of FIG.
Omit it.

The flow of calculating the corrected image data of the image display device shown in FIG. 34 will be described below.

(1) Calculate discrete corrected image data CDA (that is, the correction result which is the sum of the discrete corrected data and the image data reference value) with respect to the discrete horizontal position and the image data reference value (discrete corrected image). Data calculation unit 14
a).

(2) The corrected image data calculated discretely is interpolated to obtain the size of the input image data Data,
Corrected image data corresponding to the horizontal display position x is calculated (corrected image data interpolation circuit 14b).

(3) The gain is calculated by performing overflow processing so that the maximum value of the interpolated corrected image data corresponds to the input range of the modulating means (gain calculating means).

(4) Then, in the above overflow processing, even if the corrected image data has a protruding and large row,
In order to maintain the brightness of the screen, the first method of smoothing means described in the first embodiment is used. The circuit configuration and the like have been described with reference to FIG.

(5) The calculated gain is multiplied by the corrected image data (multiplier), the amplitude of the corrected image data is completely limited by the limiter, and the corrected image data is input to the shift register, the latch and the modulation means.

The method of calculating the discrete correction image data CDA described in (1) can be easily calculated by modifying the above-described methods (Expression 6) to (Expression 16) of calculating discrete correction data.

That is, the same equation is applied to the image data reference value = 0,
Although it was an equation for calculating the discrete correction data for 64, 128, 192, the value obtained by adding the respective image data reference values to this discrete correction data may be used as the discrete correction image data CDA.

In such a configuration, since the corrected image data in which the image data and the correction data are added is calculated at the stage of discretely calculating, it is not necessary to add the image data and the correction data after the interpolation. Absent. Therefore, the adder 12 of FIG. 19 is no longer necessary.

The correction image data interpolation circuit 14b can be configured in the same manner as the correction data interpolation unit of FIG. 31 described in the first embodiment.

The inventors have confirmed that the above smoothing means can obtain a sufficient effect even if the smoothing means are replaced by the second to fourth smoothing means.

As described above, also in the second embodiment configured as described above, it is preferable that the display image is deteriorated due to the voltage drop on the scanning wiring, which is a conventional problem in the image display device. I was able to improve.

Further, by introducing some approximations, the correction amount of the image data for correcting the voltage drop can be easily and suitably calculated, and it can be realized by very simple hardware. It had a very good effect.

Further, by using the smoothing means for the overflow processing, it is possible to prevent the brightness of the screen from being lowered due to the influence of a large row due to the projection of the corrected image data with a simple hardware.

(Third Embodiment) A third embodiment of the present image display device has been devised.

That is, the input image data is multiplied by a gain obtained by an overflow process incorporating a smoothing means in advance, and discrete corrected image data is calculated for the input image data multiplied by the gain.

The correction data calculated in accordance with the horizontal display position of the input image data and its size is calculated by interpolating the correction data calculated discretely, and the correction data is added to the image data to correct the correction data. To realize.

FIG. 35 shows its schematic diagram and circuit configuration diagram.
FIG. 35 shows a circuit configuration in which the gain output portion of the smoothing processing unit in the circuit configuration of FIG. 19 is replaced with a feedback configuration for outputting to the modulated image calculation means 914 after the output of the inverse γ processing unit 17. is there. Since the reference numerals, configurations and the like described in FIG. 19 of FIG. 35 are the same, description thereof will be omitted.

Also in the smoothing processing section, the circuit configuration etc. is the same as the first method of the smoothing means of the first embodiment,
Since the output destination is changed to the modulated image calculation means and the configuration and the like are the same, description thereof will be omitted.

In FIG. 35, the gain is calculated for the image data of the frame before the current frame in the overflow processing section incorporating the smoothing means, and the gain value is calculated for the input image data of the current frame. The modulation image calculation means portion performs multiplication, and correction calculation is performed on the multiplied input image data.

Since the gain is applied to the input image, the output value of the adder after the correction calculation rarely exceeds the allowable value of the modulating means, and the slightly exceeded amount is set to the allowable value by the limiter. It is configured to fit.

Further, by incorporating the smoothing means described in the first embodiment in the overflow processing, it is possible to prevent the phenomenon in which the corrected image data protrudes and the large line is suppressed, and the screen becomes dark.

In the smoothing means, even if the second to fourth methods of the smoothing processing described in the first embodiment are used, the brightness of the screen is lowered due to the influence of the large row of the corrected image data. It has been confirmed to be extremely effective in preventing

The circuit configuration of the second to fourth methods of the smoothing means is the same as that described in the first embodiment, and the details of the circuit will be omitted.

[0451]

As described above, according to the image display device of the present invention, it is possible to suitably improve the deterioration of the display image due to the voltage drop on the scanning wiring, which has been a problem in the past.

Also, by introducing some approximations, the correction amount of the image data for correcting the voltage drop can be easily and suitably calculated, and this can be realized by very simple hardware. It had a very good effect.

Further, by incorporating the filter processing for each row in the overflow processing, it is possible to prevent the brightness of the screen from being lowered due to the influence of a large row in which the corrected image data is projected.

[Brief description of drawings]

FIG. 1 is a diagram showing an overview of an image display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an electrical connection of a display panel.

FIG. 3 is a diagram showing characteristics of a surface conduction electron-emitting device.

FIG. 4 is a diagram showing a driving method of a display panel.

FIG. 5 is a diagram illustrating an influence of a voltage drop.

FIG. 6 is a diagram illustrating a degenerate model.

FIG. 7 is a graph showing a discretely calculated voltage drop amount.

FIG. 8 is a graph showing the amount of change in emission current calculated discretely.

FIG. 9 is a diagram for explaining another method of calculating correction data.

FIG. 10 is a diagram showing an example of calculation of correction data when the size of image data is 128.

FIG. 11 is a diagram showing an example of calculation of correction data when the size of image data is 192.

FIG. 12 is a diagram for explaining an interpolation method of correction data.

FIG. 13 is a block diagram showing a schematic configuration of an image display device incorporating a correction circuit.

FIG. 14 is a block diagram showing a configuration of a scanning circuit of the image display device.

FIG. 15 is a block diagram showing a configuration of an inverse γ processing unit of the image display device.

FIG. 16 is a block diagram showing a configuration of a data array conversion unit of the image display device of the present invention.

FIG. 17 is a diagram illustrating an example in which a row having a large amount of corrected corrected image data occurs.

FIG. 18 is a graph showing changes in the maximum value of the corrected image data for each row wiring before and after the smoothing means by the low-pass filter in FIG.

FIG. 19 is a block diagram showing a schematic configuration of an image display device that incorporates a correction circuit and a smoothing circuit (first method of smoothing means) using a low-pass filter.

FIG. 20 is a low-pass filter circuit that smoothes changes in the maximum value for each row by smoothing means.

FIG. 21 is a block diagram showing a schematic configuration of an image display device incorporating a correction circuit and a smoothing circuit (second method of smoothing means) using a low-pass filter.

FIG. 22 is a low-pass filter circuit that smoothes a change in gain for each row by a smoothing unit.

FIG. 23 is a block diagram showing a schematic configuration of an image display device including a correction circuit and a smoothing circuit (third method of smoothing means) using a logical filter.

FIG. 24 is a logic filter circuit that smoothes changes in the maximum value for each row by a smoothing means.

FIG. 25 is a graph showing changes in the maximum value of the corrected image data for each row wiring before and after the smoothing means using the logical filter in FIG. 17.

FIG. 26 is a diagram showing characteristics of the limiter according to the embodiment of the present invention.

FIG. 27 is a diagram illustrating the configuration and operation of the modulation means of the image display device.

FIG. 28 is a timing chart of the modulation means of the image display device.

FIG. 29 is a block diagram showing a configuration of a correction data calculation unit of the image display device.

FIG. 30 is a block diagram showing a configuration of a discrete correction data calculation unit of the image display device.

FIG. 31 is a block diagram showing a configuration of a correction data interpolation unit.

FIG. 32 is a block diagram showing a configuration of a linear approximation means.

FIG. 33 is a timing chart of the image display device.

FIG. 34 is a block diagram showing a schematic configuration of an image display device in which a correction circuit and a smoothing circuit by a low-pass filter (first method of smoothing means) are incorporated in the second embodiment.

FIG. 35 is a block diagram showing a schematic configuration of an image display device in which a correction circuit and a smoothing circuit (first method of smoothing means) are incorporated in the third embodiment.

FIG. 36 is a block diagram showing a configuration of a conventional image display device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 display panel 2 scanning circuit 8 pulse width modulation means 12 adder 14 correction data calculation means 14a discrete correction image data calculation section 14b corrected image data interpolation circuit 17 inverse γ processing section 19 delay circuit 20 maximum value detection means 21 gain calculation means 22 Multipliers 100a, 100b, 100c, 100d Lighting number counting means 101a, 101b, 101c, 101d Register group 103 Table memory 111 Table memory 2 107a, 107b, 107c Comparator 123, 124 Decoder 901 Maximum value detection circuits 902, 909 Gain calculation means 904 Multiplier 905 Limiter 906 Row direction maximum value detection circuits 907 and 913 Maximum value smoothing means 908 Smoothing maximum value detection circuit 910 Row direction gain calculation means 911 Gain smoothing means 912 Gain minimum value detection means 914 Tone image calculating unit 1001 substrate 1002 cold cathode devices 1003 line wiring (scanning wiring) 1004 column wirings (modulation wiring) 1007 face plate 1008 phosphor layer

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 641 G09G 3/20 641A 642 642A (72) Inventor Kohei Inamura 3-30 Shimomaruko, Ota-ku, Tokyo No. 2 Canon Inc. (72) Inventor Naoto Abe 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Osamu Sagano 3-30-2 Shimomaruko, Ota-ku, Tokyo Non-Co., Ltd. F term (reference) 5C080 AA06 AA08 AA18 BB05 CC03 DD05 DD22 DD27 EE19 EE29 EE30 FF12 GG08 GG12 HH09 HH17 JJ01 JJ02 JJ03 JJ04 JJ05 JJ06 KK04 KK43

Claims (24)

[Claims] 1. An image forming element which is arranged in a matrix and is driven through a plurality of row wirings and column wirings and used for image formation; a scanning unit which sequentially selects and scans the row wirings; and the column wirings. And a correction means connected to the correction image data calculation means for calculating the correction image data for the input image data by correcting the influence of the voltage drop caused by the resistance of the row wiring. Amplitude adjusting means for adjusting the amplitude of the corrected image data so as to correspond to the input range of the modulating means, the modulating means according to the corrected image data adjusted by the amplitude adjusting means. An image display device for modulating a drive waveform applied to a column wiring, wherein the amplitude adjusting means detects a maximum value in a row direction for detecting a maximum value in a row of the corrected image data for each row wiring. Output function, a maximum value smoothing function that smoothes the detected maximum value in the row by a filter, and a smoothing maximum value detection function that detects a maximum value in the frame from the maximum value in the row that is smoothed by the filter, And a function of adjusting the amplitude of the corrected image data so that the maximum value in the frame corresponds to the maximum value of the input range of the modulator. 2. An image forming element arranged in a matrix and driven through a plurality of row wirings and column wirings and used for image formation, a scanning unit for sequentially selecting and scanning the row wirings, and the column wirings. An image display device including a modulator connected to the corrected image data, the corrected image data calculating the corrected image data in which the influence of the voltage drop caused by the resistance of the row wiring is corrected with respect to the input image data. A calculation unit and an amplitude adjustment unit that adjusts the amplitude of the corrected image data so that the corrected image data corresponds to the input range of the modulation unit, and the modulation unit is adjusted by the amplitude adjustment unit. An image display device that modulates a drive waveform applied to the column wiring in accordance with the corrected image data, wherein the amplitude adjusting means is provided for each row wiring within the row of the corrected image data. A row-direction maximum value detection function for detecting a maximum value; a row coefficient calculation function for calculating a row coefficient for each row so that the detected maximum value in the row falls within the maximum value of the input range of the modulation means; A row coefficient smoothing function for smoothing coefficients by a filter, a row coefficient minimum value detecting function for detecting a frame inline coefficient minimum value from the row coefficients smoothed by a filter, and an amplitude based on the frame inline coefficient minimum value. An image display device having a function of calculating a coefficient for adjustment and adjusting the amplitude of the corrected image data. 3. The amplitude adjusting means calculates a coefficient for performing amplitude adjustment from the maximum value in the frame, and multiplies an output of the corrected image data by the coefficient. Image display device. 4. The amplitude adjusting means calculates a coefficient for performing amplitude adjustment from the maximum value in the frame, multiplies input image data by the coefficient for performing amplitude adjustment, and obtains the corrected image data. The image display device according to claim 1, wherein the calculation means calculates corrected image data for the image data that has been multiplied. 5. The image display device according to claim 2, wherein the amplitude adjusting means multiplies the output of the corrected image data calculating means by a coefficient for adjusting the amplitude. 6. The amplitude adjusting means multiplies the input image data by a coefficient for amplitude adjustment, and the corrected image data calculating means applies the corrected image data to the multiplied image data. The image display device according to claim 2, which is calculated. 7. The image display device according to claim 1, wherein the filter is a low-pass filter. 8. The image display device according to claim 1, wherein the filter is a logical filter. 9. The correction image data calculating means predicts and calculates, in the spatial direction and the time direction, a voltage drop amount to be generated on a row wiring during one horizontal scanning period with respect to input image data. The image display device according to claim 1 or 2, further comprising: a unit that calculates corrected image data obtained by correcting the input image data from the calculated voltage drop amount. 10. The correction image data calculation means discretely predicts and calculates a voltage drop amount to be generated on a row wiring in one horizontal scanning period in the spatial direction and the time direction with respect to input image data. The image display device according to claim 1 or 2, further comprising: means for calculating the corrected image data obtained by correcting the input image data from the calculated discrete voltage drop amount. 11. The coefficient G for adjusting the amplitude is G = INMAX / MAX, where MAX is the maximum value in the frame for each frame and INMAX is the maximum value in the input range of the modulating means. The image display device according to claim 3. 12. A coefficient G for performing the amplitude adjustment is as follows: MAX is the maximum value in the frame for each frame, INMAX is the maximum value in the input range of the modulating means, and is one frame before the current frame. The image display device according to claim 4, wherein when the coefficient is Go, G = INMAX / MAX × Go. 13. The coefficient G for performing the amplitude adjustment is a row coefficient for each row calculated from the maximum value in the previous row, Gl,
If the maximum value in the row for each row is MAXl and the maximum value of the input range of the modulating means is INMAX, then Gl = INMAX / MAXl, and the row coefficient Gl is smoothed by the filter, and one frame is output from the smoothed output. Frame inward coefficient minimum value s
The image display apparatus according to claim 5, wherein Gl is detected, and the minimum value of the in-frame coefficient sGl becomes the coefficient G. 14. The coefficient G for adjusting the amplitude of the input image data is a row coefficient G for each row calculated from the maximum value in the row.
l ′, the maximum value in the row for each row is MAXl, the maximum value in the input range of the modulation means is INMAX, and the coefficient in the frame immediately before the current frame is Go, Gl ′ = INMAX / MAX1 × Go Then, the row coefficient Gl ′ is smoothed by the filter, and after smoothing, the frame inner row coefficient minimum value s is calculated for each frame.
Gl ′ is detected, and the minimum value of the intra-frame coefficient sG
The image display device according to claim 6, wherein l ′ is the coefficient G. 15. The coefficient G for adjusting the amplitude of the input image data is a row coefficient Gl calculated for each row from the maximum value in the previous term.
Let MAX1 be the maximum value in the row for each row and INMAX be the maximum value in the input range of the modulation means, then Gl = INMAX / MAX1 and the row coefficient Gl is smoothed by the filter, and one frame is output from the smoothed output. Frame inward coefficient minimum value sG
The image display device according to claim 6, wherein, when l is detected, and the coefficient in the frame immediately preceding the current frame is Go, G = sGl × Go. 16. The coefficient for performing the amplitude adjustment is a coefficient of the current frame in the amplitude adjusting means calculated for each of a plurality of frames before the current frame. The image display device according to claim 3. 17. The coefficient for adjusting the amplitude is calculated by calculating the coefficient for each of a plurality of frames before the current frame and smoothing each coefficient in the frame direction by a low-pass filter. The image display device according to claim 16, wherein the value is the coefficient of the current frame. 18. The image display device according to claim 1, wherein the amplitude adjusting means includes a limiter for limiting a maximum value of input data to the modulating means. 19. The corrected image data includes: a limiter that is preset; and a comparator that compares the output data whose amplitude is adjusted by the amplitude adjusting means with the output data and the limit value. If the limit value is smaller than the output data whose amplitude has been adjusted, the limit value is output, and if the limit value is larger than the output data for which the amplitude adjustment of the corrected image data has been made, the amplitude adjustment of the corrected image data is made. 19. The image display device according to claim 18, wherein the output data is output. 20. The modulation means is pulse width modulation means for performing modulation by varying the pulse width of the voltage pulse waveform applied to each column wiring in accordance with the input of the modulation means. Items 1 to 19
The image display device according to any one of 1. 21. The image display device according to claim 1, wherein the image forming element is a cold cathode element. 22. The image display device according to claim 21, wherein the cold cathode device is a surface conduction electron-emitting device. 23. An image forming element which is arranged in a matrix and is driven through a plurality of row wirings and column wirings and used for image formation; a scanning unit which sequentially selects and scans the row wirings; and the column wirings. And a correction means connected to the correction image data calculation means for calculating the correction image data for the input image data by correcting the influence of the voltage drop caused by the resistance of the row wiring. The image display device is provided with an amplitude adjusting means for adjusting the amplitude of the corrected image data so as to correspond to the input range of the modulating means, and the modulating means includes the corrected image data adjusted by the amplitude adjusting means. According to the above, the drive waveform applied to the column wiring is modulated, and the amplitude adjusting means detects the maximum in-row value of the corrected image data for each row wiring, and the detected in-row A large value is smoothed by a filter, an in-frame maximum value is detected from the in-row maximum value smoothed by the filter, and the correction is performed so that the in-frame maximum value corresponds to the maximum value of the input range of the modulating means. An image display method characterized by adjusting the amplitude of image data and displaying the image. 24. An image forming element arranged in a matrix and driven through a plurality of row wirings and column wirings and used for image formation; scanning means for sequentially selecting and scanning the row wirings; and the column wirings. And a correction means connected to the correction image data calculation means for calculating the correction image data for the input image data by correcting the influence of the voltage drop caused by the resistance of the row wiring. The image display device is provided with an amplitude adjusting means for adjusting the amplitude of the corrected image data so as to correspond to the input range of the modulating means, and the modulating means includes the corrected image data adjusted by the amplitude adjusting means. According to the above, the drive waveform applied to the column wiring is modulated, and the amplitude adjusting means detects the maximum in-row value of the corrected image data for each row wiring, and the detected in-row A row coefficient is calculated for each row so that a large value falls within the maximum value of the input range of the modulation means, the row coefficient is smoothed by a filter, and the intra-frame row coefficient minimum value is calculated from the row coefficient smoothed by the filter. An image display method comprising: detecting a coefficient, calculating a coefficient for amplitude adjustment based on the minimum value of the in-frame coefficient, adjusting the amplitude of the corrected image data, and displaying an image.