JP2002229506A - Image display device and driving method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image display device and a driving method therefor, capable of displaying a high quality picture by calculating a correction amount to a voltage drop with a simple constitution and a less calculation amount, and. SOLUTION: The image display device which is provided with a display panel 1 comprising a multi-electron source formed by connecting two- dimensionally arranged cold cathode elements in a matrix form with a plurality of row wiring and a plurality of column wiring, and which drives a plurality of the cold cathode elements connected with a single row wiring, comprises a correction amount calculation means 14 for calculating a voltage drop amount at a prescribed number of nodes defined on the row wiring based on each picture signal inputted from a signal switching part 13, and an arithmetic calculation part 12 for calculating a correction amount of each picture signal based on the voltage drop amounts at a plurality of nodes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an image display device having a display panel in which a plurality of display elements are arranged in a matrix.

[0002]

2. Description of the Related Art Conventionally, as this type of image display device,
For example, as disclosed in Japanese Patent Application Laid-Open No. 8-248920, a total of N × M cold cathode elements in a row direction and M columns are arranged two-dimensionally in a matrix, and they are arranged in a row direction. There is known a configuration provided with a multi-electron source formed by matrix wiring with M row wirings provided in a matrix and N column wirings provided in a column direction.

In this image display device, a predetermined driving voltage is applied to both a row wiring and a column wiring to drive a cold cathode element connected to both wirings to emit electrons, and to face a multi-electron source. An image is displayed by irradiating the arranged phosphor with an electron beam.

When a large number of cold-cathode devices arranged in a matrix are driven, a group of elements for one row of the matrix (the group of elements for one row are connected to one row wiring) is driven simultaneously. The way has been done.

That is, a predetermined selection potential is applied to one row wiring, and a predetermined selection potential is applied only to a column wiring connected to an element to be driven among the N cold cathode elements connected to the row wiring. , A plurality of elements in one row are simultaneously controlled. Then, the drive rows are switched one after another to scan all the rows, and a two-dimensional image is formed using the visual afterimage phenomenon.

According to this method, the driving time assigned to each element is secured N times longer than in the method of scanning one element at a time, so that the brightness of the image display device can be increased. There are advantages.

[0007]

However, in the case of the above-described prior art, the following problems have occurred.

The N cold cathode elements for one row are connected to one row wiring, but the connection positions are different for each element. In this case, the brightness of each element varies due to the influence of the voltage drop due to the wiring resistance.

In order to compensate for the decrease in luminance due to the voltage drop, Japanese Patent Laid-Open No. Hei 8-248920 proposes a configuration in which a correction amount is calculated by a statistical operation, and a correction value is combined with a required electron beam value. ing.

FIG. 25 shows the configuration of the first embodiment of Japanese Patent Application Laid-Open No. 8-248920. A detailed description is omitted because it is written in the official gazette. However, in order to perform correction as shown in FIG. A configuration has been proposed in which data is multiplied and corrected data is transferred to a modulation signal generator 1003.

However, in the above configuration, since the correction amount calculation is required for each column wiring, the amount of calculation is enormous, the multiplier 1001 for each column wiring, and a memory means for outputting correction data. 1002 and a summer 100 for providing an address signal to the memory means 1002
However, there still remains a problem that large-scale hardware such as 4 is required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art. It is an object of the present invention to calculate a correction amount for a voltage drop with a simple configuration and a small amount of calculation to obtain a high-quality image. It is an object of the present invention to provide an image display device capable of displaying an image and a method of driving the image display device.

[0013]

According to one aspect of the present invention, a plurality of display elements arranged two-dimensionally are connected in a matrix by a plurality of row wirings and a plurality of column wirings. Input means for inputting an image signal of each column for one row, comprising: a plurality of driven parts comprising: a plurality of driven portions; and a plurality of cold cathode elements connected to one row wiring. Means for setting a plurality of column wirings between adjacent nodes, calculating voltage drop amounts at respective nodes based on an input image signal, and a voltage calculated by the calculating means. A correction means for correcting a signal waveform applied to each of the plurality of column wirings based on the amount of drop.

With this configuration, the effect of the voltage drop can be easily reduced.

Preferably, the nodes are set such that power-of-two column wirings are located between adjacent nodes.

Further, in each of the above inventions, the image signal of each column of one row is divided into a plurality of blocks each corresponding to each of the plurality of nodes, and the image signal of each node is determined based on the image signal of each block. A configuration for calculating the voltage drop amount is particularly preferable. Specifically, the amount of current flowing through the wiring when an image is displayed for each block is obtained, the amount of voltage drop is obtained, and the amount of voltage drop at each node is obtained in consideration of the effect of the voltage drop by each block. It is possible.

It is preferable that the plurality of blocks are set so that an image signal corresponding to a column wiring sandwiched between adjacent nodes is one block.

Further, in each of the above inventions, the row wiring is supplied with a selection potential from both ends thereof, and the node has a number of column wirings located between adjacent nodes near the center of the row wiring. The row wiring is set so as to be larger than the column wiring between adjacent nodes near the end on the row wiring, or the row wiring is supplied with a selection potential from only one end thereof, The number of column wirings located between adjacent nodes near the end opposite to the one end on the wiring is larger than the number of column wirings located between adjacent nodes near the one end on the row wiring. It is preferable to set to. Preferably, the number of column wirings located between the nodes is varied depending on the distance from the position to which the selection potential is applied.

In each of the above-mentioned inventions, it is possible to suitably employ a configuration in which the signal waveform is a signal waveform for performing peak value modulation.

In each of the above inventions, the correction of the signal waveform may be performed not by correcting the image data but by forming the signal waveform in consideration of the correction amount when forming the signal waveform corresponding to the image data. However, if a configuration for correcting the image data itself, for example, a configuration for correcting the gradation data of the image data is adopted, and a signal waveform is formed based on the corrected image data, a simple configuration can be achieved. Correction can be realized.

Further, in each of the above-mentioned inventions, it is possible to adopt a configuration in which the correction of the signal waveform corrects the peak value or the pulse width.

In each of the above inventions, the correction of the signal waveform applied to each of the plurality of column wirings based on the voltage drop amount calculated by the calculation means is performed based on the voltage drop amount for each node. It is preferable to calculate the amount of voltage drop at the position of each column wiring on the wiring. Here, the calculation of the amount of voltage drop at the position of each column wiring can be obtained by interpolation based on the amount of voltage drop at the position of each node. A straight-line approximation can be simply used as the interpolation method.

In each of the above inventions, a memory functioning as a conversion table in which a value determined by referring to image data (such as an element current amount shown in the embodiment) and a voltage drop amount are correlated for correction. Can be preferably adopted.

Further, in each of the above inventions, the correction means may include a restriction means for restricting a value of the image signal corrected by the image signal correction means.

Further, the input means may include a limiting means for limiting a value of the image signal.

In each of the above inventions, an electron-emitting device, preferably a cold cathode device, can be used as the display device. In particular, it has been found that when the display element is a surface conduction type emission element, a voltage drop is likely to occur in the row wiring, and the present invention can be particularly suitably applied.
In the case where an electron-emitting device such as a surface-conduction emission device is used as a display block, a light-emitting member that emits light by the electrons emitted from the device may be provided. In addition, the invention of this application
The present invention can also be applied to a configuration in which an (electroluminescence) element is used as a display element.

According to the present invention, as a method of driving an image display device, there is provided a driven portion in which a plurality of display elements arranged two-dimensionally are connected in a matrix by a plurality of row wirings and a plurality of column wirings. In a method for driving an image display device for simultaneously driving a plurality of display elements connected to one row wiring, an input step of inputting image signals of each column for one row, and a plurality of nodes adjacent to each other on the row wiring A calculating step of calculating a voltage drop amount at each node based on an input image signal by setting a plurality of column wirings to be located between the nodes, based on a voltage drop amount calculated by the calculating unit, And a correcting step of correcting a signal waveform applied to each of the plurality of column wirings.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As described above, in a display device in which cold cathode devices such as surface conduction electron-emitting devices are arranged in a simple matrix structure, a display image is deteriorated due to a voltage drop in a row wiring. There was a problem to do.

The present invention relates to an image display device provided with means for correcting the effect of a voltage drop, and in particular, it can be realized with a relatively small circuit scale.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In particular, in each of the embodiments described below, a correction amount for correcting a voltage drop is calculated by introducing small approximations by using some approximations, and the image signal is corrected based on the calculation. It is intended to improve the deterioration of the image due to the effect of the voltage drop.

It should be noted that the dimensions, materials, shapes, relative arrangements, and the like of the components described in each embodiment are intended to limit the scope of the present invention only to them unless otherwise specified. Not a thing.

First Embodiment First, an overview of a display panel of an image display device according to a first embodiment of the present invention, electrical connection of the display panel, and characteristics of a surface conduction type emission device will be briefly described. I do.

<Overview of Image Display Apparatus> FIG. 1 is a perspective view of a display panel 1 used in an image display apparatus according to the present embodiment, in which a part of the panel is cut away to show the internal structure. ing.

In the figure, 105 is a rear plate, 106 is a side wall, 107 is a face plate,
An airtight container for maintaining the inside of the display panel 1 at a vacuum is formed by the side wall 05, the side wall 106 and the face plate 107.

When producing an airtight container, it is necessary to seal the joints of the members in order to maintain sufficient strength and airtightness. For example, frit glass is applied to the joints,
400 degrees Celsius to 500 degrees Celsius in air or nitrogen atmosphere
It can be manufactured by baking for 10 minutes or more and sealing.

A substrate 101 is fixed to the rear plate 105, and N × M cold cathode elements 102 are formed on the substrate 101. Row wiring 103 and column wiring 10
4 and the cold cathode element 102 are connected as shown in FIG.

That is, M row wirings 103 in the row direction
However, the N column wirings 104 are provided so as to cross each other in the column direction, and the row wirings 103 and the column wirings 104 are insulated at the intersections. The pair of row wirings and column wirings are connected so that one cold cathode element 102 is connected. Such a connection structure is called a matrix wiring or a simple matrix.

DxM are connection terminals for applying a voltage to each row wiring 103, and Dy1, Dy2,..., DyN are each column wiring 104.
This is a connection terminal for applying a voltage to.

In the matrix wiring, for example, a predetermined driving potential is applied only to the connection terminal Dx1 and the connection terminal Dy2, so that only the cold cathode elements 102a connected to both wirings are driven by a potential difference applied to each of them. can do.

Here, the substrate 101, the cold cathode device 10
2, a portion constituted by the row wiring 103 and the column wiring 104 is referred to as a multi-electron source.

On the lower surface of the face plate 107,
A fluorescent film 108 as a light emitting means is formed. Since the image display device of the present embodiment is a color display device,
The fluorescent film 108 has red,
Phosphors of three primary colors of green and blue are separately applied. The phosphors are formed in a matrix corresponding to each pixel (picture element) of the rear plate 105 and irradiated with the emitted electrons (emitted current, also referred to as electron beam) from the cold cathode element 102. Thus, a pixel is formed.

A metal back 10 is provided on the lower surface of the fluorescent film 108.
9 are formed. Hv in the figure is a high voltage terminal, which is electrically connected to the metal back 109. By applying a high voltage to the Hv terminal, a potential difference occurs between the rear plate 105 and the face plate 107. That is,
The metal back 109 functions as an anode electrode for attracting electrons emitted from the cold cathode device 102.

In this embodiment, a surface conduction electron-emitting device was manufactured as a cold cathode device in the display panel 1 as described above.

<Characteristics of Surface Conduction Type Emission Element> The surface conduction type emission element generally includes two electrodes and an electron emission portion formed between them. Each of the two electrodes is a row wiring 1
03 and the column wiring 104, and a predetermined potential is applied to both electrodes (the potential difference becomes the element driving voltage Vf).
Is applied, electrons are emitted from the electron emission portion.
Here, the current caused by the emitted electrons is called an emission current Ie, and the current flowing between both electrodes is called an element current If.

A typical surface conduction electron-emitting device has (emission current Ie) vs. (device drive voltage Vf) characteristics and (device current If) vs. (device drive voltage Vf) characteristics as shown in FIG. Note that the emission current Ie is significantly smaller than the element current If, and it is difficult to draw the same current on the same scale.
The graphs in the book are shown on different scales.

That is, it can be seen that the emission current Ie has the following three characteristics.

First, a certain voltage (this is referred to as a threshold voltage Vth
When the above voltage is applied to the element, the emission current Ie sharply increases. On the other hand, when the voltage is lower than the threshold voltage Vth, the emission current Ie is hardly detected. That is, it can be said that the surface conduction electron-emitting device is a non-linear device having a clear threshold voltage Vth with respect to the emission current Ie.

Second, since the emission current Ie changes depending on the device drive voltage Vf applied to the device, the magnitude of the emission current Ie can be controlled by changing the device drive voltage Vf.

Third, since the cold cathode device has a high-speed response, the emission time of the emission current Ie can be controlled by the application time of the device drive voltage Vf.

The inventors have found that the surface conduction electron-emitting device can be suitably used for a display device due to the above-described characteristics. For example, in the image display apparatus using the display panel 1 shown in FIG. 1, if the first characteristic is used, it is possible to sequentially scan and display the display screen. That is, a voltage equal to or higher than the threshold voltage Vth is appropriately applied to the element being driven, and a voltage lower than the threshold voltage Vth is applied to the element in a non-selected state. By sequentially switching the elements to be driven, the display screen can be sequentially scanned and displayed.

Further, by utilizing the second characteristic,
The light emission luminance of the phosphor can be controlled by the magnitude of the element drive voltage Vf applied to the element, and the display of a gradation image and the adjustment of image quality can be performed.

Also, by utilizing the third characteristic,
The emission time of the phosphor can be controlled by the time during which the element drive voltage Vf is applied to the element, and the display of a gradation image and the adjustment of image quality can be performed.

In the image display device of the present embodiment, the amount of the electron beam of the display panel 1 is modulated using the second characteristic.

The voltage of each part is set by setting the selection potential Vs applied to the row wiring to -0.5 VSEL (here, VSEL is
This is the absolute value of the potential difference between the selection potential and the modulation potential when giving the maximum luminance. ), The modulation potential VOL applied to the column wiring when the image data is 0 is Vth + Vs, and the modulation potential VOH applied to the column wiring when the image data is the maximum is VS.
EL + Vs. That is, VOL = Vth−0.5
VSEL, VOH = 0.5 VSEL.

<Overall System and Functional Description of Each Part> FIG.
FIG. 2 is a block diagram schematically showing the circuit configuration. In the figure, 1 is a display panel, Dx1 to DxM and Dx1 'to Dx
xM ′ is a connection terminal of the row wiring of the display panel 1, and Dy1 to DyD
yN is a connection terminal of the column wiring of the display panel, Hv is a high voltage terminal for applying an acceleration voltage between the face plate 107 and the rear plate 105, Va is a high voltage power supply, 2 is a scanning circuit, 3 is a synchronization signal separation circuit, 4 is a timing generation circuit,
Reference numeral 7 denotes an RGB conversion circuit for converting a YPbPr signal into an RGB signal by a synchronization separation circuit. Reference numeral 13 denotes a signal switching unit which switches between an HD RGB signal and a VGA signal and also has a function as an input means for inputting an image signal. 5, a shift register for one line of image data, 6 a latch circuit for one line of image data, 8 a display panel 1
Is a modulation means for outputting a modulation signal to the column wirings, 10 is a controller, 12 is a calculation unit for calculating image data and a correction amount, and outputs a corrected image signal Dout, and 14 is a correction amount calculation means. The function of each part will be briefly described below.

<Synchronization Separation Circuit and Timing Generation Circuit> The image display device of the present embodiment can display both an HD video signal and a VGA signal output from a computer or the like. However, the present embodiment is one example, and is similarly applicable to other standards such as NTSC, PAL, and SECAM.

The VGA signal is supplied to the signal switching unit 13 and the synchronization signals Vsync and Hsync are supplied to the VGA signal.
c is supplied to the timing generation circuit 4.

On the other hand, in the case of an HD video signal, first, a synchronization signal Tsync (including vertical synchronization and horizontal synchronization) is separated by a synchronization signal separation circuit 3 and supplied to a timing generation circuit 4. Then, the YPbPr signal is supplied to the RGB conversion circuit 7. In the RGB conversion circuit 7, Y
A low-pass filter and an A / D converter (not shown) are provided in addition to the PbPr to RGB conversion circuit.
The digital RGB signals converted from PbPr are supplied to the signal switching unit 13.

<Signal Switching Unit, Controller, Timing Generation Circuit> The signal switching unit 13 is a circuit for selecting between VGA and HD, and a selection signal Ts from the controller.
The video source is switched in accordance with “el”.

When a video source to be selected is set by a remote controller (not shown) or a switch, the controller 10 supplies a selection signal Tsel to each unit.

The timing generation circuit 4 outputs the selection signal Tse
The operation timing of each unit is determined in synchronization with the synchronization signal of the video source on the side selected based on 1. That is, the timing generation circuit 4 controls the operation timing of the shift register 5 by Tsft and the control signal TLo for latching data from the shift register 5 to the latch circuit 6.
ad, TPW for controlling the output of the modulating means 8, scanning circuit 2
The signals of Tscan and others for controlling the operation are generated to time the operation of each unit.

<Scanning Circuit> The scanning circuits 2 and 2 'are connected to the connection terminals Dx in order to scan the display panel 1 line by line.
Selection potential Vs or non-selection potential Vn for 1 to DxM
This is a circuit that outputs s.

The scanning circuits 2 and 2 ′ are circuits for sequentially switching the selected scanning wiring every one horizontal period and scanning in synchronization with the timing signal Tscan from the timing generating circuit 4.

Note that Tscan is a timing signal group generated from a vertical synchronizing signal, a horizontal synchronizing signal, and the like.

The scanning circuits 2 and 2 'are respectively provided with M switches 201 and shift registers 202 as shown in FIG.
Etc. These switches are preferably constituted by transistors and FETs.

In order to reduce the voltage drop in the row wiring, it is preferable to connect the scanning circuits 2 and 2 'to both ends of the row wiring of the display panel 1 and drive from both ends as shown in FIG. . Of course, the present invention is effective even when the scanning circuit is not connected to both ends of the row wiring, and it is needless to say that the present invention can be applied only by changing the parameters of the correction means described later.

In the present embodiment, the selection potential Vs output from the scanning circuits 2 and 2 'is -0.5 VSEL, the non-selection potential V
ns was set to 0V.

<Data array converter> Data array converter 9
Is a circuit for converting the arrangement of the digital RGB signals received from the signal switching unit 13 in accordance with the pixel arrangement of the display panel 1. As shown in FIG. 6, the configuration of the data array conversion unit 9 is a FIFO memory 901R, 901 for each RGB color.
G, 901B and selector 902.

Although not shown in the figure, the FIFO (F
(first-In First-Out) memory 901
R, 901G and 901B have two FIFOs for one horizontal period, one for odd lines and one for even lines.

When the odd-numbered video data is input, the data is written into the odd-line FIFO, while the image signal accumulated in the previous horizontal period is read from the even-line FIFO memory. It is. When the video data of the even line is input, the FIFO for the even line is
While the image signal accumulated in the previous horizontal period is read from the odd-number line FIFO memory.

The data read from the FIFO memory is parallel / serial converted from RGB image signals by the selector 902 in accordance with the pixel arrangement of the display panel 1 and output. These operation timings operate based on a timing control signal from the timing generation circuit 4 (FIG. 4).

<Simple Description of Correction Amount Calculating Means and Calculation Means> The functions of the correction amount calculating means 14 and the calculation unit 12 will be briefly described as detailed description will be given later. The digital video signal RGB output from the signal switching unit 13 is input to the correction amount calculation unit 14 in parallel with the input to the data array conversion unit 9.

The correction amount calculation means 14 is a circuit (calculation means) for calculating a voltage drop amount for each of the plurality of divided blocks (more precisely, for each node described later) by a correction amount calculation method described later. The voltage drop amount calculated for each block is interpolated between blocks by linear approximation. The interpolated voltage drop amount is added to the image signal in the arithmetic unit 12 and output to the shift register 5 as a corrected image signal Dout.

These operation timings operate based on a timing control signal from the timing generation circuit 4.

<Shift register and latch circuit> Operation unit 1
2 is serial / parallel converted from a serial data format to parallel image signals ID1 to IDN for each column wiring by the shift register 5, and immediately before one horizontal period starts. ,
Loaded into the latch circuit 6 by the timing signal TLoad. The output of the latch circuit 6 is supplied to the modulating means 8 as parallel image signals D1 to DN.

In this embodiment, the image signals ID1 to ID1
Each of DN and D1 to DN is an 8-bit image signal. These operation timings operate based on the timing control signals Tsft and TLoad from the timing generation circuit 4.

<Modulation means of the present embodiment> Latch circuit 6
Are output to the amplitude modulation means 8. As shown in FIG. 4, the modulator 8 includes a DA converter (DAC) 801 and a switch 802 for each column wiring. The DAC 801 has input / output characteristics as shown in FIG.

The above-mentioned latch circuit 6 outputs the parallel image signal I
To load D1 to IDN once in one horizontal period, DA
The data D1 to DN to C801 are also rewritten once in one horizontal period.

The switch 802 is provided so that the DAC 801 does not generate an abnormal potential during the settling period. When the DAC 801 is settling, the switches 802 output the potentials of AM1 to AMN at the ground potential. You. An output disable function is provided so that the output of the DAC 801 is not output while the switch 802 is in a short-circuit state.

<Method of Calculating Voltage Drop Amount of the Present Embodiment> FIG. 8 is a diagram for explaining a state of a voltage drop in a row wiring.

In the figure, the row wirings and the surface conduction type emission elements of the non-selected rows which do not contribute to the voltage drop in the selected row wiring 103 are omitted. Further, since no current is concentrated on the column wiring 104, the voltage drop there is not affected, and the column wiring 10
The resistance of 4 is ignored.

Since the illustrated row wiring 103 is a selected row,
A selection potential Vs of -0.5 VSEL is applied to both ends. The column wiring 104 has a D for generating an amplitude modulation signal.
AC 801 is connected to each column wiring 104,
The output potential AMi (i is a column number, i = 1, 2,... N) of the DAC 801 varies according to the input data to the AC 801.

Here, the current output to each column wiring 104 is defined as Ifi (i is a column number, i = 1, 2,..., N).

When a modulation signal having the amplitude shown in FIG. 7 is applied to the column wiring 104 according to the image signal, the row wiring 10 selected from each column wiring 104 is applied as shown in FIG.
3 causes a voltage drop on the row wiring 103 (as already shown in JP-A-8-248920).

In this embodiment, the selection potential Vs applied to the row wiring 103 is set to a negative potential of -0.5 VSEL, and the potential applied to the column wiring is higher than that. Due to the voltage drop on 103, the potential on row wiring 103 rises as shown in FIG. Because of this voltage drop, the voltage applied to both ends of the surface conduction electron-emitting device 102 in the selected row decreases.
It has been a conventional problem that the emission current from the surface conduction type emission element 102 decreases.

In this embodiment, a voltage drop generated on the row wiring 103 is estimated, and a potential obtained by adding the voltage drop to the amplitude value of the modulation signal applied to the column wiring 104 is applied. As a result, even if a voltage drop occurs on the row wiring 103, a desired voltage can be applied to both ends of the surface conduction electron-emitting device 102, and the effect of the voltage drop on the row wiring on the emission current is removed. It is.

The present inventors have proposed the following 1) of the display panel in order to predict the value of the voltage drop occurring on the row wiring 103.
3) were considered.

1) The value of the element current If can be obtained from the input image data based on the Vf vs. If characteristics shown in FIG. 3 and the input / output characteristics of the modulation means shown in FIG.

2) In the Vf vs. If characteristic curve of FIG. 3, if the device current when a voltage VF0 is applied to both ends of the surface conduction electron-emitting device is defined as If0, the device current of If0 is conversely reduced to the surface conduction electron-emitting device. , A voltage VF0 is generated at both ends of the element.

3) The element current If1 is applied to the column wiring 1 and the column wiring 2
, The element current IfN in the column wiring N
The voltage drop that occurs in the selected row wiring when the current flows is the same as the so-called overlapping principle. It can be easily calculated (details will be described below).

In the conventional image display device, a potential determined by the input / output characteristics of the DAC shown in FIG. 7 is applied to each column wiring according to input image data. In this case, a voltage drop occurs on the selected row wiring due to an element current flowing from the modulating means from each column wiring to the selected row wiring. The voltage determined by the potential difference between the selection potential Vs and the modulation potential was not applied, and the amount of electrons emitted from the surface conduction electron-emitting device was affected.

On the other hand, in this embodiment, first, the image data is converted into an element current value to be passed according to the characteristic of 1), and the voltage drop amount on the row wiring when the element current is passed is 3). The calculation was performed according to the characteristics of Further, if a modulation potential offset by the amount of the voltage drop is applied to each column wiring, a desired voltage is applied to each of the surface-conduction emission devices in the selected row (that is, a desired device current flows). Further, since a voltage drop determined by the characteristic 3) occurs on the selected row wiring), an image can be displayed without being affected by the voltage drop.

FIG. 9 shows an example in which the voltage drop on the row wiring is calculated based on the characteristic 3).

In the figure, the number of columns is set to 4 for simplicity,
As for the row wiring, as in FIG. The potential of the selected row is set to the ground potential for simplification (if the selected potential is -0.5 VSEL, the offset potential may be added by that amount).

The resistance value of the row wiring between a certain column and the adjacent column is set to r, which is common in all sections. Also, the resistance of the row wiring take-out portion was set to r. Also, the surface conduction electron-emitting device connected between the column wiring and the row wiring is omitted because it is not necessary for calculation.

FIG. 9A shows an example in which the current If1 is injected only into the column wiring 1. At this time, the potentials generated at ΔV1 to ΔV4 are as shown by the broken lines on the right side of the drawing (the height of the broken lines represents the potential), and the following potential difference is generated with respect to the ground potential. ΔV1 = 4/5 × r × If1 ΔV2 = 3/5 × r × If1 ΔV3 = 2/5 × r × If1 ΔV4 = 1/5 × r × If1

Similarly, FIG. 9B shows that the current I is applied only to the column wiring 2.
This is an example when f2 is injected. At this time, ΔV1 to ΔV
The potential generated at 4 is as shown by the polygonal line on the right side of the figure, and the following potential difference is generated between the potential and the ground potential. ΔV1 = 3/5 × r × If2 ΔV2 = 6/5 × r × If2 ΔV3 = 4/5 × r × If2 ΔV4 = 2/5 × r × If2

Similarly, FIG. 9C shows that the current I is applied only to the column wiring 3.
This is an example when f3 is injected. At this time, ΔV1 to ΔV
The potential generated at 4 is as shown by the broken line on the right side of the figure, and the following potential difference is generated between the potential and the ground potential. ΔV1 = 2/5 × r × If3 ΔV2 = 4/5 × r × If3 ΔV3 = 6/5 × r × If3 ΔV4 = 3/5 × r × If3

Similarly, FIG. 9D shows that the current I
This is an example when f4 is injected. At this time, ΔV1 to ΔV
The potential generated at 4 is as shown by the broken line on the right side of the figure, and the following potential difference is generated between the potential and the ground potential. ΔV1 = 1/5 × r × If4 ΔV2 = 2/5 × r × If4 ΔV3 = 3/5 × r × If4 ΔV4 = 4/5 × r × If4

Between these, due to the above-mentioned characteristic 3),
Since the logic of superposition holds, the element currents If
The potentials generated at ΔV1 to ΔV4 when 1 to If4 are injected follow Equation 1.

[0101]

(Equation 1)

In this example, a simple model with four column wirings has been described. However, even if the number of columns is larger or the resistance values of the wirings become uneven, the constants and the like will change. It was confirmed that this law holds.

Although the number of column wirings of an image display device is several hundreds or more, even if the number of column wirings increases, the above calculation method is repeated for each column wiring.
It is possible to calculate the amount of voltage drop on the selected row wiring.

The above operation is a matrix operation shown in Expression 2 for a display panel having N column wirings. However, in order to perform the operation of Equation 2 in synchronization with one horizontal period,
Since the amount of calculation is very large, large-scale hardware is required (N × N multiply-accumulate operations need to be performed N times).

[0105]

(Equation 2) Here, aij (i = 1 to N, j = 1 to N) is a constant determined by the value of the wiring resistance.

Therefore, the present inventors have proposed a display panel as shown in FIG. 10A to simplify the calculation.
An approximate solution of the voltage drop amount is calculated using the degenerated approximate model as shown in FIG.

That is, as shown in the figure, the following modeling was performed.

The N column wirings were divided into four blocks (n = N / Block, where Block = 4).

The sum of the device currents in the block flows into the row wiring at the center of each block.

Nodes P1 to P5 are defined at positions that are boundaries between blocks, and the potential difference (voltage drop amount) between the potential of the nodes P1 to P5 and the supply end potential (Vs) of the selected row wiring is represented by ΔV1 to ΔV5. (Since the node is defined by the position of the boundary between the blocks, the calculation becomes easier when performing a linear approximation described later.)

The resistance between adjacent nodes is multiplied by n in consideration of degeneration.

Note that ΔV1 to ΔV5 in the approximation model of FIG. 10B can be easily calculated by the matrix operation shown in Equation 3 as in FIG.

[0113]

(Equation 3)

Note that IFj is the sum of the current values If of the block j. The current If of a certain column wiring can be obtained from the input / output characteristics of the modulation means in FIG. 7 and the characteristics of the surface conduction electron-emitting device in FIG. Therefore, IFj can be easily calculated by dividing the image data for one horizontal period into a plurality of blocks, determining the element current for each block, and adding the element current for each block.

Also, bij is i when the unit current is injected into the j-th block with reference to the end of the row wiring.
The potential of the node. This is a constant determined by the value of the wiring resistance and the like, and can be easily calculated according to Kirchhoff's law.

Therefore, the values ΔV1 to ΔV5 of the voltage drops at the nodes P1 to P5 can be approximately obtained by performing the calculation of Expression 3.

Next, in the present embodiment, the amount of voltage drop in the column wiring located between the nodes is based on Equation 4, and the amount of voltage drop ΔVk,
It was determined by linear approximation from ΔVk + 1.

[0118]

(Equation 4)

As described above, by defining the position of the node on the boundary of the block, there is an advantage that the voltage drop amount at a point inside the block can be easily linearly approximated even at the end block. (In other words, straight line approximation at the end block can be performed more easily than defining a node at the center of the block.)

In the above example, an example in which the number of blocks is four has been described, but it goes without saying that approximation errors can be reduced by further increasing the number of blocks. The present inventors have confirmed that, since the curve of the voltage drop generated on the row wiring is a smooth curve, if the number of blocks is sufficiently increased, the approximation error due to the linear approximation has almost no problem in practical use. I have.

The optimum number of blocks may be selected in consideration of the value of the wiring resistance, the characteristics of the surface conduction electron-emitting device, the modulation voltage, the number of column wirings, errors caused thereby, and the like.

The amount of calculation is N before approximation.
Had to be repeated N times,
As shown in the matrix operation of Expression 3, the product-sum operation may be repeated (Block) × (Block + 1) times, and the amount of calculation can be greatly reduced (in the above example, since Block = 4, 4 × 5 = 20 product-sum operations.In general, this degree of calculation is performed for one horizontal period.
Can be executed in a sufficiently short time. ).

The voltage drop amount calculated as described above is added to the modulation potential applied to the column wiring, and is applied to the column wiring with an offset by that amount. The current is not affected by the voltage drop on the row wiring.

Therefore, by performing such correction,
It is possible to improve the image degradation due to the influence of the voltage drop, which has been a problem to date.

Further, the calculation is not performed for all the column wirings, but is performed by approximation according to the above-described calculation method. Since the calculation can be performed by the matrix operation of Expression 3 and the linear approximation of Expression 4, the calculation amount can be significantly reduced.

Further, since the amount of calculation is reduced, the calculation of Expressions 3 and 4 can be realized by hardware having a very simple configuration as described below.

<Detailed Description of Correction Amount Calculation Means> The correction amount calculation means 14 includes two parts, a ΔIf calculation unit 400 and a voltage drop calculation unit 410, as shown in FIG.

The 計算 If calculating section 400 constitutes a first calculating means for dividing the video signal for one horizontal period into a plurality of blocks and calculating the sum of the element currents If of the individual blocks. In the figure, reference numeral 401 denotes a conversion table as conversion means for converting image data into If values. Also 402
Denotes a selector, 403 denotes an adder, and 405 denotes a group of registers for $ If provided with registers A1 to A4 for storing the calculated sum (IF) of If for each block.

The input RGB parallel digital image signal is switched by the selector 402, converted into serial image data, and output to the conversion table 401. The conversion table 401 is shown in FIG. 7 (image signal).
This is a table created from the relationship between the pair (drive potential) and the relationship between the (drive voltage) and the (device current If) shown in FIG. 3, and converts image data into a device current If. Thereafter, the addition is performed by the adder 403 for each area of the block.
The value of IF obtained for each block is stored in the registers A1 to A4 upon completion of the calculation.

The voltage drop calculator 410 has a four-input one-output selector 411, an integrator 412, an adder 413, registers B1 to B5 for storing calculation results, and a pattern memory for storing a matrix of the formula (3). 414.

Here, the voltage drop calculator 410 constitutes the second calculating means, and the pattern memory 414 stores
, That is, parameters obtained from the wiring resistance between the nodes.

When the IF calculation unit 400 calculates the IF for each block, the selector 411 appropriately selects the value of the IF. In synchronism therewith, the elements of the matrix of Equation 3 are appropriately read from the pattern memory 414, accumulated by the integrator 412, and transferred to the adder 413. The adder 413 appropriately adds the data from the integrator 412 to perform the matrix operation of Expression 3, and stores the data in the registers B1 to B5 when the calculation is completed.

The timing generation circuit 4 shown in FIG. 4 controls the timing of the selector 411, the pattern memory 414, the integrator 412, the adder 413, and the registers B1 to B5 so that the operation of Equation 3 is performed.

By performing the above processing, ΔV1 to ΔV1
The amount of voltage drop to V5 is calculated and transferred to the calculation unit. Note that ΔV1 to ΔV5 are digital signals.

<Details of Calculation Unit> The calculation unit 12 calculates the voltage drop amount ΔV of each node calculated by the correction amount calculation unit 14.
This is an image signal correction means for calculating a voltage drop correction amount of each column wiring by linear approximation (linear interpolation) of 1 to ΔV5 and adding the correction value to image data.

Voltage drop ΔV at column address x
(X) can be calculated according to Equation 4 using ΔVk and ΔVk + 1 and the column addresses Xk and Xk + 1 of the respective nodes, where k is the block to which the column wiring x belongs. FIG. 12 is a diagram schematically showing Equation 4. Here, the voltage drop amount ΔV obtained based on Equation 4
(X) is the voltage drop correction amount for the column wiring of the column address x.

The operation unit 12 reads out ΔV1 to ΔV5 calculated by the correction amount calculation means 14 in synchronization with the transfer of the image data Data from the data array conversion unit 9, and reads out each column address in accordance with Equation 4. The voltage drop correction amount is calculated by linear approximation, and added to the image data Data.

FIG. 13 shows the configuration of the arithmetic unit 12. In the figure, 301 and 302 are selectors, 303 and 304 are integrators, 305 and 309 are adders, 306 is a divider, 3
07 and 308 are subtractors.

The selectors 303 and 304 determine whether the voltage drop calculator 410 of the correction amount calculator 14 has ΔV1 to ΔV
When the voltage drop amount of 5 is calculated, the voltage drop amounts ΔV1 to ΔV5 are appropriately selected and supplied to the integrator 303 in synchronization with the transfer of the image data Data.

The subtracters 307 and 308 respectively calculate x−Xk and Xk + from the column addresses x and Xk and the address Xk + 1 transferred from the timing generation circuit 4.
1−x is calculated and output to the integrators 303 and 304.

The integrator 307 performs the integration of the first term of the numerator of Formula 4, and the integrator 308 performs the operation of the second term.
Transfer the result to 05.

The adder 305 calculates the numerator of Equation 4 and
The result is transferred to the divider 306.

The divider 306 divides the numerator of Equation 4 received from the adder 305 by the value of Xk + 1−Xk, and transfers the result to the adder 309. The result obtained here is the voltage drop correction amount of the column wiring of the column address x.

The adder 309 as an adding means adds the voltage drop correction amount to the input image data Data, and transfers the corrected image data Dout to the shift register 5. Each of the above-described units operates based on the timing control of the timing generation circuit 4. It is noted that the column address of the input image data Data and the column address of the correction amount are synchronized at the time of being input to the adder 309. Needless to say.

In the above example, the example including the divider 306 is shown, but it is more preferable to select the number of column wirings in one block to a power of two. This is because if the number of column wirings in a block is a power of 2, the above-described divider 306 can be replaced with a bit shift circuit and can be implemented very easily. Also, the subtractors 307 and 308 can be configured by a simple decoding circuit if the number of column wirings in one block is selected to be a power of 2, which is very advantageous.

Further, even if the total number of column wirings on the display panel is not a multiple of a power of two, if the total number is close to that value, the number of column wirings in the block is selected to be a power of two, and fractions are ignored. There is a great merit that hardware can be easily realized by doing.

For example, in an image display device in which the number of pixels in the horizontal direction is 640 (the number of column wirings = 1920 (three RGB column wirings are required for one pixel)), the number of column wirings per block is 128, and the number of blocks is 128. Was set to 15.

In another example, the number of pixels in the horizontal direction is 852.
In the image display device of (the number of column wirings = 2556), the number of column wirings for one block is 256, and the number of blocks is 1
0 was set. The four fractions are assumed to have virtually no wiring in which current does not flow in the blocks at both ends.

The arithmetic unit 12 has the effect of smoothing the correction amount for each block by interpolating the voltage drop correction amount by linear approximation. However, if the number of block divisions is increased, it is necessary to perform linear approximation. However, even if the voltage drop amount for each block from the correction amount calculation means is added to the image data as it is, a satisfactory image display can be performed.

The number of column wirings for the divided blocks does not necessarily have to be the same.

In particular, the shape of the potential distribution generated on the row wiring is a curve that is upwardly convex, and has a characteristic that the slope becomes steeper toward the end of the row wiring (FIG. 8).
(B)). Taking this feature into account, by dividing the block into smaller blocks toward the ends of the row wiring and coarser blocks toward the center, errors can be reduced without increasing the number of blocks, and the amount of calculation is further reduced. There is a merit such that the number can be reduced (if the division is performed unequally, the parameter may be changed accordingly).

In the above example, the correction amount of the voltage drop in the block is interpolated by linear approximation. However, the present invention is not limited to this, and other approximation methods such as polynomial approximation can be used.
Interpolation may be performed.

In the correction amount calculating means 14 and the calculating section 12, the bit width for calculating the correction amount does not necessarily need to have the same width as the image data. For example, if the maximum value of the correction amount is 50, the calculation may be performed with a bit number of 6 bits, and the correction amount may be added to the lower 6 bits of the image data.

<Operation Timing of Each Unit> FIGS. 14 and 1
FIG. 5 shows a timing chart of the operation timing of each unit. FIGS. 15A, 15B, and 15C show the details of the parts 501, 502, and 503 in FIG. 14, respectively.

In the figure, HD is a horizontal synchronizing signal,
DotCLK is a clock generated from the horizontal synchronizing signal HD by the PLL circuit in the timing generation circuit 4, R,
G and B are digital image signals from the signal switching unit 13, Data is an image signal after data array conversion, Dout
Is the digital image signal after voltage drop correction,
TSFT is a shift clock for transferring the image data Dout to the shift register 5, TLoad is a load pulse for latching data to the latch circuit 6, TPW is a timing for controlling the switch 802 of the modulation means 8, and is the same signal. Is high, the output of the modulating means 8 is grounded. The modulation signal AM1 is an example of an amplitude modulation signal supplied to the column wiring 1.

At the start of one horizontal period, the digital image signals RGB are transferred from the signal switching section 13. After storing the image data for one horizontal period, the data array conversion unit 9 rearranges the RGB digital image signals according to the pixel arrangement of the display panel 1 and outputs the rearranged image signals in the next horizontal period.

The digital image signals RGB are input to the correction amount calculating means 14 at the same time. As shown in FIG. 11, the correction amount calculation means 14 calculates the sum of the element currents for each block together with the input of the image signal RGB in the ΣIf calculation section 400, and upon completion of the calculation, outputs the calculation results IF1 to A4 to registers A1 to A4. IF4 is stored.

When the calculation of IF4 of the last block is completed, the voltage drop amount calculating section calculates Δ4 according to Equation 3.
The correction amounts of V1 to ΔV5 are appropriately calculated, and the calculation results are stored in registers B1 to B5 upon completion of the calculation.

In the next scanning period, in synchronization with the transfer of the image data Data having been subjected to the data array conversion to the arithmetic unit 12, the arithmetic unit 12 calculates the correction amount between the nodes based on the equation (4). Is calculated by linear approximation, added to the image data Data, and the corrected image data Dout is transferred to the shift register 5.

The shift register 5 stores image data Dout for one horizontal period in accordance with Tsft, performs serial / parallel conversion, and outputs parallel image data ID1 to IDN to the latch circuit 6.

The latch circuit 6 latches the parallel image data ID1 to IDN from the shift register 5 according to the rise of Tload, and latches the latched image data D1.
1 to DN are transferred to the modulating means 8.

The modulating means 8 has a DAC
801 and a switch 802, etc.
The amplitude modulation signals AM1 to AMN having the amplitudes corresponding to the image data D1 to DN are supplied to each column wiring according to the input / output characteristics shown in FIG. FIG. 14 shows an example of AM1. These amplitude modulation signals AM1 to AMN are signals having amplitudes determined from the input image data and the correction amount of the voltage drop in the horizontal period. The image display device of the present embodiment (FIG. 4) displays an image according to such timing.

When an image is displayed by such an image display device, it is possible to suppress the influence of the voltage drop in the row wiring, which has been a conventional problem, and to suppress the deterioration of the display image due to the voltage drop. It could be improved and a very good image could be displayed.

Further, by introducing the approximation calculation described in Expressions 3 and 4, the calculation amount required for calculating the correction amount can be significantly reduced, and the calculation amount can be reduced with very simple hardware. There was a very good effect that it could be realized.

(Second Embodiment) In the first embodiment, the amount of correction for correcting a voltage drop is calculated by small-scale hardware by introducing some approximations. The correction amount is added to the image signal based on the correction value to correct the voltage drop.

The present inventors have found that in the configuration of the first embodiment, by providing a limit means so that overflow does not occur due to the addition of the correction amount to the image signal, it is more effective.

FIG. 16 shows a second embodiment of the present invention. FIG. 16A shows a part of the display circuit according to the present embodiment, in which 13 is a signal switching unit, 9 is a data array conversion unit, 14 is a correction amount calculation unit, 12 is a calculation unit,
0 is a limit means of the present embodiment.

In the first embodiment, the signal switching unit 13, the data array conversion unit 9, and the correction amount calculation unit 14
Although the image signals RGB are directly supplied to the image forming apparatus (FIG. 4), in the present embodiment, as shown in FIG. 16A, a limiting means 20 as a limiting means is newly provided between the two.

Since other configurations and operations are the same as those of the first embodiment, the same components are denoted by the same reference numerals and description thereof will be omitted.

The limit means 20 is a circuit for converting the input image signal, for example, as shown in FIG. 16 (b) and limiting the maximum value of the image signal. It is assumed that the signal has 8 bits and takes a value in the range of 0 to 255.) As a result, the input image signals R, G, and B are converted into image signals R ′, G ′, and B ′ from the minimum 0 to the maximum 200, respectively, and supplied to the data array conversion unit 9 and the correction amount calculation unit 14. Is done.

In the correction amount calculating means 14 and the calculating section 12,
As in the first embodiment, a correction amount is calculated, and correction is applied to the image data.

In the image display device of the present embodiment, when the correction amount of the voltage drop is calculated, the correction amount of the voltage drop occurs when all white is displayed on the display panel, and the maximum value of the correction amount is It was 50. Therefore, even when the correction amount is added to the image data by the correction amount calculating means 14 and the calculation unit 12, the corrected image data is 2 at a maximum.
Since it was suppressed to 50 (= 200 + 50), overflow did not occur due to the correction, and the image was displayed very well when displayed.

(Third Embodiment) In the second embodiment, when correcting the image data based on the voltage drop correction amount, the image data is limited to a certain value or less in advance so as not to overflow. This is an example in which a correction amount is added thereto.

In the third embodiment of the present invention shown in FIG. 17, overflow is prevented by a different configuration from the second embodiment.

FIG. 19 shows a part of the display circuit of the present embodiment, in which 13 is a signal switching unit, 9 is a data array conversion unit, 14 is a correction amount calculating unit, 12 is a calculation unit, and 21 is a unit of the present embodiment. The limiting means is a limiting means of the form (1).

In the second embodiment, the data is directly supplied from the operation unit 12 to the shift register 5. In this embodiment, however, a limit means 21 is newly provided between the operation unit 12 and the shift register 5. ing.

The other configuration and operation are the same as those of the first embodiment. Therefore, the same components are denoted by the same reference numerals and description thereof will be omitted.

The arithmetic unit 12 according to the present embodiment performs the arithmetic described in the first embodiment. However, in this embodiment, the input image data is processed so that the processing by the arithmetic unit 12 does not cause an overflow. The data width (the number of bits) of the data is larger than that of RGB or Data (for example, when the input image data is 8 bits, the operation of the operation unit is 9 bits).

In the image display device according to the present embodiment, when the correction amount of the voltage drop is calculated, the correction amount of the voltage drop occurs when all white is displayed on the display panel, and its magnitude is 50 at the maximum. Met. Therefore, when this is added to the image signal, the corrected image signal has a maximum of 305
(= 255 + 50).

The limit means 21 is a means for converting the image signal corrected by the calculation unit 12 as shown in FIG. That is, the input image data Dout ′ having a value of 0 to 305 is linearly converted to a value of 0 to 255. When a value of 306 or more is input, 255 is output uniformly.

By providing the limit means 21 as described above, the corrected image signal is limited to a maximum of 255. When the image signal was limited by such a limit means 21, there was no overflow due to the correction, and the image could be displayed satisfactorily.

(Fourth Embodiment) In the first embodiment, the voltage drop correction amount is reflected on the amplitude of the modulation signal by digitally adding the voltage drop correction amount for each column address to image data. This is an example.

In the present embodiment, as a configuration for obtaining the same effect, an analog offset terminal is provided in the DA converter of the modulating means 8, the voltage drop correction amount is D / A converted, and the converted analog potential is modulated. It is configured to supply the offset of the means 8. In this way, the present inventors have confirmed that the same effect as in the above embodiment can be obtained by adding in an analog manner. Other configurations and operations are the same as those of the first embodiment.

When the voltage drop amount is subjected to D / A conversion, all the voltage drop correction amounts are continuous amounts that are convex upward in the column wiring direction (FIG. 8B). It is not necessary to provide a DA converter for the column wiring. For example, one DA converter for converting a digital voltage drop amount into an analog signal may be provided for each of the K columns (K is a certain integer), thereby adjusting the offset amount of the modulation means 8. Alternatively, a voltage may be divided by connecting a plurality of resistors in series between the plurality of DA converters, and a potential obtained by the divided voltage may be supplied to an offset terminal of the modulating unit 8.

With such a configuration, since the image data is not corrected, it is not necessary to provide the limit means and the like described in the second and third embodiments, and the entire data width of the image data can be reduced. Therefore, there is an advantage that the correction does not reduce the effective number of gradations.

(Fifth Embodiment) In each of the first to fourth embodiments, the voltage drop correction amount is added to the image signal to control the amplitude of the modulation signal applied to each column wiring. Thus, the voltage drop is corrected.

In this embodiment, the amount of voltage drop on the row wiring generated according to the image pattern is calculated with a relatively small circuit scale, and the pulse width of the modulation signal applied to each column wiring is controlled based on the calculated voltage drop. Thereby, the deterioration of the image due to the influence of the voltage drop is improved. That is, in the present embodiment, the third characteristic of the cold cathode device described above is used. Note that the modulating means of this embodiment is a voltage amplitude modulating means as in the first embodiment.

The configuration of the image display apparatus according to the present embodiment will be described below with reference to the drawings. The same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted. Shall be omitted.

<Description of Function of Entire System and Each Part> FIG.
FIG. 8 is a block diagram schematically showing a circuit configuration of the image display device according to the present embodiment. In the figure, 1 is a display panel, Dx1 to DxM and Dx1 'to DxM' are row wiring terminals of the display panel 1, Dy1 to DyN are column wiring terminals of the display panel 1, Hv is a face plate 107 and a rear plate 105. Is a high voltage terminal for applying an acceleration voltage, Va is a high voltage power supply, 2 is a scanning circuit, 3 is a synchronization signal separation circuit, 4 is a timing generation circuit, and 7 is a synchronization separation circuit for converting the YPbPr signal into an RGB signal. RGB for
A conversion circuit 13, a signal switching section 13 for switching between HD RGB signals and VGA signals, a shift register 5 for one line of image data, a latch circuit 6 for one line of image data, and a controller 10 are shown.

Further, reference numeral 15 denotes a correction amount calculating means of the present embodiment, 16 denotes an operation section which is an application time determining means of the present embodiment, 17 denotes a shift register for pulse data, and 18 denotes a pulse width modulation circuit. . Reference numeral 19 denotes a modulation unit 19 that outputs a modulation signal to a column wiring of the display panel 1.

<Description of Correction Amount Calculation Means and Calculation Means> The digital video signal R output from the signal switching unit 13
GB is input to the correction amount calculating means 15 in parallel with the input to the data array conversion unit 9.

The correction amount calculating means 15 calculates ΔI as shown in FIG.
It is composed of two parts, an f calculation unit 400 and a voltage drop calculation unit 420. Since the configuration and operation of the ΣIf calculation unit 400 are the same as those of the first embodiment, the description is omitted here.

The voltage drop calculator 420 of the present embodiment
As shown in FIG. 19, it is configured by a voltage drop memory 421 and registers B1 to B5.

The voltage drop memory 421 stores the I
This is a conversion table in which the values of ΔV1 to ΔV5 for the size of F are stored, and the addresses thereof are the amounts of IF (IF1 to IF) for each block from the ΣIf calculation unit 400.
4) is connected. That is, IF1 is assigned to each address.
.DELTA.V, which is the calculation result of Equation 3, just by inputting .about.IF4.
1 to ΔV5 can be obtained.

It is not necessary to input all bits of the IF size for each block to the address of the voltage drop memory 421. For example, the MSB (Most) of the data is not required.
Only three bits may be input from the Significant Bit (most significant bit). In this case, if the number of blocks is 4, 3 bits × 4 + 3 bits (ΔV
(For selection of 1 to ΔV5) = Simple configuration with a memory having an address of 15 bits.

As a method of calculating the voltage drop amount ΔV from the IF of each block, the calculation may be performed as needed using an integrator and an adder as in the first embodiment, or the present embodiment may be used. The voltage drop memory 42 uses a value calculated in advance or an actually measured voltage drop amount as a conversion table as shown in FIG.
It may be stored as 1 or the like.

Of course, it goes without saying that the voltage drop correction amount may be calculated based on the conversion table used in the present embodiment in the first to fourth embodiments.

The voltage drop amounts ΔV1 to ΔV5 obtained by the voltage drop memory 421 in which the conversion tables are stored are stored in registers B1 to B5 as appropriate based on a timing control signal from the timing generation circuit 4.

<Details of Arithmetic Unit> FIG. 20 shows the configuration of the arithmetic unit 16 which is the application time determining means of this embodiment.

The calculating section 16 calculates the voltage drop amounts ΔV1 to ΔV5 at each node calculated by the correction amount calculating means 15.
Is linearly approximated and the pulse width data CData is output.

In the arithmetic section 16, as in the first embodiment, selectors 301 and 302, integrators 303 and 304,
Adder 305, divider 306, subtractors 307 and 308
Is used to calculate the voltage drop amount ΔVf by linear approximation.

The calculated voltage drop amount ΔVf is input to ΔVf versus pulse width conversion table 310. The ΔVf-to-pulse width conversion table 310 stores pulse widths corresponding to voltage drop amounts ΔVf in association with each other.

FIG. 21 shows a ΔVf-to-pulse width conversion table 3
FIG. 10 is a diagram for explaining FIG. FIG. 3A plots the relationship between the voltage drop ΔVf and the emission current Ie. FIG. 21A shows the relationship between (drive voltage) and (element current If) shown in FIG. 3 with the amount of voltage drop ΔVf from the potential VSEL on the horizontal axis. Note that FIG.
In FIG. 3A, the voltage drop amount ΔVf is plotted on the horizontal axis, so that the left and right sides are inverted as compared with FIG.

FIG. 21B shows values of (voltage drop) vs. (pulse width) stored in the ΔVf versus pulse width conversion table 310 and obtained from the graph of FIG. 21A.

In the case of display panel 1 of the present embodiment, the maximum amount of voltage drop is when a modulation signal having the maximum amplitude is applied to all column wirings, and the amount of voltage drop at that time is the center of row wiring. In the section, ΔVf was 0.5 V, and the emission current Ie at that time was 80% of that when ΔVf = 0 V (FIG. 21A).

In this embodiment, ΔVf shown in FIG.
In determining the value of the pulse width conversion table 310, the pulse width was determined so that the product of the emission current and the pulse width was constant. That is, the pulse width when ΔVf = 0.5V (maximum voltage drop) is 255, the pulse width when ΔVf = 0.25V is PW1, and the pulse width when ΔVf = 0V is PW1.
When W2 is set, the following equation is satisfied. 255 × 80% (ΔVf = 0.5V) = PW1 × 88% (ΔVf = 0.25V) = PW2 × 100% (ΔVf = 0V)

From the above equations, PW1 and PW2 are obtained as follows. PW1 = 231 PW2 = 204

Similarly, the value of the pulse width for each voltage drop amount was calculated, and a conversion table as shown in FIG. 21B was created.

Using the above conversion table, the voltage drop amount was converted into a pulse width value, and the data CData was transferred to the shift register 17.

[0210] In this embodiment, an example is shown in which the pulse width is represented by 8 bits, but the present invention is not particularly limited to this.

In the above description, the conversion was performed using the conversion table shown in FIG. 21B. For example, FIG. 22A and FIG.
The conversion table shown by a solid line may be used in FIG. 5 (in the figure, the conversion table of FIG. 515 (b) is shown by a dotted line).

[0212] Although the voltage drop is not sufficiently corrected in the table shown in the figure, the time width of the modulation signal is set longer than that in the table of FIG. There is another advantage of not.

For example, when displaying an image of a computer, it is desired to remove the influence of the voltage drop.
It is preferable to use the conversion table of FIG. 22. However, when displaying an image such as a natural image, in order to increase the overall display luminance, the correction width of the correction amount of the voltage drop is reduced.
It is preferable to use a table such as that shown in FIG.

Therefore, it is preferable to determine what type of conversion table to use in consideration of the degree of image deterioration due to the voltage drop, the emission luminance of the entire display image, the type of display image, and the like.

<Shift register 17 and pulse width modulation circuit 18> Returning to FIG. 18, the shift register 17 and pulse width modulation circuit 18 will be described.

Image data CDa output from the operation unit 16
ta is converted from a serial data format by the shift register 17 into a parallel image signal C for each column wiring.
D1 to CDN are serially / parallel-converted, and immediately before one horizontal period starts, the timing signal Tstart
Is loaded into the pulse width modulation circuit 18. The pulse width modulation circuit 18 outputs pulse width modulation signals CD1 to CDN having a pulse width corresponding to CD1 to CDN to the modulation means 19.

These operation timings are determined by the timing control signals Tsft, TLoad from the timing generation circuit 4.
And Tstart. In this example, since the entire timing is created so that the image signal Data and the pulse width data CData for the same column are accumulated in the shift register at the same timing, the shift registers 5 and 17 are operated with the same shift signal. But I'm not particular about this.

<Modulation means of the present embodiment> Latch circuit 6
Are output to the amplitude modulating means 19. As shown in FIG. 18, the modulating means 19 includes a DA converter (DAC) 8 for each column wiring.
03 and a switch 804. DAC 803
It has input / output characteristics as shown in FIG. The above-described latch circuit 6 loads the parallel image signals ID1 to IDN once in one horizontal period.
To DN are also rewritten once in one horizontal period.

The switch 804 is turned on / off based on the pulse width modulation signals CD1 to CDN from the pulse width modulation circuit 18. When the switch is in the short-circuit state, the DAC 803 controls the modulation means 19 so as not to output.
Was prepared.

<Operation Timing of Each Unit> FIGS. 23 and 2
FIG. 4 shows a timing chart of the operation timing of each unit. FIGS. 24A, 24B and 24C show the details of the parts 504, 505 and 506 in FIG. 23, respectively.

[0220] In the figure, HD is a horizontal synchronizing signal,
DotCLK is a dot clock, R, G, and B are digital image signals from the input switching unit 13, Data is an image signal after data array conversion, CData is a voltage drop correction amount, TSFT is in the shift registers 5 and 17, and the image data is A shift clock for transferring CData, TLoad is a load pulse for latching data to the latch circuit 6, Tstart is a count start signal of the pulse width modulation circuit 18, and the modulation signal AM1 is supplied to the column wiring 1. It is an example of an amplitude modulation signal.

At the start of one horizontal period, digital image signals RGB are transferred from signal switching section 13. After storing the image data for one horizontal period, the data array conversion unit 9 rearranges the RGB digital image signals according to the pixel arrangement of the display panel 1 and outputs the rearranged image signals in the next horizontal period.

The digital image signals RGB are input to the correction amount calculating means 15 at the same time. The correction amount calculating means 15 calculates the sum of the element currents for each block together with the input of the image signal RGB, and upon completion of the calculation, stores the calculation results IF1 to IF4 in the registers A1 to A4.

At the end of the calculation of IF4 of the last block, the voltage drop amount calculating section calculates Δ
The correction amounts of V1 to ΔV5 are read from the voltage drop memory 421 as needed, and the calculation results are stored in the registers B1 to B5.

In the next scanning period, in synchronization with the transfer of the image data Data having undergone the data array conversion to the arithmetic unit 12, the arithmetic unit 12 calculates the amount of correction between nodes based on Equation 4. Is calculated by linear approximation, and the voltage drop amount ΔVf in each column is calculated. The calculated ΔVf is Δ
The data is input to the Vf-to-pulse width conversion table 310, converted into pulse width data CData, and transferred to the shift register 17 in synchronization with Tsft.

The shift register 17 stores image data Dout for one horizontal period in accordance with Tsft, performs serial / parallel conversion, and outputs parallel pulse width data IW1 to IWN to the pulse width modulation circuit 18.

The pulse width modulation circuit 18 starts counting according to the rise of Tstart, and at the same time when the count becomes data IWi (i = 1, 2,..., N), the pulse whose output changes from low to high at the same time. The width modulation signals CD1 to CDN are supplied to the modulation means 19. C
An example of D1 is shown in FIG. The modulating means 19 outputs modulation signals AM1 to AMN having amplitudes corresponding to the image data D1 to DN and pulse widths corresponding to CD1 to CDN to each column wiring.

Image display device of the present embodiment (FIG. 18)
Displayed an image according to such a timing.

When an image is displayed by such an image display device, it is possible to suppress the influence of the voltage drop in the row wiring, which has been a problem in the past, and to suppress the deterioration of the display image caused by the voltage drop. It could be improved and a very good image could be displayed.

Further, by using the voltage drop correcting means and the calculating means of the present embodiment, the amount of calculation required to calculate the amount of correction can be significantly reduced, and furthermore, very simple hardware can be used. There was a very good effect, such as being able to achieve that.

[0231]

As described above, according to the present invention, a plurality of nodes are provided on a row wiring, a voltage drop amount at each node is calculated based on an input image signal for one row, and the voltage drop amount is calculated. Since the element drive voltage applied to each of the plurality of column wirings is corrected based on the above, degradation of a display image due to a voltage drop on a row wiring, which has been a conventional problem, can be improved.

Also, the amount of calculation for calculating the amount of correction of the voltage drop can be significantly reduced, and it can be realized with very simple hardware.
There was a very good effect.

[Brief description of the drawings]

FIG. 1 is a schematic perspective view of a display panel used in an image display device according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram of a matrix wiring.

FIG. 3 is a diagram illustrating characteristics of a surface conduction electron-emitting device.

FIG. 4 is a block diagram schematically illustrating a circuit configuration of the image display device according to the first embodiment of the present invention.

FIG. 5 is a schematic configuration diagram of a scanning circuit of the embodiment.

FIG. 6 is a schematic configuration diagram of a data array conversion unit of the embodiment.

FIG. 7 is a diagram showing input / output characteristics of a DAC of the modulation means of the embodiment.

FIG. 8 is a diagram for explaining a state of a voltage drop in a row wiring.

FIG. 9 is a diagram for explaining a method of calculating a voltage drop amount according to the first embodiment.

FIG. 10 is a diagram showing an approximate model introduced in the voltage drop amount calculating method according to the embodiment;

FIG. 11 is a schematic configuration diagram of a correction amount calculating unit of the embodiment.

FIG. 12 is a diagram schematically showing Expression 4 and illustrating linear interpolation between nodes.

FIG. 13 is a schematic configuration diagram of a calculation unit according to the first embodiment.

FIG. 14 is a timing chart showing operation timing of each unit of the image display device according to the embodiment.

FIG. 15 is a detailed view of a main part of the timing chart.

FIG. 16A is a block diagram schematically illustrating a circuit configuration of an image display device according to a second embodiment of the present invention;
(B) is a diagram showing input / output characteristics of the limit means of the embodiment.

FIG. 17A is a block diagram schematically illustrating a circuit configuration of an image display device according to a third embodiment of the present invention;
(B) is a diagram showing input / output characteristics of the limit means of the embodiment.

FIG. 18 is a block diagram schematically illustrating a circuit configuration of an image display device according to a fifth embodiment of the present invention.

FIG. 19 is a schematic configuration diagram of a correction amount calculating unit of the embodiment.

FIG. 20 is a schematic configuration diagram of a calculation unit according to the embodiment.

FIG. 21 is a diagram for explaining a ΔVf-to-pulse width conversion table of the embodiment.

FIG. 22 is a diagram showing a modified example of the ΔVf versus pulse width conversion table.

FIG. 23 is a timing chart showing the operation timing of each unit of the image display device according to the fifth embodiment.

FIG. 24 is a detailed view of a main part of the timing chart.

FIG. 25 is a block diagram schematically showing a circuit configuration of a conventional image display device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Display panel 2, 2 'scanning circuit 3 Synchronization signal separation circuit 4 Timing generation circuit 5, 17 Shift register 6 Latch circuit 7 RGB conversion circuit 8, 19 Modulation means 9 Data array conversion part 10 Controller 12 Operation part (Image signal correction means 13) Signal switching unit (input means) 14, 15 Correction amount calculation unit (calculation unit) 16 Operation unit (wiring voltage drop amount calculation unit) 18 Pulse width modulation circuit 20, 21 Limiting unit (limiting unit) 101 Substrate 102, 102a Surface conduction type emission device (cold cathode device) 103 row wiring 104 column wiring 105 rear plate 107 face plate 108 fluorescent film (light emitting means) 109 metal back 201 switch 202 shift register 301, 302 selector 303, 304 accumulator 305 adder 306 Divider 307, 08 Subtractor 309 Adder (adding means) 310 ΔVf to pulse width conversion table (application time determining means) 400 ΣIf calculating section (first calculating means) 401 Conversion table (converting means) 402 Selector 403 Adder 410 Voltage drop calculation Section (second operation means) 411 selector 412 integrator 413 adder 414 pattern memory 420 voltage drop calculation section (second operation means) 421 voltage drop memory P1 to P5 nodes

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/22 G09G 3/22 DH

Claims (16)

[Claims] A plurality of display elements arranged two-dimensionally connected in a matrix by a plurality of row wirings and a plurality of column wirings; and a plurality of driving elements connected to one row wiring. In the image display device for simultaneously driving the display elements, input means for inputting an image signal of each column for one row, and a plurality of column wirings are located between adjacent nodes on the row wirings. Calculating means for calculating the amount of voltage drop at each node based on the input image signal, based on the amount of voltage drop calculated by the calculating means,
An image display device comprising: a correction unit configured to correct a signal waveform applied to each of a plurality of column wirings. 2. The node is set such that power-of-two column wirings are located between adjacent nodes.
An image display device according to claim 1. 3. An image signal of each column of one row is divided into a plurality of blocks each corresponding to each of the plurality of nodes, and a voltage drop amount at each node is calculated based on the image signal of each block. The image display device according to claim 1. 4. The image display device according to claim 3, wherein the plurality of blocks are set such that an image signal corresponding to a column wiring sandwiched between adjacent nodes is one block. 5. A row wiring to which a selection potential is applied from both ends thereof, wherein the number of column wirings located between adjacent nodes near the center of the row wiring is equal to the number of ends of the row wiring. The image display device according to any one of claims 1 to 4, wherein the number is set so as to be larger than the column wiring between adjacent nodes in the vicinity of the unit. 6. A row wiring to which a selection potential is applied from only one end thereof, wherein said node is a column wiring of a column wiring located between adjacent nodes near an end opposite to said one end on the row wiring. The image display device according to claim 1, wherein the number is set to be larger than the number of column wirings located between adjacent nodes near the one end on the row wiring. 7. The image display device according to claim 1, wherein the signal waveform is a signal waveform for performing peak value modulation. 8. The image display device according to claim 1, wherein the correction of the signal waveform is performed by correcting the image data. 9. The image display device according to claim 1, wherein the correction of the signal waveform is performed by adding a voltage drop amount calculated by the calculation unit to the image data. 10. The image display device according to claim 1, wherein the correction of the signal waveform corrects a peak value of the signal waveform. 11. The image display device according to claim 1, wherein the correction of the signal waveform corrects a pulse width thereof. 12. A method of correcting a signal waveform applied to each of the plurality of column wirings based on the voltage drop amount calculated by the calculation unit, the correction being performed on each column on the row wiring based on the voltage drop amount for each node. The image display device according to claim 1, wherein the amount of voltage drop at a position of the wiring is calculated. 13. The image display device according to claim 12, wherein the calculation of the voltage drop amount at each column wiring position is obtained by interpolation based on the voltage drop amount at each node position. 14. The image display device according to claim 1, wherein said display element is an electron-emitting device. 15. The image display device according to claim 14, wherein said electron-emitting device is a surface conduction electron-emitting device. 16. A driven part comprising a plurality of display elements arranged two-dimensionally connected in a matrix by a plurality of row wirings and a plurality of column wirings, wherein a plurality of display elements are connected to one row wiring. A driving method of an image display device for simultaneously driving the display elements of the above, wherein an input step of inputting an image signal of each column for one row, and a plurality of column wirings between adjacent nodes on the row wirings. Is set to be located, based on the input image signal, a calculation step of calculating the voltage drop amount at each node, and based on the voltage drop amount calculated by the calculation means,
A correction step of correcting a signal waveform applied to each of the plurality of column wirings.