JP2002311885A - Circuit for driving picture display device, picture display device, and method for driving the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable picture display device capable of reducing deterioration in reproducing gradations caused by the fluctuation of a power source and an element characteristic with a small scale circuit composition, and also realizing excellent reproduction of gradations even in picture signals or the like provided with gamma-correction beforehand. SOLUTION: Based on the brightness data inputted, instead of a part or the whole of the voltage V1 having a predetermined pulse width, the voltage V2 (V1<V2) is modulated to the same pulse width as the part, thereby generates a pulse voltage to be applied to a cold-cathode element 1001.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for an image display device for displaying a television image signal or the like, and more particularly, to a driving circuit suitably used for an image display device having a driven portion in which image display elements are connected in a matrix. It is possible.

[0002]

2. Description of the Related Art Conventionally, in this type of image display device,
Driving methods for controlling the light emission luminance of the image display element are roughly classified into a PWM (pulse width modulation) method and a PA method.
An M (pulse amplitude modulation) system is known.

In the PWM method, the light emission luminance is controlled by changing the pulse width (application time) of a drive voltage applied to an image display element. In a typical image display device such as a cold cathode type electron emission device, the amount of electron emission changes linearly with the application time of a voltage.
There is an advantage that the brightness control is easier than the method. However, in order to improve the gradation of one element, it is necessary to increase the reference clock (operating frequency) of the pulse width modulation, which has the disadvantage of increasing the cost of the drive circuit and increasing the power consumption.

On the other hand, the PAM system controls the light emission luminance of an image display device by changing the amplitude (voltage value) of a drive voltage. In the case of this method, although it is possible to secure the gradation without increasing the reference clock,
Generally, an electron-emitting device exhibits a non-linear electron emission characteristic with respect to a voltage value, and the amount of change in the emitted electrons is large.
There is a problem that stable brightness control is difficult.

Therefore, recently, an attempt has been made to solve the above-mentioned problem of the PWM system by performing pulse width modulation using a plurality of drive voltages.

For example, Japanese Patent Application Laid-Open No. H10-39825 discloses a method of suppressing the operating frequency of a drive circuit by using two types of drive voltages, a voltage V1 and a voltage V2, by the present applicant. Also, JP-A-8-22
No. 261 discloses a method of dividing luminance data (digital video word) into upper bits and lower bits (upper nibble / lower nibble) and selecting pulse widths of a plurality of drive current sources. . Also, Japanese Patent Application Laid-Open No. 7-1819
Japanese Patent No. 16 discloses a method for controlling both the drive voltage and the pulse width based on luminance data.

[0007]

However, the drive control of the prior art as described above is susceptible to fluctuations in the power supply (voltage and current), variations in the characteristics of the image display element, and aging. In addition, there is a problem that variations in luminance gradation and deterioration in image quality are likely to occur. Also,
There is also a problem that the gradation reproducibility of an image signal that has been subjected to gamma correction in advance like a TV signal is difficult.

For example, in the configuration disclosed in Japanese Patent Application Laid-Open No. 10-39825, the luminance driven by the voltage V2 with the same pulse width is (k + 1) / k of the luminance driven by the voltage V1.
The pulse width of the driving voltages V1 and V2 is determined so that the emission luminance is linear with respect to the input luminance data. For this reason, when displaying an image signal that has been gamma-corrected in advance, there is a waste that low-luminance gradations are slightly insufficient, and conversely, there are unused gradations at high luminances. If this configuration is designed to provide sufficient low-luminance gradation, hardware such as a pulse width modulation circuit must be increased, resulting in an increase in the size and cost of the device. I will.

Further, in order to further divide the luminance between the luminance gradations in the pulse width unit (time slot) of the drive voltage V1, the luminance is further modulated by the drive voltage V2. The luminance between them was further divided. For this reason, the light emission luminance characteristic deviates from a desired characteristic (linear) with respect to luminance data due to fluctuations in the power supply voltage of V2, variations in element characteristics, changes over time, and the like. There was a possibility of dropping.

[0010] In the configuration disclosed in JP-A-8-22261, the driving current I ₁ of the drive time obtained by pulse width modulating the data of the lower nibble D _L, the data of the upper nibble and a pulse width modulation driving current I ₂ of the obtained drive time D _M was added driving the field emission device. Although an example of driving with a voltage source is disclosed and disclosed, a driving voltage is selected so that the driving current in the case of the current driving also results in the case of voltage source driving.

The pulse width of the drive current I ₁ and the pulse width of the drive current I ₂ are determined so that the brightness becomes linear with respect to the input brightness data (digital video word). In the case of voltage source driving, the driving current is selected to be the same as in the case of current source driving, so that the luminance is linear with respect to the digital video word.

Therefore, in this case also,
As in the configuration of Japanese Patent Application Laid-Open No. 0-39825, when displaying an image signal that has been gamma-corrected in advance, there is a waste that a low-luminance gradation is slightly insufficient, and conversely, there is a gradation that is not used at a high luminance. Will occur. Further, if the design is made so that the gradation of low luminance is sufficient, it is necessary to increase hardware, which leads to an increase in the size of the device and an increase in cost.

Further, in the driving method disclosed in Japanese Patent Application Laid-Open No. 8-222261, fluctuations in the output currents of the current sources I ₁ and I ₂ greatly affect the gradation of light emission luminance. For example,
According to Equation 2 of the first embodiment of the publication, luminances L _{14 to} L ₁₇ for inputting video words _{14 to 17} (decimal) are described.
Has the following relationship. _{L 14 αI m αI 1 × 14} L 15 αI m αI 1 × 15 L 16 αI m αI 2 × 1 L 17 αI m αI 2 × 1 + I 1 × 1

Thus, the video word is 15 to 1
6, the input / output characteristics of the luminance data and the emission luminance change from desired characteristics (linear) due to output current fluctuations of the current source, variations in element characteristics, changes over time, and the like. It is easy to come off, and in the worst case, the reversal of the gradation occurs, and there is a possibility that the display quality is remarkably deteriorated. Also, in the case of the embodiment in which the voltage source drive is performed in the same publication, since the drive voltage is set so that the current value becomes the same as the current value in the case of the current source drive, the above problem may occur. there were.

In the configuration disclosed in Japanese Patent Application Laid-Open No. 7-181916, M bits (M
= K + L), the voltage determined by L bits is modulated to a pulse width determined by K bits. As described in this publication, L-bit PAM data is used to correct display unevenness on an image surface and gamma characteristics. For example, as described in FIG.
When gradation driving is performed in the M16 stage and the PAM16 stage (K = L = 4 bits), the dynamic range of the light amount can be widened, and as shown in FIG. There is also disclosed an example in which the gamma characteristic can be arbitrarily set.

However, in this case, not all M bits have the number of luminance gradations. In particular, in the case of performing gamma correction as shown in FIG. , K must be prepared as image data. In the case of performing gamma correction, for example, in the case of 8-bit gradation number (256), PA
M also requires 8-bit gray scale, and when a drive circuit is integrated into a circuit, a pulse width modulator and a D / A converter for PAM are required for each X electrode (column wiring), and as hardware increases, There was a problem that the cost to realize was high. Further, as described above, in the PAM system, stable luminance control is difficult, and the PAM system is susceptible to fluctuations in the voltage source and changes over time in element characteristics, so that it is difficult to ensure highly reliable gradation reproducibility. It can be said that.

The present invention has been made in view of the above circumstances, and has as its object to reduce the deterioration of gradation reproduction due to fluctuations in power supply and element characteristics with a small-scale circuit configuration. An object of the present invention is to provide a highly reliable image display device capable of realizing excellent tone reproduction even with an image signal or the like which has been subjected to gamma correction in advance, and a driving circuit and a driving method for realizing the device.

[0018]

According to the present invention, there is provided a driving circuit for an image display device for generating a pulse voltage to be applied to an image display element based on input luminance data. , Two voltages V having a relationship of V _m <V _{m + 1} (m = 0, 1, 2,..., N−1) from n + 1 (n> 1) different voltages based on the luminance data. _m, a driving voltage selecting means for selecting the V m _{+ 1,} based on the luminance data, instead of a part or all of the pulse of the voltage V _m with a pulse width of a predetermined time, the same pulse width as that portion The voltage V
pulse width modulation means for modulating _{m + 1} .

N + 1 voltages V _m (m = 0, 1, 2,...)
., N) are applied to the image display element with the same pulse width so that the luminance L _m ′ for each voltage satisfies the relationship L _m ≦ (m / n) × L _n ′. The n + 1 voltages may be set.

Further, n + 1 voltages V _m (m = 0, 1,
,..., N) are applied to the image display element with the same pulse width, and the luminance L _m ′ for each voltage is obtained.
_{There, L m '/ L n'} ≒ (m / n) γ γ> still good by setting the (n + 1) voltage so as to satisfy 1.0 the relationship.

The voltage V _m (m = 0, 1, 2,...,
n-1) is applied to the image display device with a pulse width of the predetermined time, the luminance is L _m , the luminance data value corresponding to the pulse voltage is D _m , and the pulse width of the voltage V _{m + 1} is the maximum. When the value of the luminance data when greatly modulated is D _{m + 1} , and the luminance when a pulse voltage modulated based on the value D _{m + 1} is applied to the image display element is L _{m + 1} , in at least one of m, it is also preferable to set the (n + 1) voltage so as to satisfy _{L m ≦ (D m / D} m + 1) × L m + 1 the relationship.

The voltage V _m (m = 0, 1, 2,...)
.., n-1) is applied to the image display element with a pulse width of the predetermined time, the luminance is L _m , the luminance data value corresponding to the pulse voltage is D _m , and the voltage V _{m + 1 is} a pulse of the voltage V _{m + 1} . The value of the luminance data when the width is modulated to the maximum width is D _{m + 1} , the value D
Assuming that the luminance when the pulse voltage modulated based on _{m + 1} is applied to the image display element is L _{m + 1} , at least one of m, L _m / L _{m + 1} ≦ (D _m / D _{m + 1} ) ^γ It is also preferable to set the n + 1 voltages so as to satisfy the relationship of γ> 1.0.

The above γ is preferably γ ≒ 2.2.

The voltage V _m (m = 1, 2,..., N−
In 1), the pulse width of the predetermined time is changed by the pulse width modulation means to the same pulse width as that part of the pulse of the voltage _Vm-1 having a pulse width of the predetermined time instead of part or all of the pulse. when the modulating V _m, may equal to the maximum pulse width of the same voltage V _m.

The pulse width of the predetermined time of the voltage V _0, the pulse width modulating means, long and better than or equal to the maximum pulse width of the voltages V ₁ when modulating the voltages V _1.

The driving voltage selecting means uses the upper j bits (j is a natural number) of the luminance data to generate two voltages V
_m , V _{m + 1} (m = 0, 1, 2,..., n−1), and the pulse width modulation means uses the remaining lower k bits of the luminance data to generate a voltage V _{m + 1} Should be modulated.

The drive voltage selection means may select two voltages V _Dj and V _{Dj + 1} from 2 ^j +1 different voltages using a value Dj represented by the upper j bits of the luminance data.

When the value represented by the lower k bits of the luminance data is Dk, and the period of the pulse width modulation clock is T _pclk , the pulse width modulation means generates the pulse width T of the voltage V _{m + 1. It} is _{preferable that w} be modulated so that _Tw = T _pclk × Dk.

It is preferable that the predetermined time T _wb is T _wb = T _pclk × 2 ^k .

It is preferable that the voltage V ₀ is a potential that makes the image display element emit no light.

The reference potential is a reference potential (for example, V ₀
= 0 V).

Further, in the image display device of the present invention,
A plurality of image display elements arranged two-dimensionally are connected in a matrix by a plurality of row wirings and a plurality of column wirings, and a driven portion is provided. In an image display device that performs scanning, the drive circuit is provided for each of the plurality of column wirings.

It is preferable that the predetermined time is equal to or shorter than the row wiring selection time.

It is preferable to have a conversion means for converting image data to be displayed into luminance data to be input to the driving circuit.

Preferably, the conversion means is a memory storing a conversion table for inputting a bit width of image data and outputting a bit width of luminance data.

The image display device is constituted by a cold cathode type electron emitting device, and a substrate having a phosphor which emits light by the electrons emitted from the cold cathode type electron emitting device is provided facing the driven portion, An acceleration voltage for accelerating the electrons may be applied to the substrate.

The cold cathode type electron emitting device is preferably a surface conduction type electron emitting device.

Further, the cold cathode type electron emitting device may be an FE type electron emitting device or a MIM type electron emitting device.

The image display device may be an EL device.

According to a method of driving an image display device of the present invention, in the method of driving an image display device which generates a pulse voltage to be applied to an image display element based on input luminance data, Based on n + 1 (n
> 2) selecting two voltages V _m and V _{m + 1} having a relationship of V _m <V _{m + 1} (m = 0, 1, 2,..., N−1) from different voltages of> 1) Modulating the voltage V _{m + 1} to the same pulse width as the part instead of part or all of the voltage V _m pulse having a pulse width of a predetermined time based on the luminance data. It is characterized by including.

N + 1 voltages V _m (m = 0, 1, 2,...)
., N) are applied to the image display element with the same pulse width so that the luminance L _m ′ for each voltage satisfies the relationship L _m ≦ (m / n) × L _n ′. The n + 1 voltages may be set.

Further, n + 1 voltages V _m (m = 0, 1,
,..., N) are applied to the image display element with the same pulse width, and the luminance L _m ′ for each voltage is obtained.
_{There, L m '/ L n'} ≒ (m / n) γ γ> still good by setting the (n + 1) voltage so as to satisfy 1.0 the relationship.

The voltage V _m (m = 0, 1, 2,...,
n-1) is applied to the image display device with a pulse width of the predetermined time, the luminance is L _m , the luminance data value corresponding to the pulse voltage is D _m , and the pulse width of the voltage V _{m + 1} is the maximum. When the value of the luminance data when greatly modulated is D _{m + 1} , and the luminance when a pulse voltage modulated based on the value D _{m + 1} is applied to the image display element is L _{m + 1} , in at least one of m, it is also preferable to set the (n + 1) voltage so as to satisfy _{L m ≦ (D m / D} m + 1) × L m + 1 the relationship.

The voltage V _m (m = 0, 1, 2,...)
.., n-1) is applied to the image display element with a pulse width of the predetermined time, the luminance is L _m , the luminance data value corresponding to the pulse voltage is D _m , and the voltage V _{m + 1 is} a pulse of the voltage V _{m + 1} . The value of the luminance data when the width is modulated to the maximum width is D _{m + 1} , the value D
Assuming that the luminance when the pulse voltage modulated based on _{m + 1} is applied to the image display element is L _{m + 1} , at least one of m, L _m / L _{m + 1} ≦ (D _m / D _{m + 1} ) ^γ It is also preferable to set the n + 1 voltages so as to satisfy the relationship of γ> 1.0.

[0045]

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, the specific circuit configurations described in the embodiments are not intended to limit the scope of the present invention to them unless otherwise specified.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
1 shows a driving circuit of an image display device according to an embodiment. In order to explain the drive circuit of the present embodiment in an easily understandable manner,
FIG. 1 shows only a circuit for driving one column wiring.
In the following, with reference to FIG.
Cold cathode element 100 connected to 003 and column wiring 1002
1 will be described.

In the image display device according to the present embodiment,
A plurality of cold-cathode devices (also referred to as cold-cathode electron-emitting devices) serving as image display devices are two-dimensionally arranged, and each is connected in a matrix by a plurality of row wirings and a plurality of column wirings to be driven. The matrix image display panel 1 as a part is constituted. Needless to say, a driving circuit similar to that in FIG. 1 is provided for column wiring other than the column wiring 1002 shown in FIG.

As shown in FIG. 1, the driving circuit according to the present embodiment uses a clock (PCLK) as a reference for pulse width modulation.
A counter 101 for counting in response to the
2, 103, a constant register 104, and an AND circuit 10
5, 106, an OR circuit 107, and switches 108, 1
09 is provided.

The cold cathode device 1001 is formed on a substrate (not shown). Further, there is a substrate made of glass or the like to which a phosphor (not shown) is applied and to which a high voltage (acceleration voltage) is applied, facing the cold cathode element 1001, and emits light by electrons emitted from the cold cathode element 1001. The intersections of the column wirings 1002 and the row wirings 1003 are insulated from each other, and the cold cathode elements 1001 formed near the intersections are connected to the column wirings 1002 and the row wirings 1003 by extraction electrodes.

In the configuration shown in FIG. 1, as will be described later, a selection potential is sequentially applied to the row wiring in units of horizontal synchronization signals, and the column wiring is simultaneously driven in accordance with the image data of the selected row wiring to form an image. Is done.

In the figure, S11 is luminance data input to the drive circuit, S12 is output data of the counter 101, S13 is an output signal of the comparator 102, and S14 is AND.
An output signal of the circuit 105, S15 is a control signal of the switch 108, S16 is a control signal of the switch 109, S17 is a drive signal, S21 is a power supply line of the voltage V1, S22
Indicates a power supply line of the voltage V2.

Next, the operation of this embodiment will be described.

In FIG. 1, the luminance data S11 corresponding to each row wiring is determined by the rising pulse of the load signal LD synchronized with the horizontal synchronizing signal. The lower 8 bits (D0 to D7) of the luminance data S11 are
And the upper one bit (D8) is the AND circuit 105, 106
Is input to In the present embodiment, the luminance data S11 is 9
Although an example of bits has been described, the number of bits is not limited to 9 bits. Further, the luminance data S11 is divided into upper 1 bit and lower 8 bits for processing, but the present invention is not limited to this.

On the other hand, the counter 101 is reset by the load signal LD synchronized with the horizontal synchronizing signal, and sequentially increases from 0 in synchronization with the rise of PCLK which is the pulse width modulation reference clock. Output data S of counter 101
Reference numeral 12 denotes 9 bits, which are input to the comparator 103 in the present embodiment, similarly to the luminance data. Also, counter 1
01 low-order 8 bits of the output data S12
Is input to

The other input of the comparator 103 receives the output of the constant register 104. The value of the constant register is “1000
00000b "(binary number; 1 means H level)
That is, it is '256' (decimal number; hereinafter, no comment is given in the case of a decimal number), and the comparator 103 outputs an H level signal when the output data S12 of the counter 101 is 1 or more and 256 or less.

In this embodiment, the output data S12 of the counter 101 is calculated using the comparator 103 to be 1 to 256.
Although the function of outputting the H level was realized at the time of (1), it may be realized by another method. For example, it can be realized by inverting the upper one bit of the output data S12 of the counter 101 and delaying it by one PCLK.

On the other hand, the comparator 102 compares the lower 8 bits of the output data S12 of the counter 101 with the lower 8 bits of the luminance data S11, and determines that the value represented by the lower 8 bits of the output data S12 of the counter 101 is 1. When the value is equal to or less than the value represented by the lower 8 bits of the luminance data S11,
An H level signal S13 is output.

The AND circuit 105 ANDs the upper one bit of the luminance data S11 and the output signal of the comparator 103.
That is, only when the upper one bit of the luminance data S11 is at the H level (the luminance data S11 is 256 or more), the signal S14 in which the output data S12 of the counter 101 is at the H level from 1 to 256 is output.

The OR circuit 107 ORs the output signal S14 of the AND circuit 105 and the output signal S13 of the comparator 102 and outputs a control signal S15. That is, the luminance data S11
Is less than 256, the output data S12 of the counter 101
During which the lower 8 bits of the control signal S1 change from 1 to the value represented by the lower 8 bits of the luminance data.
5 is output. When the luminance data S11 is 256 or more, the output data S12 of the counter 101 becomes 1 to 256.
During this time, the control signal S15 at the H level is output.

On the other hand, the AND circuit 106 outputs the luminance data S1
1 and the output signal S13 of the comparator 102 as A
ND. Only when the luminance data S11 is equal to or greater than 256, the control signal S16 at the H level is output during a period from when the lower 8 bits of the output data S12 of the counter 101 becomes a value represented by 1 to the lower 8 bits of the luminance data. .

In this embodiment, the counter 101 has a width of 9 bits. The duty of the maximum value of the driving time in one horizontal synchronization period is 256/511 or more and 511 /.
Since it is designed to be less than 511 (specifically, about 90% of the time within one horizontal synchronization period is allocated to the light emission time), the counter 101 counts '511' for the next load signal LD. Enter before you do. Therefore, the counter 101 does not return to '0' before the load signal LD is input and does not perform an abnormal operation.

Next, the switch 108 sets the control signal S15
Open and close the switch according to. When the control signal S15 is at the H level, the switch 108 is closed. Switch 10
9 switches the switches according to the control signal S16. When the control signal S16 is at the H level, the switch 109 becomes the contact b, and when the control signal S16 is at the L level, the switch 109 is switched to the contact a. That is, when the control signal S16 is at the H level, the power supply line S
22 and the switch 109 switches the voltage V2 to the switch 1
08. Conversely, when the control signal S16 is at the L level, the power supply line S21 is selected, and the switch 109 sets the voltage V
1 is output to the switch 108.

FIG. 2 shows a timing chart of this embodiment. In FIG. 2, the luminance data S11 is “3” in the first horizontal synchronization period in the figure, and “259” in the next horizontal synchronization period.
Here is an example.

In FIG. 2, the luminance data S11 is changed by a load signal LD (synchronized with the horizontal synchronizing signal HD) supplied to a latch circuit for latching the output of a shift register for converting the luminance data into parallel data, which will be described later. Determine.

On the other hand, the counter 101 outputs the load signal LD
Resets the counter to '0' at the rising edge of PCLK at the time of H level, and sequentially counts the rising clock of PCLK. In the present embodiment, this counter 1
The drive output of pulse width modulation is determined based on the lower 8 bits of the output data S12 of 01.

To simplify the description, the counter 101
The time corresponding to the value of the output data S12 is hereinafter expressed as a time slot. For example, the time when the output data S12 of the counter 101 corresponds to “1” is set to the time slot 1
Is expressed for convenience.

The comparator 102 calculates the lower 8 bits of the luminance data S11 and the lower 8 bits of the output data S12 of the counter 101.
The bits are compared as described above and a signal S13 is output. That is, in FIG. 2, the signal S13 is at the H level during the first horizontal synchronization period during the time slots 1 to 3, and at the H level during the next horizontal synchronization period during the time slots 1 to 3.

The comparator 103 is provided in the constant register 10
4 is compared with the output data S12 of the counter 101 as described above, and a signal S14 is output. That is, in FIG. 2, in the first horizontal synchronization period, the luminance data S11
Is "3", the output signal S14 is at the L level, and in the next horizontal synchronization period, the luminance data S11 is "259". Therefore, the output signal S14 is at the H level during the time slots 1 to 256.
Level.

The control signal S15 of the switch 108 is the output of the OR circuit 107, and the control signal S16 of the switch 109 is A
Since the output is the output of the ND circuit 106, the driving signal S17 output from the driving circuit is such a pulse as to output the voltage V1 during the time slots 1 to 3 in the first horizontal synchronization period as shown in FIG. Voltage. In the next horizontal synchronization period, the pulse voltage is such that the voltage V2 is output during the time slots 1 to 3 and the voltage V1 is output during the time slots 4 to 256.

In the present embodiment, the voltage V1 and the voltage V2 are set so as to satisfy the following relationship: V1 <V2 (1)

Further, in this embodiment, a virtual voltage V0 is introduced from the viewpoint of the design concept of the drive circuit. Switch 1
08 is disconnected, the drive signal S17 is applied to the column wiring.
Is not output, the phosphor corresponding to the cold cathode element does not emit light. This state is defined as that the voltage V0 is being applied at the predetermined time T0. The predetermined time T0 is equal to or longer than the maximum time T1 (maximum pulse width) of the voltage V1 when the voltage V1 is subjected to pulse width modulation. The predetermined time T0 is selected to be equal to or shorter than the time for applying the selection potential to the row wiring. It can be said that the voltage V0 is a potential at which the phosphor corresponding to the cold-cathode device makes the non-light emitting state.

Thus, in the present embodiment, three (2 ¹ +1) voltage values having the relationship of V0 <V1 <V2... It will be used.

Here, when the value represented by the upper one bit of the input luminance data S11 is “0” (the luminance data S11
11 is equal to or less than '256'), the voltage V0 is
1 is pulse width modulated.

First, a signal S14 for modulating the pulse width of the voltage V0 and a signal S1 for modulating the pulse width of the voltage V1 are based on the value represented by the remaining lower 8 bits of the luminance data S11.
3 are generated. (However, in this embodiment, the voltage V
Since 0 is virtually set, a waveform corresponding to the voltage V0 does not appear. Then, based on the signal S14, the voltage V
In the pulse width modulation of 0, the pulse width modulation of the voltage V1 is performed based on the signal S13. The pulse voltage output at this time has a waveform in which a part of or all of the pulse of the voltage V0 having the pulse width of the predetermined time T0 is replaced by the voltage V1 modulated to the same pulse width as that part. Become.

On the other hand, when the value represented by the upper one bit of the input luminance data S11 is "1" (the luminance data S1
1 is greater than or equal to '257'), the voltage V1 is
Are pulse width modulated.

Therefore, a signal S14 for pulse width modulation of the voltage V1 and a signal S13 for pulse width modulation of the voltage V2 are generated based on the value represented by the lower 8 bits, and the signal V14 of the voltage V1 is generated based on the signal S14. If the pulse width modulation is
3, the pulse width modulation of the voltage V2 is performed. The pulse voltage output at this time has a waveform such that, instead of a part of the pulse voltage having the maximum pulse width T1 of the voltage V1, the voltage V2 modulated to have the same pulse width as that part is combined.

The driving waveform of the pulse voltage obtained by the above operation is schematically shown in FIG. FIG. 3A shows a pulse voltage waveform when the input luminance data S11 is '0' to '256', and FIG. 3B shows a pulse voltage waveform when the input luminance data S11 is '257' to '511'. It shows a waveform.

As shown in FIG. 3A, the luminance data S1
When 1 is equal to or less than '256', drive control equivalent to pulse width modulation of the voltage V1 is performed, and the voltage V1 is pulse width modulated corresponding to the time slots 1 to 256. Also, when the luminance data S11 is '257' to '511', FIG.
As shown in the figure, the voltage V2 is pulse-width modulated corresponding to the time slot determined by the time slots 1 to <the value of the lower 8 bits of the luminance data S1, and the remaining time slot 2
The voltage V1 is output until 56. In other words,
When the luminance data S11 is equal to or more than '257', the voltage V
1 is output during time slots 1 to 256, and it can be said that a pulse voltage in which a pulse width modulated voltage V2 is superimposed on this voltage V1 is obtained.

As described above, according to the driving method of the present embodiment, first, pulse width modulation is performed only with the voltage V1, and the voltage V2 is output only after the voltage V1 reaches the maximum pulse width. When outputting the voltage V2, a pulse voltage corresponding to the maximum pulse width of the voltage V1 is always ensured. Therefore, the voltages V1 and V
Even if there is a variation of 2 or a variation in variation of elements, the monotonic increase property that the emission luminance always increases as the luminance data increases can be easily and reliably realized, and the inversion of the gradation does not occur. Good tone reproduction can always be obtained.

Since the difference between the voltage V1 and the voltage V2 can be increased and it is easy to manufacture a circuit configuration in which V1 <V2, the influence of the variation in the driving circuit is not so serious. Even if the voltages V1 and V2 fluctuate, the monotonic increase of the luminance gradation is not impaired, but merely appears as a change in the gamma characteristic, so that the subjective evaluation of the displayed image is not significantly affected.

Further, according to the driving method of the present embodiment,
Since the number of gradations of the pulse width modulation corresponding to 9 bits can be realized by the PCLK having the frequency corresponding to the pulse width modulation of 8 bits,
Excellent effects such as simplification of the circuit configuration, miniaturization and cost reduction of the device, reduction of power consumption, and suppression of heat generation can be obtained.

Further, the present inventors have determined that the drive voltages V1,
By selecting the voltage V2 as described below, it has been found that when displaying an image signal such as a TV signal which has been gamma-corrected in advance corresponding to a CRT, a remarkable improvement in gradation is achieved.

That is, the value of the luminance data when the pulse width of the voltage V1 is maximum is D ₁ , the emission luminance when a pulse voltage modulated according to the value D ₁ is applied is L ₁ , and the voltage V ₂ is When the value of the luminance data when the pulse width is the maximum is D ₂ , and the light emission luminance when a pulse voltage modulated according to the value D ₂ is L ₂ , L ₁ / L ₂ ≦ D ₁ / D ₂ Equation 2) The voltage V1 and the voltage V2 may be set so as to satisfy the following relationship. In the present embodiment, D ₁ = 256, D ₂
= 511, the above conditional expression 2) becomes the following expression 2 '). L ₁ / L ₂ ≦ 256/511 (2 ′)

By setting the voltages V1 and V2 in this manner, the input / output characteristics when the luminance data value is input and the light emission luminance when a pulse voltage modulated according to the value is applied is output. Has a gamma value of 1 or more.

As a more favorable condition, it is preferable that the gamma value is close to the gamma value required for the characteristics of the display system. Specifically, a gamma value γ represented by the following equation 3)
, And the voltage V1 and the voltage V
2 may be set.

Here, for example, in the case of displaying with a gamma characteristic similar to that of a CRT, the gamma value γ is set to about 2.2. In this embodiment, as shown in FIG. 4, when setting the voltage V1, V2 so that _{L 1 / L 2 ≒ 1/} 4, to satisfactorily display the TV signal or the like which is previously gamma corrected Was completed.

When the maximum pulse width T1 of the voltage V1 and the maximum pulse width T2 of the voltage V2 are substantially the same as in the present embodiment, the following equations are used instead of the above equations 2 ') and 3). The voltages V1 and V2 may be set by the conditional expression as described above.

That is, a cold cathode element is supplied with a predetermined pulse width.
The luminance when the voltage V1 is applied is L ₁′, Same pulse
The brightness when the voltage V2 is applied to the cold cathode device by the width
L_Two′, L₁'≦ (1/2) × L_Two'Equation 2 ″) The voltage V1 and the voltage V2 are set so as to satisfy the following relationship.
However, an effect similar to the above equation 2 ') can be obtained.

[0089] Further, as an alternative to the above equation _{3), L 1 '/ L} 2' = (1/2) γ ...... formula 3 ') may be set to voltages V1, V2 to meet. Also in this case, the gamma value γ represented by the expression 3 ′) is 1.0 to 3.0.
It is preferable to set the voltages V1 and V2 so as to be about 0, and it is preferable to set the gamma value γ to about 2.2 when displaying with gamma characteristics similar to those of a CRT.

The voltages V1 and V2 are set as described above for the following reasons.

Conventionally, Japanese Patent No. 307348 by the present applicant has been disclosed.
As described in Japanese Patent Application Laid-Open No. 6-64, when the characteristics of the display system are simple pulse width modulation, the input / output characteristics of input signal-luminance generally show linear characteristics. When displaying an image signal such as a TV signal that has been subjected to gamma correction corresponding to a CRT on a display system having such linear input / output characteristics, inverse gamma conversion is performed to cancel the gamma correction. There is a need to do. For example, when pulse width modulation, which is a conventional 8-bit linear characteristic, is performed, image data is raised to the power of 2.2 in inverse gamma conversion and output as luminance data. There is a problem that an unused gradation in pulse width modulation occurs in luminance.

However, according to the driving method of the present embodiment, the input / output characteristics at low luminance (when the luminance data is equal to or less than 256) are determined by determining the voltages V1 and V2 so as to satisfy the above conditional expression. Can be reduced, that is, the gradation of low luminance can be enhanced.

For example, when the voltages V1 and V2 are set so that L ₁ / L ₂ becomes about ４, the input / output characteristic of the luminance data versus the normalized luminance is as shown in the graph of FIG. Become. In the above case, the luminance increase amount ΔI at low luminance
Can be reduced to about 1/1024. This is a gradation comparable to 10-bit pulse width modulation.

As described above, according to the present embodiment, the number of gradations (512 gradations) by 9-bit pulse width modulation can be realized with PCLK having a frequency equivalent to 8-bit pulse width modulation, and approximately 10 Since it is possible to have a luminance increase amount per gradation equivalent to bit pulse width modulation, it is possible to realize excellent gradation reproduction with a small-scale circuit configuration. Further, even on the high-luminance side, it is possible to obtain better gradation than the conventional simple 8-bit pulse width modulation.

In the present embodiment, an example has been described in which the reference clock frequency (frequency of PCLK) of the conventional simple pulse width modulation is not changed (the time of the time slot is not changed) and the gradation is improved. Naturally, even when the reference clock frequency (frequency of PCLK) of the conventional pulse width modulation is lowered (the time of the time slot is lengthened) due to problems such as the operating frequency, power consumption, and EMI of the driving circuit. In addition, it is possible to improve the gradation. Further, compared with the conventional simple pulse width modulation, it is possible to particularly improve the gradation of low luminance. In this case, it is needless to say that the table of the luminance data converter described later is preferably designed so that the input image data-luminance characteristic (characteristic of the display system) is the same as the gamma characteristic required for the display system. Not even.

FIG. 5 shows the image data-luminance data characteristic of the luminance data converter when the characteristic of the display system has the characteristic of 2.2 power of the image data as in the case of the CRT. FIG. 5A shows a portion where the above-described low luminance gradation property is improved.

FIG. 6 shows that the characteristics of the display system are BTA and S.
It is an image data-luminance data characteristic of a luminance data converter in the case of MPTE1125 / 60 studio standard. As described above, since 10 bits of low-luminance gradation are secured, there is no decrease in the number of gradations in B of FIG. 6 (that is, different luminance data can be allocated to all image data). Therefore, the gradation expression ability has been remarkably improved.

Next, the overall configuration of the image display device of the present embodiment will be described with reference to FIG.

The matrix image display panel 1 provided in the image display device of the present embodiment is provided in a thin vacuum container.
A large number of image display elements such as cold cathode elements 100 on a substrate
A multi-electron source in which one or more electron sources are arranged, and a substrate (image forming member) having a phosphor or the like that emits light by electrons emitted from the cold cathode device 1001 are arranged to face each other.

The cold cathode device 1001 is arranged near each intersection of the column wiring 1002 and the row wiring 1003 and connected to both wirings. The cold cathode elements 1001 can be precisely positioned and formed on a substrate by using a manufacturing technique such as photolithography and etching, so that a large number of cold cathode elements can be arranged at minute intervals. Moreover, conventional CRT
As compared with the hot cathode used in such a method, the cathode itself and the peripheral portion can be driven at a relatively low temperature, so that a multi-electron source having a finer arrangement pitch can be easily realized.

The present inventors used a surface conduction electron-emitting device as a cold-cathode device (cold-cathode electron-emitting device). The configuration and manufacturing method of the surface conduction electron-emitting device are described in detail in Japanese Patent Application Laid-Open No. Hei 10-39825 by the present applicant, and the description is omitted here.

FIG. 14 shows the relationship between the driving voltage Vf of the actual surface conduction electron-emitting device, the device current If, and the emission current Ie. In FIG. 14, the horizontal axis represents the drive voltage Vf applied to both electrodes of the surface conduction electron-emitting device, and the vertical axis represents the device current If flowing between both electrodes and the emission current Ie emitted from the device. As can be seen from FIG. 14, a threshold voltage (about 8 V) exists in the emission current Ie, and the emission current Ie does not flow below the threshold voltage. At a higher voltage, the emission current Ie flows according to the applied driving voltage Vf. The following simple matrix drive was performed using this characteristic.

As shown in FIG. 7, on the matrix image display panel 1 of the present embodiment, 480 elements, that is, 160 pixels (RGB) × 3 are arranged in the horizontal direction, and 240 elements are arranged in the vertical direction. I have. Note that the number of elements is not limited to 480 × 240 elements, and may be determined as needed depending on the product use and the like.

Each cold cathode element 1001 of the matrix image display panel 1 has Ru, v (u
= 1,2,3, ..., 240; v = 1,4,7, ...
, 478), Gu, v (u = 1, 2, 3,..., 2)
40; v = 2, 5, 8,..., 479), Bu, v
(U = 1, 2, 3,..., 240; v = 3, 6, 9,
.., 480). The matrix image display panel 1 has, for example, an RGB stripe pixel arrangement.

The analog-to-digital converter (A / D converter) 2 converts an analog RGB component signal (signal name is S0) decoded from, for example, an NTSC signal to an RGB signal by a decoder (not shown), for example, with an 8-bit width. Is converted to a digital RGB signal S1.

The data rearranging section 3 receives the digital RGB signal S1 from the A / D converter 2 or a computer or the like, and rearranges the digital data according to the pixel arrangement of the matrix image display panel 1 to convert the image data S2.
Is output.

The luminance data converter 4 receives the input of the image data S2, converts the image data S2 into a desired luminance characteristic, and
3 is provided. As the conversion table, for example, a table that performs inverse conversion of a signal gamma-corrected for CRT as a characteristic of a display system is preferable.

The shift register 5 includes a luminance data converter 4
The luminance data S3 output from the shift clock (SC)
LK), and luminance data corresponding to each element (column wiring) of the matrix image display panel 1 is output in parallel.

The latch circuit 6 latches the luminance data from the shift register 5 in parallel with the load signal LD synchronized with the horizontal synchronizing signal, and holds the luminance data while the next load signal LD is input.

The driving circuit 7 has the same configuration as that of FIG. 1 except that a plurality of column wirings 1002 of the matrix image display panel 1 are provided.
Of the column wiring 10
02 is driven. The above-described luminance data S11 in FIG. 1 is a signal of the XD1 to XD480 wiring in FIG. 5, and the above-described drive signal S17 in FIG. 1 corresponds to a signal of the X1 to X480 column wiring in FIG.

The scanning driver 8 is provided with a scanning signal generator 81 and switch means 82, and is connected to each row wiring 1003 of the matrix image display panel 1. The scanning signal generator 81 sequentially shifts the YST signal synchronized with the vertical synchronizing signal by the signal HD synchronized with the horizontal synchronizing signal, and outputs the signal in parallel according to the number of row wirings. Switch means 82
Is configured by a MOS transistor or the like, and switches according to the output level of the scanning signal generator 81 to switch between a selection potential (−Vss) and a non-selection potential (GND).

The timing control section 10 generates a desired timing control signal for each functional block from a synchronization signal of an input image, a data sampling clock (DCLK), and the like.

Next, the operation of the overall configuration of the image display device of the present embodiment will be described with reference to FIGS. FIG.
FIG. 3 is a timing chart of the overall configuration of the image display device.

In FIG. 7, an analog RGB component signal (S0) decoded from an input image signal such as an NTSC signal into an RGB signal by a decoder (not shown).
Is converted into a digital RGB signal (S1) having an 8-bit width, for example.

The data rearranging section 3 outputs a digital RGB signal (S) from the A / D converter 2 or a computer or the like.
Enter 1). At this time, if the number of data in one scanning line (1H) is determined by the number of pixels on the column wiring side of the matrix image display panel 1, the processing is simplified. In the case of this embodiment,
The number of pixels on the column wiring side of the matrix image display panel 1 is 16
I decided to 0.

A digital RGB signal (S1) from the A / D converter 2 or a computer is output in synchronization with a data sampling clock (DCLK) not shown.
As shown in FIG. 8, the input signal (S
1) The RGB parallel signals are switched at the timing of a shift clock (SCLK), not shown, which is a clock having a frequency three times the frequency of the data sampling clock (DCLK), and sequentially according to the RGB pixel arrangement of the matrix image display panel 1. Is output.

Output signal of data rearranging section 3 (S2)
Is input to the luminance data converter 4. The luminance data converter 4 converts the 8-bit width output signal (S2) of the data rearranging unit 3 into, for example, a display system characteristic by a conversion table (ROM) (not shown) in which desired data is stored in advance. The luminance data is converted into luminance data S3 having a 9-bit width such that luminance characteristics are equivalent to gamma characteristics of a CRT.

For example, in the drive circuit 7 and the matrix image display panel 1 having the characteristics shown in FIG. 4, the characteristics of the conversion table use the characteristics shown in FIG. 5 or FIG. 6 as described above.

The luminance data (S3) output from the luminance data converter 4 is sent to the 9-bit width shift register 5, and is sequentially shifted and transferred by the shift clock (SCLK).
The luminance data corresponding to each element of the matrix image display panel 1 is serial-parallel converted and output.

The latch circuit 6 latches the serial-parallel-converted luminance data at the rising edge of the load signal LD synchronized with the horizontal synchronizing signal.
Holds and outputs data until is input.

On the basis of the time of the load signal LD, the drive circuit 7 drives the column wirings (X1 to X480) in the manner described above in synchronization with PCLK.

The scanning driver 8 outputs a signal (YST) for determining the scanning start time to the horizontal synchronizing signal (H) as shown in FIG.
The row wiring is driven by sequentially transferring in synchronization with D). Then, the row wirings are sequentially scanned to form an image.

In this embodiment, the NTSC signal is set to 2
In order to display on the matrix image display panel 1 having 40 scanning wirings, 480 out of 485 interlaced effective scanning lines were overwritten on the matrix image display panel 1 for each field and driven. NTSC signal 1
The field is treated as one frame in the matrix image display panel 1. That is, the matrix image display panel 1
Was driven as an image signal having a frame frequency of 60 Hz and 240 scanning lines.

At this time, the time required to display one scan line is about 63.5 μSec for the NTSC signal, and about 56.5 μSec within that time is the maximum time (maximum pulse) of the driving pulse (pulse voltage) for the column wiring. Width). Therefore, for PCLK, the longest drive pulse width is selected for the time slot 256, so that the number of pulses of PCLK is 2
A frequency was selected such that the frequency was about 56.5 μSec when the number was 56. That is, the pulse width of one pulse is about 220 nSe
The clock c and the PCLK having a frequency of about 4.5 MHz were used as pulse width modulation reference clocks.

The scan driver 8 is provided with a horizontal synchronizing signal (HD)
The first row (Y1) to the 240th row (Y240) are sequentially set to the selection potential -Vss (for example, -7.5 V) in synchronization with
Are sequentially driven. At this time, the scanning driver 8 drives the voltage of the other unselected row wiring to the non-selection potential 0V.

As is apparent from FIG. 8, during the time of the longest drive pulse width (time slots 1 to 256),
The scanning driver 8 needs to keep the selected row at the selected potential. In other words, the selection time (row wiring selection time) must be always longer than or equal to the longest drive pulse width (time slot 1 to 256) in order to form an image.

Of the cold cathode elements 1001 on the row wiring selected by the scanning driver 8, the voltage V
An emission current Ie according to the potential difference (drive voltage Vf) between the selection potential −Vss and the drive signal S17 flows through the element to which the drive signal S17 of 1 or the voltages V1 and V2 is output. On the other hand, the element corresponding to the column wiring for which the drive signal S17 is not output (the switch 108 is not closed) does not flow the element current If, and thus does not emit the emission current Ie, and thus does not emit light. Then, the scanning driver 8 sequentially switches the 1st to 240th row wirings in synchronization with the horizontal synchronization signal (HD) to the selection potential -V.
The driving is sequentially performed by ss, and the driving circuit 7 is driven on the corresponding row wiring by the driving signal S17 corresponding to the luminance data at the voltages V1 and V2 to form an image.

In the present embodiment, the voltage values of the voltages V1 and V2 are determined so as to have the characteristics shown in FIG. The relationship between the luminance and the emission current Ie is almost proportional, and the relationship between the emission currents Ie1 and Ie2 in FIG. 14 can be considered to be substantially equal to the relationship between the luminances L1 and L2 described above. Emission current I corresponding to wiring voltages V1 and V2
The voltages V1 and V2 were determined so that the ratio of e1 and Ie2 was 1: 4.

More specifically, the selection potential of the row wiring is set to -7.5.
Since V1 is selected, V1 = 5V and V2 = 7.5V, and the driving voltage Vf when the driving circuit 7 outputs V1 is 1
The drive voltage Vf when the drive circuit 7 was outputting V2 at 2.5 V was 15 V. The emission current Ie1 is set to 0.
085 μA and Ie2 were 0.34 μA, and a luminance characteristic as shown in FIG. 4 could be obtained.

As described above, according to the first embodiment of the present invention, it is possible to realize the number of gradations of 9-bit pulse width modulation with PCLK having a frequency equivalent to 8-bit pulse width modulation. Further, by setting the voltages V1 and V2 so that the gamma value of the luminance data-luminance input / output characteristic is close to the gamma value required for the characteristics of a general display system, gradation of low luminance can be further improved. Well done.

(Second Embodiment) FIG. 9 shows a second embodiment of the present invention. In the first embodiment, the driving method of performing pulse width modulation using the voltages V1 and V2 has been described. In the present embodiment, a driving method using more voltage power supplies will be described.

Since the overall configuration of the image display device and the timing control of the overall configuration are the same as those in the first embodiment, the description is omitted here.

FIG. 9 shows a driving circuit of the image display device according to the present embodiment. FIG. 9 shows only a circuit for driving one column wiring in order to easily explain the driving circuit of the present embodiment. In the following, referring to FIG.
A driving circuit for driving the cold cathode element 1001 connected to the selected row wiring 1003 and column wiring 1002 will be described.

In the image display device according to the present embodiment,
A plurality of cold-cathode devices (also referred to as cold-cathode electron-emitting devices) serving as image display devices are two-dimensionally arranged, and each is connected in a matrix by a plurality of row wirings and a plurality of column wirings to be driven. The matrix image display panel 1 as a part is constituted. Needless to say, a driving circuit similar to that shown in FIG. 9 is provided for column wiring other than the column wiring 1002 shown in FIG.

As shown in FIG. 9, the driving circuit according to the present embodiment employs a clock (PCLK) as a reference for pulse width modulation.
A counter 201 for counting upon receipt of the
2, 203, a decoder 204, and a constant register 205
, OR circuits 206 and 207, and AND circuits 208 and 2
09, and switches 210, 211, 212, and 213.

The cold cathode device 1001 is formed on a substrate (not shown). Further, there is a substrate made of glass or the like to which a phosphor (not shown) is applied and to which a high voltage (acceleration voltage) is applied, facing the cold cathode element 1001, and emits light by electrons emitted from the cold cathode element 1001. The intersections of the column wirings 1002 and the row wirings 1003 are insulated from each other, and the cold cathode elements 1001 formed near the intersections are connected to the column wirings 1002 and the row wirings 1003 by extraction electrodes.

In the configuration of FIG. 9, a selection potential is sequentially applied to the row wirings in units of horizontal synchronization signals, and the column wirings are simultaneously driven in accordance with the image data of the selected row wirings to form an image.

In the figure, S31 is luminance data, S3
2 is the output data of the counter 201, S33 is the comparator 20
2, the output signal of the comparator 203, S34
5 is the output signal of the decoder 204, S36 is the switch 21
0 control signal, S37 is a control signal of the switch 211, S
38 is a drive signal, S41 is a power supply line of voltage V1, S41 is a power supply line of voltage V2, S43 is a voltage V3
A power supply line S44 indicates a power supply line of the voltage V4.

Next, the operation of this embodiment will be described.

In FIG. 9, the luminance data S31 corresponding to each row wiring is determined by the rising pulse of the load signal LD synchronized with the horizontal synchronizing signal. Then, the lower 8 bits (D0 to D7) of the luminance data S31 are compared with the comparator 202.
The upper two bits (D8, D9) are input to the decoder 204 and the OR circuit 206. In the present embodiment, an example has been described in which the luminance data S31 is 10 bits. However, the number of bits is not limited to 10 bits. Further, the luminance data S31 is divided into upper 2 bits and lower 8 bits for processing, but the present invention is not limited to this.

On the other hand, the counter 201 is reset by the load signal LD synchronized with the horizontal synchronizing signal, and sequentially increases from 0 in synchronization with the rise of PCLK which is the pulse width modulation reference clock. Output data S of counter 201
Reference numeral 32 denotes 10 bits in the present embodiment, similarly to the luminance data, and is input to the comparator 203. The lower 8 bits of the output data S32 of the counter 201 are stored in the comparator 20.
2 is input.

The other input of comparator 203 receives the output of constant register 205. The value of the constant register is “0100
000000b "(binary, 1 means H level)
That is, it is '256', and the comparator 203 outputs an H level signal S34 when the output data S32 of the counter 201 is 1 or more and 256 or less.

In the present embodiment, the output data S32 of the counter 201 is set to 1 to 256 using the comparator 203.
Although the function of outputting the H level is realized at the time of (1), it may be realized by another method.

On the other hand, the comparator 202 compares the lower 8 bits of the output data S32 of the counter 201 with the lower 8 bits of the luminance data S31, and determines that the value represented by the lower 8 bits of the output data S32 of the counter 201 is 1. When the value is equal to or less than the value represented by the lower 8 bits of the luminance data S31,
An H-level signal S33 is output.

The OR circuit 206 ORs and outputs the upper two bits of the luminance data S31. That is, the luminance data S3
When 1 is equal to or greater than 257, the OR circuit 206 outputs an H-level signal.

The AND circuit 208 ANDs the output of the OR circuit 206 (the signal at which the luminance data S31 becomes H level when it is equal to or more than '257') and the output S34 of the comparator 203. That is, when the luminance data S31 is 257 or more, a pulse which becomes H level in the time slots 1 to 256 is output.

The OR circuit 207 ORs the output of the comparator 202 and the output of the AND circuit 208 to output a control signal S36. That is, when the luminance data S31 is 256 or less, the time slots 1 to <lower 8
A pulse which goes to the H level with the value indicated by the bit> is output. When the luminance data S31 is equal to or greater than '257', a pulse which becomes H level in time slots 1 to 256 is output.

The AND circuit 209 ANDs the output of the OR circuit 206 and the output of the comparator 202 to output a control signal S37. That is, when the luminance data S31 is equal to or smaller than '256', the L level is output, and when the luminance data S31 is equal to '2'.
If it is 57 'or more, a pulse which becomes H level in time slots 1 to <value indicated by lower 8 bits of luminance data S31> is output.

In this embodiment, the counter 201 has a 10-bit width. Since the drive duty is designed to allocate about 90% of the time for light emission in one horizontal synchronization period, the next load signal LD is output to the counter 20.
Enter when 1 counts about 290. Therefore, the counter 201 does not return to “0” before the load signal LD is input and does not perform an abnormal operation.

Next, the switch 210 sets the control signal S36.
Open and close the switch according to. When the control signal S36 is at the H level, the switch 210 is set to the contact b, and when it is at the L level, the switch 210 is switched to the contact a.

That is, the switch 210 outputs the control signal S
When 36 is at the H level, the output of the switch 211 is selected,
When the control signal S36 is at the L level, the reference potential (GND potential: 0 V) is selected, and the drive signal S38 is output to the column wiring of the matrix image display panel 1.

The switch 211 switches according to the control signal S37. When the control signal S37 is at the H level, the switch 211 is set to the contact b, and when the control signal S37 is at the L level, the switch 211 is switched to the contact a.

On the other hand, the decoder 204 outputs the luminance data S3
The upper two bits of 1 are decoded, and switches 212 and 21 are decoded.
3 is output. Switch 212,
213 is switched as shown in Table 1 by the output S35 of the decoder 204.

[Table 1]

FIG. 10 is a timing chart of the present embodiment. In FIG. 10, the luminance data S31 is “3” in the first horizontal synchronization period in the figure, and is “77” in the next horizontal synchronization period.
An example of 0 'is shown.

In FIG. 10, a luminance signal S31 is generated by a load signal LD (which is synchronized with the horizontal synchronizing signal HD).
Is determined.

On the other hand, the counter 201 outputs the load signal LD
Resets the counter to '0' at the rising edge of PCLK at the time of H level, and sequentially counts the rising clock of PCLK. In the present embodiment, this counter 2
The drive output of pulse width modulation is determined based on the lower 8 bits of the output data S32 of 01.

The comparator 202 calculates the lower 8 bits of the luminance data S31 and the lower 8 bits of the output data S32 of the counter 201.
The bits are compared as described above and a signal S33 is output. That is, in FIG. 10, since the luminance data S31 is “3” in the first horizontal synchronization period, the signal S33 is at the H level during the time slots 1 to 3. In the next horizontal synchronization period, since the luminance data S31 is '770',
Signal S33 is at H level during time slots 1-2.

The comparator 203 is provided in the constant register 20
5 is compared with the output data S32 of the counter 201 as described above, and a signal S34 is output. That is, in FIG. 10, in the first horizontal synchronization period, the luminance data S3
Since 1 is '3', the signal S34 goes to L level.
In the next horizontal synchronization period, since the luminance data S31 is '770', the signal S34 is at the H level during the time slots 1 to 256.

The output S35 of the decoder 204 controls the switching operation shown in Table 1. Switches 212 and 21
3 is the switch 2 because the luminance data S31 is '3' (D9 = 0, D8 = 0) in the first horizontal synchronization period.
12 selects the contact a, and the switch 213 selects the contact a.
Then, the switch 212 selects the power supply line S42 and outputs the voltage V2. Then, the switch 213 selects the power supply line S41 and outputs the voltage V1. In the next horizontal synchronization period, the luminance data S31 becomes '770' (D9 = 1, D8
= 1), the switch 212 selects the contact c and the switch 213 selects the contact c. Then, the switch 212 selects the power supply line S44 and outputs the voltage V4. Then, the switch 213 selects the power supply line S43 and sets the voltage V
3 is output.

Therefore, as shown in FIG. 10, the drive signal S38 output from the drive circuit outputs the voltage V1 during the time slots 1 to 3 during the first horizontal synchronization period, and outputs the voltage V1 during the time slots 4 to 256. During this time, the pulse voltage is such that 0 V is output (short with GND). In the next horizontal synchronization period, the pulse voltage is such that the voltage V4 is output during the time slots 1 and 2, and the voltage V3 is output during the time slots 3 to 256.

In the present embodiment, the voltages V1, V
2, V3, and V4 are set so as to satisfy the following conditional expression 4). V1 <V2 <V3 <V4 (Equation 4)

Further, in this embodiment, the switch 210
Is connected to the GND potential (V0). According to the design concept of the drive circuit, the state in which the switch 210 is set to the contact point a is considered to output the voltage V0.
Is selected to be equal to or longer than the maximum time T1 (maximum pulse width) when the voltage V1 is subjected to pulse width modulation. Further, T0 is selected to be equal to or shorter than the time for applying the selection potential to the row wiring. That is, the voltage V0 is a potential (reference potential:
0V).

Thus, in the present embodiment, five types (2 ² +1 types) having the relationship of V0 <V1 <V2 <V3 <V4 (Equation 4 ') are applied to the upper two bits of the luminance data S31. Will be used.

The driving waveform of the pulse voltage obtained by the above operation is schematically shown in FIG. 11A shows a waveform of the pulse voltage when the input luminance data S11 is '0' to '256', and FIG. 11B shows a waveform when the luminance data S11 is '257' to '512'. (C) shows a waveform when the luminance data S11 is '513' to '768', and (d) shows a waveform when the luminance data S11 is '769' to '768'.
The waveform in the case of '1023' is shown.

As shown in FIG. 11A, the luminance data S
When 31 is equal to or smaller than 256, drive control equivalent to pulse width modulation of the voltage V1 is performed, and the voltage V1 is pulse width modulated corresponding to the time slots 1 to 256. Voltage V0 is output until the remaining time slot 256.

When the luminance data S31 is equal to or more than '257' and equal to or less than '512', as shown in FIG. 17B, the time slots 1 to <the value of the lower 8 bits of the luminance data S31> , The voltage V2 is pulse width modulated and output, and the voltage V1 is output until the remaining time slot 256.

When the luminance data S31 is equal to or more than '513' and equal to or less than '768', as shown in FIG.
Voltage V3 is pulse width modulated and output corresponding to a time slot determined by time slots 1 to <value of lower 8 bits of luminance data S31>, and voltage V2 is output until the remaining time slot 256.

When the luminance data S31 is equal to or more than '769' and equal to or less than '1023', the time determined by time slots 1 to <the value of the lower 8 bits of the luminance data S31> as shown in FIG. Voltage V4 corresponding to the slot
Are pulse width modulated and the remaining time slots 256
During this period, the voltage V3 is output.

Here, the number of upper bits of the luminance data is j,
If the number of lower bits is k, the value represented by the upper bits is D _j , the value represented by the lower bits is D _k , and the period of the PWM reference clock is T _pclk , the driving method of the present embodiment can be generalized. , As follows.

[0170] Using the upper j bits of the input luminance data, the voltage from the 2 ^j +1 different voltages V _Dj and the voltage V
_{Dj + 1} is selected. Here, 2 ^j +1 types of voltages satisfy the relationship of the following equation. V _m <V _{m + 1} (m = 0, 1, 2,..., 2 ^j −1)

[0171] Further, each of the output pulse width T _w1 and the output pulse width T _w2 voltage V _{Dj + 1} of the voltage V _Dj becomes the following equation. T _w1 = (2 ^k −D _k ) × T _pclk T _w2 = D _k × T _pclk

[0172] Further, since the maximum pulse width T _wb is described by the following formulas, satisfy the following formula to do with ^{_{T wb = 2 k × T pclk}} T w1 and T _w2. T _wb = T _w1 + T _w2

That is, the pulse voltage obtained as described above has the same pulse width as that of the voltage V _{Dj having} the maximum pulse width T _wb , instead of part or all of the pulse, based on the lower k-bit value D _k. The waveform is as if the modulated voltage V _{Dj + 1} were combined.

[0174] Up to this manner, according to the driving method of this embodiment will be output voltage V _{Dj + 1} to the voltage V _Dj, always voltage V _Dj even when further outputs a voltage V _{Dj + 1} The pulse voltage corresponding to the pulse width is maintained. Therefore, even if there is a variation in the voltage power supply of the drive circuit or a variation in the variation of the elements, the monotonic increase property that the emission luminance always increases as the luminance data increases can be easily and reliably realized, and the reversal of the gradation can be realized. Since it does not occur, good tone reproduction can always be obtained.

Since the difference between the voltages V1, V2, V3, and V4 can be increased, and it is easy to manufacture a circuit configuration in which V1 <V2 <V3 <V4, the influence of the variation in the driving circuit is small. Not very serious. If the voltage V
Even when 1, V2, V3, and V4 vary, the monotonic increase of the luminance gradation is not impaired, but merely appears as a change in the gamma characteristic. Absent.

According to the driving method of the present embodiment,
Since the number of gradations of pulse width modulation of 10 bits can be realized with PCLK of frequency equivalent to pulse width modulation of 8 bits, excellent effects such as simplification of circuit configuration, cost reduction, reduction of power consumption, and suppression of heat generation are achieved. Can be obtained.

Further, the present inventors have determined that the driving voltages V1,
By selecting the voltages V2, V3, and V4 as follows, a remarkable improvement in gradation when displaying an image signal such as a TV signal that has been gamma-corrected in advance corresponding to a CRT has been found. .

That is, the pulse width of the voltage V1 is maximized.
The value of the luminance data when₁, Value D₁Modulated according to
The light emission luminance when the applied pulse voltage is applied is L₁, Voltage V2
The value of the luminance data when the pulse width of_Two,
Value D_TwoWhen a pulse voltage modulated according to
Light brightness L_Two, When the pulse width of the voltage V3 is maximum
D is the value of the luminance data_Three, Value D_ThreePulse modulated according to
Light emission luminance when voltage is applied is L_Three, Pulse of voltage V4
The value of the luminance data when the width is the maximum is D_Four, Value D _FourIn response
The light emission luminance when applying a modulated pulse voltage is L
_Four, And ifThe voltages V1, V2, V3, and V4 are set so that the following relationship is satisfied.
It is good to set.

In this embodiment, D ₁ = 256,
Since D ₂ = 512, D ₃ = 768, and D ₄ = 1023, the above conditional expression 5) becomes the following expression 5 ′).

By setting the voltages V1, V2, V3, and V4 as described above, the value of the luminance data is input, and the emission luminance when a pulse voltage modulated according to the value is applied is output. Has a gamma value of 1 or more.

As a more preferable condition, it is preferable that the gamma value is close to the gamma value required for the characteristics of the display system. Specifically, a gamma value γ represented by the following equation 6)
Are set so that the voltages V1, V2,
V3 and V4 may be set.

Here, for example, in the case of displaying with a gamma characteristic similar to that of a CRT, the gamma value γ is set to about 2.2. In the present embodiment, as shown in FIG. When the voltages V1, V2, V3, and V4 were set so as to be as follows, a TV signal or the like that had been gamma-corrected in advance was successfully displayed.

Note that, as in the present embodiment, the voltages V1,
When the maximum pulse widths of V2, V3, and V4 are substantially equal to each other, the voltages V1, V2, V3, and V4 may be set by the following conditional expressions instead of the above expressions 5 ') and 6). Good.

That is, a cold cathode element is supplied with a predetermined pulse width.
The luminance when the voltage V1 is applied is L ₁′, Same pulse
The brightness when the voltage V2 is applied to the cold cathode device by the width
L_Two', The luminance when the voltages V3 and V4 are applied
Each L_Three', L_Four′,The voltages V1, V2, V3, and V4 are set so that the following relationship is satisfied.
Even if it is set, it is possible to obtain the effect according to the above equation 5 ′).
Wear.

As an alternative to the above equation (6), The voltages V1, V2, V3, and V4 may be set so as to satisfy the following. Also in this case, the voltages V1, V2, and V are set so that the gamma value γ represented by the expression 6 ′) becomes about 1.0 to 3.0.
It is preferable to set the gamma value γ to about 2.3 when displaying with a gamma characteristic similar to that of a CRT.
It is preferably set to 2.

Here, if generalization is attempted in the same manner as described above, if the luminance when a voltage V _m is applied to the cold cathode element with a predetermined pulse width is L _m ′, the following equation (5 ″) is obtained. Equation 6 ')
Are represented by the following equations 8) and 9), respectively. _{L m '≦ (m / n} ) × L n' ...... formula _{8) L m '/ L n} ' = (m / n) γ ...... formula 9) (where, m = 0,1,2, ·· ·, 2 ^j ; n = 2 ^j )

By setting the voltage Vm so as to satisfy the above equation 8) or 9), even when the number of voltages is further increased, the same good tone reproduction as in the present embodiment can be easily achieved. Nature can be realized. In the above equations 8) and 9), when m = 0, V ₀ indicates a reference potential (ground potential: 0 V), and L ₀ ′ has a luminance of 0.

As described above, according to the present embodiment,
The voltages V1, V2, V3, V4
Is determined, the gradient of the input / output characteristics at low luminance (when the luminance data is equal to or less than '256') can be reduced, and the gradation of low luminance can be improved.

For example, the voltage V is set so as to satisfy Expression 7).
When 1, V2, V3, and V4 are set, the input / output characteristics of the luminance data versus the normalized luminance are as shown in the graph of FIG. In the above case, it can be seen that the luminance increase ΔI at low luminance can be reduced to about 1/4096. This is a gradation property equivalent to 12-bit pulse width modulation.

As described above, according to the present embodiment, the number of gradations (1024 gradations) can be realized by 10-bit pulse width modulation with PCLK having a frequency equivalent to 8-bit pulse width modulation, and approximately 12 at low luminance. Since it is possible to have a luminance increase amount per gradation equivalent to bit pulse width modulation, it is possible to realize excellent gradation reproduction with a small-scale circuit configuration. Further, even on the high-luminance side, it is possible to obtain better gradation than the conventional simple 8-bit pulse width modulation.

Note that, in the present embodiment, the first
Similarly to the embodiment, even when the frequency of the conventional pulse width modulation reference clock (PCLK) is reduced,
It is possible to improve the gradation. In addition, compared with the conventional simple pulse width modulation, particularly, the gradation of low luminance can be improved.

FIG. 13 shows the image data-luminance data characteristic of the luminance data converter when the characteristic of the display system has the characteristic of 2.2 power of the image data like the CRT.
FIG. 13C shows a portion where the above-described low-luminance gradation property is improved. As described above, since 12 bits of the low-luminance gradation are secured, the decrease in the number of gradations in C of FIG. 13 is small. Therefore, the gradation expression ability has been remarkably improved.

As can be seen from FIG. 12, when the number of voltages is increased as in the present embodiment, it is possible to realize a gamma characteristic like a CRT only by the drive circuit 7.

That is, when the bit width of the image data is p (the number of gradations of the image data = 2 ^p ), the following equation (10) is obtained.
The bit width of the image data is made equal to the bit width of the luminance data as shown in FIG.
The drive circuit may be designed to select two voltages for performing pulse width modulation from voltage sources having four values or eight values or more (five or nine values including the reference potential V0). p = j + k Equation 10)

If the voltage _Vm is set so as to satisfy the expression 8) or the expression 9) under the condition of the expression 10), the gamma characteristic can be realized only by the driving circuit 7, so that the luminance data converter 4 And the cost can be reduced. Further, by adjusting each of the voltages Vm according to the desired gradation reproduction, the gamma characteristic of the display system can be easily adjusted.

(Other Embodiments) In the above embodiment, switches are connected in multiple stages in series, and two drive voltages for performing pulse width modulation are selected. It is also possible to form a logic that can obtain a drive signal similar to that of the first embodiment, and control and realize one switch.

Further, a configuration may be employed in which the same drive waveform as in the above-described embodiment is generated by resistance division or an analog-to-digital converter, and the column wiring is driven by a buffer amplifier.

Further, in the above-described embodiment, an example in which the upper one bit or two bits of the luminance data is used for selecting the drive voltage and the lower eight bits are used for the pulse width modulation, but the number of bits allocated to each process is described. Can be set freely. For example, when the luminance data has a 9-bit width, of which the driving voltage is selected by the upper 2 bits and the pulse width modulation is performed by the lower 7 bits, further cost reduction can be achieved.

Further, in the above-described embodiment, the maximum value of the number of pulse width modulations (time slots) for each voltage is selected to be a power of 2 (256), but the circuit becomes complicated.
Even if the maximum value of the number of pulse width modulations (time slots) at each voltage is freely selected under the condition of T _{m + 1} ≦ T _m (where T _m is the maximum pulse width of the voltage V _m ), the effect of the present invention can be obtained. Needless to say, it can be expected.

In the above embodiment, the cold cathode type electron-emitting device has been described as an example of the image display device.
The present invention can be applied to any image display device such as an EL device and an electron-emitting device other than the cold cathode type electron-emitting device. Note that, in addition to the surface conduction type electron emitting device, the cold cathode type electron emitting device includes an FE type electron emitting device and a MI type.
Although there are M-type electron-emitting devices and the like, the present invention can be suitably applied to any of them without any problem.

[0201]

As described above, according to the present invention, based on input luminance data, instead of a part or all of the pulse of voltage V _m with a pulse width of a predetermined time, the same pulse as that portion Since the voltage _{Vm + 1} is modulated to the width to generate the pulse voltage to be applied to the image display element, even if the power supply or the element characteristics fluctuate, the inversion of the luminance gradation does not occur. Good tone reproduction can be realized.

Further, by using a plurality of voltages, the reference clock of the drive circuit can be kept low while securing a sufficient number of gradations, so that the circuit configuration can be simplified, the device can be reduced in size and cost, and consumption can be reduced. Excellent effects such as reduction of power and suppression of heat generation can be obtained.

Also, by setting each voltage so that the gamma value of the input / output characteristics is 1 or more, more preferably approximately 2.2, an excellent signal can be obtained even in an image signal or the like which has been subjected to gamma correction in advance. Tone reproduction can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a drive circuit of an image display device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of the driving circuit of FIG.

FIG. 3 is a schematic diagram of a driving waveform of a pulse voltage obtained by the driving circuit of FIG. 1;

FIG. 4 is a graph showing luminance data-luminance characteristics of the drive circuit of FIG. 1;

FIG. 5 is a diagram showing image data when the gamma value is 2.2 in the image display device according to the first embodiment of the present invention.
It is a graph which shows a brightness data characteristic.

FIG. 6 is a graph showing image data-luminance data characteristics when the gamma value is set to the BTA standard in the image display device according to the first embodiment of the present invention.

FIG. 7 is a schematic diagram of the entire configuration of the image display device according to the first embodiment of the present invention.

FIG. 8 is a timing chart of the image display device of FIG. 7;

FIG. 9 is a schematic diagram of a drive circuit of an image display device according to a second embodiment of the present invention.

FIG. 10 is a timing chart of the driving circuit of FIG. 9;

FIG. 11 is a schematic diagram of a driving waveform of a pulse voltage obtained by the driving circuit of FIG. 9;

FIG. 12 is a graph showing luminance data-luminance characteristics of the drive circuit of FIG. 9;

FIG. 13 is a graph showing image data-luminance data characteristics when the gamma value is set to 2.2 in the image display device according to the second embodiment of the present invention.

FIG. 14 is a diagram illustrating an example of characteristics of a surface conduction electron-emitting device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Matrix image display panel 2 Analog-digital converter (A / D converter) 3 Data rearrangement part 4 Brightness data converter 5 Shift register 6 Latch circuit 7 Drive circuit 8 Scan driver 10 Timing control part 81 Scan signal generation part 82 Switching means 1001 Cold cathode element 1002 Column wiring 1003 Row wiring 101 Counter 102, 103 Comparator 104 Constant register 105, 106 AND circuit 107 OR circuit 108, 109 Switch 201 Counter 202, 203 Comparator 204 Decoder 205 Constant register 206, 207 OR circuit 208 , 209 AND circuit 210, 211, 212, 213 switch

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G09G 3/20 G09G 3/20 641C 3/30 3/30 K H04N 5/68 H04N 5/68 B (72) Inventor Osamu Sagano 3-30-2 Shimomaruko, Ota-ku, Tokyo F-term in Canon Inc. (reference) 5C058 AA12 AA18 BA05 BA07 BA13 BA35 BB03 5C080 AA06 AA08 AA18 DD22 DD26 DD27 EE29 JJ02 JJ04 JJ05

Claims (28)

[Claims] 1. A driving circuit for an image display device for generating a pulse voltage to be applied to an image display element on the basis of input luminance data, wherein V + 1 (n> 1) different voltages are calculated based on the luminance data. _m <V _{m + 1} (m = 0, 1, 2,..., n−1) driving voltage selecting means for selecting two voltages V _m and V _{m + 1} having a relationship of: A pulse width modulating means for modulating the voltage V _{m + 1} to the same pulse width as that part instead of part or all of the pulse of the voltage V _m having a pulse width of a predetermined time. A driving circuit for an image display device, comprising: 2. An n + 1 voltage V _m (m = 0, 1, 2,...)
., N) are applied to the image display element with the same pulse width so that the luminance L _m ′ for each voltage satisfies the relationship L _m ≦ (m / n) × L _n ′. 2. The driving circuit according to claim 1, wherein the n + 1 voltages are set. 3. An n + 1 voltage V _m (m = 0, 1, 2,...)
..., upon application to the image display device with the same pulse width of each of the n), 'it is, L _m' luminance L _m for each voltage _{/ L n '≒ (m /} n) γ γ> 1.0 2. The driving circuit according to claim 1, wherein the n + 1 voltages are set so as to satisfy the following relationship. 4. The voltage V _m (m = 0, 1, 2,...,
n-1) is applied to the image display element with a pulse width of the predetermined time, the luminance is L _m , the luminance data value corresponding to the pulse voltage is D _m , and the pulse width of the voltage V _{m + 1} is the maximum. When the value of the luminance data when greatly modulated is D _{m + 1} , and the luminance when a pulse voltage modulated based on the value D _{m + 1} is applied to the image display element is L _{m + 1} , in at least one of _{m, L m ≦ (D m} / D m + 1) × according to claim 1, characterized in that setting the (n + 1) voltage to satisfy L _{m + 1} the relationship The driving circuit of the image display device. 5. The voltage V _m (m = 0, 1, 2,...,
n-1) is applied to the image display element with a pulse width of the predetermined time, the luminance is L _m , the luminance data value corresponding to the pulse voltage is D _m , and the pulse width of the voltage V _{m + 1} is the maximum. When the value of the luminance data when greatly modulated is D _{m + 1} , and the luminance when a pulse voltage modulated based on the value D _{m + 1} is applied to the image display element is L _{m + 1} , in at least one of m, and sets the _{L m / L m + 1 ≦} (D m / D m + 1) γ γ> the (n + 1) voltage so as to satisfy 1.0 the relationship A driving circuit for an image display device according to claim 1. 6. The driving circuit for an image display device according to claim 3, wherein said γ is γ ≒ 2.2. 7. The voltage V _m (m = 1, 2,..., N−
The pulse width of the predetermined time of 1) is such that the pulse width modulation means replaces part or all of the pulse of the voltage V _m-1 having the pulse width of the predetermined time with the same pulse width as that part. when the modulating V _m, the drive circuit of an image display apparatus according to any one of claims 1 to 6, characterized in that equal to the maximum pulse width of the voltage V _m. 8. The pulse width of the predetermined time of the voltage V _0, the pulse width modulating means is equal to or longer than the maximum pulse width of the voltages V ₁ when modulating the voltages V ₁ The driving circuit for an image display device according to claim 7, wherein: 9. The driving voltage selection means uses the upper j bits (j is a natural number) of the luminance data to generate two voltages V
_m , V _{m + 1} (m = 0, 1, 2,..., n−1), and the pulse width modulation means uses the remaining lower k bits of the luminance data to generate a voltage V _{m +} 9. The driving circuit for an image display device according to claim ₁ , wherein ₁ is modulated. 10. The driving voltage selecting means uses a value Dj represented by upper j bits of the luminance data to calculate 2 ^j +1
The driving circuit according to claim 9, wherein two voltages V _Dj and V _{Dj + 1} are selected from the plurality of different voltages. 11. When the value represented by the lower k bits of the luminance data is Dk, and the period of the pulse width modulation clock is T _pclk , the pulse width modulation means outputs the pulse of the voltage V _{m + 1} Width _Tw
11. The driving circuit of the image display device according to claim 9, wherein modulation is performed such that T _w = T _pclk × Dk. 12. The driving circuit according to claim 11, wherein the predetermined time T _wb is T _wb = T _pclk × 2 ^k . 13. The apparatus according to claim 1, wherein said voltage V ₀ is a potential for bringing said image display element into a non-light emitting state.
13. The driving circuit for an image display device according to claim 1. 14. The driving circuit for an image display device according to claim 1, wherein said voltage V ₀ is a reference potential. 15. A driven part comprising a plurality of two-dimensionally arranged image display elements connected in a matrix by a plurality of row wirings and a plurality of column wirings, and a selection potential is sequentially applied to the plurality of row wirings. An image display device that performs drive scanning by applying a driving signal, wherein the drive circuit according to any one of claims 1 to 14 is provided for each of the plurality of column wirings. 16. The image display device according to claim 15, wherein said predetermined time is equal to or shorter than a row wiring selection time. 17. The image display device according to claim 15, further comprising a conversion unit for converting image data to be displayed into luminance data to be input to said driving circuit. 18. An image display apparatus according to claim 17, wherein said conversion means is a memory storing a conversion table for inputting a bit width of image data and outputting a bit width of luminance data. . 19. An image display device comprising a cold cathode type electron-emitting device, wherein a substrate having a phosphor which emits light by electrons emitted from the cold cathode type electron-emitting device is provided facing the driven portion. 19. The image display device according to claim 15, wherein an acceleration voltage for accelerating the electrons is applied to the substrate. 20. The image display device according to claim 19, wherein said cold cathode type electron-emitting device is a surface conduction type electron-emitting device. 21. The image display device according to claim 19, wherein said cold cathode type electron-emitting device is an FE type electron-emitting device. 22. The image display device according to claim 19, wherein said cold cathode type electron-emitting device is a MIM type electron-emitting device. 23. The image display device according to claim 15, wherein said image display device is an EL device. 24. A method of driving an image display device for generating a pulse voltage to be applied to an image display element based on input luminance data, comprising the steps of: calculating V + 1 from n + 1 (n> 1) different voltages based on the luminance data; _m <V _{m + 1} (m = 0, 1, 2,..., n−1) selecting two voltages V _m and V _{m + 1} having a relationship of: Modulating the voltage V _{m + 1} to the same pulse width as the part of the pulse of the voltage V _m having a pulse width of a predetermined time instead of part or all of the pulse. How to drive the device. 25. An n + 1 voltage V _m (m = 0, 1, 2, 2)
.., N) are applied to the image display element with the same pulse width so that the luminance L _m ′ for each voltage satisfies the relationship L _m ≦ (m / n) × L _n ′. 25. The method according to claim 24, wherein the (n + 1) voltages are set as the voltages. 26. An n + 1 voltage V _m (m = 0, 1, 2, 2)
..., upon application to the image display device with the same pulse width of each of the n), 'is, L _m' luminance L _m for each voltage _{/ L n '≒ (m /} n) γ γ> 1. 25. The method according to claim 24, wherein the (n + 1) voltages are set so as to satisfy a relationship 0. 27. The voltage V _m (m = 0, 1, 2,...)
., N-1) is applied to the image display element with a pulse width of the predetermined time, the luminance is L _m , the luminance data value corresponding to the pulse voltage is D _m , and the pulse width of the voltage V _{m + 1} is The value of the luminance data when D is modulated to the maximum width is D _{m + 1} , and the luminance when the pulse voltage modulated based on the value D _{m + 1} is applied to the image display element is L _{m + 1} . when, at least one of m, to claim 24, characterized in that setting the (n + 1) voltage so as to satisfy _{L m ≦ (D m / D} m + 1) × L m + 1 the relationship The driving method of the image display device described in the above. 28. The voltage V _m (m = 0, 1, 2,...)
., N-1) is applied to the image display element with a pulse width of the predetermined time, the luminance is L _m , the value of luminance data corresponding to the pulse voltage is D _m , and the pulse width of the voltage V _{m + 1} is The value of the luminance data when D is modulated to the maximum width is D _{m + 1} , and the luminance when the pulse voltage modulated based on the value D _{m + 1} is applied to the image display element is L _{m + 1} . when, wherein setting the at least one of _{m, L m / L m +} 1 ≦ (D m / D m + 1) γ γ> the (n + 1) voltage so as to satisfy 1.0 the relationship The method for driving an image display device according to claim 24, wherein