JP2000267623A - Picture displaying method of display device and its driving device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make reducible the luminance level of a display device without deteriorating a displayed picture. SOLUTION: In the case of reducing the luminance level of an FED (electric field discharging type display), the frequency of a gradation control signal CLK outputted from a gradation clock generator is controlled to vary the number of the pulses of the clock pulses CP of the signal CLK included in one horizontal scanning period in accordance with a light-reducing quantity. Thus, the pulse width of a cathode voltage VC generated based on cathode data is varied to reduce the luminance level of the FED.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display method of a display device of an information terminal such as a television receiver, a personal computer, a medical device, a measuring instrument, a POS (Point Of Sales) system, and a drive device therefor. In particular, it is suitable for a field emission type image display device using a field emission type light emitting element.

[0002]

2. Description of the Related Art An addressing method of a field emission display (FED) constructed by a planar emission type field emission cathode (FEC) is based on a method of connecting an emitter and a gate electrode of a field emission device. With an XY matrix structure wired in a matrix, image display is performed by sequential scanning for sequentially supplying image signals in the horizontal direction.

As an example of such a field emission cathode, FIG. 7 shows a perspective view of a field emission cathode called Spindt type (hereinafter referred to as “FEC”). In FIG. 7, a cathode electrode 101 formed of a metal such as aluminum is provided on a substrate 100.
On the cathode electrode 101, a resistance layer 102, an insulating layer 103 made of silicon dioxide (SiO ₂ ), and a gate electrode 104 are provided. Then, an emitter cone 115 is formed in the hole formed in the insulating layer 103, and the tip of the emitter cone 115 faces from the opening of the gate electrode 104.

The pitch between the cone-shaped emitters is 10
Tens of thousands to tens
Ten thousand FECs can be provided over one substrate. Further, since the distance between the tip of the gate electrode and the emitter cone may be submicron, by applying a voltage of the gate voltage V _G just 10 volts between the gate electrode and the cathode electrode, in a vacuum Thus, electrons can be field-emitted from the emitter. Then, the electrons are captured by the anode voltage _VA applied to the anode electrode arranged at a position facing the cathode electrode in the vacuum space. Since the FEC has a flat shape as shown in the figure, it can be used as a field emission type field emission cathode. A type display device can be constructed.

FIG. 8 shows an example of a standard electrode structure at the time of matrix driving in such a field emission display device. In this field emission display device, 21
Denotes a _first substrate disposed in a vacuum vessel, and y ₁ to y formed in a stripe shape on the first substrate 21.
_n represents a cathode electrode as a Y electrode. This respect is the cathode electrode y ₁ ~y _n, the cathode terminal CT1~CTn drive pulse to be described later is supplied, is connected.

[0006] Also, x₁ ~ X_m Is the gate as the X electrode
Electrode, cathode electrode y₁ ~ Y _n With insulator on top
And the cathode electrode y₁ ~ Y_n Strike perpendicular to
It is formed in the shape of a loop. And the gate electrode x₁ ~ X_m 
Are gate terminals G1 to Gm to which a drive pulse is supplied.
Is connected. 22 is each gate electrode x₁ ~ X_m Formed into
And the cathode electrode y₁~ Y_n Formed on
Emitted from the conical emitter (see Figure 7)
It is formed for electrons to pass through.

Reference numeral 23 denotes a second substrate disposed in the vacuum vessel so as to face the first substrate 21. Then, 24, 24... Formed on the second substrate 23.
.. Is an anode electrode, and a gate electrode x ₁ as shown in the figure.
They are arranged in stripes corresponding to the position of ~x _m.
Further, an anode extraction electrode A is connected to each anode electrode 24. In the case of a color display, the anode extraction electrode A has three R, G, and B electrodes.
Three will be drawn out corresponding to the primary colors. Reference numeral 25 denotes a phosphor, and the anode electrode 24 has a gate electrode x ₁ to a gate electrode x ₁ .
It is provided on the surface opposite to x _m and is excited by collision of electrons.

Next, an example of a driving method for displaying an image by the FED will be schematically described. Second substrate 2
A substantially constant voltage is supplied to each of the anode electrodes 24 formed by the anode extraction electrodes A. On the other hand, the gate electrodes (x electrodes) x _{1 to} x _m are scanned by supplying scan pulses to the respective gate terminals G _{1 to} Gm, whereby the respective stripe-shaped gate electrodes are sequentially selected and driven.

Therefore, the gate terminals G1 to Gm are sequentially scanned while a positive anode voltage is applied to the anode extraction electrode A in order to drive the anode electrode 24.
At this time, when the cathode terminal CT1~CTn voltage is applied in accordance with the data of the image signal according to timing of scanning, the gate electrodes x ₁ ~x _m and the cathode electrode y ₁ ~y
The pixels emitted from the FEC block at the intersection of _n scan the pixels of the phosphor 25 provided on the anode electrode 24, and the pixels are controlled to emit light according to the voltages applied to the cathode terminals CT1 to CTn. Thus, one screen (one field) of the image is displayed in this manner.

As one of the methods of performing gradation control for adjusting the composition of light and dark or light and shade in this image display, the application time of the drive pulse applied to the cathode electrodes x _{1 to} x _m is controlled. There is a PWM (pulse width modulation) driving method, in which the gradation is controlled by controlling the pulse width tw of the driving voltage waveform.

That is, in the case of the line-sequential system in which a signal corresponding to the luminance level of each pixel of the display image is pulse-width modulated, a PWM signal pulse-modulated for each horizontal line is supplied to the cathode electrodes CT1 to CTn. When a scanning signal is sequentially supplied to the gate electrode, a portion having a wide pulse width emits light brightly, and a pixel having a narrow pulse width emits dark light, so that a color image with gradation can be displayed.

In order to obtain a PWM signal corresponding to each pixel of an image to be displayed as described above, a driver constituted by a digital IC is used. For example, when gradation display of 64 steps (0 to 63) is performed, For example, an IC circuit that performs pulse width modulation in accordance with the input image data is provided.

FIG. 9 shows the structure of the FED as described above.
FIG. 4 is a diagram illustrating an example of a driving voltage waveform applied to a gate electrode and a cathode electrode of an FED when displaying an image of four gradations. In this case, the gate driver of FIG.
Gate voltage V _G of a predetermined potential as shown in (a) is applied. Further, a cathode voltage Vc converted into a PWM signal from a cathode driver is applied to the cathode electrode. The cathode voltage Vc is, for example, in a cathode driver.
It is generated based on the input image data (cathode data) and the gradation control signal CLK shown in FIG.

The frequency of the gradation control signal CLK during normal operation depends on the specifications of the cathode driver, the number of gradations, and the like.
The frequency is set so that 63 clock pulses CP are output within the horizontal scanning period 1H.

[0015] Here, for example, when the cathode data "63" indicating the brightest gradation cathode driver is supplied, 63 th from the start t ₀ of 1 horizontal scanning period 1H as shown in FIG. (B) , A cathode voltage Vc (63) having a pulse width of a period T ₁₁ (corresponding to one horizontal scanning period 1H) until the clock pulse CP is counted is generated and applied to the cathode electrode of the FED.

Further, when the cathode data "2" indicating a relatively dark tone to the cathode driver is supplied, a clock pulse CP of two from the start t ₀ as shown in FIG. 2 (c) is counted cathode voltage Vc (2) is produced at the cathode driver that the period T ₁₂ until the pulse width,
This is applied to the cathode electrode of the FED.

[0017]

By the way, not only in the FED but also in a display device, for example, when a display image is viewed in a dark room or in a car at night, the brightness is higher than when the display image is viewed in a relatively bright place. It is desirable to lower the level.
For example, when the FED is used in a dark room, the display may be dimmed to about 3% of the brightness during normal use. For this reason, some FEDs can adjust the brightness level according to the environment (ambient illuminance) around the place where the FED is used.

As a dimming (adjustment) method for dimming a luminance level to a desired luminance level in the FED, for example, a method of converting input image data (hereinafter, referred to as a “data conversion method”) or an FED (Hereinafter referred to as “gate voltage control method”) and the like have been proposed.

FIG. 10 is a diagram for explaining the case where the brightness level of the FED is reduced by the data conversion method. For example, the gate electrode of the FED when the brightness level is reduced from the normal brightness level to 50% by the data conversion method. FIG. 3 is a diagram illustrating an example of a driving voltage waveform applied to a cathode electrode. When the FED is dimmed by the data conversion method, for example, the value of image data (cathode data) input to the cathode driver is converted according to the dimmed light, and based on the converted data value. A cathode voltage Vc is generated. Therefore, when the brightness level of the FED is reduced to 50% of the normal brightness level, for example, the input image data is converted into half value data.

Here, for example, if image data “63” is input to the cathode driver, the cathode driver converts the input image data “63” to half-value data “3”.
1 ". Then, the converted half-value data “3”
1 ”and the clock pulse CP of the gradation control signal CLK shown in FIG. 10D, the period from the start point t ₀ to the 31st clock pulse CP being counted as shown in FIG. cathode voltage Vc (3 with the T ₂₁ and the pulse width
1) is generated and applied to the cathode electrode of the FED.

Further, for example, when the cathode data "2" is supplied to the cathode driver, the cathode driver converts the cathode data "2" into half-value data "1". In response to the clock pulse CP of the gradation control signal CLK, a period T ₂₂ shown in FIG.
To generate a cathode voltage Vc (1) having a pulse width of
The voltage is applied to the cathode electrode of the ED.

That is, when the brightness level is reduced to 50% of the normal level by the data conversion method, for example, the number of gradations is set to an even number (for example, 64 gradations), and one horizontal scanning period 1
When the number N of clock pulses CP output as the gradation control signal CLK in H is an odd number (for example, N = 63), (N-1) / 2 clocks out of the N clock pulses CP The cathode voltage Vc is generated using the pulse CP. As a result, the pulse width of the cathode voltage Vc becomes the cathode voltage Vd during normal use shown in FIG.
Since the value is approximately 1/2 of c, the brightness level of the FED can be reduced to about 50% of that in normal use. In addition,
Figure 10 gate voltage V _G shown in (a), FIG 9 (a)
Is the same as the gate voltage V _G shown in.

It should be noted that the number of gray scales that can be displayed is an odd number,
When the pulse number N of the clock pulse CP output in the horizontal scanning period 1H is an even number, the cathode voltage is generated using N / 2 clock pulses CP.

FIG. 11 is a diagram for explaining the case where the brightness level of the FED is reduced by the gate voltage control method. For example, the gate electrode and the cathode of the FED when the brightness level is reduced from a normal brightness level to a brightness level of 50%. FIG. 3 is a diagram illustrating an example of a drive voltage waveform applied to an electrode. When dimming the brightness level of the FED by the gate voltage control method, for example, the voltage level of the gate voltage V _G is supplied to the gate electrode in accordance with the dimming adjustment amount is variably by the gate driver.

For example, when the brightness level of the FED is reduced to about 50% of that in normal use, the gate voltage V during scanning is
_By setting _G ′ to a voltage (about 70 V) lower than the normal gate voltage V _G (about 80 V), the amount of electron emission from the cathode electrode is reduced, and the brightness level of the FED is reduced. In this case, FIG.
The cathode voltage Vc and the gradation control signal CLK shown in (d) are the same as those in the case shown in FIG.

However, when the FED is dimmed by the data conversion method shown in FIG. 10, for example, if the dimming amount of the FED is increased, the maximum luminance level becomes "63" → "31" → "15". → The number of gradations that can be expressed in the FED is reduced from “64” → “32” → “16” →
There is a drawback that the displayed image is remarkably deteriorated because the number is reduced to “8”.

Further, the gate voltage control method shown in FIG 11, when dimming the brightness level of the FED is less electron emission from the FED cathode electrode according to the gate voltage V _G is lower Therefore, the cathode substrate 100 and the emitter cone 115 shown in FIG.
The current stabilizing effect of correcting the variation of the emission current of each emitter due to the resistance layer 102 provided between them is reduced, and there is a disadvantage that display unevenness occurs in a display image.

As described above, the dimming of the FED by the data conversion method or the gate voltage control method is accompanied by deterioration of the displayed image. Therefore, the brightness level of the FED is sufficiently dimmed by these methods to, for example, about 3% of the normal state. It was very difficult to do.

[0029]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and is directed to a display apparatus for displaying an image by driving pixels arranged in a matrix in a line-sequential manner. As an image display method, when the luminance level of the display device is dimmed to a required luminance level, the frequency of the gray scale clock is varied according to the dimmed light amount, and the input is performed based on the gray scale clock with the changed frequency. A pulse width modulated signal obtained by pulse width modulating image data is supplied to a display device as a drive signal.

Further, as a driving device of a display device for displaying an image by driving pixels arranged in a matrix in a line-sequential manner, a gradation clock generating means for generating a gradation clock of a predetermined frequency; Pulse width modulation signal generation means for generating a pulse width modulation signal corresponding to input image data based on a clock; driving means for driving the display device using the pulse width modulation signal as a drive signal; and brightness of the display device When the level is reduced to a required luminance level, a control means is provided for varying the frequency of the gradation clock in accordance with the reduced amount of light.

According to the present invention, when dimming the luminance level of the display device to a required luminance level, the frequency of the gray scale clock is varied according to the dimmed light amount, and based on the gray scale clock whose frequency has been changed. Since a pulse width modulation signal obtained by pulse width modulation of input image data is supplied to the display device as a drive signal, the amount of light can be reduced without reducing the number of gradations determined by the number of gradation clocks. A corresponding drive signal can be generated.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a driving apparatus for a display device including a field emission device will be described as an embodiment of the present invention. FIG. 1 is a block diagram showing a configuration example of a display device employing the FED. In this figure, 1 uses a field emission element for displaying an image in a multi-matrix system in which the anode electrodes are A1 and A2 and the gate electrodes are divided into two groups and image data is supplied from the cathode electrode, as described later. This is the FED.

That is, the anode electrodes A1 and A2 are composed of two comb-shaped anode electrodes A1 and A2 as shown in the electrode arrangement of FIG. 2, and the three primary colors R and A are formed on the anode transparent electrode plate. G and B fluorescent materials are applied so as to form display pixels. Also, the gate electrode G
, G2, G3, G4,... Are arranged in a direction orthogonal to the anode electrode, and the structure of the gate electrodes G1, G2,. Are alternately staggered along upper and lower horizontal lines.

Each of the gate electrodes is an anode electrode A
Scanning is performed so that the scan pulse is supplied to the odd gate electrodes in the first half of the field where 1 is selected, and the scan pulse is supplied to the even gate electrodes in the second half of the field where the anode electrode A2 is selected. Will be Also,
The cathode electrodes C1, C2, C3,... Are arranged so as to be opposed to the respective anode electrodes, and are driven so as to supply horizontal image data in synchronization with gate scanning.

In FIG. 1, reference numeral 2 denotes input digital image (video) data, and reference numeral 3 denotes an image input buffer circuit.
An image data signal received by the image input buffer circuit 3 is a controller 4 for forming data necessary for controlling image display.
Has been transmitted to. Reference numeral 5 denotes a display memory (RAM) for storing image data before processing and reading the data in accordance with a display method.

Image data for controlling the brightness of the FEC is supplied from the controller 4 to the cathode drivers 6A and 6B, and as shown in FIG.
A drive signal PWM-modulated for C3... Is transmitted to each pixel in the horizontal direction. A scanning signal for scanning the gate electrodes G1, G2,... Arranged in the horizontal direction as shown in FIG.
7 are arranged on a line-sequential matrix in which gate electrodes are sequentially selected in accordance with a display system, but are driven in a manner similar to that of the conventional system.

Reference numeral 8 denotes an anode power supply for supplying an anode voltage and a switching circuit. In particular, in order to select three primary colors of a color image, two anode electrodes A1 and A2 are synchronized with the scanning timing of the gate driver 7 and the order thereof. To choose. Reference numeral 9 denotes a gate voltage control circuit which sets the scanning order and timing of the gate electrodes G1, G2,... And sends a predetermined pulse voltage to the gate driver 7.
The gate electrodes arranged in the horizontal direction are arranged in a zigzag pattern so that adjacent pixels in the horizontal direction can be selected alternately in the horizontal direction, and have a focusing action on the electron beam emitted from the emitter. I have to have

Reference numeral 10 denotes a power supply section of the cathode drivers 6A and 6B and a power supply section of the gate driver 7. By appropriately setting the voltage value of the cathode drive signal and the voltage value of the gate drive signal supplied from the power supply. The dynamic range of the luminance of the display unit can be adjusted. 2
Reference numeral 1 denotes a grayscale clock generator that supplies a grayscale clock (grayscale control signal) CLK having a predetermined frequency to the cathode drivers 6A and 6B, and is configured by an oscillation circuit such as a crystal oscillator or a VCO. At the same time, the oscillation frequency can be controlled.

In the case of such a display device, the gate electrodes are first scanned in an odd-numbered column and then in even-numbered columns while alternately selecting the anode electrodes A1 and A2 in one frame period (or one field period). Control, the pixels of the three primary colors formed on the anode electrode can sequentially emit light.
By changing the pulse width of the WM signal in accordance with the image data, it is possible to give gradation to the color display image.

FIG. 3 is a diagram showing the configuration of cathode drivers 6A and 6B for taking in input image data and forming a pulse width modulated cathode drive signal.
In FIG. 3, reference numeral 11 denotes a shift register which stores pixel data input as serial data for one horizontal line. If the number of bits of the data length of one pixel in the serial data is M bits, the shift register 11 is controlled so as to take in M-bit image data.

Reference numeral 12 denotes a latch circuit, which is controlled to convert serial pixel data taken into the shift register 11 into parallel image data and hold it for a predetermined time within one horizontal period. 13 is a plurality of comparators c
(1,... M), which compares each pixel data input from the latch circuit 12 with the output of the counter 14 that counts the gradation control signal CLK. During the period until the counted value matches the value of the image data, the comparator c (1, 2,.
m), and the signals are supplied to the gate unit 15 respectively.

The gate section 15 controls the time from when the counter 14 is cleared and the data is latched by the latch circuit 12 to when the signal indicating that the count value of the counter 14 matches the value of the image data is output. Is formed as a pulse width, and the pulse signal is supplied to the high-voltage buffer unit 1.
6 The high-voltage buffer unit 16 includes a plurality of buffer amplifiers f (1, 2,..., M) that are switching-controlled by the pulse signal, and converts a cathode voltage Vc supplied from a cathode power supply as a predetermined voltage into the buffer amplifier. f (1, 2,... m) are supplied to the respective cathode electrodes. Therefore, the cathode voltage Vc pulse-width-modulated according to the image data (cathode data) is applied from the high voltage buffer unit 16 to each cathode electrode.

Hereinafter, a method of dimming the FED driving device, which is a feature of the present invention, will be described with reference to FIGS. FIG. 4 shows an example of the driving voltage waveform applied to the gate electrode and the cathode electrode of the FED when the brightness level of the FED is reduced to, for example, 50% of the normal level in the FED driving device of the present embodiment. FIG. Note that the driving device of the FED of the present embodiment has 64 gradations (0 to 6).
It is assumed that the image display of 3) can be performed, and the frequency of the grayscale clock CLK is a frequency at which 63 clock pulses CP are output within one horizontal scanning period 1H.

[0044] In this case, the gate electrode, in one horizontal scanning period 1H, the gate voltage V _G of a predetermined potential as shown in FIG. 4 (a) from the gate driver 7 (see FIG. 1) is applied. A cathode voltage Vc that has been subjected to pulse width modulation (PWM) so as to correspond to input image data (cathode data) is applied to the cathode electrode.

The cathode voltage V applied to the cathode electrode
c is the image data and the grayscale clock (grayscale control signal) CLK in the cathode drivers 6A and 6B as described above.
Obtained by the count value of the counter 14 that counts
Generated based on the WM signal.

Therefore, in the display device of the present embodiment, for example, the brightness level of the FED 1 is set to 50 times the normal brightness level.
In the case of dimming to%, the controller 4 controls the frequency of the grayscale control signal CLK output from the grayscale clock generator 11 to be twice that in normal use. That is, in this case, as shown in FIG. 4D, the pulse number N of the clock pulse CP output as the gradation control signal CLK within one horizontal scanning period 1H is doubled as compared with the normal time. The pulse width of the cathode voltage Vc generated based on the cathode data is set to be １ ／ of the pulse width in the normal state.

[0047] For example, the cathode driver 6A, when the brightest cathode data "63" is supplied to the 6B, start counting from the time t ₀ when the counter 14 is cleared as shown in FIG. (B) 63 th cathode voltage Vc having a period T ₁ of the up pulse width clock pulse CP is output (63) is to be applied to the cathode electrode of. Also, when a relatively dark cathode data "2" is supplied to the cathode driver pulse duration T ₂ of the up clock pulses CP of two counted from the starting point t _0, as shown in FIG. 2 (c) is output The width of the cathode voltage Vc (2) is applied to the cathode electrode.

Therefore, the pulse width of the cathode voltage Vc generated in the cathode drivers 6A and 6B is almost の of the normal cathode voltage Vc shown in FIG. 9, and in this case, the brightness level of the FED 1 is changed to the normal state. 50% of
It can be dimmed to a degree. In this case, even when the pulse width of the cathode voltage is set to の of the normal time, the cathode voltage Vc corresponding to the gradation of the input image data can be generated. Is not reduced and the display image is not degraded. Also, the gate voltage V _G applied to the gate electrode of FED1
Need not be varied, the gate-cathode voltage, which is the operating condition of the FEC, can be stabilized. Therefore, as shown in FIG.
Since the current stabilizing effect of the resistance layer 102 between 0 and the emitter cone 115 can be maintained, display unevenness does not occur in a display image.

As described above, in the present embodiment, when the brightness level of the FED 1 is reduced, the frequency of the gradation control signal CLK is increased by an amount corresponding to the reduced light amount, so that the display displayed on the display device is reduced. The brightness level can be adjusted without deteriorating the image.

In the FED driving apparatus according to the present embodiment as described above, if the frequency of the gradation control signal CLK is increased by an amount corresponding to the amount of light reduction of the FED 1, the displayed image is deteriorated. For example, the brightness level of the display image can be reduced to about 3% of the normal level, but the frequency of the gradation control signal CLK is set to a sufficiently high frequency due to the switching characteristics of the cathode drivers 6A and 6B. It is also conceivable that it cannot be changed to.

Therefore, in such a case, the dimming by the frequency control of the gradation control signal CLK described above (hereinafter referred to as “frequency control method”) and the gate voltage control method described above with reference to FIG. Combined with FED1
It is also possible to diminish the brightness level of.

FIG. 5 shows a driving voltage waveform applied to the gate electrode and the cathode electrode of the FED 1 when the frequency control method and the gate voltage control method are used in combination and, for example, the brightness level is reduced by 50% by each method. FIG. 4 is a diagram showing an example of the above. Such dimming control is realized by the controller 4 shown in FIG. 1 controlling, for example, the gate voltage control circuit 9 in addition to the control of the grayscale clock generator 21. The controller 4 uses the frequency control method shown in FIG.
In addition to frequency control of the gray scale control signal CLK explained in FIG. 5 the gate voltage V _G 'supplied to the gate electrode of FED1 (a), the normal use gate voltage V _G (about 80V ) Is controlled so as to have a lower voltage (about 70 V). Therefore, in this case, it is possible to perform sufficient dimming that cannot be realized by the frequency control method alone due to the characteristics of the driver IC and the like.

When such a frequency control method and a gate voltage control method are used together, the dimming by the frequency control method and the dimming by the gate voltage control method are performed only when the dimming cannot be performed to a target luminance level. Is performed, the voltage drop between the gate and the cathode, which is a drawback of the gate voltage control method, can be minimized, so that, for example, display unevenness of a display image is suppressed to a minimum.

Further, in addition to the frequency control method and the gate voltage control method, the brightness level of the FED 1 can be reduced by using the data conversion method shown in FIG. FIG. 6 shows the driving voltage waveforms applied to the gate electrode and the cathode electrode of the FED 1 when the data conversion method further reduces the light intensity by 50% in addition to the frequency control method and the gate voltage control method shown in FIG. FIG. 4 is a diagram showing an example of the above. In this case, the controller 4 controls not only the gradation clock generator 21 and the gate voltage control circuit 9 but also control so that the input image data is converted to half value data and output.

As described above, when the dimming control by the three dimming methods by the gate voltage control method and the data conversion method is performed in addition to the frequency control method, the target luminance level can be obtained only by the dimming by the frequency control method. Even when the light cannot be dimmed, for example, the FED is controlled by a combination of the frequency control method, the gate voltage control method and the data conversion method, or a combination of the frequency control method and the data conversion method
Normal luminance level 3 where the luminance level of 1 is the target luminance level
%.

Also in this case, only when the dimming by the frequency control method fails to reduce the brightness to the target luminance level, the dimming is performed by the gate voltage control method, the data conversion method, or a combination thereof. This can minimize the deterioration of the displayed image, which is a disadvantage of the gate voltage control method and the data voltage method.

In this embodiment, for simplicity of explanation, a case where the brightness level of the FED 1 is reduced by 50% by the frequency control method, the gate voltage control method, and the data conversion method will be described as an example. Although described, this is merely an example, and it goes without saying that further dimming can be performed in each system.

The display device according to the present embodiment includes:
A so-called gate scan type FED in which image data is supplied to the cathode electrode and a scanning voltage is applied to the gate electrode has been described as an example. For example, a so-called cathode that applies image data to the gate electrode and applies a scanning voltage to the cathode electrode The present invention can be applied to a scan type FED. Further, in the present embodiment, the FED has been described as an example of the display device, but the display device may be any device that displays a display image by the PWM method.

[0059]

As described above, according to the present invention,
When dimming the luminance level of the display device to a required luminance level, the frequency of the gradation clock is varied according to the dimming amount,
A pulse width modulation signal obtained by pulse width modulation of input image data is supplied to a display device as a drive signal based on a grayscale clock having a variable frequency. This makes it possible to reduce the brightness of the display device without reducing the number of gradations of the image data. Therefore, the brightness level of the display device can be reduced to the desired brightness level without deteriorating the display image displayed on the display device. Can be dimmed.

Further, the dimming control such as changing the voltage level of the scanning signal supplied to the display device by the control means or converting the data value of the input image data into a required data value is performed together. Accordingly, it is possible to surely reduce the luminance level of the display device to a target luminance level while minimizing deterioration of a display image displayed on the display device.

[Brief description of the drawings]

FIG. 1 is a diagram showing circuit blocks adapted to a driving method of a display device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a drive electrode of the display device of the present embodiment.

FIG. 3 is a block diagram illustrating an example of a drive IC circuit that forms a PWM signal.

FIG. 4 is a diagram illustrating an example of a driving voltage waveform supplied to a gate electrode and a cathode electrode of the FED when dimming of the FED is performed by a frequency control method.

FIG. 5 shows the FE using both the frequency control method and the voltage control method.
FIG. 4 is a diagram illustrating an example of a drive voltage waveform supplied to a gate electrode and a cathode electrode when D dimming is performed.

FIG. 6 is a diagram illustrating an example of a driving voltage waveform supplied to a gate electrode and a cathode electrode when dimming of an FED is performed by a frequency control method, a voltage control method, and a data conversion method.

FIGS. 7A and 7B are a perspective view and a sectional view showing a Spindt-type field emission cathode. FIGS.

FIG. 8 is a diagram showing a standard drive electrode driven by a line-sequential matrix method.

FIG. 9 is a diagram illustrating an example of a drive voltage waveform supplied to a gate electrode and a cathode electrode.

FIG. 10 is a diagram showing an example of a drive voltage waveform supplied to a gate electrode and a cathode electrode when dimming of an FED is performed by a data conversion method.

FIG. 11 is a diagram showing an example of a drive voltage waveform supplied to the gate electrode and the cathode electrode of the FED when dimming the FED by the gate voltage control method.

[Explanation of symbols]

 4 Controller 6A, 6B Cathode driver 7 Gate driver 21 Tone clock generator 11 Shift register 12 Latch circuit 13 Comparison unit 14 Counter 16 Gate unit 17 High voltage buffer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/28 G09G 3/28 K

Claims (4)

[Claims] An image display method for a display device that performs image display by driving pixels arranged in a matrix in a line-sequential manner, wherein the brightness level of the display device is reduced to a required brightness level , The frequency of the gradation clock is varied according to the amount of light reduction, and based on the gradation clock with this frequency varied,
An image display method for a display device, wherein a pulse width modulation signal obtained by pulse width modulation of input image data is supplied to the display device as a drive signal. 2. A grayscale clock generating means for generating a grayscale clock of a predetermined frequency, comprising: a grayscale clock generating means for generating a grayscale clock of a predetermined frequency; A pulse width modulation signal generating unit that generates a pulse width modulation signal corresponding to input image data based on the grayscale clock; a driving unit that drives the display device using the pulse width modulation signal as a driving signal; When the brightness level of the device is dimmed to a required brightness level, a control device for varying the frequency of the gradation clock according to the dimming amount is provided. 3. The display device according to claim 2, wherein the control unit changes a voltage level of a scan signal supplied from the drive unit to the display device according to the light quantity reduction. Drive. 4. The driving device according to claim 2, wherein the control unit converts a data value of the image data into a required data value according to the light quantity reduction.