JP2001331143A - Display method and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display method by which the gradation display capability of a display panel is drawn out and a high display quality picture can be displayed by optimizing a gradation display characteristics of the display panel by matching it to a video signal of a picture information signal. SOLUTION: In an organic EL panel 11 comprising plural data electrodes 2... extended in a 1st direction, and plural scanning electrodes 3... extended in the direction orthogonal to the above 1st direction, pixels are formed at the crossing parts of the above data electrodes 2 and scanning electrodes 3, and when the above scanning electrodes 3 are sequentially selected in the 1st direction, this selected duration is varied according to picture information to be inputted to a selected scanning electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film EL (Electr
o Luminescence element, FED (Field Emission Devic)
e) The present invention relates to a display method and a display device for displaying an image on a display panel in which self-luminous elements such as elements are two-dimensionally arranged.

[0002]

2. Description of the Related Art In recent years, as a candidate for a flat panel display that competes with a liquid crystal display, for example, an organic EL display
A display device (display) using a self-luminous element such as a thin-film EL element or an FED element typified by an element has attracted attention.

As shown in FIG. 16, the thin-film EL element applies a voltage to a light-emitting display element 102 which is at least one of which is transparent and which is interposed between a first electrode 101 and a second electrode 103 which intersect each other in a matrix. When applied, a pixel formed at the intersection of each electrode emits light.

Therefore, in a display using the above-mentioned thin film EL element, one of the electrode groups intersecting in a matrix is defined as a scanning line and the other is defined as a data line, and one or a plurality of scanning lines are selected. One screen is constituted by scanning and displaying an image by a signal from the data line. As described above, in a simple matrix type display in which electrodes are arranged in a matrix, an image is displayed by line-sequential driving.

On the other hand, the above-mentioned FED element is shown in FIG.
As shown in (b), the gate electrode Gx (x = 1, 2, 2)
..) Are formed in a structure in which a plurality of pixels having the field emission type emitter 112 driven by the two-dimensional array are formed. Also, the display substrate 110 constituting the FED element
Represents each pixel Pij (i = 1, 1) on the silicon substrate 111.
2,..., J = 1, 2,...) Are composed of R, G, and B dots, and, for example, four field emission type emitters (hereinafter simply referred to as emitters) 112 each having a sharp tip in each dot region. Each is formed. In addition,
FIG. 17B shows only one emitter 112 for each dot for convenience of explanation.

In the FED element having the above structure, the emitter wiring 113 (11) for commonly driving the emitters 12 in the column direction is used.
3 _1R , 113 _1G , 113 _1B ,...) Are separated from each other by an insulating film 115, and R, G, B
Are arranged three by one, and the emitter terminal E is externally provided.
(E _1R , E _1G , E _1B ,...). Also,
The gate wirings (electrodes) 114 (114 ₁ , 114 ₂ ,...) For commonly driving the respective emitters 112 in the row direction are formed on the silicon substrate 111 via the insulating film 116, and holes for exposing the respective emitters 112 are formed. It is to be processed. Each gate wiring 114 has a gate terminal G (G
1, G2,...).

Further, as shown in FIG.
Counter substrate 120 facing display substrate 110 of ED element
Is formed using a transparent substrate 121 made of glass or the like, and an anode electrode 122 made of a transparent conductive film such as ITO (Indium-tin Oxide) is formed on the surface thereof.
On the upper side, the phosphor films 123 (123 _R , 12 _R ) for R, G, and B correspond to the R, G, and B dots of each pixel Pij, respectively.
3 _G , 123 _B ) are formed.

Although not shown, the space between the display substrate 110 and the counter substrate 120 is vacuum-sealed with a sealing material such as low-melting glass. In this case, preferably, a getter material such as a barium alloy or a zirconium alloy is sealed inside the FED element body. Note that the space between the display substrate 110 and the counter substrate 120 is evacuated.

In a display using the above-mentioned FED element, as shown in FIG. 18, a plurality of gate lines Gx (x
, P) are connected to the gate drive circuit 132, and a plurality of emitter wirings Ey (y = 1, 2,..., Q) that commonly drive the field emission emitters of the pixels in the column direction are ,
It is connected to the emitter drive circuit 133. In this display, a pixel Pxy is formed at the intersection of the gate line Gx and the emitter line Ey.

Therefore, in the display using the FED elements, for example, while the gate lines Gx are sequentially driven, image data of one line is applied to the emitter lines Ey in synchronization with the gate lines Gx, thereby two-dimensionally arranging the lines. An image is displayed on the selected pixel to constitute one screen. Thus, an image is displayed by line-sequential driving even in a display using the FED element.

As described above, in many XY matrix display devices in which pixels are arranged in the row and column directions, an image is displayed mainly by line-sequential scanning. In such a line-sequential scan, in a specific time zone, only some pixels on the display are lit, but since the human eye has an integration effect,
If all the pixels are turned on at a cycle that cannot be discriminated by the human eye, an image can be obtained with the average brightness. The repetition frequency of the line-sequential scanning, that is, the driving frequency is generally set to 50 Hz or more at which humans do not feel flicker.

In order to perform gradation display in a display having such an XY matrix electrode structure, it is necessary to control light emission luminance based on gradation information of an input video signal. For this light emission luminance control, a method of changing an applied voltage or current to change an integrated value of light emission luminance with time,
There is a method of changing the integrated value of the emission luminance by combining them. The display determines whether current control or voltage control is advantageous.

The gradation control used in the thin film EL element and the FED element includes a voltage (or current) modulation method,
There are a pulse width modulation method, a voltage (or current) / pulse width modulation method, and the like. Here, the voltage (or current) modulation method is a method of performing gradation control by changing the applied voltage (or current) according to the gradation when selecting and scanning a pixel. The pulse width modulation method is a method in which the applied voltage (or current) is kept constant and the pulse width is varied to temporally control the gradation. The voltage (or current) / pulse width modulation method is a method of performing gradation control by making an applied voltage and a pulse width variable.

[0014]

However, in the above-described line-sequential scanning, scanning lines (or gate electrodes) are not used.
It is considered that the time for selecting one or more by one, that is, one scanning selection period is constant. In addition, how many gradations can be displayed in this fixed period is a problem.

For example, Japanese Patent Application Laid-Open No. H11-296131 discloses a pulse width modulation gray scale driving method for realizing gray scale control of a thin film EL element. In this pulse width modulation gradation driving method, as shown in FIG. 19, one scanning selection time is divided into a plurality of time widths having different relative ratios, and the divided periods are controlled in accordance with gradation display information. This is a gradation control method of obtaining a gradation by emitting light.

In the above gradation control method, when an input video signal as image information has 256 gradations, one scanning line selection time is in a ratio of 1: 2: 4: 8: 16: 32: 64: 128. Of the pulse width. By making these eight pulses having different widths correspond to display or non-display, 25 pulses can be displayed.
Six types of voltage application time are made to perform gradation display.

In the gradation control method for a thin film EL element disclosed in the above publication, specifically, one scanning line selection period is (1/60) when the frame frequency is 60 Hz and the number of scanning electrodes is 240.
× (1/240) seconds, and this scanning selection period is fixedly captured. The gradation frequency is 115 kHz (frame frequency 60 Hz × number of scanning electrodes 240 × number of pulses 8).
, And the number of gray scales displayed during one scanning line selection period is also fixed.

As described above, in the conventional pulse width modulation gray scale driving method applied to the thin film EL device, one scanning line selection period and the number of gray scales displayed during one scanning line selection period are fixed.

On the other hand, Japanese Patent Application Laid-Open No. H11-15430 discloses a voltage / pulse width modulation gradation driving method for realizing a gradation control method for an FED element. This voltage / pulse width modulation gradation driving method uses an emitter voltage pulse as
Pulse width control corresponding to M gradations (M is an arbitrary integer) and N
This is a gray scale control method for obtaining a gray scale by generating a pulse waveform including information of M × N gray scale defined by pulse amplitude control corresponding to gray scale (N is an arbitrary integer).

In the above publication, the reference amplitude value P0
When displaying 640 × 480 pixels at a frame frequency of 60 Hz using the minimum amplitude value P0 / 16, the basic pulse width W0 is expressed as: W0 = 1 / (60 × 480 × 16) ≒ 2.17 [μs
c], and the number of gradations to be displayed in one scanning line selection period is fixed.

As described above, even in the voltage / pulse width modulation gray scale driving method applied to the conventional FED element, one scanning line selection period and the number of gray scales displayed during one scanning line selection period are fixed.

Incidentally, the average luminance of the actual video signal varies in various ways, and accordingly, the maximum luminance and the optimal luminance of the pixels on each scanning electrode are also variously distributed. Therefore, the gradation distribution of each color of RGB is examined for a certain standard image, and the maximum gradation and the minimum gradation are shown for each scanning line in a graph shown in FIG. 10, which is an explanatory diagram of the present invention.

From the graph shown in FIG. 10, the maximum gradation included in this video signal is 240 gradation levels or less,
Further, it can be seen that the minimum gradation is larger than the 20 gradation level. This means that 0-255 is required to express the video signal.
Even in a display that requires 256 gradations up to the gradation level (hereinafter referred to as a display panel), not all images always use 256 gradations up to the 0-255 gradation level. 0-255 for all scanning lines.
This indicates that 256 gradations up to the gradation level are not used. In other words, this indicates that it is not necessary to use the gradation expression capability of the display panel to the maximum in a normal image.

Further, the maximum expression gradation level of the display panel used does not always coincide with the theoretical maximum value of the input gradation level. In this case, if the input 0-255 gradation level is displayed as the gradation level of the display panel regardless of the display image, the maximum gradation of the input signal is (the maximum expression gradation level of the display panel / the input gradation level). The theoretical maximum value is 255) times, and when the maximum expression gradation level of the display panel is smaller than the theoretical maximum value of the input gradation level, the gradation range of the display panel becomes small.

Therefore, in each of the gradation control methods disclosed in each of the above publications, one scanning line selection period and the number of gradations displayed during one scanning line selection period are fixed, so that the video signal side This means that the image is displayed without considering the gradation level and the gradation display performance of the display panel at all.

For this reason, it is impossible to display an image according to the gradation display characteristics of the display panel, and there is a problem that the display quality is remarkably reduced.

The present invention has been made to solve the above problems, and an object of the present invention is to optimize a gradation display characteristic on a display panel side in accordance with a video signal which is an image information signal. It is an object of the present invention to provide a display method and a display device that can display a high-quality image by drawing out the gradation expression capability of the display panel.

[0028]

In order to achieve the above object, a display method according to the present invention provides a display in which pixels are arranged in a matrix and a first electrode is a scanning line.
This is a display method in which the time width Wi of one scanning selection period corresponding to each scanning line Li is converted in accordance with image information of a pixel corresponding to each scanning line Li (i is an integer of 2 or more).

As the display method, m (m is an integer of 2 or more) in a first direction and a second display orthogonal to the first direction.
In the display panel, n elements (n is an integer of 2 or more) are two-dimensionally arranged in the direction of a pixel Aij (i = 1, 2).
2,..., M, j = 1, 2,.
j, a plurality of pixels Aa1, arranged in the second direction
Aa2,..., Aan (a = 1, 2,..., M) are simultaneously selected, and the selected pixels Aa1, Aa2,
, Aan are sequentially selected in the first direction, and the pixels Aa1, Aa2,.
is selected in the first direction by the pixel Aa.
1, Aa2,..., Aan.

In this case, simultaneously selected pixels Aa1,
The selection time width of Aa2,..., Aan in the first direction is changed according to the image information input to the pixels Aa1, Aa2,. By changing according to the display characteristics, the gradation display characteristics of the display panel can be changed to image information (video signal).
Can be optimized for

Therefore, since the gradation expression ability of the display panel can be brought out, the display quality of the displayed image can be greatly improved.

In the above display method, for example, the maximum value Bi of the signal level of the image information input to the pixels Ai1 to Ain simultaneously selected at a certain moment is detected over a certain period, and the average value A is obtained. Aa1, Aa2, ..., Aan
May be determined by the following equation: Wi = maximum value Bi / average value A.

In the display method, the pixel Ai
The reference voltage or the reference current applied to each of the pixels Ai1 to Ain may be changed according to the value of the average value A during the period of detecting the maximum value Bi of the signal level of the image information input to 1 to Ain. .

In this case, since the basic gradation period (that is, the selection time width Wi) in the pulse width modulation gradation control method can be generally lengthened, the influence of the distortion of the data waveform propagating in the display panel. Can be relatively reduced, and the gradation display with the reduced effect can be stabilized.

Further, in the display method, when the maximum value Bi of the signal level of the image information input to the pixels Ai1 to Ain selected simultaneously at a certain moment is detected for a predetermined period, the maximum value Bi is determined in advance. Compared with a set reference value C (arbitrary integer), if the maximum value Bi is larger than the reference value C, the maximum value Bi is set as a calculated value Di, and the maximum value Bi is the same as the reference value C. If it is smaller or smaller, the reference value C is stored as the calculated value Di, and the average value E of the calculated values Di stored during the predetermined period is obtained.
The selection time width Wi of Ain in the first direction may be calculated by the following equation: Wi = calculated value Di / average value E.

In this case, since the basic gradation period (ie, the selection time width Wi) in the pulse width modulation gradation control method can be generally lengthened, the influence of the distortion of the data waveform propagating in the display panel. Can be relatively reduced, and the gradation display with the reduced effect can be stabilized.

Further, in the above display method, the pixel Ai
During the period of detecting the maximum value Bi of the signal levels of the image information input to 1 to Ain, the reference voltage or the reference current applied to each of the pixels Ai1 to Ain may be changed according to the value of the average value E. .

Further, in the above display method, the pixel Ai
The reference voltage or the reference current applied to each of the pixels Ai1 to Ain during the period of detecting the maximum value Bi of the signal level of the image information input to 1 to Ain is expressed by the following expression. It may be obtained at the key level.

Further, in the display method, the pixel Ai
The period for detecting the maximum value Bi of the signal level of the image information input to 1 to Ain may be one field or one frame period.

In this case, the period for detecting the maximum value Bi of the signal level of the image information input to the pixels Ai1 to Ain is set to one field or one frame period.
A certain period for obtaining the average value A or the average value E based on the detected maximum value Bi is one field or one frame period. As a result, the switching of the synchronization signal can be performed during the vertical blanking period, so that it is possible to obtain an effect that the switching is hardly noticeable and is preferable.

As another display method, the maximum value Bi of the signal level of the image information input to the pixels Ai1 to Ain simultaneously selected at a certain moment is detected, and the pixel Ai1 is detected.
The signal level F of image information to be input to .about.Ain is expressed by the following equation: F = the maximum expressible gradation level of the display panel / the maximum value B
i.

In this case, since the gradation range of the display panel can be adjusted according to the image information, an image can be displayed in a wider gradation range.
The display quality of the display image can be improved.

The display device to which the display method of the present invention is applied includes, for example, m (m is an integer of 2 or more) in the first direction,
A display panel in which n (n is an integer of 2 or more) elements are two-dimensionally arranged in a second direction orthogonal to the first direction;
Each element in the display panel is represented by a pixel Aij (i = 1, 2, 2).
, M, j = 1, 2,..., N) and a plurality of pixels Aa1, Aa2,
, Aan (a = 1, 2,..., M) are simultaneously selected, and the selected pixel is sequentially selected in the first direction to drive the display panel so as to display an image. And the pixels Aa1, Aa2,
, Aan are selected for the pixels Aa1, Aa2,.
To change according to the image information input to Aan,
The display device may include a control circuit that generates a control signal for controlling the drive circuit.

According to the above configuration, the selection time width of the simultaneously selected pixels Aa1, Aa2,..., Aan in the first direction is determined according to the image information input to the pixels Aa1, Aa2,. In other words, by changing the selection time width according to the gradation display characteristics of the display panel, the gradation display characteristics of the display panel can be optimized according to the image information (video signal).

Accordingly, since the gradation expression capability of the display panel can be brought out, the display quality of the displayed image can be greatly improved.

[0046]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1] A matrix type display according to the present embodiment, as shown in FIG.
The display panel includes an organic EL panel 11 using an organic EL element (thin film EL element) as a display panel, a scanning side driving circuit 12 as a driving circuit for driving the organic EL panel 11, and a data side driving circuit 13. .

The organic EL panel 11 is a glass substrate 1
A plurality of data electrodes 2 formed thereon and a plurality of scan electrodes 3 formed orthogonally to the data electrodes 2. An organic thin film is provided between the data electrodes 2 and the scan electrodes 3. 4 (FIG. 3) are formed. The details of the organic EL panel 11 will be described later.

The data electrode 2 is electrically connected to a data drive circuit 13, and the scan electrode 3 is electrically connected to a scan drive circuit 12.

The scanning side drive circuit 12 receives drive circuit control signals (OFP, OHP) and drives the scan electrodes 3 by the drive circuit control signals.

The data side drive circuit 13 comprises a field memory 14, a data hold timing control circuit 1
5. A constant current circuit 16 is provided.

The field memory 14 receives an image information signal and a synchronizing signal (IHP, IFP, ICLK). Then, the input image information signal is written to the field memory 14 in synchronization with the clock signal ICLK, and the field memory 1 to which each image information signal is written is written.
4 is reset in synchronization with the horizontal synchronization signal IHP, and the upper address is reset in synchronization with the vertical synchronization signal IFP. Then, the field memory 14
The image information signal stored once in
The signals are input to the timing control circuit 15 in parallel.

Further, drive circuit control signals (OHP, OGP) are input to the data hold / timing control circuit 15, and a gradation control signal is input to the constant current circuit 16.

The data side drive circuit 13 supplies a data signal generated from each input signal to the data electrode 2.

The details of the signal processing in the data side drive circuit 13 will be described later.

The drive circuit control signals (OFP, OHP) supplied to the scan side drive circuit 12 and the drive circuit control signals (OHP, OG) supplied to the data side drive circuit 13
P) and the gradation control signal are generated by the control circuit 17 shown in FIG.

As shown in FIG. 2, the control circuit 17
A comparator 18, a line memory 19, and a computing unit 20 are provided. Based on the input vertical synchronizing signal, horizontal synchronizing signal, and image information signal (video signal), the drive circuit control signal
HP, OFP, OGP) and a gradation control signal.

The comparator 18 receives the horizontal synchronizing signal and the image information signal, detects the maximum value of the signal level of the image information signal, and stores the maximum value in the line memory 19.
Output. Here, the signal level indicates a gradation level.

The line memory 19 receives and stores the maximum value of the image information signal, and receives the horizontal synchronizing signal. Based on this horizontal synchronizing signal, the maximum value of the image information sequentially stored for a certain period is determined. The values are collectively output to the arithmetic unit 20.

When the maximum value of the image information is inputted collectively by a predetermined amount, the arithmetic unit 20 calculates an average value, a total sum, and the like of these maximum values, and outputs drive circuit control signals (OHP, OFP, OFP).
GP) and a gradation control signal, and outputs these control signals to the scanning side driving circuit 12 and the data side driving circuit 13 based on the input vertical synchronizing signal.

The details of signal generation in the control circuit 17 will be described later.

Here, the details of the organic EL panel 11 constituting the matrix type display having the above configuration will be described below.

As shown in FIG. 3, the organic EL panel 11 includes a plurality of data electrodes 2 made of a transparent electrode such as ITO extending on the glass substrate 1 in one direction (first direction).
Are formed on the data electrode 2 and a plurality of scanning electrodes 3 made of a metal electrode such as Al extending in a direction (second direction) orthogonal to the data electrode 2 via the organic thin film 4 via the organic thin film 4. You.

A region where the data electrode 2 and the scanning electrode 3 intersect is defined as a pixel. Therefore, the data electrode 2
Is m (m is an integer of 2 or more) and n (n is an integer of 2 or more) is the number of the scanning electrodes 3.
The panel 11 has m × n pixels.

As shown in FIG. 4A, the organic thin film 4 has a hole injection layer 5, a hole transport layer 6,
It has a laminated structure in which the light emitting layer 7 and the electron transport layer 8 are laminated. That is, the hole injection layer 5 is arranged to be in contact with the data electrode 2 serving as an anode, and the electron transport layer 8 is
The organic E is disposed so as to be in contact with the scanning electrode 3 serving as a cathode.
It constitutes an L element.

As the light emitting layer 7, for example, FIG.
And the like. Examples of the material used for the organic thin film 4 include, for example, JP-A-3-15289.
7, JP-A-5-70773, JP-A-5-1
98377, JP-A-5-214332, JP-A-6-172751, JP-A-11-33996
No. 5 and the like are mentioned.

The hole transport layer 6 includes, for example, a compound represented by the chemical formula shown in FIG.
For example, the compound shown in FIG. 6 is used as the electron transport layer 8. In the chemical formula shown in FIG.
, M is an integer of 2 or 3, R ₁ is a hydrogen atom, a halogen atom, a lower alkyl group or a lower alkoxy group, and Ar is an optionally substituted aryl group having 6 to 13 carbon atoms.
In the chemical formula shown in FIG. 6, R ₂ is a halogen atom, a lower alkyl group or a lower alkoxy group.

The light emission characteristics of the organic EL device are described below with reference to the graphs shown in FIGS.

The horizontal axis of the graph shown in FIG. 7 indicates the voltage value applied between the cathode (scanning electrode 3) and the anode (data electrode 2), and the vertical axis indicates the current value flowing through the light emitting layer 7. . This graph shows that the temperature of the organic EL element was -40 ° C., 20 ° C., 8
The measured values when set at 0 ° C. are shown.

From the above graph, it can be seen that the cathode (data electrode 2)
It can be seen that the current flowing through the light emitting layer 7 is determined by the voltage applied between the anode and the anode (scanning electrode 3).

The horizontal axis of the graph shown in FIG. 8 indicates the value of the current flowing through the light emitting layer 7, and the vertical axis indicates the light emission luminance of the light emitting layer 7.

From the above graph, it can be seen that the light emission luminance of the light emitting layer 7 is determined in proportion to the value of the current flowing through the light emitting layer 7.

A method of driving a matrix-type display having the above-described structure provided with the organic EL panel 11 composed of the organic thin film 4 having such characteristics will be described below with reference to a schematic diagram shown in FIG. FIG. 9 shows a method of driving an organic EL panel including scanning electrodes (row electrodes) K1 to K64 and data electrodes (column electrodes) A1 to A256.

Here, the organic EL panel is constructed.
After 256 × 64 pixels, pixel E _Two._TwoAnd pixel E_Two._ThreeWhen
Will be described.

[0074] When light emission of the pixel _{E 2. 2, E 2.} 3, as shown in FIG. 9, dropped scan electrodes K2 selected to the GND potential, identify other scanning electrode potential (in this case about 10V)
And then, pixel E ₂ desired to emit light. _2, E _2. Flows a constant current (driving current) from the data electrodes A2, A3 corresponding to _3, the data electrodes corresponding to the pixels that do not want to emit light is open. In this way, a desired image is displayed by causing only the pixel to emit light to emit light.

In order to display multiple gradations in each pixel,
The data electrode is turned on in proportion to the gradation level desired to be displayed on each image. That is, the gradation display method applied in this case is a pulse width modulation gradation control method in which the current output from the drive circuit to the data electrode is fixed and the pulse width is varied.

Here, the data side drive circuit 13 and the control circuit 1 provided in the matrix type display having the above-described structure are used.
7 will be described. The organic EL panel 11 provided in the matrix type display has a size of m × n.
(M is an integer of 2 or more, n is an integer of 2 or more) pixels and any pixel Aij (i = 1, 2,...,
m, j = 1, 2,..., n).

First, as shown in FIG. 2, the control circuit 17 controls the pixels Ai1 to Ain selected simultaneously at a certain moment.
The maximum value Bi of the signal level of the image information input to the pixel Aa1, the average value A is obtained over a certain period, and the pixel Aa1,
Selection time width W of Aa2,..., Aan in the first direction
i is obtained by the following equation: Wi = maximum value Bi / average value A.

During the certain period, the pixels Ai1 to Ain
This is a period for detecting the maximum value Bi of the signal level of the image information input to.

That is, in the control circuit 17, the comparator 1
8, the maximum value Bi (i = 1, 2,... M) of the input image information signal in one horizontal synchronizing signal cycle is detected and stored in the line memory 19. From the line memory 19, a certain period (preferably one field period or one frame period)
The plurality of maximum values Bi input during T0 are output to the arithmetic unit 20, and the arithmetic unit 20 outputs 1 during the predetermined period T0.
Times, the average value A of the maximum values Bi is calculated, and each maximum value B is calculated.
A selection period Wi is set for each line Li giving i, and the average value A is output as a line synchronization signal OHP (drive circuit control signal).

The computing unit 20 calculates the maximum value B
i, and a grayscale synchronization signal OGP indicating a basic grayscale period by dividing a certain period T0 based on the total sum.
(Drive circuit control signal) and a gradation control signal.

The computing unit 20 further includes a vertical synchronizing signal IF
Based on P, a field synchronization signal OFP (drive circuit control signal) is output.

During the arithmetic processing in the arithmetic unit 20, the image information signal is stored in the field memory 14 constituting the data side drive circuit 13 shown in FIG. The field memory 14 can be replaced with a frame memory. That is, the field memory and the frame memory are substantially the same, and are properly used according to the type of the image information signal. For example, in the case of an image information signal for performing interlaced scanning of NTSC TV broadcasting,
Since one frame is composed of odd and even fields, a field memory is used. On the other hand, in the case of an image information signal to be subjected to non-interlaced scanning (progressive scanning) by a computer or the like, a frame memory is used because it is not expressed as a field but expressed as a frame.

Of the drive circuit control signals generated by the arithmetic unit 20, the field synchronization signal OFP and the line synchronization signal OHP are input to the scanning side drive circuit 12, and the line synchronization signal OHP and the gradation synchronization signal OGP are applied to the data side. It is input to the drive circuit 13.

Therefore, in the scanning side drive circuit 12, 1
A field synchronization signal OF for setting the scanning electrode 3 to the GND state once in a field period (or one frame period)
P is transferred to the scan electrode Li at a predetermined timing by a line synchronization signal OHP for setting the selection period Wi for each line Li.

In the data drive circuit 13, the data is selected by the scan drive circuit 12 (the gate electrode is G
The image data corresponding to the scan electrode Li (to be in the ND state) is transferred from the field memory 14 to the data hold timing control circuit 15 in synchronization with the line synchronization signal OHP corresponding to the start timing of the scan electrode Li. Has become.

The constant current circuit 16 in the data side drive circuit 13 counts the number of the grayscale synchronizing signals OGP in accordance with the grayscale data of the pixel held by the data hold / timing control circuit 15, The constant current circuit 16 is turned on in proportion to the tone data. The value of the current output from the constant current circuit 16 (the time when the constant current circuit 16 is in the ON state) is set by the gradation control signal output from the control circuit 17.

In the control circuit 17, for example, the processing when the gradation level of the image information signal serving as the standard image is a graph as shown in FIG. 10 will be described. This graph shows an output from the comparator 18, and shows a state in which each of RGB colors is expressed by 0 to 255 gradation display, and the maximum value is detected without distinction of each of RGB colors.

That is, in the control circuit 17, the comparator 1
8, the maximum value B of the signal level (gradation level) included in the image information signal input based on the horizontal synchronization signal
i is detected, the maximum value Bi is stored in the line memory 19, and the arithmetic unit 20 calculates the total sum (about 39930) of the maximum value Bi in the 180 line period.

Assuming that this 180 line period is one frame (the cycle is 1/60 second), the arithmetic unit 20 sets the basic gradation period as follows: 1 gradation period = (1/60) / 39930 ≒ 417 [n
s].

The selection period W1 corresponding to the line L1
Is set as: W1 = 214 × 1 gradation period ≒ 89.3 [μs].

The current output Px from the constant current circuit 16 shown in FIG. 1 is calculated based on the reference value P0 as follows: Px = P0 × 39930 / (180 × 255) ≒ 0.8
A gradation control signal is output from the control circuit 17 so as to be 70 × P0.

Therefore, the control circuit 17 can change the basic gradation period, that is, the pulse width according to the image information signal.

On the other hand, if the conventional method is used, that is, if each scanning electrode can always output the gradation level of 0 to 255 regardless of the image information signal, the basic gradation period becomes , 1 gradation period = (1/60) / (180 × 255) ≒ 36
3 [ns]. At this time, the current output remains at the reference value P0.

In general, when the pulse width modulation gradation control method is used, the amount of distortion of the data waveform propagating in the display panel becomes constant. Therefore, as the pulse width becomes narrower, the influence of the distortion becomes relatively large. That is, the gradation is distorted, and the gradation display becomes unstable.

However, when the same standard image is displayed, the basic gradation period obtained by the control circuit 17 according to the present invention is 417 [ns], and each scanning electrode is irrespective of the image information signal. In the case where the output can be always performed up to the gradation level of 0 to 255, the basic gradation period is longer than 363 [ns]. In other words, in the present invention, the pulse width is wider than the pulse width according to the conventional method, and the period of the gradation period is longer.

Therefore, in the matrix type display having the above structure, the period of the basic gradation period in the pulse width modulation gradation control method is lengthened, and the influence of the distortion of the data waveform transmitted through the panel is relatively reduced. Thus, there is an effect that the gradation display can be stabilized.

[Embodiment 2] As shown in FIG. 11, a matrix type display according to the present embodiment has an FED panel 31 using an FED element as a display panel and a driving circuit for driving the FED panel 31. And a data-side drive circuit 33.

The FED panel 31 includes a plurality of electrode wiring layers 52 formed on a substrate 51 and the electrode wiring layers 5.
A plurality of electron extraction electrodes 53 formed orthogonal to the second electrode wiring layer 52.
Are electrically connected to each other, and the scanning side drive circuit 32 is electrically connected to the electron extraction electrode 53.

The scanning side drive circuit 32 receives a drive circuit control signal (OFP, OHP), and drives the electron extraction electrode 53 according to the drive circuit control signal.

The data side drive circuit 33 includes a line memory 34, a data hold timing control circuit 35, and a constant current circuit 36. The line memory 34 has a delayed image information signal and a drive circuit control signal (OHP, OCL
K) is input, drive circuit control signals (OHP, OGP) are input to the data hold / timing control circuit 35, and a gradation control signal is input to the constant current circuit 36.

The data side drive circuit 33 supplies a data signal generated from each input signal to the electrode wiring layer 52.

The details of the signal processing in the data side drive circuit 33 will be described later.

The data driving circuit 33 and the FED
The panel 31 is connected via a power supply 37, and a constant potential is applied from the power supply 37 to the FED panel 31.

The driving circuit control signals (OFP, OHP) supplied to the scanning side driving circuit 32 and the driving circuit control signals (OHP, OGP, OGP) supplied to the data side driving circuit 13 are provided.
CLK), the delayed image information signal, and the gradation control signal
It is generated by the control circuit 38 shown in FIG.

The control circuit 38 includes a comparator 39, a field memory 40, a line memory 41, and a calculator 42. The control circuit 38 controls the drive circuit based on the input vertical synchronizing signal, horizontal synchronizing signal, and image information signal. Signal (OHP, O
FP, OGP) and a gradation control signal.

When the horizontal synchronizing signal and the image information signal are input, the comparator 39 detects the maximum value of the signal level of the image information signal, and stores the maximum value in the line memory 41.
Output. During this time, the comparator 39
Are stored in the field memory 40 and output to the data side driving circuit 33 as a delayed image information signal.

The line memory 41 receives and stores the maximum value of the image information signal, and receives the horizontal synchronizing signal. Based on the horizontal synchronizing signal, the maximum value of the image information sequentially stored for a predetermined period is determined. The values are collectively output to the arithmetic unit 42.

When the maximum value of the image information is collectively input by a predetermined amount, the arithmetic unit 42 calculates an average value, a total sum, and the like of these maximum values and obtains drive circuit control signals (OHP, OFP, OFP).
GP, OCLK) and a gradation control signal, and output these signals to the scanning side driving circuit 32 and the data side driving circuit 33 at timing based on the input vertical synchronizing signal.

The details of signal generation in the control circuit 38 will be described later.

Here, the FED panel 31 will be described below with reference to FIGS. 13 (a) to 13 (c). 13A and 13B are cross-sectional views of the FED panel 31, and FIG.
(C) is a plan view of the FED panel 31, (a) is a cross-sectional view taken along line AA 'of (c), and (b) is (c).
(C) is a cross-sectional view taken along the line BB 'of FIG.
FIG. 4 is a plan view of the electron emission portion side in a state of being cut along an X ′ line.

In the FED panel 31, an electrode wiring layer 52 serving as a data electrode is formed on a substrate 51, and an insulating film 54 is formed on the electrode wiring layer 52. On the insulating film 54, substrate-side ribs 55 are arranged at predetermined intervals.

An electron emitting portion 56 is formed at a predetermined interval between the insulating film 54 and the substrate-side rib 55. The electron emitting portion 56 is connected to any wiring of the electrode wiring layer 52 via a through hole formed in the insulating film 54.

On the substrate-side rib 55, an electron extraction electrode 53 for electron extraction serving as a scanning electrode is formed.

A transparent front glass substrate 57 is arranged opposite to the substrate 51. This front glass substrate 57
And the substrate 51, the substrate-side rib 55 and the substrate-side rib 55
The front ribs 58 are arranged at a predetermined distance apart from each other by the front ribs 58 arranged orthogonally to. The space between the substrate 51 and the front glass substrate 57 is evacuated.

A light emitting portion 5 made of a phosphor is provided in a region between the front ribs 58 on the inner surface of the front glass substrate 57.
9 (pixels) are formed in a stripe shape, and a metal back film 60 formed by evaporating an aluminum film is formed on the surface thereof.

A constant potential is applied to the metal back film 60 from the power supply 37 (FIG. 11).

The number of the light emitting portions 59 is m (m is an integer of 2 or more) in the first direction, and n (n is an integer of 2 or more) in the second direction orthogonal to the first direction. , And an arbitrary light-emitting portion is defined as a pixel Aij (i = 1, 2,..., M,
j = 1, 2,..., n).

The fluorescent material constituting the light emitting section 59 may be a fluorescent material used in a CRT (Cathode-Ray Tube) or the like.
A phosphor that emits light by colliding electrons accelerated with energy as high as 10 keV is used.

In the FED panel 31 having the above structure, a predetermined potential of the electrode wiring layer 52 is applied to the metal back film 60 while a positive potential is applied to the metal back film 60 and a positive or zero potential is applied to the electron extraction electrode 53. By applying a negative potential,
Electrons are emitted from the electron emitting portion 56 connected to the wiring. Then, the emitted electrons are attracted to the positive potential of the metal back film 60 and reach the light emitting portion 59 at a position facing the electron emitting portion 56, and the portion of the light emitting portion 59 emits light. Will do.

A plurality of electron-emitting portions 56 are arranged in a matrix so as to face a plurality of light-emitting portions 59 arranged in a stripe pattern, as shown in FIG. Has become.

For example, a certain light emitting portion 59 is made of a phosphor that emits red light, an adjacent light emitting portion 59 is made of a phosphor that emits blue light, and an adjacent light emitting portion 59 is made of a fluorescent material that emits green light. If it is composed of a body, color display can be realized.

In the present embodiment, the electron emitting portion 56 is made of carbon nanotube. That is, the needle-shaped columnar graphite having a length of several μmm to several mm made of an aggregate of carbon nanotubes is fixedly arranged in a predetermined area with, for example, a conductive adhesive or the like so as to form the electron emission portion 56. ing. Note that the electron emission portion 56 may be formed by pattern formation by printing using a columnar graphite paste. At this time, the longitudinal direction of the columnar graphite is substantially oriented in the direction of the light emitting portion 59.

In the FED panel 31, similarly to the organic EL panel 11 described in the first embodiment, the current flowing through the light emitting section 59 as a light emitting layer due to the potential difference between the electron emitting section 56 and the electron extraction electrode 53. Is determined, and the light emission luminance of the light emitting section 59 is determined in proportion to the current drawn from the electron emitting section 56.

The drive of the FED panel 31 having the above configuration is controlled by inputting various control signals generated by the control circuit 38 shown in FIG.

Here, the data side driving circuit 33 and the control circuit 3 provided in the matrix type display having the above configuration
8 will be described.

First, the control circuit 38 detects the maximum value Bi of the signal level of the image information input to the pixels Ai1 to Ain, which are the light-emitting portions 59 selected simultaneously at a certain moment, over a certain period. The maximum value Bi is compared with a preset reference value C (arbitrary integer), and when the maximum value Bi is larger than the reference value C, the maximum value Bi is set as a calculated value Di. When the reference value C is equal to or smaller than the reference value C, the reference value C is stored as a calculated value Di,
The average value E of the operation values Di stored in the predetermined period is obtained, and the selection time width Wi for selecting the pixels Ai1 to Ain in the first direction is obtained by the following equation: Wi = operation value Di / average value E .

That is, in the control circuit 38,
As shown in (2), the maximum value Bi of the input image information signal in one horizontal synchronization signal cycle is detected by the comparator 39. If the maximum value Bi is larger than a predetermined reference value C, the detected maximum value is set. The value is output to the line memory 41 as the value Bi.

The line memory 41 stores the input maximum value Bi, and collectively outputs the maximum value Bi input during a certain period (preferably one field period or one frame period) T0 to the arithmetic unit 42. I do.

The arithmetic unit 42 calculates the average value E of the maximum values Bi once every fixed period T0, sets the selection period Wi for each line Li that gives the maximum value Bi, and sets the average value E As a line synchronization signal OHP (drive circuit control signal).

On the basis of the sum of the maximum values Bi, the fixed period T0 is divided to divide the predetermined period T0 into a grayscale synchronizing signal OGP (drive circuit control signal) and a grayscale control signal indicating the basic grayscale period. The signal is output to the circuit 33. During this time, the image information signal is stored in the field memory 40 and output to the data side drive circuit 33 as a delayed image information signal.

Further, the control circuit 38 generates a data transfer clock OCLK, which is one of the drive circuit control signals, based on the clock signal ICLK.
Output to 3.

On the other hand, the control circuit 38 supplies the scanning electrode (electrode extraction electrode 53) to the selected state (a state where a positive potential is applied) once in one field (or one frame) period. (A drive circuit control signal), and a line synchronization signal OHP for setting the selection period Wi for each line Li in order to transfer the field synchronization signal OFP.

The data side driving circuit 33 stores the delayed image information signal sent from the control circuit 38 in the line memory 34. Then, the image data corresponding to the scanning electrode Li to be selected by the scanning side drive circuit 32 (the electron extraction electrode 53 becomes positive potential) is converted into the scanning electrode Li.
Line synchronization signal OHP corresponding to the start timing of
In synchronization with the data hold from the line memory 34.
The grayscale data of the pixel is transferred to the timing control circuit 35.

In the constant current circuit 36 in the data side drive circuit 33, the data hold / timing control circuit 35
The number of the grayscale synchronizing signals OGP is counted in accordance with the grayscale data of the pixel held in the step (1), and the constant current circuit 36 is turned on for a period proportional to the grayscale data. Note that this constant current circuit 3
The value of the current output from the control circuit 6 (the time when the constant current circuit 36 is in the ON state) is set by the gradation control signal output from the control circuit 38.

In the control circuit 38, for example, the processing in the case where the gradation level of the image information signal serving as the standard image is a graph as shown in FIG. 10 of the first embodiment will be described. This graph shows the output from the comparator 18, where each of the RGB colors is represented by a 0-255 gradation display, and
This shows a state in which the maximum value is detected without distinction of each color of GB.

Here, the comparator 39 provided in the control circuit 38 detects and outputs the maximum value Bi based on the result of the comparator 18 provided in the control circuit 17 of the first embodiment. Circuit. That is, the comparator 39 is the comparator 1
If the result of No. 8 is not less than the reference value C, this result is output as the maximum value if the result of the comparator 18 is not more than the reference value C. If this reference value C is 210 or less, the result is the same as that of the first embodiment.

Normally, the reference value C secures a minimum time required for transferring the delayed image information signal from the field memory 40 shown in FIG. 12 to the line memory 34 in the data side driving circuit 33 shown in FIG. Decide so you can. Therefore, the reference value C may be set to about 160.

In this embodiment, the reference value C is set to 220 in order to show a difference from the first embodiment.

In the comparator 39, the reference value C is set to 22
The maximum value Bi obtained by setting it to 0 is output to the line memory 41, and the total sum of the maximum values in the 180-line period is obtained as about 404000 by the calculator 42. Assuming that this 180 line period is one frame (the cycle is 1/60 second), the arithmetic unit 42 sets the basic gradation period as 1 gradation period = (1/60) / 404000 ≒ 412 [n
s].

The selection period W1 corresponding to the line L1
Is set as W1 = 220 × 1 gradation period ≒ 90.8 [μs].

The current output Px from the constant current circuit 36 shown in FIG. 11 is Px = P0 × 4 with respect to the reference value P0.
The gradation control signal is output from the control circuit 38 so that 04000 / (180 × 255) ≒ 0.888 × P0.

Therefore, the control circuit 38 can change the basic gradation period, that is, the pulse width, according to the image information signal.

On the other hand, if the conventional method is adopted, that is, if the scanning electrodes can always output to the 0-255 gradation level regardless of the image information signal, the basic gradation period is , 1 gradation period = (1/60) / (180 × 255) ≒ 36
3 [ns]. At this time, the current output remains at the reference value P0.

In general, when the pulse width modulation gradation control method is used, the amount of distortion of the data waveform propagating in the display panel becomes constant. The tonality is distorted, and the gradation display becomes unstable.

However, when displaying the same standard image, the basic gradation period obtained by the control circuit 17 according to the present invention is 412 [ns]. In the case where the output can be always performed up to the gradation level of 0 to 255, the basic gradation period is longer than 363 [ns]. In other words, in the present invention, the pulse width is wider than the pulse width according to the conventional method, and the period of the gradation period is longer.

Therefore, in the matrix type display having the above-described structure, the period of the gradation period which is the basis of the pulse width modulation gradation control method is lengthened, and the influence of the distortion of the data waveform transmitted through the display panel is relatively reduced. In addition, there is an effect that the gradation display can be stabilized by that amount.

Further, in the present embodiment, since it is possible to use a line memory 34 instead of a field memory for the data side driving circuit 33,
It is possible to reduce the manufacturing cost of the circuit as compared with the data-side drive circuit 13 of the first embodiment that uses the above.

[Embodiment 3] As shown in FIG. 14, a matrix type display according to this embodiment has an organic EL panel 11 as a display panel,
A scanning-side drive circuit 12 and a data-side drive circuit 71 are provided as drive means for driving. The organic E
The L-panel 11 and the scanning-side drive circuit 12 are the same as those described in the first embodiment, and a description thereof will be omitted.

As shown in FIG. 14, the data side drive circuit 71 includes a line memory 72, a gradation level conversion circuit 7,
3, a data hold / timing control circuit 74 and a constant current circuit 75, and the line memory 72 has a drive circuit control signal (OHP,
OCLK), a display image control signal is input to the gradation level conversion circuit 73, and the data hold
The timing control circuit 74 supplies a drive circuit control signal (OH
P, OGP) are input, and a gradation control signal is input to the constant current circuit 75.

The data driving circuit 71 supplies a data signal generated from each input signal to the data electrode 2.

Various signals input to the scanning drive circuit 12 and the data drive circuit 71 are generated by a control circuit 76 shown in FIG.

The control circuit 76 detects the maximum value Bi of the signal level of the image information input to the pixels Ai1 to Ain which are simultaneously selected at a certain moment.
The signal level F of the image information to be input to the display panel is represented by the following equation: F = the maximum expressible gradation level of the display panel / the maximum value B
i.

That is, the control circuit 76 includes a comparator 77, a first arithmetic unit 78, and a second arithmetic unit 79. Based on the input vertical synchronizing signal, horizontal synchronizing signal, and image information signal, Circuit control signals (OHP, OFP, OG)
P, OCLKk), a gradation control signal, and a display image control signal.

When the horizontal synchronizing signal and the image information signal are input, the comparator 77 detects the maximum value Bi of the signal level of the image information signal, and outputs the maximum value Bi to the first computing unit 78. Output.

The first computing unit 78 outputs a gradation control signal and a display image control signal to the data driving circuit 71 based on the input maximum value Bi.

The second arithmetic unit 7 in the control circuit 76
Numeral 9 indicates that a vertical synchronizing signal and a horizontal synchronizing signal are inputted, so that a line synchronizing signal OHP, a field synchronizing signal OFP, a gray scale synchronizing signal OGP, a data synchronizing signal, The clock OCLK is generated and output to the data side driving circuit 71.

In the data-side drive circuit 71, image data corresponding to the scan electrode Li which is to be selected in the scan-side drive circuit 12 and whose gate electrode is to be in the GND state,
Read from the line memory 72 and read the gradation level conversion circuit 7
3 is input.

In the above tone level conversion circuit 73, FIG.
The image data is converted into a gradation level by the display image control signal input from the control circuit 76 shown in (1), and the data is held in synchronization with a line synchronization signal OHP which is a drive circuit control signal corresponding to the start timing of the scanning electrode Li. • Transfer to the timing control circuit 74.

The data hold / timing control circuit 74 counts the number of the grayscale synchronizing signals OGP according to the held grayscale data of the pixel, and turns on the constant current circuit 75 for a period proportional to the grayscale data. Is transferred to the constant current circuit 75.

The constant current circuit 75 outputs a predetermined current to the data electrode 2 during the ON state. The current value output from the constant current circuit 75 is set by the gradation control signal input from the control circuit 76.

In the control circuit 76, for example, the processing in the case where the gradation level of the image information signal serving as the standard image is a graph as shown in FIG. 10 described in the first embodiment will be described. This graph shows an output from the comparator 18, and shows a state in which each of RGB colors is expressed by 0 to 255 gradation display, and the maximum value is detected without distinction of each of RGB colors.

The gradation expressing ability of the organic EL panel 11 in this embodiment is 64 gradations of 0 to 63.
Therefore, the maximum expression gradation level of the organic EL panel 11 is 63.

In the graph shown in FIG. 10, line L1
Is 214, the output R for each pixel in the line L1 with respect to the gradation signal Q input to the gradation level conversion circuit 73 shown in FIG. The expression image control signal is controlled as shown in FIG. 15 so that the expression gradation level) / (the maximum value Bi corresponding to each scanning line)) × Q = (63/214) × Q ≒ 0.2944 × Q. It is generated by the circuit 76 and input to the gradation level conversion circuit 73. At this time, the input gradation levels 0 to 214 are displayed on the display in a gradation range of 0 to 63 gradation levels.

Further, the current output Px from the constant current circuit 75 shown in FIG. 14 is expressed by Px = ((maximum value Bi corresponding to each scanning line) / (theoretical maximum of the input gradation level) with respect to the reference value P0. Value)) × P0 = (214/255) × P0 ≒ 0.839 × P0 The gradation control signal is applied to the control circuit 76 shown in FIG.
And is input to the constant current circuit 75.

On the other hand, the inputted 0-255 gradation level is changed to 0-6 on the display regardless of the gradation level of the display image.
In the case of displaying as three gradation levels, the maximum value 214 of the input signal corresponding to the line L1 of the graph shown in FIG. 10 is 214 × (63/255) ≒ 53, and the gradation range of the display corresponding to the line L1 Is 0 to 53. Note that the output current to the scan electrode at this time remains at the reference value P0.

Therefore, in the matrix type display according to the present embodiment, the gradation range can be changed according to the gradation level of the display image. The display can be set finely, and as a result, the display quality can be improved.

This embodiment is different from the first embodiment.
It can be used in combination or not. When this embodiment and the first embodiment are used together, an effect of stabilizing the gradation display is also exhibited in addition to an effect that the gradation display can be set finely.

[0168]

According to the display method of the present invention, as described above, in a display in which pixels are arranged in a matrix and the first electrode is a scanning line, each scanning line Li (i is an integer of 2 or more) is used. This is a method of converting the time width Wi of one scanning selection period corresponding to each scanning line Li according to the image information of the corresponding pixel.

As the display method, m (m is an integer of 2 or more) in the first direction, and the second display is orthogonal to the first direction.
In the display panel, n elements (n is an integer of 2 or more) are two-dimensionally arranged in the direction of a pixel Aij (i = 1, 2).
2,..., M, j = 1, 2,.
j, a plurality of pixels Aa1, arranged in the second direction
Aa2,..., Aan (a = 1, 2,..., M) are simultaneously selected, and the selected pixels Aa1, Aa2,
, Aan are sequentially selected in the first direction, and the pixels Aa1, Aa2,.
is selected in the first direction by the pixel Aa.
1, Aa2,..., Aan.

As a result, the gradation display characteristics of the display panel can be optimized according to the image information (video signal). As a result, the gradation expression capability of the display panel can be brought out. This has the effect that the display quality can be greatly improved.

In the above display method, for example, the maximum value Bi of the signal level of the image information input to the pixels Ai1 to Ain simultaneously selected at a certain moment is detected over a certain period, and the average value A is obtained. Aa1, Aa2, ..., Aan
May be determined by the following equation: Wi = maximum value Bi / average value A.

In the display method, the pixel Ai
The reference voltage or the reference current applied to each of the pixels Ai1 to Ain may be changed according to the value of the average value A during the period of detecting the maximum value Bi of the signal level of the image information input to 1 to Ain. .

Thus, the basic gradation period (ie, the selection time width Wi) in the pulse width modulation gradation control method.
Can be generally lengthened, so that the influence of the distortion of the data waveform propagating in the display panel can be relatively reduced, and the gradation display with the reduced effect can be stabilized. This has the effect.

In the above display method, when the maximum value Bi of the signal level of the image information input to the pixels Ai1 to Ain selected simultaneously at a certain moment is detected for a certain period, the maximum value Bi is set in advance. Compared with a set reference value C (arbitrary integer), if the maximum value Bi is larger than the reference value C, the maximum value Bi is set as a calculated value Di, and the maximum value Bi is the same as the reference value C. If it is smaller or smaller, the reference value C is stored as the calculated value Di, and the average value E of the calculated values Di stored during the predetermined period is obtained.
The selection time width Wi of Ain in the first direction may be calculated by the following equation: Wi = calculated value Di / average value E.

Thus, the basic gradation period (ie, the selection time width Wi) in the pulse width modulation gradation control method.
Can be generally lengthened, so that the influence of the distortion of the data waveform propagating in the display panel can be relatively reduced, and the gradation display with the reduced effect can be stabilized. This has the effect.

Further, in the above display method, the pixel Ai
During the period of detecting the maximum value Bi of the signal levels of the image information input to 1 to Ain, the reference voltage or the reference current applied to each of the pixels Ai1 to Ain may be changed according to the value of the average value E. .

Further, in the above display method, the pixel Ai
The reference voltage or the reference current applied to each of the pixels Ai1 to Ain during the period of detecting the maximum value Bi of the signal level of the image information input to 1 to Ain is expressed by the following expression. It may be obtained at the key level.

Further, in the above display method, the pixel Ai
The period for detecting the maximum value Bi of the signal level of the image information input to 1 to Ain may be one field or one frame period.

Thus, in one field or one frame period, the repetition frequency of line-sequential scanning, that is, the driving frequency is 50 Hz or more at which humans do not feel flickering, so that display according to human visual characteristics is performed. This has the effect that it can be performed.

As another display method, the maximum value Bi of the signal level of the image information input to the pixels Ai1 to Ain simultaneously selected at a certain moment is detected, and the pixel Ai1 is detected.
The signal level F of image information to be input to .about.Ain is expressed by the following equation: F = the maximum expressible gradation level of the display panel / the maximum value B
i.

As a result, the gradation range of the display panel can be adjusted according to the image information, so that the image can be displayed in a wider gradation range, and as a result, the display quality of the displayed image is improved. The effect that it can be made to play is produced.

The display device to which the display method of the present invention is applied includes, for example, m (m is an integer of 2 or more) in the first direction,
A display panel in which n (n is an integer of 2 or more) elements are two-dimensionally arranged in a second direction orthogonal to the first direction;
Each element in the display panel is represented by a pixel Aij (i = 1, 2, 2).
, M, j = 1, 2,..., N) and a plurality of pixels Aa1, Aa2,
, Aan (a = 1, 2,..., M) are simultaneously selected, and the selected pixel is sequentially selected in the first direction to drive the display panel so as to display an image. And the pixels Aa1, Aa2,
, Aan are selected for the pixels Aa1, Aa2,.
To change according to the image information input to Aan,
And a control circuit for generating a control signal for controlling the drive circuit.

Therefore, the gradation display characteristics of the display panel can be optimized according to the image information (video signal).
As a result, the gradation expression capability of the display panel can be brought out, so that the display quality of the displayed image can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a matrix type display using an organic EL panel according to an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a control circuit that generates a control signal for driving and controlling the matrix type display shown in FIG.

FIG. 3 is a schematic configuration diagram of an organic EL panel provided in the matrix type display shown in FIG.

FIG. 4 shows an organic EL constituting the organic EL panel shown in FIG.
4A and 4B show a device, wherein FIG. 4A is a schematic sectional view, and FIG. 4B is a structural formula of a light emitting layer shown in FIG.

FIG. 5 is a structural formula of a hole transport layer of the organic EL device shown in FIG.

FIG. 6 is a structural formula of a light emitting layer and an electron transport layer of the organic EL device shown in FIG.

7 is a graph showing voltage-current characteristics of the organic EL device shown in FIG.

8 is a graph showing current-emission luminance characteristics of the organic EL device shown in FIG.

FIG. 9 is an explanatory diagram showing a driving method of the organic EL panel shown in FIG.

FIG. 10 is a graph showing a maximum value and a minimum value of a gradation level of a standard image in scan electrode units.

FIG. 11 is a schematic configuration diagram of a matrix type display using an FED panel according to another embodiment of the present invention.

12 is a schematic configuration diagram of a control circuit that generates a control signal for driving and controlling the matrix display shown in FIG.

13 (a) to 13 (c) are a cross-sectional view and a plan view of an FED panel provided in the matrix type display shown in FIG.

FIG. 14 is a schematic configuration diagram of a matrix type display using an organic EL panel according to another embodiment of the present invention.

15 is a schematic configuration diagram of a control circuit that generates a control signal for driving and controlling the matrix display shown in FIG.

FIG. 16 is a schematic configuration diagram of an organic EL element.

17A and 17B show an FED element, wherein FIG. 17A is a plan view and FIG.
FIG. 3A is a cross-sectional view taken along line ZZ ′ of FIG.

18 is a schematic configuration diagram of a conventional matrix type display using the FED element shown in FIG.

FIG. 19 is an explanatory diagram showing a conventional driving method of a matrix type display using an organic EL element.

[Explanation of symbols]

 Reference Signs List 1 glass substrate 2 data electrode 3 scan electrode 4 organic thin film 11 organic EL panel (display panel) 12 scan side drive circuit (drive circuit) 13 data side drive circuit (drive circuit) 14 field memory 15 data hold / timing control circuit 16 constant Current circuit 17 Control circuit 18 Comparator 19 Line memory 20 Computing unit 31 FED panel (Display panel) 32 Scanning side drive circuit (Drive circuit) 33 Data side drive circuit (Drive circuit) 34 Line memory 35 Data hold / timing control circuit 36 Constant current circuit 38 Control circuit 39 Comparator 40 Field memory 41 Line memory 42 Computing device 71 Data side drive circuit (drive circuit) 72 Line memory 73 Gray level conversion circuit 74 Data hold / timing control circuit 75 Constant current circuit 76 Control circuit 77較器 78 first computing unit 79 the second computing unit

Claims (9)

[Claims] (1) m pieces (m is an integer of 2 or more) in a first direction;
Each element in the display panel in which n (n is an integer of 2 or more) elements are two-dimensionally arranged in a second direction orthogonal to the first direction is referred to as a pixel Aij (i = 1, 2,...) m, j = 1,
2,..., N) and a plurality of pixels Aa1, Aa2,..., Aan arranged in the second direction among the pixels Aij
(A = 1, 2,..., M) at the same time, and the selected pixels Aa1, Aa2,.
, Aan, Aa1, Aa2,..., Aan, the selection time width of the pixels Aa1, Aa2,.
2,..., A display method characterized by changing according to image information input to Aan. 2. A pixel Ai1 selected simultaneously at a certain moment.
Maximum value Bi of signal level of image information input to Ain
Is detected over a certain period of time to obtain an average value A.
2. The display method according to claim 1, wherein a selection time width Wi of a1, Aa2,..., Aan in the first direction is obtained by the following equation: Wi = maximum value Bi / average value A. 3. A reference voltage or a reference current applied to each of the pixels Ai1 to Ain is changed to a value of the average value A during a period of detecting a maximum value Bi of signal levels of image information input to the pixels Ai1 to Ain. 3. The display method according to claim 2, wherein the display method is changed in response to the change. 4. A pixel Ai1 selected simultaneously at a certain moment.
Maximum value Bi of signal level of image information input to Ain
Is detected for a certain period of time, the maximum value Bi is compared with a preset reference value C (an arbitrary integer), and when the maximum value Bi is larger than the reference value C, the maximum value Bi is When the maximum value Bi is equal to or smaller than the reference value C, the reference value C is stored as the calculation value Di, and the average value E of the calculation values Di stored during the certain period is obtained. 2. The display method according to claim 1, wherein a selection time width Wi for selecting the pixels Ai1 to Ain in the first direction is obtained by the following equation: Wi = calculated value Di / average value E. 5. A reference voltage or a reference current applied to each of the pixels Ai1 to Ain during a period for detecting the maximum value Bi of the signal level of the image information input to the pixels Ai1 to Ain to the value of the average value E. 5. The display method according to claim 4, wherein the display method is changed in accordance with the change. 6. A reference voltage or a reference current applied to each of the pixels Ai1 to Ain during a period for detecting the maximum value Bi of the signal level of the image information input to the pixels Ai1 to Ain is represented by the following formula. The display method according to claim 2, wherein the value is obtained at a maximum reproducible gradation level of the panel. 7. The period for detecting the maximum value Bi of the signal level of the image information input to the pixels Ai1 to Ain is one field or one frame period. Display method described in. 8. A pixel Ai1 selected simultaneously at a certain moment.
The maximum value Bi of the signal level of the image information input to Ain is detected, and the signal level F of the image information input to the pixels Ai1 to Ain is expressed by the following equation: F = the maximum expressible gradation level / maximum value of the display panel B
2. The display method according to claim 1, wherein the value is obtained by i. 9. A method according to claim 1, wherein m (m is an integer of 2 or more) in a first direction;
A display panel in which n (n is an integer of 2 or more) elements are two-dimensionally arranged in a second direction orthogonal to the first direction, and each element in the display panel is defined as a pixel Aij (i = 1 , 2,
, M, j = 1, 2,..., N) and a plurality of pixels Aa1, Aa2,
, Aan (a = 1, 2,..., M) are simultaneously selected, and the selected pixel is sequentially selected in the first direction to drive the display panel so as to display an image. , Aan in the display panel, and a control signal for controlling the driving circuit so as to change a selection period of the pixels Aa1, Aa2,..., Aan according to image information input to the pixels Aa1, Aa2,. And a control circuit for generating the data.