JP3696360B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP3696360B2
JP3696360B2 JP03481997A JP3481997A JP3696360B2 JP 3696360 B2 JP3696360 B2 JP 3696360B2 JP 03481997 A JP03481997 A JP 03481997A JP 3481997 A JP3481997 A JP 3481997A JP 3696360 B2 JP3696360 B2 JP 3696360B2
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Japan
Prior art keywords
chip
adhesive film
bump
electrode pad
electrode pads
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Expired - Fee Related
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JP03481997A
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Japanese (ja)
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JPH10233406A (en
Inventor
和孝 柴田
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Description

【０００１】
【発明の属する技術分野】
本発明は，回路素子の多数個を形成したＩＣチップを，別のＩＣチップ又は回路基板等に対して，これらにおける各電極パッドの相互間を電気的に接続した状態で，ボンディング（接合）して成る半導体装置に関するものである。
【０００２】
【従来の技術】
従来，ＩＣチップを，別のＩＣチップ又は回路基板等に対して，これらにおける各電極パッドの相互間を電気的に接続した状態で，ボンディングするに際しては，前記ＩＣチップに形成した各電極パッドと，前記別のＩＣチップ又は回路基板等に形成した各電極パッドのうちいずれか一方バンプを設けて，このバンプを，他方の電極パッドに対して圧着するか，両方の電極パッドの各々にバンプを設けて，このバンプ同士を圧着すると言う方法を採用している。
【０００３】
【発明が解決しようとする課題】
しかし，この方法において，ＩＣチップと別のＩＣチップ又は回路基板等とのうちいずれか一方の電極パッドに設けたバンプを他方の電極パッドに対して圧着するか，又は，一方の電極パッドに設けたバンプを他方の電極パッドに設けたバンプに対して圧着するには，比較的大きい押圧力を加えなければならず，ＩＣチップ，及び電極パッド並びにバンプに欠け又は割れが発生するおそれが大きいから，不良品の発生率が高いと言う問題があった。
【０００４】
本発明は，これらの問題を解消することを技術的課題とするものである。
【０００５】
【課題を解決するための手段】
この技術的課題を達成するため本発明は，
「第１ＩＣチップと，この第１ＩＣチップの表面側に当該第１ＩＣチップの周囲が突出するように配設した小さい形状の第２ＩＣチップと，前記第１ＩＣチップの周囲に配設した複数本のリード端子とから成り，前記第１ＩＣチップにおける表面のうち前記第２ＩＣチップより外側の部分に，前記各リード端子との間をワイヤボンディングするためのワイヤボンディングパッドの複数個を周囲方向に並べて設ける一方，前記第２ＩＣチップを，その片面に形成した電極パッドを前記第１ＩＣチップの表面に形成した電極パッドに対面するようにし，前記第２ＩＣチップにおける各電極パッド及び前記第１ＩＣチップにおける各電極パッドのうちいずれか一方にバンプを，電極パッドから突出するように設け，前記第２ＩＣチップを，前記第１ＩＣチップに対して，その間に介挿した接着フィルムにて接着する一方，前記接着フィルムのうち前記バンプに該当する部分に，当該接着フィルムを貫通する小孔の多数個を，当該小孔のうち複数個が前記バンプの箇所に位置するようなピッチ間隔で穿設し，この各小孔内に，導電粒子の粉末を互いに接触するように充填する。」
と言う構成にした。
【０００６】
【発明の作用・効果】
前記したように構成したことにより，第２ＩＣチップを，これよりも大きくて，且つ，リード端子に対してワイヤボンディングにて電気的に接続される第１ＩＣチップに対して，接着フィルムを介して強固にボンディングすることができると同時に，この接着フィルムに穿設の小孔に充填した導電粒子の粉末を介して電気的に接続できるのである。
【０００７】
このように，第２ＩＣチップを，これよりも大きくて，且つ，リード端子に対してワイヤボンディングにて電気的に接続される第１ＩＣチップに対して，その間に介挿した接着フィルムにて接着する場合において，前記接着フィルムに導電粒子の粉末を混入することにより，この導電粒子の粉末により電気的に接続することができると考えられる。
【０００８】
しかし，この接着フィルムに混入した導電粒子の粉末により電気的に接続するためには，接着フィルムをバンプにて大きく圧縮変形することにより，各導電粒子が互いに接触するようにしなければならないが，接着フィルムをバンプにて圧縮変形するとき，これに混入されている導電粒子が，バンプと電極パッドとの間の部分を逃げることになるから，電気的接続に不良が発生すると言うように，電気的接続の確実性が低下することになる。
【０００９】
これに対して，本発明のように，前記接着フィルムにこれを貫通する小孔を多数個を穿設し，この各小孔内に，導電粒子の粉末を互いに接触するように充填すると言う構成にすると，前記接着フィルムを大きく圧縮変形することなく，接着フィルムに穿設の小孔に充填した導電粒子の粉末を介して電気的に接続することができるのである。
【００１０】
従って，本発明によると，第２ＩＣチップを，これよりも大きくて，且つ，リード端子に対してワイヤボンディングにて電気的に接続される第１ＩＣチップに対して，その電極パッド同士を確実に電気的に接続した状態のもとで，強固にボンディングすることができるものでありながら，前記第２ＩＣチップを，前記第１ＩＣチップに対して，その間に接着フィルムを接着するだけで良いから，ボンディングの工程が簡単になり，これに要するコストを大幅に低減できるのであり，しかも，前記の押圧は，従来におけるバンプ接合のよりも遙かに軽いから，ＩＣチップに欠け又は割れが発生することを大幅に低減できると言う効果を有する。
【００１１】
【発明の実施の形態】
以下，本発明の実施の形態を図面について説明する。
【００１２】
図１〜図６において，符号１は，矩形状のチップマウント部１ａと，このチップマウント部１ａにおける四つの各辺から外向きに延びる複数本のリード端子１ｂとを備えたリードフレームを示す。
【００１３】
また，符号２は，前記リードフレーム１におけるチップマウント部１ａに対してダイボンディングされる第１ＩＣチップを示し，この第１ＩＣチップ２の上面には，図示しない能動素子又は受動素子等のような回路素子の多数個が形成されていると共に，その周囲，つまり，後述する第２ＩＣチップ３より外側の部分にワイヤボンディングパッド２ａの多数個が周囲方向に並べて設けられ，更に，その内側に後述する第２ＩＣチップ３に対する接続用の電極パッド２ｂの多数個が形成されている。また，この第１ＩＣチップ２の上面には，前記各ワイヤボンディングパッド２ａ及び各電極パッド２ｂの部分を除く部分に，絶縁性のパシベーション膜２ｃが形成されている。
【００１４】
更にまた，符号３は，前記第１ＩＣチップ２の上面にボンディングされる小さい形状の第２ＩＣチップを示し，この第２ＩＣチップ３における表裏両面のうち少なくとも片面には，前記第１ＩＣチップ２と同様に図示しない能動素子又は受動素子等のような回路素子の多数個が形成されている共に，前記第１ＩＣチップ２における各電極パッド２ｂの各々に対応する箇所ごとに接続用の電極パッド３ａが形成され，この各電極パッド３ａの各々には，バンプ３ｂが，電極パッド３ａから突出するように設けられている。
【００１５】
そして，前記第２ＩＣチップ３を，その回路素子，電極パッド３ａ及びバンプ３ｂを形成した片面を下向きにして，前記第１ＩＣチップ２の上面側に配設し，その間に接着フィルム４を介挿したのち，前記第２ＩＣチップ３を，第１ＩＣチップ２に向かって，その間における前記接着フィルム４を，第２ＩＣチップ３における各バンプ３ｂと第１ＩＣチップ２における各電極パッド２ｂとで挟むように押圧し，この押圧を保持した状態で，加熱等にて前記接着フィルム４を乾燥・硬化することにより，前記第２ＩＣチップ３を，第１ＩＣチップ２に対して，図４に示すように，その間に介挿した接着フィルム４を介してボンディングすることができるのである。
【００１６】
この場合において，前記接着フィルム４に，図５に示すように，前記バンプ３ｂの直径よりも小さい内径にした小孔４ｂの多数個を，当該小孔４ｂのうち複数個が前記バンプ３ｂの箇所に位置するようなピッチ間隔で穿設し，この各小孔４ｂ内に，導電粒子の粉末４ｃを，その導電粒子が互いに接触するような密度で充填するのであり，これにより，第２ＩＣチップ３における各バンプ３ｂと第１ＩＣチップ２における各電極パッド２ｂとの間には，前記接着フィルム４に穿設した多数個の小孔４ｂのうち少なくとも一つ以上の小孔４ｂが位置することになるから，第２ＩＣチップ３における各電極パッド３ａと，第１ＩＣチップ２における各電極パッド２ｂとの相互間を，前記バンプ３ｂと電極パッド２ｂとの間に位置する各小孔４ｂ内に充填した導電粒子の粉末４ｃによって，電気的に確実に接続することができるのである。
【００１７】
このようにして，第１ＩＣチップ２に対して第２ＩＣチップ３をボンディングすると，この第１ＩＣチップ２を，図６に示すように，前記リードフレーム１におけるチップマウント部１ａに対してダイボンディングし，次いで，この第１ＩＣチップ２における各ワイヤボンディングパッド２ａと，リードフレーム１における各リード端子１ｂとの間を，細い金属線５によるワイヤボンディングにて電気的に接続したのち，これらの全体を，合成樹脂製のパッケージ体６にて密封することにより，密封型の半導体装置とするのである。 なお，前記の説明は，突出する形態のバンプ３ｂを，第２ＩＣチップ３における各電極パッド３ａに設けた場合であったが，これに代えて，突出する形態のバンプ３ｂを，第１ＩＣチップ２における各電極パッド２ｂに設けた構成にしても良いことは言うまでもない。
【図面の簡単な説明】
【図１】 本発明の実施形態を示す分解斜視図である。
【図２】 図１の縦断正面図である。
【図３】 図２の要部拡大図である。
【図４】 第２ＩＣチップを第１ＩＣチップに対してボンディングした状態を示す縦断正面図である。
【図５】 本発明の実施形態に使用する接着フィルムの要部拡大断面図である。
【図６】 密封型半導体装置の縦断正面図である。
【符号の説明】
１ リードフレーム
１ａ チップマウント部
１ｂ リード端子
２ 第１ＩＣチップ
２ａ 第１ＩＣチップのワイヤボンディングパッド
２ｂ 第１ＩＣチップの電極パッド
３ 第２ＩＣチップ
３ａ 第２ＩＣチップの電極パッド
３ｂ バンプ
４ 接着フィルム
４ｂ 小孔
４ｃ 導電粒子の粉末[0001]
BACKGROUND OF THE INVENTION
In the present invention, an IC chip in which a large number of circuit elements are formed is bonded to another IC chip or a circuit board in a state where the electrode pads are electrically connected to each other. The present invention relates to a semiconductor device .
[0002]
[Prior art]
Conventionally, when bonding an IC chip to another IC chip or a circuit board in a state where the respective electrode pads are electrically connected to each other, each electrode pad formed on the IC chip and , Either one of the electrode pads formed on the other IC chip or the circuit board is provided with a bump, and this bump is pressed against the other electrode pad, or the bump is applied to each of both electrode pads. A method is used in which the bumps are crimped together.
[0003]
[Problems to be solved by the invention]
However, in this method, a bump provided on one of the electrode pads of the IC chip and another IC chip or circuit board is pressure-bonded to the other electrode pad, or provided on one electrode pad. In order to crimp the bump on the other electrode pad, a relatively large pressing force must be applied, and the IC chip, the electrode pad, and the bump are likely to be chipped or cracked. There was a problem that the incidence of defective products was high.
[0004]
The present invention has a technical problem to solve these problems.
[0005]
[Means for Solving the Problems]
In order to achieve this technical problem, the present invention
“A first IC chip, a small second IC chip arranged so that the periphery of the first IC chip protrudes from the surface of the first IC chip, and a plurality of leads arranged around the first IC chip. A plurality of wire bonding pads arranged in the peripheral direction on the outer side of the second IC chip on the surface of the first IC chip, the wire bonding pads for wire bonding to the lead terminals, The electrode pad formed on one side of the second IC chip is opposed to the electrode pad formed on the surface of the first IC chip, and each of the electrode pads in the second IC chip and the electrode pads in the first IC chip a bump on one, provided so as to protrude from the electrode pad, the first 2IC chip, the first While adhering to the C chip with an adhesive film interposed therebetween, a large number of small holes penetrating the adhesive film are attached to portions corresponding to the bumps of the adhesive film. A plurality of holes are formed at pitch intervals so as to be located at the bumps , and the small particles are filled with the conductive particle powder so as to be in contact with each other. "
It was made the composition called.
[0006]
[Operation and effect of the invention]
With the above-described configuration, the second IC chip is larger than the second IC chip and is firmly connected to the first IC chip electrically connected to the lead terminal by wire bonding via an adhesive film. At the same time, it can be electrically connected through the conductive particle powder filled in the small holes formed in the adhesive film.
[0007]
In this way, the second IC chip is bonded to the first IC chip which is larger than this and is electrically connected to the lead terminal by wire bonding with an adhesive film interposed therebetween. In some cases, it is considered that the conductive film powder can be electrically connected by mixing the conductive film with the conductive particle powder.
[0008]
However, in order to electrically connect with the conductive particle powder mixed in the adhesive film, the adhesive film must be greatly compressed and deformed by bumps so that the conductive particles come into contact with each other. When the film is compressed and deformed by bumps, the conductive particles mixed in the film escape through the part between the bumps and the electrode pads. The reliability of connection will be reduced.
[0009]
On the other hand, as in the present invention, the adhesive film is provided with a plurality of small holes penetrating the adhesive film, and the conductive particles are filled in the small holes so as to contact each other. In this case, the adhesive film can be electrically connected via the conductive particle powder filled in the small holes formed in the adhesive film without greatly compressing and deforming the adhesive film.
[0010]
Therefore, according to the present invention, the electrode pads are reliably connected to the first IC chip which is larger than the second IC chip and is electrically connected to the lead terminals by wire bonding. The second IC chip can be bonded firmly to the first IC chip while it can be firmly bonded under the condition of being connected to the first IC chip. The process becomes simple and the cost required for this can be greatly reduced. Moreover, since the above-mentioned pressing is much lighter than the conventional bump bonding, the occurrence of chipping or cracking in the IC chip is greatly reduced. It has an effect that it can be reduced.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0012]
1 to 6, reference numeral 1 denotes a lead frame including a rectangular chip mount portion 1a and a plurality of lead terminals 1b extending outward from the four sides of the chip mount portion 1a.
[0013]
Reference numeral 2 denotes a first IC chip which is die-bonded to the chip mount portion 1a in the lead frame 1. On the upper surface of the first IC chip 2, a circuit such as an active element or a passive element (not shown) is provided. A large number of elements are formed, and a large number of wire bonding pads 2a are arranged side by side in the periphery, that is, outside the second IC chip 3 to be described later. A large number of electrode pads 2b for connection to the 2IC chip 3 are formed. In addition, an insulating passivation film 2c is formed on the upper surface of the first IC chip 2 except for the portions of the wire bonding pads 2a and the electrode pads 2b.
[0014]
Further, reference numeral 3 denotes a small second IC chip bonded to the upper surface of the first IC chip 2. At least one of the front and back surfaces of the second IC chip 3 is similar to the first IC chip 2. A large number of circuit elements such as active elements or passive elements (not shown) are formed, and electrode pads 3a for connection are formed at locations corresponding to the electrode pads 2b in the first IC chip 2. Each of the electrode pads 3a is provided with a bump 3b protruding from the electrode pad 3a.
[0015]
Then, the second IC chip 3 is disposed on the upper surface side of the first IC chip 2 with the circuit element, the electrode pad 3a and the bump 3b formed on one side, and the adhesive film 4 is interposed therebetween. Thereafter, the second IC chip 3 is pressed toward the first IC chip 2 so that the adhesive film 4 therebetween is sandwiched between the bumps 3b of the second IC chip 3 and the electrode pads 2b of the first IC chip 2. In the state where the pressure is held, the adhesive film 4 is dried and cured by heating or the like, so that the second IC chip 3 is interposed between the first IC chip 2 and the first IC chip 2 as shown in FIG. Bonding can be performed via the inserted adhesive film 4.
[0016]
In this case, as shown in FIG. 5, a plurality of small holes 4b having an inner diameter smaller than the diameter of the bump 3b are formed on the adhesive film 4, and a plurality of small holes 4b are located at the positions of the bumps 3b. drilled at a pitch interval as located, in the respective small holes 4b, and powder 4c of the conductive particles, and of being filled with a density such that the conductive particles are in contact with each other, thereby, the 2IC chip 3 Between each of the bumps 3b and the electrode pads 2b of the first IC chip 2, at least one of the small holes 4b formed in the adhesive film 4 is positioned. from each electrode pad 3a in the 2IC chip 3, the mutual between the electrode pads 2b in the 1IC chip 2, in each small hole 4b which is located between the bump 3b and the electrode pads 2b By powder 4c Hama and conductive particles, it is possible to reliably electrically connected.
[0017]
When the second IC chip 3 is bonded to the first IC chip 2 in this way, the first IC chip 2 is die-bonded to the chip mount portion 1a in the lead frame 1, as shown in FIG. Next, each wire bonding pad 2a in the first IC chip 2 and each lead terminal 1b in the lead frame 1 are electrically connected by wire bonding using a thin metal wire 5, and then the whole is synthesized. By sealing with a package body 6 made of resin, a sealed semiconductor device is obtained. In the above description, the protruding bump 3b is provided on each electrode pad 3a of the second IC chip 3. Instead, the protruding bump 3b is replaced with the first IC chip 2. Needless to say, it may be configured to be provided on each electrode pad 2b.
[Brief description of the drawings]
FIG. 1 is an exploded perspective view showing an embodiment of the present invention.
FIG. 2 is a longitudinal front view of FIG. 1;
FIG. 3 is an enlarged view of a main part of FIG.
FIG. 4 is a longitudinal front view showing a state where a second IC chip is bonded to the first IC chip.
FIG. 5 is an enlarged cross-sectional view of a main part of an adhesive film used in an embodiment of the present invention.
FIG. 6 is a longitudinal front view of a sealed semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Lead frame 1a Chip mount part 1b Lead terminal 2 1st IC chip 2a Wire bonding pad of 1st IC chip 2b Electrode pad of 1st IC chip 3 2nd IC chip 3a Electrode pad of 2nd IC chip 3b Bump 4 Adhesive film 4b Small hole 4c Conductivity Particle powder

Claims (1)

第１ＩＣチップと，この第１ＩＣチップの表面側に当該第１ＩＣチップの周囲が突出するように配設した小さい形状の第２ＩＣチップと，前記第１ＩＣチップの周囲に配設した複数本のリード端子とから成り，前記第１ＩＣチップにおける表面のうち前記第２ＩＣチップより外側の部分に，前記各リード端子との間をワイヤボンディングするためのワイヤボンディングパッドの複数個を周囲方向に並べて設ける一方，前記第２ＩＣチップを，その片面に形成した電極パッドを前記第１ＩＣチップの表面に形成した電極パッドに対面するようにし，前記第２ＩＣチップにおける各電極パッド及び前記第１ＩＣチップにおける各電極パッドのうちいずれか一方にバンプを，電極パッドから突出するように設け，前記第２ＩＣチップを，前記第１ＩＣチップに対して，その間に介挿した接着フィルムにて接着する一方，前記接着フィルムのうち前記バンプに該当する部分に，当該接着フィルムを貫通する小孔の多数個を，当該小孔のうち複数個が前記バンプの箇所に位置するようなピッチ間隔で穿設し，この各小孔内に，導電粒子の粉末を互いに接触するように充填したことを特徴とする半導体装置。A first IC chip, a small second IC chip arranged so that the periphery of the first IC chip protrudes on the surface side of the first IC chip, and a plurality of lead terminals arranged around the first IC chip A plurality of wire bonding pads for wire bonding between the lead terminals on the outer surface of the second IC chip on the outer surface of the first IC chip. The electrode pad formed on one side of the second IC chip faces the electrode pad formed on the surface of the first IC chip, and any one of the electrode pads in the second IC chip and the electrode pads in the first IC chip while the bump or, provided so as to protrude from the electrode pad, the first 2IC chip, the first 1I The chip is bonded to the chip with an adhesive film interposed therebetween, and a plurality of small holes penetrating the adhesive film are formed in a portion corresponding to the bump in the adhesive film. A semiconductor device characterized in that a plurality of holes are formed at a pitch interval so as to be located at the location of the bumps , and each small hole is filled with powder of conductive particles so as to contact each other.
JP03481997A 1997-02-19 1997-02-19 Semiconductor device Expired - Fee Related JP3696360B2 (en)

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