JP3543254B2 - Structure of a semiconductor device having a plurality of ic chips - Google Patents

Structure of a semiconductor device having a plurality of ic chips Download PDF

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JP3543254B2
JP3543254B2 JP15991297A JP15991297A JP3543254B2 JP 3543254 B2 JP3543254 B2 JP 3543254B2 JP 15991297 A JP15991297 A JP 15991297A JP 15991297 A JP15991297 A JP 15991297A JP 3543254 B2 JP3543254 B2 JP 3543254B2
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ic chip
barrier metal
electrode pads
opening
portion
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JPH118348A (en
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和孝 柴田
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ローム株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Description

【0001】 [0001]
【発明の属する技術分野】 BACKGROUND OF THE INVENTION
本発明は、複数個のICチップを、その相互間を電気的に接続した状態で一体的に接合した半導体装置の構造に関するものである。 The present invention, a plurality of IC chips, it relates to a structure of a semiconductor device which is integrally joined in a state of electrically connecting the other.
【0002】 [0002]
【従来の技術】 BACKGROUND OF THE INVENTION
従来、二つのICチップを、その相互間を電気的に接続した状態で、一体的に接合するに際しては、前記両ICチップのうち一方のメインICチップに形成した各電極パッド及び前記両ICチップのうち他方のサブICチップに形成した各電極パッドのうちいずれか一方の電極パッドにバンプを設けて、このバンプを、他方の電極パッドに対して圧着すると言う方法を採用している。 Conventionally, the two IC chips, while electrically connecting the mutual, when integrally joined, the electrode pads formed on one of the main IC chip of the two IC chips and the two IC chips and a bump on one of the electrode pads of the respective electrode pads formed on the other sub IC chip provided of, the bumps employs a method called crimping relative to the other electrode pads.
【0003】 [0003]
【発明が解決しようとする課題】 [Problems that the Invention is to Solve
しかし、この方法において、メインICチップとサブICチップとの一体化を、メインICチップの各電極パッド及びサブICチップの各電極パッドのうちいずれか一方の電極パッドに設けたバンプにおける他方の電極パッドへの圧着のみに依存することができず、前記した圧着後において、両ICチップの間に、その両者を一体的に接着するための合成樹脂を充填するようにしなければならないから、両ICチップを一体化することに要するコストが大幅にアップすると言う問題があった。 However, in this method, the integration of the main IC chip and the sub IC chip, the other electrode of bumps provided in one of the electrode pads of the respective electrode pads of each electrode pad and sub IC chip of the main IC chip It can not be dependent only on the bonding to the pad, after crimping described above, between the two IC chips, because must be such to fill the synthetic resin for bonding integrally the both, both IC the cost required for integrating the chip there was a problem to say that significantly up.
【0004】 [0004]
しかも、前記ICチップにおける電極パッドは、一般的に言ってアルミニウム製であるのに対し、バンプは、アルミニウムと異質の金又は半田製であることにより、一方の電極パッドに設けたバンプを、他方の電極パッドに対して圧着することの確実性が低く、その確実性を確保するためには、その押圧力を可成り強くしなければならず、このバンプを他方の電極パッドに圧着するときに、この他方の電極パッドに対して大きなダメージを及ぼすことになるから、電気的接続の信頼性が低くて、不良品の発生率が高いと言う問題もあった。 Moreover, the electrode pads in the IC chip is generally speaking whereas is made of aluminum, bumps, by aluminum and heterogeneous gold or solder made, a bump provided on one electrode pad, other low reliability of crimping of the electrode pads, in order to ensure the reliability has to strongly become soluble to the pressing force, when crimping the bumps to the other electrode pads since would exert a great damage to the other electrode pad, and low reliability of the electrical connection, problems were called high incidence of defective products.
【0005】 [0005]
本発明は、これらの問題を解消できるようにした半導体装置の構造を提供することを技術的課題とするものである。 The present invention is directed to the technical problem of providing a structure of a semiconductor apparatus which can solve these problems.
【0006】 [0006]
【課題を解決するための手段】 In order to solve the problems]
この技術的課題を達成するため本発明は、 The present invention for achieving this technical problem,
「少なくとも上面に回路素子、この回路素子に対する電極パッドを形成したメインICチップと、少なくとも片面に回路素子とこの回路素子に対する電極パッドとを形成したサブICチップとから成り、前記サブICチップを、前記メインICチップの上面側に、当該サブICチップにおける回路素子及び電極パッドが前記メインICチップにおける回路素子及び電極パッドに対面するように下向きにして配設し、前記メインICチップにおける電極パッド及びサブICチップにおける電極パッドのうち一方の電極パッドにバンプを設け、前記メインICチップにおける電極パッド及びサブICチップにおける電極パッドのうち他方の電極パッドが設けられる側のICチップに、当該ICチップにおける回路素子及び前記他方の電極パッドを "At least the upper surface to the circuit element, and the main IC chip forming the electrode pads for the circuit element consists of a sub-IC chip forming the electrode pads for the circuit element and the circuit element on at least one surface, the sub-IC chip, the upper surface side of the main IC chip, is disposed facing downward so that the circuit element and the electrode pads in the sub IC chip faces the circuit element and the electrode pad in the main IC chip, and the electrode pads in the main IC chip bumps provided on one electrode pad of the electrode pads in the sub-IC chip, on the side of the IC chip and the other electrode pads provided among the electrode pads in the electrode pad and the sub IC chip in the main IC chip, in the IC chip the circuit element and the other electrode pads う保護膜を形成し、この保護膜のうち前記他方の電極パッドを覆う部分に、当該電極パッドの周囲に保護膜の電極パッドに対する重なり部を残して開口部を設け、前記他方の電極パッドのうち前記開口部内の部分に、バリアメタルを、当該バリアメタルの周囲が前記保護膜のうち前記開口部の周囲縁の部分に重なるように形成して、前記バリアメタルにおける上面のうち前記開口部の部分に前記バンプが嵌まる凹所を設け、更に、前記両ICチップの相互間を、その間に介挿した導電粒子混入の接着フィルムにて、前記バンプが当該接着フィルムを前記バリアメタルに対して圧縮変形するようにして接着する。」 Cormorants protective film is formed, in the portion covering the other electrode pads of the protective film, an opening is provided, leaving the overlapped portion with respect to the electrode pads of the protective film around the electrode pad, the other electrode pads the portion a of the said opening, a barrier metal, and around the barrier metal is formed so as to overlap the portion of the peripheral edge of said opening of said protective layer, of the opening of the top surface of the barrier metal the bump fits recess provided in a portion, further, a mutual of both IC chip, by an adhesive film of conductive particles mixed with interposed therebetween, the bump is the adhesive film to the barrier metal to adhere so as to be compressed and deformed. "
と言う構成にした。 It was constructed to say.
【0007】 [0007]
【発明の作用・効果】 [Operation and effect of the invention]
このように構成することにより、両ICチップを、その間に介挿した接着フィルムにて強固に一体化することができる一方、前記接着フィルムを、一方の電極パッドに設けたバンプが他方の電極パッドに設けたバリアメタルに対して圧縮変形することにより、この接着フィルムに混入されている導電粒子が、このバンプと、他方の電極パッドの表面に形成されているバリアメタルとの間に挟まれることになり、しかも、この導電粒子が前記バンプとバリアメタルとの間から横方向に逃げるのを、前記バリアメタルの上面に設けられる凹所にて阻止でき、換言すると、前記バリアメタルの上面における凹所内に、多くの導電粒子を確保することができるから、前記接着フィルムへの導電粒子の混入量を多くすることなく、メインICチップにお With this configuration, the two IC chips, while it is possible to firmly integrated by an adhesive film interposed therebetween, the adhesive film, the bump and the other electrode pads provided on one electrode pad the by compression deformation to the barrier metal provided, the conductive particles are mixed into the adhesive film is sandwiched between the bump, the barrier metal formed on the surface of the other electrode pads to be, moreover, the conductive particles from escaping laterally from between the bump and the barrier metal, can prevent at recesses provided on the upper surface of the barrier metal, in other words, concave on the upper surface of the barrier metal a house, because it is possible to secure a large number of conductive particles, without increasing the mixing amount of the conductive particles into the adhesive film, our main IC chip る各電極パッドと、サブICチップにおける各電極パッドとの相互間を電気的に確実に接続することができるのである。 And the electrode pads that, it is possible to reliably electrically connect the mutually between each of the electrode pads in the sub-IC chip.
【0008】 [0008]
しかも、前記一方の電極パッドに設けたバンプが他方の電極パッドに対してダメージを及ぼすことを、この他方の電極パッドの表面に形成されているバリアメタルによって確実に低減できるのである。 Moreover, that the bump provided on said one electrode pad exerts damage to the other electrode pad is able reliably reduced by the barrier metal formed on the surface of the other electrode pads.
従って、本発明によると、メインICチップとサブICチップとを、その間に接着フィルムを介挿したのち押圧するだけで、その相互間を電気的に接続した状態で簡単に一体化することができる一方、その相互間に電気的な接続に際して、電極パッドに対して及ぼすダメージが小さいと共に、電気的接続の信頼性を高くて、不良品の発生率が低いから、前記一体化が簡単にできることと相俟って、製造コストを大幅に低減できる効果を有する。 Therefore, according to the present invention, a main IC chip and the sub IC chip, just pressed After interposed the adhesive film between them, it can be easily integrated in a state of electrical connection between the mutual on the other hand, when electrical connection between the mutually with damage on the electrode pad is small, and high reliability of electrical connection, because there is a lower incidence of defective products, and that the integration can be easily Coupled with, has an effect that can greatly reduce the production cost.
【0009】 [0009]
【発明の実施の形態】 DETAILED DESCRIPTION OF THE INVENTION
以下、本発明の実施の形態を、一つのパッケージ体にて二つのICチップを密封した形式の半導体装置に適用した場合の図面(図1〜図8)について説明する。 Hereinafter, the embodiments of the present invention, the drawing is applied to the semiconductor device of the type sealed two IC chips in a single package body (FIGS. 1-8) will be described.
この図において、符号1は、矩形状のチップマウント部1aと、このチップマウント部1aにおける四つの各辺から外向きに延びる複数本のリード端子1bとを備えたリードフレームを示す。 In this figure, reference numeral 1 denotes a rectangular chip mounting portion 1a, the lead frame comprising a plurality of lead terminals 1b extending outwardly from the four sides of the chip mounting portion 1a.
【0010】 [0010]
また、符号2は、前記リードフレーム1におけるチップマウント部1aに対してダイボンディングされるメインICチップを示し、このメインICチップ2の上面には、図示しない能動素子又は受動素子等のような回路素子の多数個が形成されている共に、その周囲にワイヤボンディング用電極パッド2aの多数個が、その内側に後述するサブICチップ3に対する接続用の電極パッド2bの多数個が形成されている。 Further, reference numeral 2 denotes a main IC chip is die-bonded to the chip mounting portion 1a of the lead frame 1, on the upper surface of the main IC chip 2, the circuit such as an active element or a passive element (not shown) both the large number of elements are formed, a large number of wire bonding electrode pads 2a around it, a large number of electrode pads 2b for connection is formed for the sub IC chip 3 to be described later on the inside .
【0011】 [0011]
この場合において、前記メインICチップ2の上面には、図3に示すように、当該上面に形成されている各種の回路素子を覆う保護膜2cが、前記各電極パッド2bの部分に開口部を設けて形成され、更に、前記各電極パッド2bの部分には、バリアメタル2eが、当該電極パッド2bのうち前記保護膜2cにおける開口部内の部分及び前記保護膜2cのうち開口部の周囲縁の部分を覆うように形成されている。 In this case, the upper surface of the main IC chip 2, as shown in FIG. 3, the protective film 2c which covers the various circuit elements are formed on the upper surface, an opening in a portion of the respective electrode pads 2b is formed by providing, further wherein the portion of each electrode pad 2b, a barrier metal 2e is the peripheral edge of the opening of the part and the protective layer 2c in the opening in the protective film 2c of the electrode pads 2b It is formed so as to cover the portion.
つまり、このように構成することにより、前記バリアメタル2eの上面に、前記保護膜2cの膜厚さと略等しい深さの凹所を形成することができる。 That is, by this configuration, the upper surface of the barrier metal 2e, it is possible to form a recess in the film thickness is substantially equal to the depth of the protective film 2c.
なお、このバリアメタル2eは、例えば、チタンを下層としタングステンを上層とするか、クロムを下層とし銀を上層とする二層構造に構成されている。 It should be noted that the barrier metal 2e, for example, either an upper layer of tungsten to titanium and lower, and a silver and chromium as a lower layer in a two-layer structure in which an upper layer.
【0012】 [0012]
更にまた、符号3は、前記メインICチップ2の上面に一体化されるサブICチップを示し、このサブICチップ3における表裏両面のうち少なくとも片面には、前記メインICチップ2と同様に図示しない能動素子又は受動素子等のような回路素子の多数個が形成されている共に、前記メインICチップ2における各電極パッド2bの各々に対応する箇所ごとに接続用の電極パッド3aが形成されている。 Furthermore, reference numeral 3 denotes a sub-IC chip which is integrated into the upper surface of the main IC chip 2, at least one surface of both sides in the sub-IC chip 3, not shown in the same manner as the main IC chip 2 both large number of circuit elements, such as active elements or passive elements are formed, the electrode pads 3a for connection for each portion corresponding to each of the electrode pads 2b in the main IC chip 2 is formed .
【0013】 [0013]
そして、前記サブICチップ3を、前記メインICチップ2に対して、これらにおける電極パッド2b,3bの相互間を電気的に接続した状態で一体化するに際しては、前記サブICチップ3における各電極パッド3aの各々に、金又は半田等によるバンプ3bを設けるのである。 Then, the sub-IC chip 3, wherein the main IC chip 2, when the integrated electrode pad 2b in these, 3b among each other while electrically connected, the electrodes in the sub-IC chip 3 to each of the pads 3a, it is of providing a bump 3b by gold or solder.
次いで、前記サブICチップ3を、その回路素子、電極パッド3a及びバンプ3bを形成した片面を下向きにして、前記メインICチップ2の上面側に配設し、その間に導電粒子を混入した接着フィルム4を介挿したのち、前記サブICチップ3を、メインICチップ2に向かって、その間における前記接着フィルム4を、図5に示すように、各バンプ3bにより圧縮変形するように押圧し、この押圧を保持した状態で、加熱等にて前記接着フィルム4を乾燥・硬化することにより、前記サブICチップ3を、メインICチップ2に対して、その間に介挿した接着フィルム4により確実に且つ強固に一体化できるのである。 Then, the adhesive film in which the sub-IC chip 3, the circuit elements, and one side forming an electrode pad 3a and the bumps 3b downwardly, and disposed on the upper surface side of the main IC chip 2, was mixed with conductive particles therebetween 4 After interposed and the sub IC chip 3 toward the main IC chip 2, the adhesive film 4 in between them, as shown in FIG. 5, pressed to compressive deformation by the bumps 3b, this pressing while holding the, by drying and curing the adhesive film 4 in a heating or the like, the sub-IC chip 3, the main IC chip 2, reliably and with adhesive film 4 interposed therebetween it can be firmly integrated.
【0014】 [0014]
また、前記サブICチップ3における各バンプ3bが、前記接着フィルム4を、圧縮変形することにより、この接着フィルム4に混入されている導電粒子が、この各バンプ3bと、メインICチップ2における各電極パッド2bの表面に形成したバリアメタル2eとの間に挟まれることにより、サブICチップ3における各電極パッド3aと、メインICチップ2における各電極パッド2bとの相互間を電気的に接続することができるのであり、前記した押圧のときにおいて、サブICチップ3における各電極パッド3aに設けたバンプ3bが、メインICチップ2における各電極パッド2bに対してダメージを及ぼすことを、この各電極パッド2bの表面に形成されているバリアメタル2dによって確実に低減できるのである。 Each bump 3b in the sub IC chip 3, the adhesive film 4, by compression deformation, the conductive particles are mixed into the adhesive film 4, and the respective bump 3b, each of the main IC chip 2 by being sandwiched between the barrier metal 2e formed on the surface of the electrode pad 2b, and the electrode pads 3a in the sub-IC chip 3 is electrically connected to each other with the respective electrode pads 2b in the main IC chip 2 it is than it is, at the time of pressing mentioned above, the bump 3b provided to each electrode pad 3a in the sub-IC chip 3, that exerts damage to the electrode pads 2b in the main IC chip 2, the respective electrodes it can be reliably reduced by the barrier metal 2d formed on the surface of the pad 2b.
【0015】 [0015]
この場合において、図示のように、メインICチップ2の上面における保護膜2cのうち各電極パッド2bを覆う部分に、当該電極パッド2bの周囲に保護膜2cの電極パッド2bに対する重なり部を残して開口部を設ける一方、バリアメタル2dを、電極パッド2bのうち前記保護膜2cにおける開口部内の部分及び前記保護膜2cのうち開口部の周囲縁の部分を覆うように形成することにより、このバリアメタル2dの上面には、前記バンプ3bが嵌まる凹所が形成されることになる。 In this case, as shown, the portion covering the electrode pads 2b of the protective film 2c on the upper surface of the main IC chip 2, leaving the overlapped portion with respect to the electrode pads 2b of the protective film 2c around the electrode pad 2b while providing the opening, a barrier metal 2d, by forming so as to cover the portion of the peripheral edge of the opening of the part and the protective layer 2c in the opening in the protective film 2c of the electrode pad 2b, the barrier on the upper surface of the metal 2d, so that the bump 3b is full recess fitted is formed.
【0016】 [0016]
これにより、前記接着フィルム4がバンプ3bによって前記バリアメタル2dにおける凹所内に向かって圧縮変形されるときに、この接着フィルム4に混入した導電粒子が前記バンプ3bとバリアメタル2dとの間から横方向に逃げるのを、前記バリアメタル2dの上面に形成される凹所にて阻止でき、換言すると、前記バリアメタル2dの上面における凹所内に、多くの導電粒子を確保することができるから、前記接着フィルム4への導電粒子の混入量を多くすることなく、電気的接続の確実性を向上できるのである。 Thus, the when the adhesive film 4 is compressed and deformed toward the recess in said barrier metal 2d by the bump 3b, the horizontal from between entrained conductive particles to the adhesive film 4 and the bump 3b and the barrier metal 2d from escaping in a direction, the can prevent at recess formed on the upper surface of the barrier metal 2d, in other words, in the recess in the top surface of the barrier metal 2d, because it is possible to secure the number of conductive particles, wherein without increasing the mixing amount of the conductive particles into the adhesive film 4, it can improve the reliability of electrical connection.
【0017】 [0017]
このようにして、メインICチップ2に対してサブICチップ3を一体化すると、このメインICチップ2を、図6に示すように、前記リードフレーム1におけるチップマウント部1aに対してダイボンディング 、次いで、このメインICチップ2における各ワイヤボンディング用電極パッド2aと、リードフレーム1における各リード端子1bとの間を、細い金属線5によるワイヤボンディングにて電気的に接続したのち、これらの全体を、図7に示すように、合成樹脂製のパッケージ体6にて密封し、次いで、図8に示すように、リードフレーム1から切り離したのち、各リード端子1bのうちパッケージ体6から突出する部分を、パッケージ体6の下面の同一平面状に折り曲げることにより、密封型半導体装置の完成品とするのであ Thus, when integrating the sub IC chip 3 to the main IC chip 2, the main IC chip 2, as shown in FIG. 6, and die bonding the chip mounting portion 1a of the lead frame 1 , then each electrode for wire bonding pads 2a in the main IC chip 2, after between each lead terminal 1b of the lead frame 1, and electrically connected by wire bonding using thin metal wires 5 in their entirety the, as shown in FIG. 7, sealed with synthetic resin package body 6 and then, as shown in FIG. 8, after disconnecting from the lead frame 1, projects from the package body 6 of the lead terminals 1b the portion, by bending the lower surface of the same planar package body 6, Nodea to finished sealing type semiconductor device .
【0018】 [0018]
なお、前記の説明は、バンプ3bを、サブICチップ3における各電極パッド3aに設けて、このバンプ3bを、メインICチップ2における各電極パッド2bに設けたバリアメタル2dに対して電気的に接続する場合を示したが、これに代えて、バンプを、メインICチップ2における各電極パッド2bに設けて、このバンプを、サブICチップ3における各電極パッド3aに設けたバリアメタルに対して電気的に接続するように構成にしても良く、また、本発明は、前記のように、メインICチップ2に対して一つのサブICチップ3を一体化することに限らず、メインICチップ2に対して二つのサブICチップ3を一体化する場合にも適用できることは言うまでもない。 Incidentally, the foregoing description, the bumps 3b, provided to each electrode pad 3a in the sub-IC chip 3, the bump 3b, electrically relative to the barrier metal 2d provided on the electrode pads 2b in the main IC chip 2 shows the case of connecting, instead of this, the bumps provided on the respective electrode pads 2b in the main IC chip 2, the bump, the barrier metal provided to each electrode pad 3a in the sub-IC chip 3 may be configured to be electrically connected, also, the present invention is, as described above, not limited to integrating the one sub IC chip 3 to the main IC chip 2, the main IC chip 2 the present invention can be applied when integrating the two sub IC chip 3 against.
【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS
【図1】本発明の実施の形態を示す分解斜視図である。 1 is an exploded perspective view showing an embodiment of the present invention.
【図2】図1の縦断正面図である。 Is a longitudinal front view of FIG. 1;
【図3】図2の要部拡大図である。 FIG. 3 is an enlarged view of an essential part of Figure 2.
【図4】サブICチップをメインICチップに対して一体化した状態を示す縦断正面図である。 4 is a vertical sectional front view showing a state in which integrated sub IC chip to the main IC chip.
【図5】図4の要部拡大図である。 An enlarged view of a main portion of FIG. 5] FIG. 4.
【図6】リードフレームに対してマウントした状態を示す縦断正面図である。 6 is a longitudinal front view showing a state in which the mount to the lead frame.
【図7】全体をパッケージ体に密封した状態を示す縦断正面図である。 7 is a longitudinal sectional front view showing a state in which sealed the whole package body.
【図8】半導体装置の縦断正面図である。 8 is a vertical sectional front view of a semiconductor device.
【符号の説明】 DESCRIPTION OF SYMBOLS
1 リードフレーム1a チップマウント部1b リード端子2 メインICチップ2b 電極パッド2c 保護膜2d バリアメタル3 サブICチップ3a 電極パッド3b バンプ4 接着フィルム5 金属線6 パッケージ体 1 lead frames 1a chip mounting portion 1b lead terminals 2 main IC chip 2b electrode pads 2c protective film 2d barrier metal 3 sub IC chip 3a the electrode pad 3b bumps 4 adhesive film 5 metal wire 6 package body

Claims (1)

  1. 少なくとも上面に回路素子、この回路素子に対する電極パッドを形成したメインICチップと、少なくとも片面に回路素子とこの回路素子に対する電極パッドとを形成したサブICチップとから成り、前記サブICチップを、前記メインICチップの上面側に、当該サブICチップにおける回路素子及び電極パッドが前記メインICチップにおける回路素子及び電極パッドに対面するように下向きにして配設し、前記メインICチップにおける電極パッド及びサブICチップにおける電極パッドのうち一方の電極パッドにバンプを設け、前記メインICチップにおける電極パッド及びサブICチップにおける電極パッドのうち他方の電極パッドが設けられる側のICチップに、当該ICチップにおける回路素子及び前記他方の電極パッドを覆 At least the upper surface to the circuit element, and the main IC chip forming the electrode pads for the circuit element consists of a sub-IC chip forming the electrode pad and the at least one surface to a circuit element for the circuit elements, the sub-IC chip, the on the upper surface of the main IC chip, it is disposed facing downward so that the circuit element and the electrode pads in the sub IC chip faces the circuit element and the electrode pad in the main IC chip, the electrode pads and the sub in the main IC chip bumps provided on one electrode pad of the electrode pads of the IC chip on the side of the IC chip and the other electrode pads provided among the electrode pads in the electrode pad and the sub IC chip in the main IC chip, circuit in said IC chip covering the element and the other electrode pads 保護膜を形成し、この保護膜のうち前記他方の電極パッドを覆う部分に、当該電極パッドの周囲に保護膜の電極パッドに対する重なり部を残して開口部を設け、前記他方の電極パッドのうち前記開口部内の部分に、バリアメタルを、当該バリアメタルの周囲が前記保護膜のうち前記開口部の周囲縁の部分に重なるように形成して、前記バリアメタルにおける上面のうち前記開口部の部分に前記バンプが嵌まる凹所を設け、更に、前記両ICチップの相互間を、その間に介挿した導電粒子混入の接着フィルムにて、前記バンプが当該接着フィルムを前記バリアメタルに対して圧縮変形するようにして接着したことを特徴とする複数のICチップを備えた半導体装置の構造。 The protective film is formed, the portion covering the other electrode pads of the protective film, an opening is provided, leaving the overlapped portion with respect to the electrode pads of the protective film around the electrode pad, among the other electrode pads the portion in the opening, a barrier metal, and around the barrier metal is formed so as to overlap the portion of the peripheral edge of said opening of said protective layer, portions of the opening of the top surface of the barrier metal the bump fits recess provided, further compressing said mutual both IC chip, by an adhesive film of conductive particles mixed with interposed therebetween, the bump is the adhesive film to the barrier metal structure of a semiconductor device having a plurality of IC chips, characterized in that it has adhered as deformed.
JP15991297A 1997-06-17 1997-06-17 Structure of a semiconductor device having a plurality of ic chips Expired - Fee Related JP3543254B2 (en)

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JP15991297A JP3543254B2 (en) 1997-06-17 1997-06-17 Structure of a semiconductor device having a plurality of ic chips

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JP15991297A JP3543254B2 (en) 1997-06-17 1997-06-17 Structure of a semiconductor device having a plurality of ic chips
US09/155,134 US6133637A (en) 1997-01-24 1998-01-22 Semiconductor device having a plurality of semiconductor chips
PCT/JP1998/000281 WO1998033217A1 (en) 1997-01-24 1998-01-22 Semiconductor device and method for manufacturing thereof
KR10-1998-0707403A KR100522223B1 (en) 1997-01-24 1998-01-22 Semiconductor device and method for manufacturing thereof
KR10-2004-7000090A KR100467946B1 (en) 1997-01-24 1998-01-22 Method for manufacturing a semiconductor chip
EP98900725A EP0890989A4 (en) 1997-01-24 1998-01-22 Semiconductor device and method for manufacturing thereof
US09/612,480 US6458609B1 (en) 1997-01-24 2000-07-07 Semiconductor device and method for manufacturing thereof

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US8981574B2 (en) 2012-12-20 2015-03-17 Samsung Electronics Co., Ltd. Semiconductor package

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US4659117A (en) * 1982-08-10 1987-04-21 Iwk Regler Und Kompensatoren Gmbh Flexible coupling for pipes in exhaust systems of motor vehicles
JP2006237280A (en) * 2005-02-25 2006-09-07 Sony Corp Semiconductor device and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8981574B2 (en) 2012-12-20 2015-03-17 Samsung Electronics Co., Ltd. Semiconductor package
US9633973B2 (en) 2012-12-20 2017-04-25 Samsung Electronics Co., Ltd. Semiconductor package

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