JP3686267B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP3686267B2
JP3686267B2 JP30707898A JP30707898A JP3686267B2 JP 3686267 B2 JP3686267 B2 JP 3686267B2 JP 30707898 A JP30707898 A JP 30707898A JP 30707898 A JP30707898 A JP 30707898A JP 3686267 B2 JP3686267 B2 JP 3686267B2
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JP
Japan
Prior art keywords
semiconductor chip
metal plate
chip
insulating adhesive
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP30707898A
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English (en)
Japanese (ja)
Other versions
JP2000133762A5 (https=
JP2000133762A (ja
Inventor
朋子 東野
一成 鈴木
宏明 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP30707898A priority Critical patent/JP3686267B2/ja
Publication of JP2000133762A publication Critical patent/JP2000133762A/ja
Publication of JP2000133762A5 publication Critical patent/JP2000133762A5/ja
Application granted granted Critical
Publication of JP3686267B2 publication Critical patent/JP3686267B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP30707898A 1998-10-28 1998-10-28 半導体装置の製造方法 Expired - Fee Related JP3686267B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30707898A JP3686267B2 (ja) 1998-10-28 1998-10-28 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30707898A JP3686267B2 (ja) 1998-10-28 1998-10-28 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2000133762A JP2000133762A (ja) 2000-05-12
JP2000133762A5 JP2000133762A5 (https=) 2005-02-03
JP3686267B2 true JP3686267B2 (ja) 2005-08-24

Family

ID=17964781

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30707898A Expired - Fee Related JP3686267B2 (ja) 1998-10-28 1998-10-28 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP3686267B2 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4173346B2 (ja) * 2001-12-14 2008-10-29 株式会社ルネサステクノロジ 半導体装置
JP7346372B2 (ja) 2020-09-08 2023-09-19 株式会社東芝 半導体装置
CN114420569B (zh) * 2021-12-23 2024-08-20 南通通富微电子有限公司 扇出式封装方法及封装结构

Also Published As

Publication number Publication date
JP2000133762A (ja) 2000-05-12

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