JP3675642B2 - Method for manufacturing dielectric separated wafer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a dielectric isolation wafer, and more particularly, in manufacturing a dielectric isolation wafer having a dielectric isolation silicon island, a depression (step) on the wafer surface caused by the isolation polishing of the silicon island of the dielectric isolation wafer is disclosed. The present invention relates to a method of manufacturing a dielectric isolation wafer to be planarized.
[0002]
[Prior art]
For example, a bonded dielectric isolation wafer is known as a kind of bonded silicon wafer. A conventional bonded dielectric isolation wafer has been manufactured through the steps shown in FIG. FIG. 1 is an explanatory view showing a manufacturing process of a general dielectric isolation wafer.
That is, first, a silicon wafer 10 having a mirror-finished surface to be an active layer wafer is prepared (FIG. 1A). Next, a mask oxide film 11 is formed on the surface of the silicon wafer 10 (FIG. 1B), and then a resist film 12 with a window is formed by photolithography. A window having a predetermined pattern is formed in the oxide film 11 through this window, and the surface of the silicon wafer 10 is exposed. Next, after removing the resist film 12, this silicon wafer 10 is immersed in an etching solution (IPA / KOH / H ₂ O) to anisotropically etch the inside of the window on the wafer surface (FIG. 1 (c)). . In this manner, the dielectric separating groove 13 having a V-shaped cross section is formed on the wafer surface.
The anisotropic etching here refers to etching in which the etching rate in the depth direction is larger than the horizontal direction and the etching rate has direction dependency due to the crystal plane orientation of the silicon wafer 10. is there.
[0003]
Next, the mask oxide film 11 is removed by washing with dilute HF solution (see FIG. 1D). At this time, a dopant such as Sb (antimony) or As (arsenic) may be thermally diffused or ion implanted into the silicon wafer 10 as necessary. Then, a dielectric isolation oxide film 14 is formed on the wafer surface by an oxidation heat treatment (FIG. 1E). As a result, an oxide film 14 is also formed on the surface of the dielectric separation groove 13. Then, the wafer surface is cleaned.
[0004]
Subsequently, a seed polysilicon layer 15 is deposited on the surface of the silicon wafer 10 by a low temperature CVD (Chemical Vapor Deposition) method at about 550 to 700 ° C. After cleaning, the high-temperature polysilicon layer 16 is grown thickly on the seed polysilicon layer 15 by high-temperature CVD at about 1200 to 1300 ° C. (FIG. 1F). Then, the outer periphery of the wafer is chamfered, and the back surface of the wafer is flattened as necessary. Next, the high-temperature polysilicon layer 16 on the wafer surface is ground and polished to a thickness of about 10 to 80 μm (FIG. 1G).
Alternatively, after that, if necessary, a low temperature polysilicon layer 17 having a thickness of 1 to 5 μm is formed on the wafer surface by a low temperature CVD method at 550 to 700 ° C. The surface of the polysilicon layer 17 is polished and polished.
[0005]
On the other hand, a silicon wafer 20 (here, covered with a silicon oxide film 21) to be a support substrate wafer is prepared (FIG. 1 (h)). This is a mirror-finished wafer surface. Next, the silicon wafer 10 for the active layer wafer is bonded to the silicon wafer 20 with the mirror surfaces in contact with each other (FIG. 1 (i)). Then, heat treatment for increasing the bonding strength of the bonded wafer 30 is performed. Next, as shown in FIG. 1 (j), the outer peripheral portion of the active layer wafer is chamfered, and the oxide film 21 of the support substrate wafer 20 is removed by HF cleaning as necessary. Grind and polish the wafer surface. The amount of grinding of the active layer wafer is such that the dielectric isolation oxide film 14 is exposed to the outside, and the dielectric isolation silicon island 10A partitioned by the dielectric isolation oxide film 14 on the surface of the high temperature polysilicon layer 16 is used. Until it appears (see also FIG. 3 ).
[0006]
[Problems to be solved by the invention]
By the way, according to such a conventional dielectric isolation wafer manufacturing method, in the finishing process of the laminated dielectric isolation wafer, the surface of the active layer wafer 10 is ground, and this ground surface is used with an alkaline abrasive. The dielectric isolation silicon island (Si island) 10A partitioned by the dielectric isolation oxide film 14 is polished until it is exposed.
At this time, as shown in FIG. 3 , a recess 16a is formed on the polished surface of the active layer wafer 10 due to a difference in polishing rate between the respective layers 10A, 14 and 16 constituting this surface. In particular, the grain boundary portion where the high-temperature polysilicon layer 16 is grown along the V-groove-shaped dielectric isolation oxide film 14 is compared with the portions of the other dielectric isolation silicon islands 10A and the dielectric isolation oxide film 14. As a result, the progress of the etching is increased and the depth of the recess 16a may be about 0.3 μm.
[0007]
If such a deep step is formed, for example, in the photolithographic process when a device is manufactured on the user side after product shipment, it may hinder uniform application of resist on the wafer surface, circuit disconnection, or resolution. In addition, there is a possibility that a part of the film may remain on the wafer surface when the resist film is removed after the exposure. Further, in the other processes, the recess 16a was a dust adsorption site. In addition, the dust adsorbed in the depression 16a usually has a problem that it cannot be easily removed because the width of the depression 16a is narrow.
[0008]
Therefore, the inventor can polish and remove the polysilicon layer by depositing (growing) polysilicon on the wafer surface after polishing the surface of the dielectric isolation wafer, leaving a portion where the recess on the wafer surface is buried. For example, the present invention has been completed by paying attention to the elimination of the various problems that occur during device manufacture on the user side.
[0009]
OBJECT OF THE INVENTION
An object of the present invention is to provide a method of manufacturing a dielectric isolation wafer that can flatten the surface of the dielectric isolation wafer.
Another object of the present invention is to provide a method of manufacturing a dielectric isolation wafer that does not cause deterioration of the quality of silicon islands when a buried polysilicon layer is deposited.
Furthermore, an object of the present invention is to provide a method for manufacturing a dielectric-isolated wafer in which a recess on the wafer surface is less likely to be re-formed when the polysilicon layer is polished and removed.
[0010]
[Means for Solving the Problems]
According to the first aspect of the present invention, the step of forming a dielectric separation groove having a V-shaped cross section on the surface of the active layer wafer, and then the surface of the active layer wafer including the dielectric separation groove, A step of forming a dielectric isolation oxide film having a predetermined thickness by an oxidation heat treatment, and thereafter, a high-temperature polysilicon layer having a predetermined thickness is grown on the surface of the active layer wafer by a high-temperature CVD method at 1200 to 1300 ° C. And then flattening the surface by grinding and polishing the high-temperature polysilicon layer, and then bonding the planarized active layer wafer surface to the support substrate wafer. A step of forming a bonded wafer, a step of performing a predetermined bonding heat treatment on the bonded wafer, and then exposing the dielectric isolation oxide film. Grinding and polishing the active layer wafer surface of the bonded wafer until the dielectric isolation silicon island partitioned by the dielectric isolation oxide film appears, and then the entire surface of the active layer wafer is 550 to 700 The active layer wafer is formed by forming a low-temperature polysilicon layer having a thickness of 0.4 to 1.0 μm by a low-temperature CVD method at a temperature of less than that of the high-temperature polysilicon layer. Filling a recess in the surface other than the dielectric-isolated silicon island generated during the step of grinding and polishing the surface, and thereafter polishing the low-temperature polysilicon layer until the surface of the dielectric-isolated silicon island is exposed And a method of manufacturing a dielectric isolation wafer.
[0011]
The CVD method for forming a polysilicon layer is a method in which a source gas containing silicon is introduced into a reaction furnace together with a dilution gas (usually N ₂ gas), and the source gas is pyrolyzed on a silicon wafer heated to a high temperature. Or it is the method of depositing the silicon | silicone produced | generated by reduction | restoration. SiH ₂ Cl ₂ , SiH ₄ or the like is used as the compound containing silicon. As this CVD method, a low temperature CVD method of 550 to 700 ° C. is used. If it is less than 550 ° C., there is a disadvantage that the deposition rate is delayed. Further, when the temperature exceeds 700 ° C., the grain size of the polysilicon becomes large, and there is a problem that it is difficult to flatten by subsequent flattening polishing.
Further, the pressure during film formation by this low temperature CVD method is 10 to 80 Pa in the low pressure CVD method and under normal pressure in the normal pressure CVD method.
As a reaction furnace, for example, there is a horizontal furnace in which a silicon wafer on a boat fixed in a horizontally long quartz tube is resistance-heated while introducing gas. In addition, there is a vertical furnace in which gas is introduced and high-frequency induction heated while rotating a vertical quartz (SiC) boat on which a silicon wafer is placed in a bell-shaped quartz (SiC) bell jar.
[0012]
The thickness of the polysilicon layer deposited (grown) by the CVD method is 0.4 to 1.0 μm. If it is less than 0.2 μm, there arises a disadvantage that the step does not disappear sufficiently. On the other hand, if the thickness exceeds 5 μm, there arises a disadvantage that the time for flattening polishing becomes unnecessarily long.
[0013]
As a polishing liquid at the time of polishing the surface of the dielectric separation wafer, ₃ to 4 weights of abrasive grains (SiO ₂ , Al ₂ O _3, etc.) having an average particle diameter of about 1 μm are contained in an alkaline etching liquid such as NaOH and KOH. % Can be used.
The amount of polishing of the polysilicon layer is an amount that can be polished and removed in accordance with the thickness of the polysilicon, leaving a recessed portion embedded in the surface of the dielectric isolation wafer.
[0014]
[Action]
According to the present invention, after polishing the surface of the dielectric isolation wafer on which the dielectric isolation silicon island is formed, the polysilicon layer is deposited (grown) on the surface of the dielectric isolation wafer by the low temperature CVD method. As a result, the depression generated during the surface polishing of the dielectric isolation wafer is filled with the polysilicon layer. The polysilicon layer is then polished away from the surface. At this time, polishing is performed leaving a portion in which the recess on the wafer surface is embedded. As a result, the surface of the dielectric isolation wafer can be planarized.
[0015]
In particular, the present invention can also be applied to bonded dielectric isolation wafers. Therefore, when compared with a method of manufacturing a dielectric separation wafer by a method without bonding, the warpage of the wafer can be suppressed to be small, so that it can be applied to a large-diameter wafer of 5 inches or more.
[0016]
Furthermore, since the polysilicon layer for filling the recess is a low temperature polysilicon formed by a low temperature CVD method at 550 to 700 ° C., its crystal particles are smaller than the high temperature polysilicon layer, and the polysilicon layer is polished and removed. At times, the risk of recesses on the wafer surface being re-formed can be reduced.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a dielectric isolation wafer and a method of manufacturing the same according to a first embodiment of the present invention will be described. Here, the bonded dielectric isolation wafer described in the prior art section will be described as an example. Accordingly, the same parts are denoted by the same reference numerals.
First, a silicon wafer 10 having a mirror-finished surface to be an active layer wafer is prepared and prepared (FIG. 1A).
Next, a mask oxide film 11 is formed on the surface of the silicon wafer 10 (FIG. 1B).
[0018]
Next, a resist film 12 is deposited on the oxide film 11. A window having a predetermined pattern is formed in the resist film 12.
Then, a window having the same pattern is formed in the oxide film 11 through this window, and a part of the surface of the silicon wafer 10 is exposed.
Next, the resist film 12 is removed.
Further, the silicon wafer 10 is immersed in an etching solution (IPA / KOH / H ₂ O) for a predetermined time. As a result, concave portions (dents) having a predetermined pattern are formed on the silicon wafer surface. The wafer surface is subjected to anisotropic etching (FIG. 1C), and a dielectric separating groove 13 having a V-shaped cross section is formed.
[0019]
Next, the mask oxide film 11 is removed by washing with dilute HF solution (FIG. 1D). At this time, a dopant can also be introduced into the silicon bulk.
Next, a dielectric isolation oxide film 14 having a predetermined thickness is formed on the silicon wafer surface by an oxidation heat treatment (FIG. 1E).
Then, the wafer surface is cleaned.
[0020]
Next, a seed polysilicon layer 15 is deposited on the surface of the silicon wafer 10 by a low temperature CVD method at about 600 ° C.
Further, after cleaning, a high-temperature polysilicon layer 16 is grown on the seed polysilicon layer 15 to a predetermined thickness by a high-temperature CVD method at about 1250 ° C. (FIG. 1F).
Next, the outer periphery of the wafer is chamfered and the back surface of the wafer is flattened as necessary.
Next, the high-temperature polysilicon layer 16 on the wafer surface is ground and polished to a thickness of 30 μm (FIG. 1G).
Alternatively, after that, if necessary, a low-temperature polysilicon layer 17 having a thickness of 3 μm is deposited on the wafer surface by a low-temperature CVD method at 600 ° C., and the surface is polished.
[0021]
On the other hand, a silicon wafer 20 for a support substrate is prepared (FIG. 1 (h)).
Next, the silicon wafer 10 for the active layer wafer is laminated on the silicon wafer 20 with the mirror surfaces thereof overlapped (FIG. 1 (i)).
Then, a predetermined bonding heat treatment is performed on the bonded wafer 30.
Next, as shown in FIG. 1 (j), the outer peripheral portion on the active layer wafer side is chamfered and, if necessary, the oxide film 21 of the support substrate wafer 20 is removed. Grind and polish. The amount of grinding of the active layer wafer is set until the dielectric isolation silicon island 10A partitioned by the dielectric isolation oxide film 14 appears (see also FIG. 3 ).
[0022]
FIGS. 2A and 2B are explanatory views showing a manufacturing process of a bonded dielectric isolation wafer according to the first embodiment of the present invention.
Thus, the bonded dielectric isolation wafer shown in FIG. 1 (j) is manufactured. At this time, a recess 16a having a depth of about 0.3 μm generated during the surface polishing is formed on the surface of the active layer wafer (see also FIG. 3).
Then, after charging the bonded dielectric separation wafer into the reaction furnace, SiH ₄ as a growth gas having a predetermined concentration is introduced into the furnace together with a diluting gas (N ₂ gas), and is heated to 600 ° C. by a resistance heater. A low-temperature polysilicon layer 30 is laminated on the entire surface of the heated active layer wafer until the thickness reaches 0.5 μm. The pressure during film formation is 50 Pa. As a result, the recess 16a is filled with the low-temperature polysilicon layer 30 (see the two-dot chain line in FIG. 4). FIG. 2A shows this state.
[0023]
Next, as shown in FIG. 2B, the surface of the polysilicon layer 30 is left with only the embedded portion 30A of the recess 16a, and a NaOH solution and an Al ₂ O ₃ polishing abrasive are used as the polishing liquid. Polishing is removed by a known polishing apparatus. Specifically, the surface of the dielectric isolation silicon island 10A is polished until the surface is exposed.
Thereby, the surface of the wafer for active layers can be planarized. As a result, for example, a resist can be uniformly applied to the wafer surface in a photolithographic process during device fabrication on the user side. Further, it is possible to prevent circuit disconnection and resolution deterioration during exposure in the photolithography process, and to eliminate the possibility that a part of the film remains on the wafer surface when removing the resist film after exposure. Also, in other processes, it is possible to prevent dust from entering into the recess 16a and becoming a dust adsorption site.
[0024]
As described above, the active layer wafer having the dielectric isolation silicon island 10A and the support substrate wafer 20 are bonded together to produce the bonded dielectric isolation wafer. High temperature heating is unnecessary. Further, the warpage of the dielectric separation substrate can be kept small.
Further, since the recess 16a is filled with the low-temperature polysilicon layer 30 by the low temperature CVD method at 550 to 700 ° C., the possibility that the recess 16a is re-formed on the wafer surface when the low-temperature polysilicon layer 30 is removed by polishing is reduced. Can do. This is because the low-temperature polysilicon layer has smaller crystal grains than the high-temperature polysilicon layer.
Thereafter, the flatness of the surface of the dielectric separated wafer on the active layer wafer side was actually measured with a stylus type flatness measuring device.
The average flatness of the surface of 25 active layer wafers produced by the conventional method was 0.24 μm. In contrast, the average flatness when the manufacturing method of the present invention was adopted was suppressed to 0.01 μm.
[0025]
Next, based on FIG. 5, a dielectric isolation wafer according to a reference example and a manufacturing method thereof will be described. FIGS. 5A to 5C are explanatory views showing a manufacturing process of a bonded dielectric isolation wafer according to a reference example of the present invention.
In this reference example , a method of forming SOG (ethyl silicate) on the surface of the active layer wafer is employed as a method of providing the embedded portion 300A that fills the recess 16a on the surface of the active layer wafer.
That is, as shown in FIG. 5A, SOG 300 is spin-coated on the surface of the active layer wafer to a thickness of 0.6 μm. Thereafter, as shown in FIG. 5B, the SOG layer 300 is baked and hardened while the alcohol is vaporized by the harness. This firing is performed at a firing temperature of 200 to 250 ° C. and a firing time of 30 to 60 minutes in an N ₂ gas atmosphere. Thereafter, similarly to the low-temperature polysilicon layer 30, polishing is performed to flatten the wafer surface (see FIG. 5C).
When this SOG is used, HF processing cannot be performed. This is because when immersed in an HF solution, the original state is instantly etched off. In addition, the termination | terminus detection of the SOG surface can be confirmed by the presence or absence of the water breach.
When the average flatness of the surface of 25 active layer wafers manufactured by this SOG was measured, a good result of 0.02 μm was obtained as compared with 0.24 μm of the conventional method.
[0026]
【The invention's effect】
According to the present invention, after the surface of the dielectric isolation wafer is polished, polysilicon is deposited (grown) on the wafer surface by the CVD method to fill the recess on the wafer surface. Thereafter, the polysilicon layer is polished and removed while leaving the recessed portion buried, so that the surface of the dielectric isolation wafer can be flattened.
In addition, since the polysilicon layer for filling the recess is formed by a low temperature CVD method at 550 to 700 ° C., it is possible to reduce the possibility that the recess is re-formed on the wafer surface when the polysilicon layer is removed by polishing. .
[0027]
In particular, an active layer wafer having a dielectric isolation silicon island and a support substrate wafer are bonded together to produce a bonded dielectric isolation wafer. The following advantages are obtained with respect to a dielectric separated wafer that is not based on the bonding method. That is, by replacing the support substrate with a single crystal silicon wafer, the warpage of the wafer can be kept at, for example, 150 μm or less even for a large diameter wafer of 5 inches or more.
[Brief description of the drawings]
FIG. 1 is an explanatory view showing a manufacturing process of a general dielectric isolation wafer.
FIG. 2 is an explanatory view showing a manufacturing process of a bonded dielectric isolation wafer according to the first embodiment of the present invention.
FIG. 3 is an enlarged cross-sectional view of a main part of a bonded dielectric isolation wafer manufactured by conventional means.
FIG. 4 is an enlarged cross-sectional view of a main part of a bonded dielectric isolation wafer manufactured by the dielectric isolation wafer manufacturing method according to the first embodiment of the present invention.
FIG. 5 is an explanatory view showing a manufacturing process of a bonded dielectric isolation wafer according to a reference example of the present invention.
[Explanation of symbols]
10 Silicon wafer for dielectric separation wafer,
10A dielectric isolation silicon island,
16a depression,
20 Silicon wafer for supporting substrate wafer,
30 Low temperature polysilicon layer (polysilicon layer),
300 SOG layer.

Claims (1)

Forming a dielectric separating groove having a V-shaped cross section on the surface of the active layer wafer;
  Next, a step of forming a dielectric isolation oxide film having a predetermined thickness on the surface of the active layer wafer including the dielectric isolation groove by an oxidation heat treatment;
  Thereafter, a step of growing a high-temperature polysilicon layer having a predetermined thickness on the surface of the active layer wafer by a high-temperature CVD method at 1200 to 1300 ° C .;
  Next, the process of flattening the surface by grinding and polishing the high-temperature polysilicon layer,
  Then, the step of forming the bonded wafer by bonding the planarized active layer wafer surface as a bonding surface to the support substrate wafer,
  After this, for the bonded wafer, a step of performing a predetermined bonding heat treatment,
  Next, the step of grinding and polishing the wafer surface for the active layer of the bonded wafer until the dielectric isolation oxide film is exposed and the dielectric isolation silicon island partitioned by the dielectric isolation oxide film appears.
  Then, the entire surface of the active layer wafer is formed at a low temperature polycrystal having a thickness of 0.4 to 1.0 μm by a low temperature CVD method at 550 to 700 ° C. and having a crystal grain size smaller than that of the high temperature polysilicon layer. Forming a silicon layer, filling a recess in a surface other than the dielectric-isolated silicon island generated during the step of grinding and polishing the wafer surface for active layer, and
  Then, polishing the low-temperature polysilicon layer until the surface of the dielectric isolation silicon island is exposed,
  A method for manufacturing a dielectric isolation wafer including:

Images