JP3601763B2 - Dielectric separation wafer and method of manufacturing the same - Google Patents

Description

【００２５】
表１から明らかなように、種ポリシリコン層を介さず、直接、高温ポリシリコン層を成長させた従来法では、１回目の実験時にはウェーハ１枚あたり平均１６．７個の巣の発生があった。また、２回目もほぼ同様の平均１７．９個の巣が発生した。これに対して、種ポリシリコン層を介したこの発明では、１回目および２回目とも巣は発生しなかった。
【００２６】
【発明の効果】
この発明によれば、誘電体分離酸化膜上にポリシリコン層を成長させる際に、低温ＣＶＤ法による種ポリシリコン層を介在させて、ポリシリコン層を成長させるようにしたので、露出したポリシリコン層表面の凹み、および、ポリシリコン層と誘電体分離酸化膜との界面に生じる巣の発生を抑えることができる。
【図面の簡単な説明】
【図１】この発明の一実施例に係る種ポリシリコン層上の高温ポリシリコン層の成長過程を示す説明図である。
【図２】この発明の一実施例に係る誘電体分離ウェーハの製造工程を示す説明図である。
【図３】シリコンウェーハ表面の全体における異方性エッチングのパターンを示す説明図である。
【図４】シリコンウェーハ表面の一部分における異方性エッチングのパターンを示す説明図である。
【図５】一般的な誘電体分離ウェーハの製造工程を示す説明図である。
【図６】従来手段に係るポリシリコン層の成長工程を示す説明図である。
【符号の説明】
１０ シリコンウェーハ、
１０Ａ 誘電体分離シリコン島、
１１ マスク酸化膜、
１２ レジスト膜、
１３ 誘電体分離用溝、
１４ 誘電体分離酸化膜、
１５ 種ポリシリコン層、
１６ 高温ポリシリコン層。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a dielectric isolation wafer and a method of manufacturing the same, and more particularly, to a dielectric isolation wafer and a method of manufacturing the same which can suppress generation of cavities (voids) when a polysilicon layer is grown on the surface of a dielectric isolation oxide film.
[0002]
[Prior art]
For example, as a kind of bonded silicon wafer, a bonded dielectric separation wafer is known. A conventional bonded dielectric separation wafer has been manufactured through the steps shown in FIG. FIG. 5 is an explanatory view showing a manufacturing process of a conventional dielectric separation wafer.
That is, first, a silicon wafer 10 having a mirror-finished surface to be an active layer wafer is prepared (FIG. 5A). Next, a mask oxide film 11 is formed on the surface of the silicon wafer 10 (FIG. 5B). Then, a resist film 12 with a window is formed by photolithography. A window of a predetermined pattern is formed in oxide film 11 through this window, and the surface of silicon wafer 10 is exposed. Next, after removing the negative resist film 12, the silicon wafer 10 is immersed in an etching solution (IPA / KOH / H ₂ O) to anisotropically etch the inside of the window on the wafer surface (FIG. 5C). ). In this manner, a dielectric isolation groove 13 having a V-shaped cross section is formed on the wafer surface.
In addition, the anisotropic etching referred to here is etching in which the etching rate in the depth direction is higher than that in the horizontal direction and the etching rate has direction dependency due to the crystal plane orientation of the silicon wafer 10. is there.
[0003]
Next, the mask oxide film 11 is removed (FIG. 5D). Then, a dielectric isolation oxide film 14 is formed on the wafer surface by oxidizing heat treatment (FIG. 5E). As a result, an oxide film 14 is also formed on the surface of the dielectric isolation trench 13. Then, the wafer surface is cleaned.
Subsequently, a high-temperature polysilicon layer 16 is grown thicker on the surface of the dielectric isolation oxide film 14 by a high-temperature CVD method at about 1200 to 1300 ° C. (FIG. 5F).
Then, the outer peripheral portion of the wafer is chamfered, and if necessary, the back surface of the wafer is flattened.
Next, the high-temperature polysilicon layer 16 on the wafer surface is ground and polished to a thickness of about 10 to 80 μm (FIG. 5G).
Thereafter, if necessary, a low-temperature polysilicon layer 17 having a thickness of 1 to 5 μm is formed on the wafer surface by a low-temperature CVD method at 550 to 700 ° C., and then the low-temperature polysilicon layer 17 is mirror-finished for bonding. 17 is polished.
[0004]
On the other hand, a silicon wafer 20 to be a support substrate wafer is prepared (FIG. 5H). This is a mirror-finished wafer surface.
Next, the silicon wafer 10 for the active layer wafer is bonded to the silicon wafer 20 by bringing mirror surfaces into contact with each other (FIG. 5 (i)).
Then, a heat treatment is performed to increase the bonding strength of the bonded wafer.
Next, as shown in FIG. 5 (j), the outer peripheral portion of the active layer wafer is chamfered, and the surface of the active layer wafer is ground and polished. The amount of grinding of the active layer wafer is such that the dielectric isolation oxide film 14 is exposed to the outside, and the dielectric isolation silicon island 10A partitioned by the dielectric isolation oxide film 14 appears on the surface of the high-temperature polysilicon layer 16. Until it does.
[0005]
[Problems to be solved by the invention]
However, according to such a conventional method of manufacturing a dielectric isolation wafer, when the polysilicon layer 16 is grown by the high-temperature CVD method, the polysilicon is deposited on the surface of the dielectric isolation oxide film 14 as shown in FIG. When particles P, scratches, and the like are present in the substrate, they gradually grow using these as growth nuclei.
As a result, nests (voids) B, which are bubble defects, may be generated between adjacent polysilicon strains 16a among a group of a large number of polysilicon strains 16a having the particles or the like as growth nuclei. was there.
Therefore, when the nest B is exposed on the surface of the dielectric isolation wafer through the subsequent steps, there is a concern that the portion may be dented and refuse or the like may remain there. Further, even when the nest B is not exposed on the surface of the dielectric isolation wafer, there is a possibility that the dielectric isolation wafer is thermally deteriorated due to the nest B in the device manufacturing process on the user side. FIG. 6 is an explanatory view showing a polysilicon layer growth step according to the conventional means.
[0006]
Therefore, the inventor has previously grown a thin seed polysilicon layer on a dielectric isolation oxide film by a low-temperature CVD method, and then grown a high-temperature polysilicon layer on this seed polysilicon layer. The inventors have found that polysilicon grows almost uniformly from the entire surface of the seed polysilicon layer having a small diameter and high coverage, and have completed the present invention.
[0007]
[Object of the invention]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a dielectric isolation wafer capable of eliminating a dent on an exposed surface of a polysilicon layer and a nest from an interface between a polysilicon layer and a dielectric isolation oxide film.
It is another object of the present invention to provide a method of manufacturing a dielectric isolation wafer that does not generate nests at the interface between the dielectric isolation oxide film and the polysilicon layer.
[0008]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a dielectric material comprising: a polysilicon layer bonded to a wafer for a support substrate; and a plurality of silicon islands formed on the surface of the polysilicon layer and insulated from each other by a dielectric isolation oxide film. in the separation wafer, the polysilicon layer, said dielectric isolation oxide film and the low-temperature CVD method thickness of the seed polysilicon layer 50~5000nm grown by at the interface side five hundred forty to six hundred seventy ° C. of this kind poly This is a dielectric isolation wafer having a silicon layer and a high-temperature polysilicon layer grown by a high-temperature CVD method at 1200 to 1290 ° C.
The dielectric isolation wafer is a wafer in which a support substrate wafer is bonded to the back surface of a dielectric isolation wafer in which a polysilicon layer is thinned.
The thickness of the seed polysilicon layer is 50 to 5000 nm, preferably 100 to 3000 nm. If the thickness is less than 50 nm, when stacking the high-temperature polysilicon layer, a part of this kind of polysilicon layer may be lost due to the etching action of polysilicon, and a hole may be generated. If it exceeds 5000 nm, there is a disadvantage that the film becomes unnecessarily thick.
[0009]
According to a second aspect of the present invention, a dielectric isolation groove is formed on the surface of a silicon wafer, and a dielectric isolation oxide film is formed on the surface of the silicon wafer including the surface of the dielectric isolation groove. A polysilicon layer is grown on the surface of the isolation oxide film, and the silicon wafer is ground and polished from the back side to reveal a plurality of dielectric isolation silicon islands separated by the dielectric isolation oxide film on the polished surface. In the method of manufacturing a dielectric isolation wafer to be grown, before growing the polysilicon layer, a seed poly having a thickness of 50 to 5000 nm is formed on the surface of the dielectric isolation oxide film by low-temperature CVD at 540 to 670 ° C. A silicon layer is grown, and then a dielectric layer is formed on the surface of the polysilicon layer using a high-temperature CVD method at 1200 to 1290 ° C. This is a method for manufacturing a body separation wafer.
[0010]
As a method for growing the polysilicon layer, a high-temperature CVD method can be adopted. In this method, a source gas containing silicon is introduced into a reaction furnace together with a carrier gas (such as H ₂ gas), and silicon generated by thermal decomposition or reduction of the source gas is deposited on a silicon wafer heated to a high temperature. Is the way. As the compound containing silicon, SiCl ₂ H ₂ , SiCl ₄ , SiHCl _{3 and the} like are usually used.
As a reaction furnace, for example, there is a high-frequency induction heating furnace in which a gas is introduced while rotating a susceptor on which a silicon wafer is placed in a dome-shaped quartz bell jar, and heating is performed by high-frequency induction. In addition, for example, a silicon wafer is attached to each surface of a hexagonal column-shaped susceptor housed in a quartz container, and then the susceptor is rotated while heating with a gas introduction and an infrared lamp. Can also be employed.
[0011]
The growth temperature of polysilicon by the high-temperature CVD method differs depending on the heating method of the furnace. In the most common high-frequency induction heating furnace used for this purpose, 1200 to 1290 ° C, particularly 1300 to 1280 ° C is preferable. If the temperature is lower than 1200 ° C., there is a disadvantage that the silicon wafer is easily broken. On the other hand, when the temperature exceeds 1290 ° C., a slip occurs, which causes a disadvantage that the silicon wafer is liable to crack.
The thickness of the polysilicon layer is a thickness obtained by adding the thickness of the polysilicon layer to be left to two to three times the depth of the anisotropic etching. If the thickness of the polysilicon layer is not more than twice the depth at which the anisotropic etching is performed, the grooves of the anisotropic etching may not be sufficiently filled. On the other hand, if it is more than three times, it will grow unnecessarily thick, which is uneconomical.
[0012]
As a method for growing the seed polysilicon layer, a low-temperature CVD method under normal pressure or reduced pressure is employed. In this method, as in the high-temperature CVD method, a raw material gas containing silicon is introduced into a reaction furnace together with a carrier gas (H ₂ gas, etc.), and the raw material gas is thermally decomposed or deposited on a silicon wafer heated to a relatively low temperature. This is a method of depositing silicon generated by reduction. Examples of the compound containing silicon include SiH ₄ and SiH ₂ Cl ₂ . Gas was introduced into the reactor while rotating a susceptor on which a silicon wafer was placed in a quartz bell jar, and a vertical reactor in which resistance heating was performed from the outside of the quartz bell jar, or a quartz tube was laid horizontally and the silicon wafer was placed A horizontal reaction furnace can be used in which the boat is placed in a tube and resistance heating is performed from the outside of the tube while introducing gas.
The growth temperature of the seed polysilicon layer is preferably 540 to 670 ° C, particularly preferably 570 to 650 ° C. If the temperature is lower than 540 ° C., the reaction is disadvantageously slow. On the other hand, when the temperature exceeds 670 ° C., there is a disadvantage that the crystal grains become too large.
[0013]
The pressure during the growth of the seed polysilicon layer is preferably 10 Pa to normal pressure, particularly preferably 30 Pa to normal pressure. If it is less than 10 Pa, there is a disadvantage that the growth is slow. On the other hand, when the pressure exceeds the normal pressure, there is a disadvantage that the thickness distribution is deteriorated.
The thickness of the seed polysilicon layer is 50 to 5000 nm, preferably 100 to 3000 nm. If the thickness is less than 50 nm, when stacking the high-temperature polysilicon layer, a part of this kind of polysilicon layer may be lost due to the etching action of polysilicon, and a hole may be generated. If it exceeds 5000 nm, there is a disadvantage that the film becomes unnecessarily thick.
[0014]
As the anisotropic etching solution, an alkaline etching solution such as KOH (IPA / KOH / H ₂ O), KOH (KOH / H ₂ O), and KOH (hydrazine / KOH / H ₂ O) can be used. Normal conditions can be applied as the conditions for the anisotropic etching.
In addition, general conditions can be adopted as the conditions of each step for forming a window for anisotropic etching in the resist film on the wafer surface side.
[0015]
[Action]
According to the present invention, a seed polysilicon layer is grown relatively thinly on the surface of the dielectric isolation oxide film by a low-temperature CVD method, and thereafter, a polysilicon layer is grown on the surface of this seed polysilicon layer by a high-temperature CVD method. .
The growth of polysilicon by the low-temperature CVD method has a smaller crystal grain size than the growth by the high-temperature CVD method. As a result, even if particles or scratches are present on the surface of the dielectric isolation oxide film, they are gradually covered by the highly covering seed polysilicon. Therefore, the flatness of the surface of the seed polysilicon layer is increased.
Therefore, thereafter, when polysilicon is grown on this highly flat surface by the high-temperature CVD method, a growth different from the conventional growth of the polysilicon stock expansion type occurs. That is, over the entire surface of the dielectric isolation oxide film, polysilicon grows with a substantially uniform thickness. Thus, cavities generated between the dielectric isolation oxide film and the polysilicon layer can be reduced.
As a result, it is possible to eliminate a dent on the surface of the polysilicon layer exposed on the surface of the dielectric isolation wafer and a nest from the interface between the polysilicon layer and the dielectric isolation oxide film in the dielectric isolation wafer.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a dielectric isolation wafer and a method of manufacturing the same according to embodiments of the present invention will be described. Here, the bonded dielectric separation wafer described in the section of the prior art will be described as an example. Therefore, the same portions are denoted by the same reference numerals.
FIG. 1 is an explanatory diagram showing a growth process of a high-temperature polysilicon layer on a seed polysilicon layer according to one embodiment of the present invention. FIG. 2 is an explanatory view showing a manufacturing process of the dielectric isolation wafer according to one embodiment of the present invention.
First, a silicon wafer 10 having a mirror-finished surface to be an active layer wafer is prepared and prepared (FIG. 2A).
Next, after cleaning the silicon wafer 10, a mask oxide film 11 is formed on the wafer surface (FIG. 2B). Instead of the mask oxide film 11, a nitride film may be grown by a CVD method.
[0017]
Next, a resist film 12 is deposited on the mask oxide film 11. Then, a window having a predetermined pattern is formed in the resist film 12.
Subsequently, a window having the same pattern is formed in the oxide film 11 through this window, and a part of the surface of the silicon wafer 10 is exposed.
Next, the resist film 12 is removed. Then, the wafer surface is cleaned.
Further, the silicon wafer 10 is immersed in an anisotropic etching solution (IPA / KOH / H ₂ O) for a predetermined time. As a result, recesses (depressions) in a predetermined pattern are formed on the silicon wafer surface. Therefore, the anisotropic etching is performed on the wafer surface to form the dielectric separation groove 13 having a V-shaped cross section (FIG. 2C).
[0018]
Next, the mask oxide film 11 is removed (FIG. 2D).
Thereafter, if necessary, a dopant is implanted into the silicon, and then a dielectric isolation oxide film 14 is formed on the wafer surface by oxidizing heat treatment (FIG. 2E). As a result, a dielectric isolation oxide film 14 is also formed on the dielectric isolation trench 13.
Next, the wafer surface is cleaned.
[0019]
Subsequently, a seed polysilicon layer 15 is grown to a thickness of 500 nm on the surface of the dielectric isolation oxide film 14 by a pressure of 130 Pa, a source gas of SiH ₄ , and a reduced pressure / low temperature CVD method of 600 ° C. Then, after the cleaning, a high-temperature polysilicon layer 16 is grown to a thickness of 150 μm on the polysilicon layer 15 by a high-temperature CVD method at about 1200 ° C. (FIG. 2F).
Growth by the low-temperature CVD method has a high foreign matter coverage because the polysilicon has a small crystal grain size. Therefore, even if particles or scratches are present on the surface of the dielectric isolation oxide film 14, the growing seed polysilicon gradually covers them. Therefore, the surface of seed polysilicon layer 15 has high flatness.
From this, when polysilicon is grown on the high-flatness seed polysilicon layer 15 by the high-temperature CVD method, the polysilicon is maintained with a substantially uniform thickness over the entire surface of the dielectric isolation oxide film 14. Silicon grows (see FIG. 1). As a result, nests generated between the dielectric isolation oxide film 14 and the polysilicon layer can be eliminated.
As a result, after the dielectric isolation wafer is manufactured, the depression of the surface of the high-temperature polysilicon layer 16 exposed on the surface of the wafer is also eliminated.
[0020]
Then, the outer peripheral portion of the wafer is chamfered, and if necessary, the back surface of the wafer is flattened. Next, the surface of the high-temperature polysilicon layer 16 is ground and polished to a thickness of about 30 μm (FIG. 2G).
After that, a low-temperature polysilicon layer 17 having a thickness of about 3.0 μm is formed on the wafer surface by a low-temperature CVD method at 600 ° C., and then the surface of the low-temperature polysilicon layer 17 is polished to mirror the bonding surface.
[0021]
On the other hand, a silicon wafer 20 (here, covered with a silicon oxide film 21) to be a support substrate wafer is prepared (FIG. 2 (h)). The wafer surface is mirror-finished.
Next, the silicon wafer 10 for the active layer wafer is bonded onto the silicon wafer 20 by bringing the mirror surfaces into contact with each other (FIG. 2 (i)).
Then, a heat treatment for increasing the bonding strength of the bonded wafer is performed.
Then, as shown in FIG. 2 (j), the outer peripheral portion of the silicon wafer 10 for the active layer is chamfered, and if necessary, the oxide film 21 of the silicon wafer 20 for the support substrate is removed by HF cleaning. The wafer 10 is ground and polished. In this case, the amount of grinding is such that the dielectric isolation oxide film 14 is exposed to the outside, and the dielectric isolation silicon island 10A partitioned by the dielectric isolation oxide film 14 appears on the surface of the high-temperature polysilicon layer 16. The amount is such that adjacent silicon islands are completely separated.
In this way, a bonded dielectric separation wafer is manufactured.
[0022]
Here, actually, the nests appearing on the surface of each silicon wafer 10 when performing a comparison experiment between the conventional method (without the seed polysilicon layer) and the present invention (via the seed polysilicon layer). Enter the number. Note that this experiment was performed twice for each of the conventional method and the present invention, each of which consisted of 10 wafers.
In advance, a dielectric isolation oxide film of only 1 μm is formed on the surface of a silicon wafer 10 having a diameter of 5 inches, a thickness of 625 μm and a depth of 60 μm of the dielectric isolation groove 13 which has been anisotropically etched. Thereafter, a high-temperature polysilicon layer is grown on the surface of the silicon wafer 10 under the following conditions. FIG. 3 shows pattern regions of anisotropic etching at respective locations on the surface of the silicon wafer 10. Nests were observed in these areas.
[0023]
The overall dimensions of each part are 8600 × 8600 μm. 49 patterns (1100 × 1100 μm) are formed therein (see FIG. 4). The groove width of the anisotropic etching is 100 μm. However, only the groove width at the outer peripheral edge of the entire pattern is set to 150 μm. FIG. 4 is an explanatory view showing an anisotropic etching pattern on a part of the silicon wafer surface.
The growth conditions for the high-temperature polysilicon layer are a thickness of 150 μm, a source gas (TCS (trichlorosilane)), and a growth temperature of 1200 ° C. The conditions for growing the seed polysilicon layer of the present invention by low-pressure / low-temperature CVD are a thickness of 500 nm, a source gas (SiH ₄ ), a growth temperature of 600 ° C., and a pressure of 130 Pa.
Thereafter, the surface of the high-temperature polysilicon layer is subjected to primary grinding with a vitrified grinding wheel of # 300 abrasive grains, followed by finish grinding with a vitrified finishing grinding wheel of # 1500 abrasive grains, and a total of 100 μm grinding. Next, after this ground surface is polished by 20 μm, the number of cavities appearing on all of the polished surfaces of the ten silicon wafers 10 is entirely scanned under a fluorescent lamp using an optical microscope. Table 1 shows the results thus observed.
[0024]
[Table 1]

[0025]
As is apparent from Table 1, in the conventional method in which the high-temperature polysilicon layer was directly grown without the intermediary of the seed polysilicon layer, an average of 16.7 nests per wafer were generated in the first experiment. Was. In the second time, almost the same average of 17.9 nests were generated. On the other hand, in the present invention via the seed polysilicon layer, no nest was generated in the first and second times.
[0026]
【The invention's effect】
According to the present invention, when the polysilicon layer is grown on the dielectric isolation oxide film, the polysilicon layer is grown by interposing the seed polysilicon layer by the low-temperature CVD method. It is possible to suppress dents on the surface of the layer and the occurrence of cavities at the interface between the polysilicon layer and the dielectric isolation oxide film.
[Brief description of the drawings]
FIG. 1 is an explanatory view showing a growth process of a high-temperature polysilicon layer on a seed polysilicon layer according to one embodiment of the present invention.
FIG. 2 is an explanatory view showing a process of manufacturing a dielectric isolation wafer according to one embodiment of the present invention.
FIG. 3 is an explanatory diagram showing an anisotropic etching pattern over the entire surface of a silicon wafer.
FIG. 4 is an explanatory view showing a pattern of anisotropic etching on a part of the surface of a silicon wafer.
FIG. 5 is an explanatory view showing a manufacturing process of a general dielectric isolation wafer.
FIG. 6 is an explanatory view showing a polysilicon layer growth step according to a conventional means.
[Explanation of symbols]
10 silicon wafers,
10A dielectrically isolated silicon island,
11 mask oxide film,
12 resist film,
13 Dielectric isolation grooves,
14 dielectric isolation oxide film,
15 kinds of polysilicon layers,
16 High temperature polysilicon layer.

Claims (2)

In a dielectric isolation wafer having a polysilicon layer bonded to a support substrate wafer and a plurality of silicon islands formed on the surface of the polysilicon layer and insulated from each other by a dielectric isolation oxide film,
A polysilicon layer having a thickness of 50 to 5000 nm grown on the interface side with the dielectric isolation oxide film by a low-temperature CVD method at 540 to 670 ° C . ;
A dielectric isolation wafer having a high-temperature polysilicon layer grown on a surface of this kind of polysilicon layer using a high-temperature CVD method at 1200 to 1290 ° C. Form a dielectric isolation groove on the surface of the silicon wafer,
Forming a dielectric isolation oxide film on the surface of the silicon wafer including the surface of the dielectric isolation groove,
Growing a polysilicon layer on the surface of this dielectric isolation oxide film,
Grinding and polishing the silicon wafer from the back side thereof, in a method of manufacturing a dielectric isolation wafer to expose a plurality of dielectric isolation silicon islands separated by a dielectric isolation oxide film on the polished surface,
In growing the above polysilicon layer,
In advance, a seed polysilicon layer having a thickness of 50 to 5000 nm is grown on the surface of the dielectric isolation oxide film by a low-temperature CVD method at 540 to 670 ° C.
Then, a method of manufacturing a dielectric isolation wafer in which the polysilicon layer is grown on the surface of the polysilicon layer by using a high-temperature CVD method at 1200 to 1290 ° C.

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