JP2000183153A - Dielectric isolation wafer and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a dielectric isolation wafer which can grow a polysilicon layer without generation of voids on the dielectric isolation oxide film and a method of manufacturing the same wafer. SOLUTION: After a dielectric isolation oxide film 14 is formed with the oxidization heat treatment on the surface of a silicon wafer 10 having the dielectric isolation groove, a seed polysilicon layer 15 is grown on this film 14 by the 130 Pa, low pressure and low temperature CVD method at about 600 deg.C. Next, on the seed polysilicon layer 15, a thick high temperature poly- silicon layer 156 is grown by a high temperature CVD method of about 1250 deg.C. The low pressure and low temperature CVD method assures slower growth rate of polysilicon and higher flatness of the surface. Therefore, when the high temperature polysilicon layer 16 is grown by the high temperature CVD method on the surface of the seed polysilicon layer 15 as the base surface, the polysilicon grows in the uniform thickness from the entire part of such a base surface. As a result, generation of voids between the film 14 and the high temperature layer 16 is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric isolation wafer and a method of manufacturing the same, and more particularly, to a dielectric isolation wafer capable of suppressing generation of cavities (voids) when a polysilicon layer is grown on the surface of a dielectric isolation oxide film. The present invention relates to a wafer and a method for manufacturing the same.

[0002]

2. Description of the Related Art For example, a bonded dielectric isolation wafer is known as a kind of bonded silicon wafer. A conventional bonded dielectric separation wafer has been manufactured through the steps shown in FIG. FIG. 5 is an explanatory view showing a manufacturing process of a conventional dielectric separation wafer. That is, first, a silicon wafer 10 having a mirror-finished surface to be an active layer wafer is prepared (FIG. 5A). Next, a mask oxide film 11 is formed on the surface of the silicon wafer 10 (FIG. 5B). Then, a resist film 12 with a window is formed by photolithography.
A window of a predetermined pattern is formed in oxide film 11 through this window, and the surface of silicon wafer 10 is exposed. Next, after removing the negative resist film 12, the silicon wafer 10 is immersed in an etchant (IPA / KOH / H ₂ O) to anisotropically etch the inside of the window on the wafer surface (FIG. 5C). ). In this manner, the dielectric separation groove 13 having a V-shaped cross section is formed on the wafer surface. In addition, the anisotropic etching referred to here means the silicon wafer 10
, The etching rate in the depth direction is higher than that in the horizontal direction, and the etching rate has direction dependency.

Next, the mask oxide film 11 is removed (FIG. 5).
(D)). Then, a dielectric isolation oxide film 14 is formed on the wafer surface by oxidizing heat treatment (FIG. 5E).
As a result, an oxide film 14 is also formed on the surface of the dielectric isolation trench 13. Then, the wafer surface is cleaned. Subsequently, on the surface of the dielectric isolation oxide film 14, about 1200 to 13
The high-temperature polysilicon layer 16 is grown thicker by the high-temperature CVD method at 00 ° C. (FIG. 5F). Then, the outer peripheral portion of the wafer is chamfered and, if necessary, the back surface of the wafer is flattened. Next, the high-temperature polysilicon layer 16 on the wafer surface
Is ground and polished to a thickness of about 10 to 80 μm (FIG. 5).
(G)). Thereafter, if necessary, 55
A low-temperature polysilicon layer 17 having a thickness of 1 to 5 [mu] m is formed by a low-temperature CVD method at 0 to 700 [deg.] C. Then, the surface of the low-temperature polysilicon layer 17 is polished in order to achieve a mirror-finished bonding surface.

On the other hand, a silicon wafer 20 serving as a wafer for a supporting substrate is prepared (FIG. 5 (h)). this is,
The wafer surface is mirror-finished. Next, the silicon wafer 10 for the active layer wafer is bonded to the silicon wafer 20 by bringing mirror surfaces into contact with each other (FIG. 5 (i)). Then, heat treatment is performed to increase the bonding strength of the bonded wafer. Next, as shown in FIG. 5 (j), the outer peripheral portion of the active layer wafer is chamfered, and the surface of the active layer wafer is ground and polished. The grinding amount of the wafer for the active layer is such that the dielectric isolation oxide film 14 is exposed to the outside, and the dielectric isolation silicon island 10A partitioned by the dielectric isolation oxide film 14 appears on the surface of the high-temperature polysilicon layer 16. Until it does.

[0005]

However, according to such a conventional method of manufacturing a dielectric isolation wafer, during the growth of the polysilicon layer 16 by the high-temperature CVD method, the polysilicon is formed as shown in FIG. If particles P, scratches, and the like are present on the surface of the dielectric isolation oxide film 14, they gradually grow using these as growth nuclei. As a result, nests (voids) B, which are bubble defects, may be generated between adjacent polysilicon strains 16a among a group of a large number of polysilicon strains 16a having the particles or the like as growth nuclei. was there. Therefore,
If the nest B is exposed on the surface of the dielectric isolation wafer through the subsequent steps, there is a concern that the portion may be dented, and there is a problem that dust and the like remain there. Further, even when the nest B is not exposed on the surface of the dielectric isolation wafer, there is a possibility that the dielectric isolation wafer may be thermally deteriorated due to the nest B in a device manufacturing process on the user side. FIG. 6 is an explanatory view showing a process of growing a polysilicon layer according to a conventional means.

Therefore, the inventor of the present invention has previously grown a thin seed polysilicon layer on a dielectric isolation oxide film by a low-temperature CVD method, and then grown a high-temperature polysilicon layer on this seed polysilicon layer. The inventors have found that polysilicon grows substantially uniformly from the entire surface of the seed polysilicon layer having a small crystal grain size and high covering properties, and have completed the present invention.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a dielectric isolation wafer capable of eliminating a dent on the surface of an exposed polysilicon layer and an interface between the polysilicon layer and the dielectric isolation oxide film. I have. It is another object of the present invention to provide a method of manufacturing a dielectric isolation wafer that does not generate nests at the interface between the dielectric isolation oxide film and the polysilicon layer.

[0008]

According to a first aspect of the present invention, there is provided a dielectric material having a polysilicon layer and a plurality of silicon islands formed on the surface of the polysilicon layer and insulated from each other by a dielectric isolation oxide film. In the body separation wafer, the polysilicon layer is a dielectric separation wafer having a seed polysilicon layer grown on the interface side with the dielectric separation oxide film by a low-temperature CVD method. The dielectric isolation wafer may be a substrate in which a polysilicon layer is thickened as a support substrate, or a wafer in which a wafer for a support substrate is bonded to the back surface of a dielectric isolation wafer in which the polysilicon layer is thinned.

According to a second aspect of the present invention, a dielectric isolation groove is formed on the surface of the silicon wafer, and a dielectric isolation oxide film is formed on the surface of the silicon wafer including the surface of the dielectric isolation groove. A polysilicon layer is grown on the surface of the dielectric isolation oxide film, the silicon wafer is ground and polished from the back side, and a plurality of dielectric isolation silicon islands separated by the dielectric isolation oxide film are formed on the polished surface. In the method of manufacturing a dielectric isolation wafer, a seed polysilicon layer is grown on the surface of the dielectric isolation oxide film by a low-temperature CVD method before growing the polysilicon layer. This is a method for manufacturing a dielectric isolation wafer in which the polysilicon layer is grown on the surface of the polysilicon layer by using a high-temperature CVD method.

As a method for growing the polysilicon layer, a high-temperature CVD method can be adopted. In this method, a source gas containing silicon is introduced into a reaction furnace together with a carrier gas (such as H ₂ gas), and silicon generated by thermal decomposition or reduction of the source gas is deposited on a silicon wafer heated to a high temperature. Is the way. The compound containing silicon is usually SiCl ₂ H ₂ , SiCl ₄ , SiHCl ₃
Are used. As a reaction furnace, for example, there is a high-frequency induction heating type furnace in which a gas is introduced while rotating a susceptor on which a silicon wafer is mounted in a dome-shaped quartz bell jar and heated by high-frequency induction. In addition, for example, a silicon wafer is attached to each surface of a hexagonal column-shaped susceptor housed in a quartz container, and thereafter, the susceptor is rotated by heating with a gas introduction and an infrared lamp. Can also be employed.

The growth temperature of polysilicon by the high-temperature CVD method differs depending on the heating method of the furnace. In the most common high-frequency induction heating furnace used for this application, 1200 to 129
0 ° C, particularly preferably 1230 to 1280 ° C, is preferred. 1200
If the temperature is lower than ℃, there is a disadvantage that the silicon wafer is easily broken. On the other hand, if the temperature exceeds 1290 ° C., a slip occurs, which causes a disadvantage that the silicon wafer is liable to crack. The thickness of the polysilicon layer is a thickness obtained by adding the thickness of the polysilicon layer to be left to two to three times the depth of the anisotropic etching. If the thickness of the polysilicon layer is not more than twice the depth at which the anisotropic etching is performed, the grooves of the anisotropic etching may not be sufficiently filled. On the other hand,
If it is three times or more, it will grow unnecessarily thick, which is uneconomical.

A method for growing a seed polysilicon layer is usually
A low pressure or low pressure CVD method is employed. This is high
As in the case of the temperature CVD method, a raw material gas containing silicon is charged.
Rear gas (H₂Gas, etc.) into the reactor,
Raw material gas on silicon wafer heated to relatively low temperature
Deposits silicon produced by thermal decomposition or reduction of
It is a way to make it. Compounds containing silicon include S
iH₄, SiH₂Cl ₂And the like. To the reactor
Is a susceptor with a silicon wafer placed in a quartz bell jar.
Gas is introduced while rotating the putter, and the quartz bell jar
A vertical reaction furnace that heats resistance from the outside of the
Lay aside and tug the boat with the silicon wafer on it.
Inside the tube and introduce resistance from outside the tube while introducing gas
A horizontal reactor for heating can be used. Seed polysilicon layer
The growth temperature is 540-670 ° C, especially 570-650 ° C
Is preferred. Less than 540 ° C is slow
Occurs. On the other hand, when the temperature exceeds 670 ° C., crystal grains become large.
The inconvenience of being too much occurs.

The pressure during the growth of the seed polysilicon layer is 10
Pa to normal pressure, particularly 30 Pa to normal pressure, is preferred. 10Pa
If it is less than 1, the disadvantage of slow growth occurs. On the other hand, when the pressure exceeds normal pressure, there is a disadvantage that the thickness distribution is deteriorated. The thickness of the seed polysilicon layer is 50 to 5000 nm, preferably 100 to 3000 nm. If the thickness is less than 50 nm, when stacking a high-temperature polysilicon layer, a part of this kind of polysilicon layer may be lost due to the etching action of polysilicon, and a hole may be generated. If it exceeds 5000 nm, there is a disadvantage that the film becomes unnecessarily thick.

As an anisotropic etching solution, KOH (I
PA / KOH / H ₂ O), KOH (KOH / H ₂ O),
An alkaline etching solution such as KOH (hydrazine / KOH / H ₂ O) can be used. Normal conditions can be applied as the conditions for the anisotropic etching. In addition, general conditions can be adopted as the conditions of each step for forming a window portion for anisotropic etching in the resist film on the wafer surface side.

[0015]

According to the present invention, a seed polysilicon layer is grown relatively thinly on the surface of a dielectric isolation oxide film by a low-temperature CVD method.
A polysilicon layer is grown by the VD method. Low temperature CVD
The growth of polysilicon by the method has a smaller crystal grain size than the growth by the high temperature CVD method. As a result, even if particles or scratches are present on the surface of the dielectric isolation oxide film, they are gradually covered by the highly covering seed polysilicon. Therefore, the flatness of the surface of the seed polysilicon layer is increased. Therefore, thereafter, when polysilicon is grown on this highly flat surface by the high-temperature CVD method, a growth different from the conventional growth of the polysilicon stock expansion type occurs.
That is, over the entire surface of the dielectric isolation oxide film, polysilicon grows with a substantially uniform thickness. This allows
A cavity generated between the dielectric isolation oxide film and the polysilicon layer can be reduced. This makes it possible to eliminate dents from the surface of the polysilicon layer exposed on the surface of the dielectric isolation wafer and the interface between the polysilicon layer and the dielectric isolation oxide film in the dielectric isolation wafer.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a dielectric isolation wafer and a method of manufacturing the same according to an embodiment of the present invention will be described. Here, the bonded dielectric separation wafer described in the section of the prior art will be described as an example. Therefore, the same parts are denoted by the same reference numerals. FIG. 1 is an explanatory diagram showing a growth process of a high-temperature polysilicon layer on a seed polysilicon layer according to one embodiment of the present invention. FIG. 2 is an explanatory view showing a process of manufacturing a dielectric isolation wafer according to one embodiment of the present invention. First,
A silicon wafer 10 having a mirror-finished surface to be an active layer wafer is prepared and prepared (FIG. 2A). Then
After cleaning this silicon wafer 10, on the wafer surface,
A mask oxide film 11 is formed (FIG. 2B). Instead of the mask oxide film 11, a nitride film may be grown by a CVD method.

Next, a resist film 12 is deposited on the mask oxide film 11. Then, windows of a predetermined pattern are formed in the resist film 12. Subsequently, a window having the same pattern is formed in the oxide film 11 through this window, and a part of the surface of the silicon wafer 10 is exposed. Next, the resist film 12 is removed. Then, the wafer surface is cleaned. further,
This silicon wafer 10 is treated with an anisotropic etching solution (IP
A / KOH / H ₂ O) for a predetermined time. As a result, recesses (depressions) in a predetermined pattern are formed on the surface of the silicon wafer. Accordingly, anisotropic etching is performed on the wafer surface, and the dielectric isolation groove 1 having a V-shaped cross section is formed.
3 is formed (FIG. 2C).

Next, the mask oxide film 11 is removed (FIG. 2).
(D)). Thereafter, if necessary, a dopant is implanted into silicon, and then a dielectric isolation oxide film 14 is formed on the wafer surface by oxidizing heat treatment (FIG. 2E).
As a result, a dielectric isolation oxide film 14 is also formed on the dielectric isolation trench 13. Next, the wafer surface is cleaned.

Subsequently, a seed polysilicon layer 15 is formed on the surface of the dielectric isolation oxide film 14 by a low pressure / low temperature CVD method at a pressure of 130 Pa, a source gas of SiH ₄ and 600 ° C.
Growing to 00 nm. After the cleaning, a high-temperature polysilicon layer 16 is grown to 150 μm on the polysilicon layer 15 by a high-temperature CVD method at about 1200 ° C. (FIG. 2).
(F)). The growth by the low-temperature CVD method has a high foreign matter coverage because the crystal grain size of polysilicon is small. Therefore, even if particles or scratches are present on the surface of the dielectric isolation oxide film 14, the growing seed polysilicon gradually covers them. Therefore, the surface of seed polysilicon layer 15 has high flatness. For this reason, the polysilicon is then deposited on the high-flatness seed polysilicon layer 15 at a high temperature C.
When grown by the VD method, polysilicon grows over the entire surface of the dielectric isolation oxide film 14 while maintaining a substantially uniform thickness (see FIG. 1). As a result, nests generated between the dielectric isolation oxide film 14 and the polysilicon layer can be eliminated. As a result, after the dielectric isolation wafer is manufactured, the depression of the surface of the high-temperature polysilicon layer 16 exposed on the surface of the wafer is also eliminated.

Then, the outer peripheral portion of the wafer is chamfered, and if necessary, the back surface of the wafer is flattened. Next, the high-temperature polysilicon layer 16 is ground and polished to a thickness of about 30 μm (FIG. 2G). After that, 600
After a low-temperature polysilicon layer 17 having a thickness of about 3.0 .mu.m is formed by a low-temperature CVD method at a temperature of .degree. C., the surface of the low-temperature polysilicon layer 17 is polished to mirror-bond the bonding surface.

On the other hand, a silicon wafer 20 (here, covered with a silicon oxide film 21) to be a support substrate wafer is prepared (FIG. 2 (h)). The wafer surface is mirror-finished. Next, the silicon wafer 10 for the active layer wafer is bonded onto the silicon wafer 20 by bringing the mirror surfaces into contact with each other (FIG. 2).
(I)). Then, a heat treatment for increasing the bonding strength of the bonded wafer is performed. Then, as shown in FIG. 2 (j), the outer peripheral portion of the silicon wafer 10 for the active layer is chamfered, and if necessary, the oxide film 21 of the silicon wafer 20 for the support substrate is removed by HF cleaning. The wafer 10 is ground and polished. In this case, the amount of grinding is such that the dielectric isolation oxide film 14 is exposed to the outside and the dielectric isolation silicon island 10A partitioned by the dielectric isolation oxide film 14 appears on the surface of the high-temperature polysilicon layer 16. The amount is such that adjacent silicon islands are completely separated. In this way, a bonded dielectric separation wafer is manufactured.

Here, each silicon wafer 1 was actually subjected to a comparison experiment between the conventional method (without the seed polysilicon layer) and the present invention (via the seed polysilicon layer).
0 Describe the number of nests that appeared on the surface. In this experiment, both the conventional method and the present invention were applied to the wafer 10
Each sheet was used as a set, and each test was performed twice. A silicon wafer 1 having a diameter of 5 inches, a thickness of 625 μm, and a depth of the dielectric isolation groove 13 of 60 μm previously anisotropically etched.
On the surface 0, a dielectric isolation oxide film is formed by 1 μm. Thereafter, a high-temperature polysilicon layer is grown on the surface of the silicon wafer 10 under the following conditions. FIG. 3 shows a pattern region of anisotropic etching at each location on the surface of the silicon wafer 10. Nests were observed within these areas.

The overall dimensions of each part are 8600 × 8600
μm. There are 49 patterns (1 pattern 1
100 × 1100 μm) (see FIG. 4). The groove width of the anisotropic etching is 100 μm. However, only the groove width at the outer peripheral edge of the entire pattern is 150 μm.
Is set to FIG. 4 is an explanatory view showing an anisotropic etching pattern on a part of the surface of the silicon wafer. The growth condition of the high-temperature polysilicon layer is as follows.
50 μm, source gas (TCS (trichlorosilane)), growth temperature 1200 ° C. The conditions for growing the seed polysilicon layer of the present invention by the low pressure / low temperature CVD method are a thickness of 500 nm, a source gas (SiH ₄ ), a growth temperature of 600 ° C., and a pressure of 130 Pa. Thereafter, the surface of the high-temperature polysilicon layer is subjected to primary grinding with a vitrified grinding wheel of # 300 abrasive grains, and then subjected to finish grinding with a vitrified finishing grinding wheel of # 1500 abrasive grains, and is ground to a total of 100 μm. Next, this ground surface was
After polishing by m, the number of cavities appearing in the entire polished surface of the ten silicon wafers 10 is scanned over the entire surface under a fluorescent lamp using an optical microscope. Table 1 shows the results thus observed.

[0024]

[Table 1]

As is clear from Table 1, in the conventional method in which the high-temperature polysilicon layer was directly grown without using the seed polysilicon layer, an average of 16.7 nests per wafer was used in the first experiment. There was an outbreak. In the second round, almost the same average of 17.9 nests were generated. In contrast, in the present invention via the seed polysilicon layer, the first and second
No nests were generated at the second time.

[0026]

According to the present invention, when a polysilicon layer is grown on a dielectric isolation oxide film, the polysilicon layer is grown with a seed polysilicon layer interposed by a low-temperature CVD method. In addition, it is possible to suppress the occurrence of dents on the surface of the exposed polysilicon layer and the occurrence of cavities at the interface between the polysilicon layer and the dielectric isolation oxide film.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing a growth process of a high-temperature polysilicon layer on a seed polysilicon layer according to one embodiment of the present invention.

FIG. 2 is an explanatory view showing a process of manufacturing a dielectric isolation wafer according to one embodiment of the present invention.

FIG. 3 is an explanatory view showing an anisotropic etching pattern over the entire surface of a silicon wafer.

FIG. 4 is an explanatory view showing a pattern of anisotropic etching on a part of the surface of a silicon wafer.

FIG. 5 is an explanatory view showing a manufacturing process of a general dielectric isolation wafer.

FIG. 6 is an explanatory view showing a process of growing a polysilicon layer according to a conventional means.

[Explanation of symbols]

 Reference Signs List 10 silicon wafer, 10A dielectric isolation silicon island, 11 mask oxide film, 12 resist film, 13 dielectric isolation groove, 14 dielectric isolation oxide film, 15 type polysilicon layer, 16 high temperature polysilicon layer.

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) BJ01

Claims (2)

[Claims] 1. A dielectric isolation wafer comprising: a polysilicon layer; and a plurality of silicon islands formed on a surface of the polysilicon layer and insulated from each other by a dielectric isolation oxide film. A dielectric isolation wafer having a seed polysilicon layer grown by a low-temperature CVD method on an interface side with a body isolation oxide film. 2. A dielectric isolation groove is formed on a surface of a silicon wafer, and a dielectric isolation oxide film is formed on a surface of the silicon wafer including a surface of the dielectric isolation groove. A dielectric layer that grows a polysilicon layer on the surface, grinds and polishes the silicon wafer from the back side, and exposes a plurality of dielectric islands separated by a dielectric isolation oxide film on the polished surface. In the method of manufacturing a wafer, before growing the polysilicon layer, a low temperature CV
A method of manufacturing a dielectric isolation wafer in which a seed polysilicon layer is grown by a method D, and thereafter, the polysilicon layer is grown on a surface of the seed polysilicon layer by using a high-temperature CVD method.