JP3646921B2 - Manufacturing method of bonded dielectric isolation wafer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a bonded dielectric isolation wafer, and more particularly to a method of manufacturing a bonded dielectric isolation wafer having a dielectric isolation silicon island in an active layer wafer.
[0002]
[Prior art]
A conventional bonded dielectric isolation wafer has been manufactured through the steps shown in FIG.
First, a silicon wafer 10 having a mirror-finished surface to be an active layer wafer is prepared (FIG. 5A). Next, a mask oxide film 11 is formed on the surface of the silicon wafer 10 (FIG. 5B). Further, a photoresist 12 is deposited on the mask oxide film 11, and an opening is formed at a predetermined position by photolithography. Then, the oxide film 11 exposed through this opening is removed, and a window having a predetermined pattern is formed in the oxide film 11. As a result, a part of the surface of the silicon wafer 10 is exposed. Next, after removing the photoresist 12, the silicon wafer 10 is immersed in an alkaline etching solution (IPA / KOH / H ₂ O) to anisotropically etch the inside of the window on the wafer surface (FIG. 5C). . In this manner, the dielectric separating groove 13 having a V-shaped cross section is formed on the wafer surface.
[0003]
Next, the mask oxide film 11 is removed by washing with dilute HF liquid (diluted hydrofluoric acid liquid) or buffer hydrofluoric acid liquid (FIG. 5D). Then, a dielectric isolation oxide film 14 is formed on the wafer surface by an oxidation heat treatment (FIG. 5E). As a result, a dielectric isolation oxide film 14 having a predetermined thickness is formed on the surface of the silicon wafer including the surface of the dielectric isolation groove 13.
Subsequently, a seed polysilicon layer 15 is deposited to a predetermined thickness on the surface of the silicon wafer 10, that is, on the dielectric isolation oxide film 14, and thereafter, a high temperature poly-silicon film is formed by a high temperature CVD method at about 1200 to 1300 ° C. The silicon layer 16 is grown to a thickness of about 150 μm (FIG. 5F). Then, the outer periphery of the wafer is chamfered, and then the wafer back surface is polished to remove the unnecessary high-temperature polysilicon portion that wraps around the wafer back surface and the back surface protrusion 16a on which this polysilicon is deposited in a protruding shape, and is flattened. To do. Next, the high-temperature polysilicon layer 16 on the wafer surface is ground and polished to a thickness of about 10 to 80 μm, and then the silicon wafer 10 is peeled off from the wafer holding plate of the surface grinding apparatus, dewaxed and washed (FIG. 5 ( g)).
Thereafter, a low-temperature polysilicon layer 17 having a thickness of 1 to 5 μm is grown on the wafer surface by a low-temperature CVD method at 550 to 700 ° C. Then, the surface of the low-temperature polysilicon layer 17 is polished for the purpose of flattening the bonded surface (also FIG. 5G).
[0004]
On the other hand, a silicon wafer 20 covered with a silicon oxide film 21 serving as a support substrate wafer is prepared separately from the silicon wafer 10 (FIG. 5H). The wafer surface is mirror-finished. Next, the silicon wafer 10 for the active layer wafer is bonded to the silicon wafer 20 with the mirror surfaces in contact with each other (FIG. 5 (i)).
Thereafter, heat treatment for increasing the bonding strength of the bonded wafer is performed. Next, as shown in FIG. 5J, the outer peripheral portion of the bonded wafer on the active layer wafer side is chamfered. That is, it is ground obliquely from the surface of the silicon wafer 10 and chamfered until it passes through the bonding interface and reaches the surface layer portion of the silicon wafer 20.
Then, the wafer side surface for the active layer of this bonded wafer is ground and polished (FIG. 5 (k)). The amount of grinding of the active layer wafer is such that a part of the dielectric isolation oxide film 14 is exposed to the outside, and the dielectric isolation silicon island partitioned by the dielectric isolation oxide film 14 is formed on the surface of the high temperature polysilicon layer 16. Until 10A appears.
[0005]
[Problems to be solved by the invention]
However, in this prior art, the portion around the back surface of the polysilicon that appears on the back surface of the outer peripheral portion of the active layer wafer 10 and the back surface protrusion 16a on which the polysilicon is deposited in a protruding shape are removed by polishing. At that time, the wrapped polysilicon and the back surface protrusion 16a must be completely removed.
This is because in the subsequent surface polishing step, when the active layer wafer 10 is attached to the wafer support plate of the wafer polishing apparatus with wax, the irregularities on the wafer back surface due to the polysilicon 16a are transferred to the wafer surface. This is because the polishing of the outer peripheral portion of the film becomes insufficient.
As a result, voids are likely to occur at the bonding interface at the time of bonding in the subsequent process, and this is one of the causes of defects in the bonded dielectric isolation wafer.
Further, when the grinding process is reached without completely removing the back surface protrusion 16a in the back surface polishing process, cracks and cracks of the active layer wafer 10 caused by the back surface protrusion 16a are generated during the grinding, and this is also applied to the bonding dielectric. The cause of the defect of the body separation wafer.
[0006]
OBJECT OF THE INVENTION
Accordingly, the present invention provides a method for producing a bonded dielectric isolation wafer capable of removing high temperature polysilicon deposited on the back surface of a large number of active layer wafers in a short time. And that is the purpose.
The present invention also provides a bonded dielectric isolation wafer capable of performing mirror finishing and decontamination of a ground surface of a high-temperature polysilicon layer before bonding on a large number of semiconductor wafers in a short time. Its purpose is to provide a method.
[0007]
[Means for Solving the Problems]
The invention described in claim 1 includes a step of growing a high-temperature polysilicon layer on the surface of the active layer wafer via a dielectric isolation oxide film, and a back surface of the active layer wafer on which the high-temperature polysilicon layer is grown. an etching step that goes around it HTPS and the high-temperature poly-silicon is removed backside projection deposited in projecting, planarizing after grinding the high-temperature polysilicon layer, the flattened high-temperature polysilicon layer A step of growing a low-temperature polysilicon layer on the surface of the substrate, and a step of forming a bonded wafer by bonding the surface of the active layer wafer to the surface of the support substrate wafer with the surface of the low-temperature polysilicon layer as the bonding surface. a step of chamfering the outer peripheral portion of the laminated wafer, thereafter, grinding and polishing the wafer for the active layer from the back side In the manufacturing method of the laminated dielectric isolated wafer and a step of revealing the plurality of dielectric isolation silicon separated by a dielectric isolation oxide film, the etching step, a first alkaline etching using an alkaline etching solution This is a method of manufacturing a bonded dielectric isolation wafer performed by the above method.
[0008]
The high-temperature CVD method is a method in which a source gas containing silicon is introduced into a reaction furnace together with a carrier gas (such as H ₂ gas), and silicon generated by thermal decomposition or reduction of the source gas on a silicon wafer heated to a high temperature. Is a method of precipitating. As the compound containing silicon, SiCl ₂ H ₂ , SiHCl ₃ , SiCl _{4 and the} like are usually used.
As the reaction furnace, for example, a pancake type furnace, a cylinder type furnace, or the like can be adopted.
[0009]
The growth temperature of high-temperature polysilicon differs depending on the furnace heating method. In the most common vertical furnace used for this purpose, 1200 to 1290 ° C, particularly 1320 to 1280 ° C is preferable. If it is less than 1200 degreeC, the problem that a silicon wafer tends to break will arise. Further, when the temperature exceeds 1290 ° C., slip occurs, and there is a disadvantage that the silicon wafer is abnormally warped or easily cracked.
The thickness of the high-temperature polysilicon layer is set to a thickness obtained by adding the thickness of the high-temperature polysilicon layer desired to remain to the thickness two to three times the depth of the anisotropic etching. If the thickness of the high-temperature polysilicon layer is less than twice the depth of anisotropic etching, the etching groove may not be sufficiently filled. On the other hand, if it is 3 times or more, it grows unnecessarily thick, which is uneconomical.
[0010]
As this anisotropic etching solution, KOH (IPA / KOH / H ₂ O), KOH (KOH / H ₂ O), or KOH (hydrazine / KOH / H ₂ O) can be used. Normal conditions can be applied to the anisotropic etching conditions.
Moreover, general conditions can be adopted as the conditions of each step for forming the window portion for anisotropic etching in the resist film on the wafer surface side.
[0011]
There are no limitations on the type of alkaline etching solution used in the first alkaline etching for removing the high temperature polysilicon and the rear surface protrusions that have wrapped around the back surface of the active layer wafer. For example, 5 to 15% by weight of potassium hydroxide and 0.1 to 1.0% by weight of hydrogen peroxide according to claim 4 may be mixed with pure water. After the first alkaline etching , it is better to perform the HF cleaning according to claim 3.
The planarization finish of the ground surface of the high-temperature polysilicon layer is not limited to the second alkaline etching of claim 2. For example, mirror finish by general polishing may be used.
The temperature of the alkaline etchant during the first alkaline etching for removing the backside wrapping polysilicon is not limited. For example, 60-90 degreeC of Claim 5 may be sufficient.
[0012]
Further, the active layer wafer may be rotated as described in claim 6 when removing the backside wrapping polysilicon. Moreover, it is not necessary to rotate. In addition, when rotating, the rotational speed may be 20 rpm or less of Claim 6, and it is good also as other rotational speed.
[0013]
Invention according to claim 2, said Oite the step of flattening the grinding surface of the high-temperature polysilicon layer, according to claim 1 which is flattened by the second alkali etching using an alkaline etching solution This is a method for manufacturing a laminated dielectric separated wafer.
As the alkali etching solution used for the second alkali etching , for example , the alkali etching solution used for the first alkali etching can be used.
[0014]
A third aspect of the present invention is a method for manufacturing a bonded dielectric isolation wafer according to the first or second aspect, wherein HF cleaning is performed after the first alkaline etching and the second alkaline etching .
Here, the first alkaline etching includes the case of removing the high-temperature polysilicon that has wrapped around the back surface of the wafer according to claim 1 .
HF cleaning is based on a general cleaning method.
[0015]
According to a fourth aspect of the present invention, the alkali etching solution at the time of the first alkali etching and the alkali etching solution at the time of the second alkali etching are 5 to 15% by weight of potassium hydroxide and 0.1 to 1 of hydrogen peroxide. The method for producing a bonded dielectric isolation wafer according to any one of claims 1 to 3, wherein 0.0 wt% is mixed with pure water.
A preferable addition amount of potassium hydroxide is 6 to 8% by weight. If it is less than 5% by weight, the etching rate is lowered, and the ability to remove backside protrusions is lowered. On the other hand, if it exceeds 15% by weight, although there is no particular problem in terms of quality, the amount of chemical solution used increases, resulting in high costs.
And the preferable addition amount of hydrogen peroxide is 0.1 to 0.5 weight%. If it is less than 0.1% by weight, surface roughness becomes severe. On the other hand, if it exceeds 1.0% by weight, the etching rate is lowered and the ability to remove the back projections is lowered.
[0016]
Invention of Claim 5 is temperature of the alkali etching liquid at the time of said 1st alkali etching, and the alkali etching liquid at the time of 2nd alkali etching is 60-90 degreeC, Among Claims 1-4, A method for producing a bonded dielectric isolation wafer according to any one of the preceding items.
The liquid temperature of the alkali etching solution at the time of preferable 1st alkali etching and the alkali etching solution at the time of 2nd alkali etching is 80-85 degreeC. If it is less than 60 ° C., the etching rate is lowered, and there is a disadvantage that the ability to remove the back surface protrusion is lowered. On the other hand, when the temperature exceeds 90 ° C., there is no particular problem in quality, but the heating temperature of the line heater increases and the durability of the heater may decrease.
[0017]
According to a sixth aspect of the present invention, in the first to fifth aspects, the first alkaline etching is performed while the active layer wafer is rotated around its axis at 20 rpm or less. This is a method for manufacturing a laminated dielectric separated wafer.
If it exceeds 20 rpm, a problem of dust generation due to rubbing between the semiconductor wafer and the rack occurs. However, there is usually no problem in quality even if it is rotated at a high speed.
The wafer rotating device is not limited. For example, a device that stores a large number of semiconductor wafers in a rack in a lump and rotates the rack by a rotary motor can be used.
[0018]
[Action]
According to the present invention, after the growth of high-temperature polysilicon on the surface of the dielectric isolation oxide film, the high-temperature polysilicon and the back surface protrusions that have wrapped around the back surface of the active layer wafer by the first alkaline etching in which the etching surface is not easily roughened Remove. Thereby, the high-temperature polysilicon grown on the back surface of a large number of active layer wafers can be removed in a short time. If the semiconductor wafer is rotated at 20 rpm or less during the first alkaline etching , even a large rear surface protrusion that is difficult to be melted can be processed in a relatively short time without significantly roughening the etched surface.
[0019]
In particular, according to the invention of claim 2, since the planarization finish of the ground surface of the high-temperature polysilicon layer before bonding is performed by the second alkali etching using the second alkali etching solution , a large number of semiconductors With respect to the wafer, mirror finishing and contamination removal of the ground surface of the high-temperature polysilicon layer before bonding can be performed collectively in a short time.
[0020]
According to the invention of claim 6, since the first alkali etching is performed while rotating the active layer wafer at 20 rpm or less, dust generation due to rubbing between the active layer wafer and the rack holding the active layer wafer is suppressed. Effective etching can be performed.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
A method for manufacturing a bonded dielectric isolation wafer according to an embodiment of the present invention will be described below. Here, a method for manufacturing a bonded dielectric isolation wafer described in the prior art section will be described as an example. Accordingly, the same parts are denoted by the same reference numerals.
First, a silicon wafer 10 having a diameter of 4 to 6 inches in which the surface to be the active layer wafer is mirror-finished is prepared and prepared (FIG. 2A). The plane orientation is (100).
Next, the silicon wafer 10 is cleaned. Then, a mask oxide film 11 having a thickness of, for example, 1 μm is formed on the surface of the silicon wafer (FIG. 2B). Instead of the mask oxide film 11, a nitride film (SiNx) may be grown by CVD.
[0022]
Next, a photoresist film 12 is deposited on the mask oxide film 11 using a known photolithography process. Then, a window having a predetermined pattern is formed in the photoresist film 12 as usual (FIG. 2C).
Subsequently, through this window, a window having the same pattern is formed in the oxide film 11 by etching, and a part of the surface of the silicon wafer 10 is exposed. Thereafter, the photoresist film 12 is removed (also in FIG. 2C). Then, the wafer surface is cleaned.
Further, using the oxide film 11 as a mask, the silicon wafer 10 is immersed in an anisotropic etching solution (IPA / KOH / H ₂ O) for a predetermined time. As a result, concave portions (dents) having a predetermined pattern are formed on the surface of the silicon wafer. That is, anisotropic etching is performed on the wafer surface to form a dielectric separating groove 13 having a V-shaped cross section (also in FIG. 2C).
[0023]
Next, the mask oxide film 11 is removed by washing with, for example, dilute HF liquid (FIG. 2D).
Thereafter, if necessary, a dopant is implanted into the silicon, and then a dielectric isolation oxide film 14 having a predetermined thickness is formed on the wafer surface (also the back surface) by an oxidation heat treatment (FIG. 2E). At this time, the dielectric isolation oxide film 14 is also formed on the dielectric isolation trench 13. Then, the wafer surface is cleaned.
Subsequently, a seed polysilicon layer 15 is deposited to a predetermined thickness on the surface of the silicon wafer 10, that is, on the dielectric isolation oxide film 14 on the surface side (FIG. 2 (f)). Clean the surface after deposition.
[0024]
Next, a high temperature polysilicon layer 16 is grown on the surface of the seed polysilicon layer 15 to a thickness of about 150 μm by a high temperature CVD method at about 1200 to 1300 ° C. (also FIG. 2F). At this time, a part of the high-temperature polysilicon wraps around and adheres to the back surface of the wafer, and a part of the high-temperature polysilicon is deposited in a protrusion shape to form the back surface protrusion 16a. For this reason, first, after chamfering the outer peripheral portion of the wafer, the silicon wafer 10 is put into the alkali etching apparatus 30 (hereinafter sometimes simply referred to as an etching apparatus) 30 in FIG. The polysilicon and the back surface protrusion 16a that wrap around the back surface are removed. Thereby, the wafer back surface is flattened (FIG. 2G). In addition, since the mirror finish by alkali etching is employed as described above, the back surface processing of a large number of silicon wafers 10 can be performed in a short time as compared with the conventional polishing. The alkaline etching solution is an alkaline solution in which 6 to 10% by weight of potassium hydroxide and 0.1 to 0.5% by weight of hydrogen peroxide are dissolved in pure water. During etching, the liquid temperature is kept at 80 to 85 ° C. After the alkali etching, the etched surface is HF cleaned.
[0025]
Here, with reference to FIG. 1, the removal process by the etching apparatus 30 of back surface surrounding polysilicon and back surface protrusion 16a is demonstrated in detail.
As shown in FIG. 1, the etching apparatus 30 includes an SUS etching tank 31 and a wafer rotating mechanism 32 that is inserted into the etching tank 31.
The wafer rotation mechanism 32 has a rack 33, a motor 34, and a belt 35, and rotates a plurality of silicon wafers 10 loaded and mounted on the rack 33 around its central axis. Specifically, the rack 33 is configured by connecting two circular side plates 36 and 37 having a diameter larger than that of the silicon wafer 10 through three shafts 38 to 40. The shafts 38 to 40 are all disposed on the outer edge portions of the side plates 36 and 37, and the two shafts 38 and 39 are opposed to each other at a distance of about 180 degrees. The remaining shaft 40 is provided with grooves at regular intervals in the axial length direction. The grooved shaft 40 is positioned below the drive shaft when the silicon wafer 10 is mounted on the rack 33. A Teflon gear 41 is fixed to one end of the shaft 40, and the belt 35 is stretched between the gear 41 and the gear 42 fixed to the output shaft end of the motor 34. Yes.
[0026]
Therefore, when the output shaft of the motor 34 is rotated, the rotational force is transmitted to the drive-side shaft 40 via the gear 42, the belt 35, and the gear 41. As the shaft 40 rotates about the axis, a large number of silicon wafers 10 in which a part of the outer edge of the wafer is fitted in each groove rotate about each wafer central axis. The rotation speed here is 5 to 10 rpm. Thus, since the wafer rotation speed by the wafer rotation mechanism 32 is set to a low speed (5 to 10 rpm), the wafer back surface is effectively flattened while suppressing dust generation due to rubbing between the silicon wafer 10 and the rack 33. In other words, the polysilicon around the back surface including the back surface protrusion 16a can be melted away.
[0027]
Next, as shown in FIG. 2, the high-temperature polysilicon layer 16 on the wafer surface is ground to a thickness of about 10 to 80 μm and then polished. After polishing, dewaxing and cleaning are performed, and a low-temperature polysilicon layer 17 having a thickness of 1 to 5 μm is formed on the wafer surface by a low-temperature CVD method at 550 to 700 ° C. Furthermore, the surface of the low-temperature polysilicon layer 17 is polished for the purpose of mirroring the bonded surface (FIG. 2 (h)).
On the other hand, a mirror-finished silicon wafer 20 having a diameter of 4 to 6 inches covered with a silicon oxide film 21 to be a support substrate wafer is prepared (FIG. 2 (i)).
Next, the silicon wafer 10 for the active layer wafer is bonded to the silicon wafer 20 with its mirror surfaces in contact with each other (FIG. 2 (j)). Then, this is heat-treated to increase the bonding strength of the bonded wafer.
[0028]
Subsequently, the outer peripheral portion of the bonded wafer is chamfered (FIG. 2 (k)). Thereafter, the surface of the active layer wafer 10 is ground and polished (FIG. 2 (l)). The amount of grinding / polishing of the active layer wafer 10 at this time is such that the dielectric isolation oxide film 14 is exposed to the outside, and the dielectric isolation separated by the dielectric isolation oxide film 14 on the surface of the high-temperature polysilicon layer 16 is performed. The silicon island 10A appears, and the amount is such that adjacent silicon islands are completely separated. As a result, a bonded dielectric isolation wafer is manufactured.
[0029]
Next, a method for manufacturing a bonded dielectric isolation wafer according to a second embodiment of the present invention will be described with reference to FIG.
FIG. 3 is a cross-sectional view for explaining a method for manufacturing a bonded dielectric isolation wafer according to a second embodiment of the present invention.
In the method of manufacturing the bonded dielectric isolation wafer according to the second embodiment, after removing the polysilicon including the back surface protrusion 16a that wraps around the back surface of the silicon wafer 10 (FIG. 3G), the high temperature poly on the wafer surface is obtained. The silicon layer 16 is ground to a thickness of about 10 to 80 μm (FIG. 3 (h1)), and then the etching apparatus is used in the same manner as in FIG. 2 (g) instead of the polishing step of the first embodiment (FIG. 2 (h)). Alkali etching using 30 is performed. Thus, the wafer grinding surface is mirror-finished (FIG. 3 (h2)). After this alkali etching, the etched surface is HF cleaned. A low-temperature polysilicon layer 17 is formed on the wafer surface (FIG. 3 (h3)).
As described above, since the mirror finish of the ground surface of the high-temperature polysilicon layer 16 before bonding is performed by alkali etching, mirror processing of a large number of silicon wafers 10 can be performed in a short time. .
Other configurations, operations, and effects are the same as those of the first embodiment, and thus description thereof is omitted.
[0030]
Here, referring to the graph of FIG. 4, the silicon etching is actually performed by two different methods, ie, the alkali etching process shown in FIG. 2G of the first embodiment and the conventional polishing process corresponding thereto. The degree of flatness (SBIR) of the back surface of the outer peripheral portion of the wafer when the high-temperature polysilicon including the back surface protrusion 16a that wraps around the back surface of the wafer 10 is removed will be reported.
FIG. 4 is a graph showing the difference in flatness when removing back-around polysilicon by alkali etching of the present invention and conventional polishing.
As is apparent from the comparison of the two bar graphs, the removal of the back-around polysilicon by alkali etching was not much different in flatness from the removal by mirror finishing.
[0031]
【The invention's effect】
According to the present invention, after the high temperature polysilicon is grown on the surface of the dielectric isolation oxide film, the high temperature polysilicon and the back surface protrusion that have wrap around the back surface of the active layer wafer are removed by the first alkaline etching . Thereby, the high-temperature polysilicon deposited on the back surface of a large number of active layer wafers can be removed at once in a short time.
[0032]
In particular, according to the invention of claim 2, since the mirror finish of the ground surface of the high-temperature polysilicon layer before bonding is performed by the second alkali etching using the second alkali etching solution , a large number of semiconductor wafers As for, the mirror finish and the contamination removal of the ground surface of the high-temperature polysilicon layer before pasting can be performed in a short time in a lump.
[0033]
According to the sixth aspect of the invention, since the first alkali etching is performed while rotating the active layer wafer at 20 rpm or less, dust generation due to rubbing between the active layer wafer and the rack holding the active layer wafer is performed. Effective etching can be performed while suppressing.
[Brief description of the drawings]
FIG. 1 is a perspective view showing an alkaline etching apparatus used in a method for producing a bonded dielectric isolation wafer according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view for explaining a method of manufacturing a bonded dielectric isolation wafer according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view for explaining a method for manufacturing a bonded dielectric isolation wafer according to a second embodiment of the present invention.
FIG. 4 is a graph showing a difference in flatness when removing backside polysilicon by alkali etching of the present invention and conventional polishing.
FIG. 5 is a cross-sectional view for explaining a manufacturing process of a conventional bonded dielectric isolation wafer.
[Explanation of symbols]
10 Silicon wafer (wafer for active layer),
10A dielectric isolation silicon island,
14 Dielectric isolation oxide film,
16 high temperature polysilicon layer,
16a Back projection,
17 Low temperature polysilicon layer,
20 Wafer for support substrate.

Claims (6)

Growing a high-temperature polysilicon layer on the surface of the active layer wafer via a dielectric isolation oxide film;
Etching process for removing the high temperature polysilicon that wraps around the back surface of the active layer wafer on which the high temperature polysilicon layer has been grown , and the back surface protrusion on which the high temperature polysilicon is deposited in a protruding shape ,
Planarizing after grinding the high-temperature polysilicon layer,
Growing a low-temperature polysilicon layer on the surface of the planarized high-temperature polysilicon layer ;
Forming the bonded wafer by bonding the surface of the low-temperature polysilicon layer to the surface of the support substrate wafer, using the surface of the low-temperature polysilicon layer as the bonding surface;
Chamfering the outer periphery of the bonded wafer;
Thereafter, the active layer wafer is ground and polished from the back side to reveal a plurality of dielectric isolation silicon separated by the dielectric isolation oxide film. ,
The said etching process is a manufacturing method of the bonding dielectric isolation | separation wafer performed by the 1st alkali etching using alkaline etching liquid . The Oite the step of flattening the grinding surface of the high-temperature polysilicon layer, the manufacturing method of the laminated dielectric isolated wafer according to claim 1 which is flattened by the second alkali etching using an alkaline etching solution . The method for manufacturing a bonded dielectric isolation wafer according to claim 1, wherein HF cleaning is performed after the first alkali etching and the second alkali etching . The alkali etching solution at the time of the first alkali etching and the alkali etching solution at the time of the second alkali etching are mixed with 5 to 15% by weight of potassium hydroxide and 0.1 to 1.0% by weight of hydrogen peroxide in pure water. The method for producing a bonded dielectric isolation wafer according to any one of claims 1 to 3, wherein: The bonding dielectric according to any one of claims 1 to 4, wherein the temperature of the alkali etching solution during the first alkali etching and the temperature of the alkali etching solution during the second alkali etching is 60 to 90 ° C. Manufacturing method of body separation wafer. The method for producing a bonded dielectric isolation wafer according to any one of claims 1 to 5, wherein the first alkali etching is performed while rotating the wafer for active layer at 20 rpm or less around its axis. .

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