JP3671866B2 - Method for determining capacitance value of semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a method for determining a capacitance value of a capacitor used therein.
[0002]
[Prior art]
In a semiconductor memory device, a method is mainly used in which charges are accumulated in a capacitor formed in the semiconductor device, and data is stored depending on the presence or absence of the charges (generally referred to as a dynamic method memory. This type of memory is hereinafter referred to as a DRAM). In the conventional capacitor, a silicon oxide film is used as an insulating film.
[0003]
In recent years, a semiconductor memory device has been devised that attempts to realize non-volatility of stored data by using a ferroelectric material for an insulating film of a capacitor.
[0004]
A conventional semiconductor memory device using a ferroelectric material will be described below (see US Pat. No. 4,873,664).
[0005]
13 is a circuit configuration diagram of a conventional semiconductor memory device, FIG. 14 is a diagram illustrating the sense amplifier units 90 and 96 of FIG. 13 showing the circuit configuration of the conventional semiconductor memory device, and FIG. 15 is an operation timing of the conventional semiconductor memory device. FIG. 16 is a diagram showing a hysteresis characteristic of a ferroelectric in a memory cell capacitor of a conventional semiconductor memory device and data reading of the memory cell.
[0006]
In the figure, Vr16 is a data read potential difference of the memory cell, l1 and l2 are lines indicating the parasitic capacitance characteristics of the bit line, and A, B, D, E, M16, N16, O16, P16 and Q16 are data read of the memory cell. , 80a to 80d are memory cells, 81a to 81d are memory cell transistors, 82 and 84 are word lines (WORD), 83a to 83d are memory cell capacitors using a ferroelectric film, 86 and 88 , 92, 94 are bit lines, 90, 96 are sense amplifiers, 98, 100 are cell plate electrodes (PLATE), 102, 104, 106, 108 are bit line precharge transistors, φPRECHARGE is a bit line precharge control signal, φSENSE is a sense amplifier control signal, 110 and 112 are P-channel MOS transistors, 118 and 120 are N-channel MOS transistors, and 114 and 116 are signal nodes.
[0007]
In the circuit configuration of the conventional semiconductor memory device of FIG. 13, bit lines 86 and 88 are connected to a sense amplifier 90. Main memory cells 80a and 80b are connected to the bit lines 86 and 88, respectively. In the main body memory cell 80a, the first main body memory cell capacitor 83a is connected to the bit line 86 via the first MOS transistor 81a. Second main body memory cell capacitor 83a is connected to bit line 88 via second MOS transistor 81a. The gates of the first and second MOS transistors 81a are connected to the word line 82, and the first electrodes connected to the sources of the first and second MOS transistors 81a of the first and second main body memory cell capacitors 83a. The second electrode opposite to is connected to the cell plate electrode 98. The same applies to the main body memory cells 80b to 80d. The bit lines 86 and 88 are connected to the ground voltage via MOS transistors 106 and 108 whose gates are the bit line precharge control signal φPRECHARGE. As shown in FIG. 14, in the sense amplifier 90, the source of the N-channel MOS transistor 118 is connected to the ground voltage, the gate is connected to the signal node 116, the drain is connected to the signal node 114, and the P-channel MOS transistor 110 is connected. Are connected to φPRECHARGE. The gate is connected to the signal node 116, the drain is connected to the signal node 114, the source of the N-channel MOS transistor 120 is connected to the ground voltage, the gate is connected to the signal node 114, and the drain is connected to the signal node 116. The channel type MOS transistor 112 has a source connected to φPRECHARGE, a gate connected to the signal node 114, and a drain connected to the signal node 116. In the conventional semiconductor memory device of FIG. 13, one memory cell is composed of two memory cell capacitors and two MOS transistors. A reverse logic voltage is written to the two memory cell capacitors, and at the time of reading, the potential difference read from each of the two memory cell capacitors is amplified by a sense amplifier to read data.
[0008]
The operation of the circuit of this conventional semiconductor memory device will be described with reference to the operation timing chart of FIG. 15 and the hysteresis characteristics of the ferroelectric substance of the memory cell capacitor and the data reading of the memory cell of FIG.
[0009]
In the hysteresis characteristic diagram of the ferroelectric substance in FIG. 16, the horizontal axis indicates the electric field applied to the memory cell capacitor, and the vertical axis indicates the electric charge at that time. In a ferroelectric capacitor, remanent polarization remains at points B and E even when the electric field is zero. As described above, the residual polarization remaining in the ferroelectric capacitor even after the power is turned off is used as nonvolatile data to realize a nonvolatile semiconductor memory device. When the data in the memory cell is “1”, the first main body memory cell capacitor is in the state of point B in FIG. 16, and the second main body memory cell capacitor is in the state of point E in FIG. When the data in the memory cell is “0”, the first main body memory cell capacitor is in the state of point E in FIG. 16, and the second main body memory cell capacitor is in the state of point B in FIG.
[0010]
Here, in order to read the data of the main body memory cell, the bit lines 86 and 88, the word lines 82 and 84, the cell plate electrode 98, and the sense amplifier control signal φSENSE are all at the logic voltage “L” as an initial state. Bit line precharge control signal φPRECHARGE is at a logic voltage “H”. Thereafter, the bit line precharge control signal φPRECHARGE is set to the logic voltage “L”, and the bit lines 86 and 88 are set in a floating state. Next, as shown in FIG. 15, the word line 82 and the cell plate electrode 98 are set to the logic voltage “H”. Here, the MOS transistor 81a is turned on. For this reason, an electric field is applied to the main body memory cell capacitor 83a, and data is read from the main body memory cell to the bit lines 86 and 88.
[0011]
The potential difference read to the bit line at this time will be described with reference to FIG. Lines 11 and 12 shown in FIG. 16 are lines having an inclination determined by the parasitic capacitance values of the bit lines 86 and 88. The absolute value of the slope decreases as the capacitance value decreases. When the data to be read is “1”, data is read from the first main body memory cell capacitor to the bit line 86, and the state from the point B in FIG. At the point O16, when an electric field is applied to the memory cell capacitor, the hysteresis curve from the point B to the point D and the electric field generated when the logic voltage between the word line 82 and the cell plate electrode 98 is set to “H”. This is an intersection with the line l1 passing through the point M16 moved in the horizontal axis direction from the point B. Similarly, data is read from the second main body memory cell capacitor to the bit line 88, and the state from the point E in FIG. At the point P16, when an electric field is applied to the memory cell capacitor, the hysteresis curve from the point E to the point D and the electric field generated when the logic voltage between the word line 82 and the cell plate electrode 98 is set to “H”. This is the intersection with the line 12 passing through the point N16 moved in the horizontal axis direction from the point E. Here, the potential difference read to the bit line 86 and the bit line 88 is Vr16 which is an electric field difference between the point O16 and the point P16 in FIG. The same is true when the data to be read is “0”. The potential difference to be read is Vr16 only by the state of the bit line 86 and the bit line 88 being reversed. Next, the sense amplifier control signal φSENSE is set to the logic voltage “H”, and the data read to the bit line 86 and the bit line 88 is amplified by the sense amplifier 90 to read the data. When amplified by the sense amplifier 90, the state of the bit line 86 changes from the point O16 to the point Q16, and the state of the bit line 88 changes from the point P16 to the point D. Next, the cell plate electrode 98 is set to the logic voltage “L” as a data rewrite state. At this time, in FIG. 16, the state of the bit line 86 changes from the point Q16 to the point A, and the state of the bit line 88 changes from the point D to the point E. Next, the word line 82 and the sense amplifier control signal φSENSE are set to the logic voltage “L”. Thereafter, the bit line precharge control signal φPRECHARGE is set to the logic voltage “H”, and the bit lines 86 and 88 are set to the logic voltage “L” to be in the initial state.
[0012]
[Problems to be solved by the invention]
In the semiconductor memory device having the conventional configuration as described above, in FIG. 16, when the parasitic capacitance value of the bit line decreases, the absolute value of the slope of the lines l1 and l2 decreases. For example, when the parasitic capacitance value of the bit line becomes almost zero, the position of the point O16 approaches the point B, and the position of the point P16 approaches the point E. The read potential difference Vr16 generated between the bit line 86 and the bit line 88 approaches zero. Therefore, there is a problem that this potential difference cannot be accurately amplified by the sense amplifier 90. Similarly, when the bit line parasitic capacitance value is a certain value, the read potential difference Vr16 generated between the bit line 86 and the bit line 88 becomes small even if the capacitance of the ferroelectric capacitor is too small or too large. There is a problem that the potential difference cannot be amplified accurately by the sense amplifier 90.
[0013]
[Means for Solving the Problems]
In order to solve this problem, according to a method for determining a capacitance value of a semiconductor memory device of the present invention, a first bit line and a second bit line paired with a first bit line are connected to an amplifier, A first word line, a first ferroelectric capacitor, and a first bit line are connected to the MOS transistor, the first ferroelectric capacitor is connected to the first plate electrode, and the second MOS transistor In A second word line, a first capacitor, and a second bit line; But In a semiconductor memory device in which the first capacitor is connected to the second plate electrode, the first data when the data of the logic voltage “H” is read from the first ferroelectric capacitor to the first bit line is connected. Potential difference between bit line potential and second bit line potential when data of logic voltage “L” is read from first ferroelectric capacitor to first bit line Is represented by a characteristic having a maximum value with respect to the capacitance value of the first ferroelectric capacitor, and a potential difference between the first bit line potential and the second bit line potential; Relationship with capacitance value of first ferroelectric capacitor curve Seeking The potential difference between the first bit line potential and the second bit line potential is More than twice the potential difference that can be accurately amplified by an amplifier Relation curve range In addition, the capacitance value of the first ferroelectric capacitor is determined, and the third bit line potential when the data from the first capacitor is read to the second bit line is equal to the first bit line potential and the second bit line potential. The potential difference between the first bit line potential and the third bit line potential and the potential difference between the second bit line potential and the third bit line potential are both determined by an amplifier. The capacitance value of the first capacitor is determined so that the potential difference can be accurately amplified.
[0014]
According to another aspect of the present invention, there is provided a method for determining a capacitance value of a semiconductor memory device, wherein a first bit line and a second bit line paired with a first bit line are connected to an amplifier, and the first MOS transistor is connected to the first MOS transistor. A first word line, a first ferroelectric capacitor, and a first bit line are connected, a first ferroelectric capacitor is connected to a first plate electrode, and a second MOS transistor In A second word line, a first capacitor, and a second bit line; But In a semiconductor memory device in which the first capacitor is connected to the second plate electrode, the reading of data from the first capacitor is an operation that does not involve polarization inversion, and the logic voltage is applied from the first ferroelectric capacitor. A first bit line potential when reading “H” data to the first bit line, and a second when reading data of logic voltage “L” from the first ferroelectric capacitor to the first bit line. Potential difference from bit line potential Is represented by a characteristic having a maximum value with respect to the capacitance value of the first ferroelectric capacitor, and a potential difference between the first bit line potential and the second bit line potential; Relationship with capacitance value of first ferroelectric capacitor curve Seeking The potential difference between the first bit line potential and the second bit line potential is More than twice the potential difference that can be accurately amplified by an amplifier Relation curve range In addition, the capacitance value of the first ferroelectric capacitor is determined, and the third bit line potential when the data from the first capacitor is read to the second bit line is equal to the first bit line potential and the second bit line potential. The potential difference between the first bit line potential and the third bit line potential and the potential difference between the second bit line potential and the third bit line potential are both determined by an amplifier. The capacitance value of the first capacitor is determined so that the potential difference can be accurately amplified.
[0015]
The first capacitor is a ferroelectric capacitor.
[0016]
Further, the first capacitor is a ferroelectric capacitor having a shape similar to that of the first ferroelectric capacitor.
[0017]
By the method of determining the capacitance value of the semiconductor memory device operating as described above, the data read potential difference of the memory cell can be increased, and a semiconductor memory device free from malfunction during reading can be obtained.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
A first embodiment showing a method for determining a capacitance value of a semiconductor memory device of the present invention will be described with reference to the drawings. 1 is a diagram illustrating a circuit configuration of a semiconductor memory device according to the present invention, FIG. 2 is a diagram illustrating an operation timing of the semiconductor memory device according to the present invention, and FIGS. It is a figure which shows the hysteresis characteristic of the ferroelectric substance of the memory cell capacitor of the 1st-3rd capacitance value in 1st Embodiment, and the data reading of a memory cell.
[0019]
First, the circuit configuration diagram of FIG. 1 will be described. WL0 to WL7 are word lines, BL0, / BL0, BL1, and / BL1 are bit lines, CP0 to CP7 are cell plate electrodes, EQ101 is a bit line equalize and precharge control signal, SAE100 is a sense amplifier control signal, and VSS is a ground voltage. SA0 and SA1 are sense amplifiers, Cs00 to Cs17 and Cs00B to Cs17B are main body memory cell capacitors, and Qn is an N-channel MOS transistor.
[0020]
Bit lines BL0 and / BL0 are connected to sense amplifier SA0, and bit lines BL1 and / BL1 are connected to sense amplifier SA1, respectively. The operations of the sense amplifiers SA0 and SA1 are controlled by a sense amplifier control signal SAE100. A first electrode of the main body memory cell capacitor Cs00 is connected to the bit line BL0 via an N-channel MOS transistor Qn. The second electrode of the main body memory cell capacitor Cs00 is connected to the cell plate electrode CP0. The first electrode of the main body memory cell capacitor Cs00B is connected to the bit line / BL0 via the N channel type MOS transistor Qn, and the second electrode of the main body memory cell capacitor Cs00B is connected to the cell plate electrode CP0. . Similarly, the first electrodes of the main body memory cell capacitors Cs01 to Cs07 are connected to the bit line BL0 via the N-channel MOS transistor Qn, and the second electrodes of the main body memory cell capacitors Cs01 to Cs07 are respectively set. The first electrodes of the main body memory cell capacitors Cs01B to Cs07B are connected to the bit line / BL0 via the N-channel MOS transistor Qn and connected to the cell plate electrodes CP1 to CP7, and the main memory cell capacitors Cs01B to Cs07B Each second electrode is connected to cell plate electrodes CP1 to CP7, respectively. Similarly, the main body memory cell capacitors Cs10 to Cs17 and Cs10B to Cs17B are connected so that data is read out to the bit lines BL1 and / BL1. Bit lines BL0, / BL0 and bit lines BL1, / BL1 are configured to be equalized and precharged by bit line equalize and precharge control signal EQ101. Here, the precharge potential is the ground voltage.
[0021]
In FIG. 3, Vr3 is the data read potential difference of the memory cell, l1 and l2 are lines indicating the characteristics of the bit line capacitance, and A, B, D, E, M3, N3, O3, P3 and Q3 are the data read of the memory cell. It is a point in the figure. FIG. 3 is a hysteresis characteristic diagram of a ferroelectric as in the prior art, where the horizontal axis represents the electric field applied to the memory cell capacitor and the vertical axis represents the electric charge at that time. In a ferroelectric capacitor, remanent polarization remains at points B and E even when the electric field is zero. A nonvolatile semiconductor memory device is realized by utilizing the residual polarization remaining in the ferroelectric capacitor even when the power is turned off as nonvolatile data. When the data in the memory cell is “1”, the first main body memory cell capacitor is in the state of point B in FIG. 3 and the second main body memory cell capacitor is in the state of point E. When the data in the memory cell is “0”, the first main body memory cell capacitor is in the state of point E, and the second main body memory cell capacitor is in the state of point B.
[0022]
4 and 5 are also the same as FIG. 3, Vr4 and Vr5 are data read potential differences of memory cells, A, B, D, E, M4, N4, O4, P4, Q4, M5, N5, O5, P5, Q5. Is a point in the diagram showing data reading of the memory cell. The capacity of the main body memory cell capacitor is the largest in the case of FIG. 3, the next largest in the case of FIG. 4, and the smallest in the case of FIG.
[0023]
Here, in the case of FIG. 3, a method of reading data from the main body memory cell capacitors Cs00 and Cs00B will be described. First, in order to read data of the main body memory cell, as an initial state, the bit lines BL0, / BL0, the word lines WL0 to WL7, the cell plate electrodes CP0 to CP7, and the sense amplifier control signal SAE100 are set to the logic voltage “L”. The bit line precharge control signal EQ101 is set to a logic voltage “H”. Thereafter, when the bit line precharge control signal EQ101 is set to the logic voltage “L”, the bit lines BL0 and / BL0 are in a floating state. Next, the word line WL0 and the cell plate electrode CP0 are set to the logic voltage “H”. At this time, an electric field is applied to the main body memory cell capacitors Cs00 and Cs00B. In this way, data is read from the main body memory cell to the bit lines BL0 and / BL0. The potential difference read to the bit line at this time will be described with reference to FIG. The lines l1 and l2 have a slope depending on the parasitic capacitance values of the bit lines BL0 and / BL0. The absolute value of the slope decreases as the capacitance value decreases. When the read data is “1”, the data is read from the main body memory cell capacitor Cs00 to the bit line BL0, and the state from the point B in FIG. 3 changes to the point O3. A point O3 is when a logic voltage “H” is applied to the hysteresis curve of the ferroelectric memory cell capacitor from the point B to the point D and the word line WL0 and the cell plate electrode CP0 when an electric field is applied to the memory cell capacitor. This is an intersection with the line l1 passing through the point M3 moved in the horizontal axis direction from the point B by the amount of the generated electric field. Similarly, data is read from the main body memory cell capacitor Cs00B to the bit line / BL0, and the state from the point E to the state of the point P3 is changed. Point P3 corresponds to a hysteresis curve from point E to point D when an electric field is applied to the memory cell capacitor, and point E corresponding to the electric field generated when word line WL0 and cell plate electrode CP0 are set to logic voltage "H". Is an intersection with a line l2 passing through a point N3 moved in the horizontal axis direction. Here, the potential difference read between the bit lines BL0 and / BL0 is Vr3, which is the electric field difference between the points O3 and P3. Similarly, when the data to be read is “0”, the potential difference to be read is Vr3 only by the state of / BL0 being the same as that of the bit line BL0 being reversed. Next, when the sense amplifier control signal SAE100 is set to the logic voltage “H”, the data read to the bit lines BL0 and / BL0 is amplified and read by the sense amplifier SA0. When amplified by the sense amplifier SA0, the state of the bit line BL0 changes from the point O3 to the point Q3, and the state of the bit line / BL0 changes from the point P3 to the point D. Next, the cell plate electrode CP0 is set to the logic voltage “L” as a data rewrite state. At this time, the state of the bit line BL0 is changed from the point Q3 to the point A, and the state of the bit line / BL0 is changed from the point D to the point E. Thereafter, the word line WL0 and the sense amplifier control signal SAE100 are set to the logic voltage “L”. Thereafter, the bit line precharge control signal EQ101 is set to the logic voltage “H”, and the bit lines BL0 and / BL0 are set to the logic voltage “L” to set the initial state. In this operation, the potential difference Vr3 read to the bit lines BL0 and / BL0 must be a potential difference that can be accurately amplified by the sense amplifier SA0. The main body memory cell capacitor capacitance value (curve ABDEA) is determined so as to satisfy this. By determining the capacitance value of the main body memory cell capacitor so that the potential difference Vr3 is as large as possible, more accurate and faster amplification by the sense amplifier is possible.
[0024]
3 to 5, the data read potential difference of the memory cells Vr3 to Vr5 is large in Vr4, and Vr3 and Vr5 are smaller than Vr4. FIG. 6 shows the relationship between the main body memory cell capacitor capacitance value Cs and the potential difference Vr read between the bit lines BL0 and / BL0. As can be seen from FIG. 6, the potential difference Vr is represented by a curve having a maximum value with respect to the main body memory cell capacitor capacitance value Cs. In FIG. 6, Vrm indicates a minimum readable potential difference value that can be accurately amplified by the sense amplifier. Of the intersections of Vrm and the curve in the figure, the smaller main body memory cell capacitor capacitance value is Csl, and the larger main memory cell capacitor capacitance value is Csh. From this figure, the value Cs of the main body memory cell capacitor capacity needs to be between Csl and Csh. If the value Cs of the main body memory cell capacitor capacitance is between Csl and Csh, the use of a smaller value results in less deterioration of the ferroelectric film constituting the main body memory cell capacitor. In addition, the area of the main body memory cell capacitor is reduced, and high integration is achieved.
[0025]
7 shows a circuit configuration diagram of FIG. 7, an operation timing diagram of FIG. 8, a hysteresis characteristic of a ferroelectric substance of a memory cell capacitor and a memory in a second embodiment showing a method for determining a capacitance value of a semiconductor memory device of the present invention. This will be described with reference to the drawing showing cell data reading.
[0026]
In the first embodiment, one memory cell is composed of two memory cell capacitors and two MOS transistors, whereas in the second embodiment, one memory cell is one memory cell capacitor. The difference is that it is composed of one MOS transistor.
[0027]
First, the circuit configuration shown in FIG. 7 will be described. WL0 to WL3 are word lines, DWL0 and DWL1 are dummy word lines, BL0, / BL0, BL1, and / BL1 are bit lines, CP0 and CP1 are cell plate electrodes, DCP0 and DCP1 are dummy cell plate electrodes, and EQ11 is a bit line equalize and Precharge control signals, SAE0 and SAE1 are sense amplifier control signals, VSS is a ground voltage, SA0 and SA1 are sense amplifiers, Cs1 to Cs8 are main body memory cell ferroelectric capacitors, Cd1 to Cd4 are dummy memory cell ferroelectric capacitors, Qn is an N-channel MOS transistor. The main body memory cell is composed of main body memory cell ferroelectric capacitors Cs1 to Cs8 and N-channel MOS transistors Qn having word lines WL0 to WL3 connected to the gates. The first electrodes of the main body memory cell ferroelectric capacitors Cs1 to Cs8 are connected to the source of the N-channel MOS transistor Qn, and the second electrodes of the main body memory cell ferroelectric capacitors Cs1 to Cs8 are the cell plate electrodes CP0 and CP1. It is connected to the. The drains of the N-channel MOS transistors Qn constituting the main body memory cell are connected to bit lines BL0, / BL0, BL1, / BL1. Similarly, the dummy memory cell is composed of dummy memory cell ferroelectric capacitors Cd1 to Cd4 and an N-channel MOS transistor Qn having dummy word lines DWL0 and DWL1 connected to the gate. The first electrodes of the dummy memory cell ferroelectric capacitors Cd1 to Cd4 are connected to the source of the N-channel MOS transistor Qn, and the second electrodes of the dummy memory cell ferroelectric capacitors Cd1 to Cd4 are the dummy cell plate electrode DCP0. , DCP1. Further, the drains of the N channel type MOS transistors Qn constituting the dummy memory cells are connected to the bit lines BL0, / BL0, BL1, / BL1. The bit lines BL0, / BL0 and BL1, / BL1 are connected to sense amplifiers SA0 and SA1, respectively. The sense amplifiers SA0 and SA1 are controlled by sense amplifier control signals SAE0 and SAE1, respectively, and operate when the sense amplifier control signals SAE0 and SAE1 are all at the logic voltage “H”. Bit lines BL0, / BL0 and BL1, / BL1 are connected via an N channel type MOS transistor Qn whose gate is a bit line equalize and precharge control signal EQ11. Each of bit lines BL0, / BL0, BL1, / BL1 is connected to ground voltage VSS via an N-channel MOS transistor Qn whose gate is a bit line equalize and precharge control signal EQ11.
[0028]
Next, in FIG. 8 and FIG. 9, in order to read data of the main body memory cell, word lines WL0 to WL3, dummy word lines DWL0 and DWL1, cell plate electrodes CP0 and CP1, dummy cell plate electrodes DCP0 and DCP1 are set as initial states. The sense amplifier control signals SAE0 and SAE1 are set to the logic voltage “L”, the bit line equalization and precharge control signal EQ11 is set to the logic voltage “H”, and the bit line is set to the logic voltage “L”. Thereafter, the bit line equalization and precharge control signal EQ11 is set to the logic voltage “L”, and the bit line is set in a floating state. Next, when all of the word line WL1, the dummy word line DWL1, the cell plate electrode CP0, and the dummy cell plate electrode DCP0 are set to the logic voltage “H” in order to read the data of the main body memory cell capacitor Cs2, the dummy is applied to the bit line BL0. Data in the memory cell is read out, and data in the main body memory cell is read out to the bit line / BL0. At this time, when the data in the main body memory cell is “1”, the state from the point B in FIG. When the data in the main body memory cell is “0”, the state from the point E changes to the state of the point P9, and the dummy memory cell changes from the state of the point T9 to the state of the point S9. Thereafter, when the sense amplifier SA0 is operated by setting the sense amplifier control signal SAE0 to the logic voltage “H”, the data read to the bit lines BL0 and / BL0 is amplified. If the data of the main body memory cell is “1” in the state where the sense amplifier is operated and the data is amplified, the main body memory cell is changed from the state of point O9 to the state of point Q9, and the dummy memory cell is in the state of point S9. To point D. At this time, if the data in the main body memory cell is “0”, the main body memory cell changes from the state of the point P9 to the state of the point D, and the dummy memory cell changes from the state of the point S9 to the state of the point T9.
[0029]
Next, the cell plate electrode CP0 is set to the logic voltage “L”. At this time, if the data of the main body memory cell is “1”, the main body memory cell maintains the state of the point A from the state of the point Q9, and the dummy memory cell maintains the state of the point D. If the data of the main body memory cell is “0”, the main body memory cell maintains the state of the point D from the state of the point D, and the dummy memory cell maintains the state of the point T9. The word line WL1 and the dummy word line DWL1 are set to the logic voltage “L”. At this time, if the data in the main memory cell is “1”, the main memory cell is changed from the state of point A to a state between point A and point B, and the dummy memory cell is changed from the state of point D to point D and point T9. It becomes a state between. Thereafter, the dummy memory cell is brought to a state at point T9. If the data in the main memory cell is “0”, the main memory cell maintains the state of point E, and the dummy memory cell maintains the point T9. Next, the dummy cell plate electrode DCP0 is set to the logic voltage “L”, the sense amplifier control signal SAE0 is set to the logic voltage “L”, the bit line equalization and precharge control signal EQ11 is set to the logic voltage “H”, and the bit line is set to the logic voltage “L”.
[0030]
In the second embodiment, the read potential difference Vr9 between the data “1” and the data “0” of the main body memory cell is accurately detected by the sense amplifier on the lines l1, l2, and l3 having the gradient of the parasitic capacitance value of the bit line. The main body memory cell capacitor capacitance value is determined so as to be at least twice the potential difference that can be amplified. Next, in order to determine the capacitance value of the dummy memory cell, the logic voltage between the line indicating the capacitance of the dummy memory cell, that is, the line passing through the points D, S9, and T9, the word line WL0, and the cell plate electrode CP0 is set to “H”. The point of intersection with a line l3 (a line translated from lines l1 and l2) passing through a point R9 moved in the horizontal axis direction from the point T9 by the amount of the electric field generated immediately after “is defined as a point S9. At this time, the potential difference between the point S9 and the point P9 is Vl9, and the potential difference between the point S9 and the point O9 is Vh9 so that Vl9 and Vh9 are potential differences that can be accurately amplified by the sense amplifier. Ideally, Vl9 = Vh9 = Vr9 / 2. By determining the main body memory cell capacitor capacity and the dummy memory cell capacitor capacity in this manner, accurate and high-speed amplification can be performed by the sense amplifier. Here, a ferroelectric film is used for the dummy memory cell capacitor, but a normal capacitor may be used.
[0031]
A third embodiment of the semiconductor memory device of the present invention will be described with reference to the circuit configuration diagram of FIG. 10 and the operation timing diagram of FIG.
[0032]
First, the circuit configuration diagram of FIG. 10 will be described. This circuit has a configuration in which a capacitor is connected to a bit line via a MOS transistor having a switching function with respect to the circuit of the third embodiment. WL0 to WL3 are word lines, DWL0 and DWL1 are dummy word lines, BL0, / BL0, BL1, and / BL1 are bit lines, CP0 and CP1 are cell plate electrodes, DCP0 and DCP1 are dummy cell plate electrodes, and EQ11 is a bit line equalize and Precharge control signal, S100 and S101 are control signals, V10 is a signal, SAE0 and SAE1 are sense amplifier control signals, VSS is a ground voltage, SA0 and SA1 are sense amplifiers, Cs1 to Cs8 are main body memory cell ferroelectric capacitors, Cd1 Cd4 are dummy memory cell ferroelectric capacitors, Cb1 to Cb4 are bit line capacitance adjusting capacitors, and Qn is an N-channel MOS transistor. The main body memory cell is composed of main body memory cell ferroelectric capacitors Cs1 to Cs8 and N-channel MOS transistors Qn having word lines WL0 to WL3 connected to the gates. The first electrodes of the main body memory cell ferroelectric capacitors Cs1 to Cs8 are connected to the source of the N channel type MOS transistor Qn, and the second electrodes of the main body memory cell ferroelectric capacitors Cs1 to Cs8 are the cell plate electrodes CP0 and CP1. It is connected to the. The drains of the N-channel MOS transistors Qn constituting the main body memory cell are connected to bit lines BL0, / BL0, BL1, / BL1. Similarly, the dummy memory cell is composed of dummy memory cell ferroelectric capacitors Cd1 to Cd4 and an N-channel MOS transistor Qn having dummy word lines DWL0 and DWL1 connected to the gate. The first electrodes of the dummy memory cell ferroelectric capacitors Cd1 to Cd4 are connected to the source of the N-channel MOS transistor Qn, and the second electrodes of the dummy memory cell ferroelectric capacitors Cd1 to Cd4 are the dummy cell plate electrode DCP0. , DCP1. The drains of the N channel type MOS transistors Qn constituting the dummy memory cells are connected to the bit lines BL0, / BL0, BL1, / BL1. The bit lines BL0, / BL0 and BL1, / BL1 are connected to sense amplifiers SA0 and SA1, respectively. The sense amplifiers SA0 and SA1 are controlled by sense amplifier control signals SAE0 and SAE1, respectively, and operate when the sense amplifier control signals SAE0 and SAE1 are all at the logic voltage “H”. Bit lines BL0, / BL0 and BL1, / BL1 are connected via an N channel type MOS transistor Qn whose gate is a bit line equalize and precharge control signal EQ11. Each of the bit lines BL0, / BL0, BL1, / BL1 has a gate connected to the ground voltage VSS via an N-channel MOS transistor Qn which is a bit line equalize and precharge control signal EQ11. Capacitors Cb1, Cb2, Cb3, Cb4 are connected to the bit lines BL0, / BL0, BL1, / BL1 via N-channel MOS transistors Qn whose gates are signals S101, S100, S101, S100, respectively. Plate electrodes of Cb1, Cb2, Cb3, and Cb4 are connected to the signal V10. The potential of the signal V10 is appropriate depending on whether the capacitors Cb1 to Cb4 are ordinary capacitors or capacitors using a ferroelectric film, or in the case of a ferroelectric capacitor (how much curve portion of the hysteresis curve is used). Set the potential.
[0033]
Next, in order to read data of the main body memory cell, word lines WL0 to WL3, dummy word lines DWL0 and DWL1, cell plate electrodes CP0 and CP1, dummy cell plate electrodes DCP0 and DCP1, sense amplifier control signal SAE0, SAE 1 and control signals S100 and S101 are set to logic voltage “L”, bit line equalization and precharge control signal EQ11 is set to logic voltage “H”, and the bit line is set to logic voltage “L”. Thereafter, the bit line equalization and precharge control signal EQ11 is set to the logic voltage “L”, and the bit line is set in a floating state. Next, in order to read data from the main body memory cell capacitor Cs2, the word line WL1, the dummy word line DWL1, the cell plate electrode CP0, the dummy cell plate electrode DCP0, and the control signal S101 are all set to the logic voltage “H”. Data of the dummy memory cell is read to BL0, and data of the main body memory cell is read to the bit line / BL0. Here, the bit line capacity adjustment capacitor is added to the bit line from which the data of the dummy memory cell is read to increase the capacity, and the dummy memory cell has the same size as the main body memory cell capacitor. This is because an appropriate reference voltage is obtained when data “1” is read from the memory cell. The bit line capacitance adjusting capacitor may be a ferroelectric film or a normal capacitor.
[0034]
A fourth embodiment of the semiconductor memory device of the present invention will be described with reference to the circuit configuration diagram of FIG. 10 and the operation timing diagram of FIG.
[0035]
First, the circuit configuration diagram of FIG. 10 is the same as that of the third embodiment.
[0036]
Next, in order to read data of the main body memory cell, word lines WL0 to WL3, dummy word lines DWL0 and DWL1, cell plate electrodes CP0 and CP1, dummy cell plate electrodes DCP0 and DCP1, sense amplifier control signal SAE0, SAE1 is set to the logic voltage “L”, the bit line equalization / precharge control signal EQ11 and the control signals S100 and S101 are set to the logic voltage “H”, and the bit line is set to the logic voltage “L”. Thereafter, the bit line equalization and precharge control signal EQ11 is set to the logic voltage “L”, and the bit line is set in a floating state. Next, in order to read data from the main body memory cell capacitor Cs2, all of the word line WL1, the dummy word line DWL1, the cell plate electrode CP0, and the dummy cell plate electrode DCP0 are set to the logic voltage “H”, and the control signal S101 is set to the logic voltage “L”. Then, the data of the dummy memory cell is read to the bit line BL0, and the data of the main body memory cell is read to the bit line / BL0. Here, the bit line capacity adjustment capacity of the bit line from which the data of the dummy memory cell is read out is electrically cut to reduce the capacity, so that the dummy memory cell is the same as the main body memory cell capacitor. Is used to obtain an appropriate reference voltage when data is read from data “0” of the memory cell. The bit line capacitance adjusting capacitor may be a ferroelectric film or a normal capacitor.
[0037]
【The invention's effect】
According to the semiconductor memory device using the ferroelectric film for the memory cell capacitor and the capacitance value determining method thereof according to the present invention, the optimum capacitance value of the memory cell ferroelectric capacitor is set according to the parasitic capacitance value of the bit line. As a result, the data read potential difference of the memory cell can be increased, and a semiconductor memory device free from malfunction during reading can be obtained.
[Brief description of the drawings]
FIG. 1 is a diagram showing a circuit configuration of a first embodiment showing a method for determining a capacitance value of a semiconductor memory device of the present invention;
FIG. 2 is a diagram showing the operation timing of the first embodiment showing the capacitance value determining method of the semiconductor memory device of the present invention;
FIG. 3 shows a ferroelectric hysteresis characteristic and memory cell data reading of a memory cell capacitor having a first capacitance value in the first embodiment showing a method for determining the capacitance value of the semiconductor memory device of the present invention; Figure
4 shows a ferroelectric hysteresis characteristic of a memory cell capacitor having a second capacitance value and data reading of the memory cell in the first embodiment showing the capacitance value determining method of the semiconductor memory device of the present invention. FIG. Figure
FIG. 5 shows a ferroelectric hysteresis characteristic of a memory cell capacitor having a third capacitance value and data reading of the memory cell in the first embodiment showing a method for determining the capacitance value of the semiconductor memory device of the present invention; Figure
FIG. 6 is a relationship diagram between a capacitance value of a memory cell capacitor and a data read potential difference in the first embodiment showing a method for determining a capacitance value of a semiconductor memory device according to the present invention;
FIG. 7 is a diagram showing a circuit configuration of a second embodiment showing a method for determining a capacitance value of a semiconductor memory device according to the present invention;
FIG. 8 is a diagram showing the operation timing of the second embodiment showing the method for determining the capacitance value of the semiconductor memory device of the present invention;
FIG. 9 is a diagram showing hysteresis characteristics of a ferroelectric memory cell capacitor and data reading of the memory cell in the second embodiment showing the capacitance value determining method of the semiconductor memory device of the present invention;
FIG. 10 is a diagram showing a circuit configuration of third and fourth embodiments showing a semiconductor memory device of the present invention;
FIG. 11 is a diagram showing the operation timing of the third embodiment showing the semiconductor memory device of the present invention;
FIG. 12 is a diagram showing the operation timing of the fourth embodiment showing the semiconductor memory device of the present invention;
FIG. 13 is a diagram showing a circuit configuration of a conventional semiconductor memory device.
FIG. 14 is a diagram showing a sense amplifier portion of a circuit configuration of a conventional semiconductor memory device.
FIG. 15 is a diagram showing the operation timing of a conventional semiconductor memory device.
FIG. 16 is a diagram showing hysteresis characteristics of a ferroelectric memory cell capacitor and data reading of a memory cell in a conventional semiconductor memory device.
[Explanation of symbols]
l1-l3 lines
80a-80d memory cell
81a to 81d memory cell transistor
82 Word line (WORD)
83a to 83d memory cell capacitors
84 Word line (WORD)
86,88 bit line
90 sense amplifier
92,94 bit lines
96 sense amplifier
98,100 Cell plate electrode (PLATE)
102, 104, 106, 108 Bit line precharging transistors
110, 112 P-channel MOS transistor
114, 116 signal nodes
118,120 N-channel MOS transistor
BL0, / BL0, BL1, / BL1 bit lines
Cb1 to Cb4 Bit line capacitance adjustment capacitors
S100, S101, V10 control signal
Csh, Csl Main body memory cell capacity value
Cd1 to Cd4 dummy memory cell capacitors
CP0 to CP7 Cell plate electrode
Cs00 to Cs17, Cs00B to Cs17B, Cs1 to Cs8 Main body memory cell capacitor
DCP0, DCP1 Dummy cell plate electrode
DWL0, DWL1 Dummy word line
EQ11, EQ101 Bit line equalization and precharge control signal
Qn N-channel MOS transistor
SA0, SA1 sense amplifier
SAE100, SAE101 Sense amplifier control signal
Vl9, Vh9, Vr3 to Vr5, Vr16 Potential difference
Vrm Minimum potential difference value that can be read
VSS Ground voltage
WL0 to WL7 Word line
φPRECHARGE Bit line precharge control signal
φSENSE Sense amplifier control signal

Claims (4)

A first bit line and a second bit line paired with the first bit line are connected to the amplifier, and a first word line, a first ferroelectric capacitor, and the first MOS transistor are connected to the first MOS line. 1 bit line is connected, the first ferroelectric capacitor is connected to the first plate electrode , the second word line, the first capacitor, and the second bit line are connected to the second MOS transistor. : it is connected, the semiconductor memory device in which the first capacitor is connected to a second plate electrode,
The first bit line potential when the data of the logic voltage “H” is read from the first ferroelectric capacitor to the first bit line, and the logic voltage “L” from the first ferroelectric capacitor. The potential difference from the second bit line potential when reading data to the first bit line is represented by a characteristic having a maximum value with respect to the capacitance value of the first ferroelectric capacitor,
Obtaining a relationship curve between a potential difference between the first bit line potential and the second bit line potential and a capacitance value of the first ferroelectric capacitor;
In the range of the relational curve, the potential difference between the first bit line potential and the second bit line potential is more than twice the potential difference that can be accurately amplified by the amplifier. Determine the capacitance value of the capacitor,
A third bit line potential when reading data from the first capacitor to the second bit line is an intermediate potential between the first bit line potential and the second bit line potential; The potential difference between the first bit line potential and the third bit line potential and the potential difference between the second bit line potential and the third bit line potential are both greater than the potential difference that can be accurately amplified by the amplifier. A method for determining a capacitance value of a semiconductor memory device, wherein the capacitance value of the first capacitor is determined as follows. A first bit line and a second bit line paired with the first bit line are connected to the amplifier, and a first word line, a first ferroelectric capacitor, and the first MOS transistor are connected to the first MOS line. 1 bit line is connected, the first ferroelectric capacitor is connected to the first plate electrode , the second word line, the first capacitor, and the second bit line are connected to the second MOS transistor. : it is connected, the semiconductor memory device in which the first capacitor is connected to a second plate electrode,
Reading data from the first capacitor is an operation without polarization inversion,
The first bit line potential when the data of the logic voltage “H” is read from the first ferroelectric capacitor to the first bit line, and the logic voltage “L” from the first ferroelectric capacitor. The potential difference from the second bit line potential when reading data to the first bit line is represented by a characteristic having a maximum value with respect to the capacitance value of the first ferroelectric capacitor,
Obtaining a relationship curve between a potential difference between the first bit line potential and the second bit line potential and a capacitance value of the first ferroelectric capacitor;
In the range of the relational curve, the potential difference between the first bit line potential and the second bit line potential is more than twice the potential difference that can be accurately amplified by the amplifier. Determine the capacitance value of the capacitor,
A third bit line potential when reading data from the first capacitor to the second bit line is an intermediate potential between the first bit line potential and the second bit line potential; The potential difference between the first bit line potential and the third bit line potential and the potential difference between the second bit line potential and the third bit line potential are both greater than the potential difference that can be accurately amplified by the amplifier. A method for determining a capacitance value of a semiconductor memory device, wherein the capacitance value of the first capacitor is determined as follows. 3. The method of determining a capacitance value of a semiconductor memory device according to claim 1, wherein the first capacitor is a ferroelectric capacitor. 4. Said first capacitor, a semiconductor memory device according to any one of claims 1 or 2, characterized in that said first ferroelectric capacitor and the ferroelectric capacitor is comparable in shape Capacity value determination method.

Images