JP3243939B2 - Semiconductor memory device and method of determining capacitance value thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a semiconductor memory device.
And a method of determining a capacitance value of a capacitor used in the method .

[0002]

2. Description of the Related Art In a semiconductor memory device, a method of accumulating charges in a capacitor formed in the semiconductor device and storing data depending on the presence or absence of the charges is mainly used (generally, a dynamic memory). Memory is called DRAM), and its capacitor is
A silicon oxide film is used as an insulating film.

In recent years, a semiconductor memory device has been devised to realize non-volatility of stored data by using a ferroelectric material for an insulating film of a capacitor.

A conventional semiconductor memory device using a ferroelectric material will be described below (US Pat. No. 4,873,6).
No. 64).

FIG. 13 is a diagram showing a circuit configuration of a conventional semiconductor memory device, FIG. 14 is a diagram showing the sense amplifier units 90 and 96 of FIG. 13 showing a circuit configuration of a conventional semiconductor memory device, and FIG.
Is a diagram showing the operation timing of the conventional semiconductor memory device,
FIG. 16 is a diagram showing a hysteresis characteristic of a ferroelectric in a memory cell capacitor of a conventional semiconductor memory device and data reading of a memory cell.

In the figure, Vr16 is a data read potential difference of a memory cell, l1 and l2 are lines showing characteristics of a parasitic capacitance of a bit line, A, B, D, E, M16, N16, O1.
6, P16 and Q16 are points in the figure showing data reading of the memory cells, 80a to 80d are memory cells, and 81a to 8
1d is a memory cell transistor, 82 and 84 are word lines (WORD), 83a to 83d are memory cell capacitors using a ferroelectric film, 86, 88, 92 and 94 are bit lines, 90 and 96 are sense amplifiers, 98 , 100 are cell plate electrodes (PLATE), 102, 104, 106,
108 is a bit line precharge transistor, φPR
ECHARGE is a bit line precharge control signal, φS
ENSE is a sense amplifier control signal, 110 and 112 are P
Channel type MOS transistors, 118 and 120 are N-channel type MOS transistors, and 114 and 116 are signal nodes.

[0007] In the circuit configuration of the conventional semiconductor memory device shown in FIG. 13, bit lines 86 and 88 are connected to a sense amplifier 90. The main memory cells 8 are connected to the bit lines 86 and 88.
0a and 80b are connected. Main body memory cell 80a
Means that the first main body memory cell capacitor 83a has the first M
It is connected to the bit line 86 via the OS transistor 81a. Second main body memory cell capacitor 83a is connected to bit line 88 via second MOS transistor 81a. The gates of the first and second MOS transistors 81a are connected to a word line 82, and the first electrodes connected to the sources of the first and second MOS transistors 81a of the first and second main body memory cell capacitors 83a. The second electrode opposite to the above is a cell plate electrode 98.
It is connected to the. The same applies to the main body memory cells 80b to 80d. The bit lines 86 and 88 have their gates connected to the bit line precharge control signal φPRECCHARG.
It is connected to the ground voltage via MOS transistors 106 and 108 which are E. Also, the sense amplifier 90
As shown in FIG. 14, the source of N-channel MOS transistor 118 is at the ground voltage, and the gate is at signal node 11.
6, the drain is connected to the signal node 114, and the source of the P-channel type MOS transistor 110 is connected to φPRECHARGE. The gate is connected to the signal node 116 and the drain is connected to the signal node 114, respectively.
20 have a source at ground voltage and a gate at signal node 114.
The drains are respectively connected to the signal nodes 116,
The source of the P-channel MOS transistor 112 is φP
RECHARGE has a gate connected to the signal node 114 and a drain connected to the signal node 116.
In the conventional semiconductor memory device of FIG. 13, one memory cell is composed of two memory cell capacitors and two MOS transistors. Reverse logic voltages are written to the two memory cell capacitors, and at the time of reading, data is read by amplifying the potential difference read from each of the two memory cell capacitors by a sense amplifier.

The operation of the circuit of the conventional semiconductor memory device will be described with reference to the operation timing chart of FIG. 15 and the diagram showing the hysteresis characteristic of the ferroelectric of the memory cell capacitor and the data reading of the memory cell of FIG. I do.

In the hysteresis characteristic diagram of the ferroelectric shown in FIG. 16, the horizontal axis indicates the electric field applied to the memory cell capacitor, and the vertical axis indicates the electric charge at that time. In a ferroelectric capacitor, residual polarization remains as shown at points B and E even when the electric field is zero. As described above, the nonvolatile semiconductor memory device is realized by utilizing the residual polarization remaining in the ferroelectric capacitor even after the power is turned off as nonvolatile data. When the data of the memory cell is “1”, the first main body memory cell capacitor is in the state of point B in FIG. 16, and the second main body memory cell capacitor is in the state of point E in FIG. When the data of the memory cell is "0", the first main body memory cell capacitor is in the state of point E in FIG. 16, and the second main body memory cell capacitor is in the state of point B in FIG.

Here, in order to read the data of the main memory cell, the bit lines 86 and 88, the word lines 82 and 84, the cell plate electrode 98, and the sense amplifier control signal φSENSE are all set to the logic voltage “L” in the initial state. And the bit line precharge control signal φPRECHARG
E is the logic voltage “H”. Thereafter, the bit line precharge control signal φPRECHARGE is set to the logic voltage “L”, and the bit lines 86 and 88 are set in a floating state.
Next, as shown in FIG. 15, the word line 82 and the cell plate electrode 98 are set to the logic voltage “H”. Here, the MOS transistor 81a is turned on. Therefore, an electric field is applied to the main body memory cell capacitor 83a, and data is read from the main body memory cell to the bit lines 86 and 88.

The potential difference read to the bit line at this time will be described with reference to FIG. Lines l1 and l2 shown in FIG. 16 are lines having inclinations determined by the parasitic capacitance values of the bit lines 86 and 88. As the capacitance value decreases, the absolute value of the gradient decreases. When the data to be read is "1", data is read from the first main body memory cell capacitor to the bit line 86, and the state changes from the state at the point B to the state at the point O16 in FIG. Point O16 is a hysteresis curve from point B to point D when an electric field is applied to the memory cell capacitor, word line 82 and cell plate electrode 9
A line 11 passing through a point M16 shifted in the horizontal axis direction from the point B by an electric field generated when the logic voltage with the logic 8 is set to "H"
Is the intersection with Similarly, data is read from the second main body memory cell capacitor to the bit line 88, and FIG.
From the state of point E to the state of point P16. Point P16 corresponds to a hysteresis curve from point E to point D when an electric field is applied to the memory cell capacitor, and an electric field generated when the logic voltage between word line 82 and cell plate electrode 98 is set to "H". Point N16 moved in the horizontal axis direction from point E
Are the intersections with the line l2 passing through. Here, the potential difference read to the bit line 86 and the bit line 88 is the point O1 in FIG.
Vr16, which is the electric field difference between 6 and the point P16. The same applies to the case where the data to be read is “0”. Only the states of the bit lines 86 and 88 are reversed, and the potential difference to be read is Vr16. Next, the sense amplifier control signal φ
SENSE is set to the logic voltage “H”, and the data read to the bit lines 86 and 88 are amplified by the sense amplifier 90 to read the data. When amplified by the sense amplifier 90, the state of the bit line 86 changes from point O16 to point Q16, and the state of the bit line 88 changes from point P16 to point D. Next, the cell plate electrode 9 is set as a data rewrite state.
8 is a logic voltage “L”. At this time, in FIG. 16, the state of the bit line 86 changes from the point Q16 to the point A, and the state of the bit line 88 changes from the point D to the point E. Next, the word line 82 and the sense amplifier control signal φSENSE are set to the logic voltage “L”. After that, the bit line precharge control signal φPRECHARGE is set to the logic voltage “H”, and the bit lines 86 and 88 are set to the logic voltage “L” to be in an initial state.

[0012]

In the semiconductor memory device having the conventional configuration as described above, in FIG. 16, when the parasitic capacitance value of the bit line decreases, the absolute value of the inclination of the lines l1 and l2 decreases. For example, when the parasitic capacitance value of the bit line becomes almost 0, the position of the point O16 approaches the point B,
The position of 16 approaches the point E. Bit line 86 and bit line 8
8 and the read potential difference Vr16 approaching 0. For this reason, there has been a problem that the sense amplifier 90 cannot accurately amplify this potential difference. Similarly, when the bit line parasitic capacitance value is a certain value, the read potential difference Vr16 generated between the bit line 86 and the bit line 88 regardless of whether the capacitance of the ferroelectric capacitor is too small or too large.
And the potential difference cannot be accurately amplified by the sense amplifier 90.

[0013]

In order to solve this problem, a method of determining a capacitance value of a semiconductor memory device according to the present invention comprises the steps of: providing an amplifier with a first bit line and a second bit line paired with a first bit line; Are connected to the first MOS transistor, the first word line, the first ferroelectric capacitor and the first bit line are connected to the first MOS transistor, and the first ferroelectric capacitor is connected to the first MOS transistor.
Semiconductor memory device connected to the plate electrode of
And a voltage generated between the first bit line and the second bit line.
Find the relationship between the potential difference and the capacitance value of the first ferroelectric capacitor.
Therefore, the potential difference is less than the potential difference that can be accurately amplified by the amplifier.
Set the capacitance value of the first ferroelectric capacitor in the range above
Set.

The capacitance value of the first ferroelectric capacitor
And it is set to be smaller in the above range.

In addition, the content of another semiconductor memory device of the present invention.
In the method of determining the quantity value, a first bit line and a second bit line paired with the first bit line are connected to the amplifier, and the first M
The first word line, the first ferroelectric capacitor, and the first bit line are connected to the OS transistor, the first ferroelectric capacitor is connected to the first plate electrode, and the second MOS transistor is connected to the OS transistor. In a semiconductor memory device connected to a second word line, a first capacitor, and a second bit line, and the first capacitor is connected to a second plate electrode .
The logic voltage "H" from the first ferroelectric capacitor .
First bit line voltage, the logic voltage of the first ferroelectric capacitor when to exit read data to the first bit line "L"
Potential difference can be accurately amplified by the amplifier and the second bit line potential when to exit read the data into the first bit line
The capacitance value of the first ferroelectric capacitor determined as a value at least twice the potential difference, data from the first capacitor
Third bit line potential when to exit read the data to the second bit line is intermediate the first bit line potential and the second bit line potential
And the first bit line potential and the third bit line potential.
Potential difference, second bit line potential and third bit
Both the potential difference from the line potential is accurately amplified by the amplifier
Capacity of the first capacitor so that the potential difference becomes greater than
Determine the value .

Further, the first capacitor is a ferroelectric capacitor. Further, the first capacitor is a ferroelectric capacitor having a shape similar to that of the first ferroelectric capacitor.

Further, the semiconductor memory device of the present invention has an amplification
A first bit line and a second bit line paired with the first bit line
Are connected to the first MOS transistor,
1 word line, 1st ferroelectric capacitor and 1st bit.
And the first ferroelectric capacitor is connected to the first
Connected to the plate electrode and the second MOS transistor
A second word line, a first capacitor, a second bit line,
And the first capacitor is connected to the second plate electrode
Connected to the second bit line of the first capacitor.
When reading data, the capacity of the second bit line
A capacitance adjusting capacitance is connected and is larger than the capacitance of the first bit line.
The logic voltage "H" of the first ferroelectric capacitor
At the time of reading data to the first bit line.
Bit line potential and logic voltage of first ferroelectric capacitor
"L" and when reading data to the first bit line
The potential difference from the second bit line potential becomes a first desired value
The capacitance of the first ferroelectric capacitor is determined as
When reading data from the first capacitor to the second bit line
Of the first bit line and the second bit line
To a potential of a second desired value intermediate to the potential of the cut line.
, The capacitance of the first capacitor is determined . Also, the first
The bit line capacitance adjusting capacitance is a ferroelectric capacitor.

Further , another semiconductor memory device of the present invention comprises:
Amplifier paired with first bit line and first bit line
A second MOS transistor connected to a second bit line;
The first word line, the first ferroelectric capacitor and the first
And the first ferroelectric capacitor is connected to the bit line.
The second MOS transistor connected to the first plate electrode
A second word line, a first capacitor and a second bit
And the first capacitor is connected to the second plate
Pole to the first capacitor to the second bit line.
At the time of data reading, the first bit
And the capacitance of the first bit line is cut off.
The smaller the logic voltage of the first ferroelectric capacitor
"H" and when reading data to the first bit line
Logic of first bit line potential and first ferroelectric capacitor
Read data to the first bit line at voltage "L"
The potential difference from the second bit line potential at the time to the first desired value
The capacitance of the first ferroelectric capacitor is determined so that
Read data from the first capacitor to the second bit line.
The third bit line potential at the time of output is the same as the first bit line potential.
2 bit line potential and a potential of a second desired value intermediate between the bit line potentials.
Thus, the capacitance of the first capacitor is determined.

Further, the first bit line capacitance adjusting capacitance is a ferroelectric capacitor.

[0020]

According to the semiconductor memory device having the above configuration and operation and the method of determining the capacitance value thereof , the data read potential difference between the memory cells can be increased, and a semiconductor memory device free from malfunction during reading can be provided.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for determining a capacitance value of a semiconductor memory device according to the present invention.
A first embodiment showing a will be described with reference to the drawings. FIG. 1 is a diagram showing a circuit configuration of a semiconductor memory device of the present invention, FIG. 2 is a diagram showing operation timing of the semiconductor memory device of the present invention, and FIGS.
FIG. 6 is a diagram showing hysteresis characteristics of ferroelectrics of memory cell capacitors having first to third capacitance values and data reading of memory cells in the first embodiment of the capacitance value determining method .

First, the circuit diagram of FIG. 1 will be described. WL0 to WL7 are word lines, BL0, / BL0, B
L1 and / BL1 are bit lines, CP0 to CP7 are cell plate electrodes, EQ101 is a bit line equalize and precharge control signal, SAE100 is a sense amplifier control signal, VSS is a ground voltage, SA0 and SA1 are sense amplifiers, Cs00 to Cs17, Cs00B to Cs17B are main body memory cell capacitors, and Qn is an N-channel MOS transistor.

The bit lines BL0, / 0 are connected to the sense amplifier SA0.
BL0 connects the bit lines BL1, / B to the sense amplifier SA1.
L1 are respectively connected. The sense amplifiers SA0,
The operation of SA1 is controlled by the sense amplifier control signal SAE100. The first electrode of the main body memory cell capacitor Cs00 is connected to the bit line BL0 via the N-channel MOS transistor Qn. The second electrode of the main body memory cell capacitor Cs00 is a cell plate electrode C
Connected to P0. Body memory cell capacitor Cs
The first electrode of 00B is connected to the bit line / BL0 via an N-channel MOS transistor Qn, and the second electrode of the main memory cell capacitor Cs00B is connected to the cell plate electrode CP0. Similarly, the first of each of the main body memory cell capacitors Cs01 to Cs07
Are connected to the bit line BL0 via an N-channel MOS transistor Qn, the second electrodes of the main body memory cell capacitors Cs01 to Cs07 are respectively connected to the cell plate electrodes CP1 to CP7, and the main body memory cell capacitor Cs01B To Cs07B are connected to bit line / BL0 via an N-channel MOS transistor Qn, and second electrodes of main body memory cell capacitors Cs01B to Cs07B are connected to cell plate electrodes CP1 to CP7, respectively. It is connected. Main body memory cell capacitors Cs10 to Cs1
7, Cs10B to Cs17B are similarly connected so that data is read to bit lines BL1 and / BL1. The bit lines BL0 and / BL0 and the bit lines BL1 and / BL1 are configured to be equalized and precharged by a bit line equalize and precharge control signal EQ101. Here, the precharge potential is a ground voltage.

In FIG. 3, Vr3 is a data read potential difference of a memory cell, l1 and l2 are lines showing characteristics of bit line capacitance, A, B, D, E, M3, N3, O3, P3 and Q3.
Is a point in the diagram showing data reading of a memory cell. FIG. 3 is a hysteresis characteristic diagram of the ferroelectric, as in the conventional case, in which the horizontal axis indicates the electric field applied to the memory cell capacitor and the vertical axis indicates the electric charge at that time. In a ferroelectric capacitor, residual polarization remains as shown at points B and E even when the electric field is zero. A non-volatile semiconductor memory device is realized by using residual polarization remaining in a ferroelectric capacitor even as power is turned off, as non-volatile data. When the data of the memory cell is "1", the first main body memory cell capacitor is shown in FIG.
In the state of point B, the second main body memory cell capacitor is in the state of point E. When the data of the memory cell is “0”,
The first main body memory cell capacitor is at the point E,
Is in the state of point B.

FIGS. 4 and 5 are also similar to FIG.
Vr5 is the data read potential difference of the memory cell, A, B,
D, E, M4, N4, O4, P4, Q4, M5, N5
O5, P5, and Q5 are points in the diagram showing data reading from the memory cells. The capacity of the main body memory cell capacitor is the largest in the case of FIG. 3 among the three, the case of FIG. 4 is the next largest, and the case of FIG. 5 is the smallest of the three.

Here, a method of reading data from the main body memory cell capacitors Cs00 and Cs00B in the case of FIG. 3 will be described. First, in order to read data from the main body memory cell, the bit line BL
0, / BL0, word lines WL0-WL7, cell plate electrodes CP0-CP7, and sense amplifier control signal S
The AE100 is set to the logic voltage “L”, and the bit line precharge control signal EQ101 is set to the logic voltage “H”. Thereafter, when the bit line precharge control signal EQ101 is set to the logic voltage “L”, the bit lines BL0 and / BL0 are in a floating state. Next, the word line WL0 and the cell plate electrode CP0 are set to the logic voltage “H”. At this time, an electric field is applied to the main body memory cell capacitors Cs00 and Cs00B. In this way, BL0, //
Data is read to the BL0 bit line. The potential difference read to the bit line at this time will be described with reference to FIG. Lines l1 and l2 are bit lines BL0 and / BL
It has a slope depending on the value of the parasitic capacitance of 0. As the capacitance value decreases, the absolute value of the gradient decreases. When the data to be read is "1", the data is read from the main body memory cell capacitor Cs00 to the bit line BL0, and the state changes from the point B to the point O3 in FIG. Point O3 is when the electric field is applied to the memory cell capacitor, when the hysteresis curve of the ferroelectric memory cell capacitor from point B to point D, and when the word line WL0 and the cell plate electrode CP0 are set to the logic voltage “H”. This is an intersection with a line 11 passing through a point M3 moved in the horizontal axis direction from the point B by the amount of the generated electric field.
Similarly, data is read from the main body memory cell capacitor Cs00B to the bit line / BL0, and the state changes from the point E to the point P3. The point P3 corresponds to the hysteresis curve from the point E to the point D when an electric field is applied to the memory cell capacitor and the point E3 corresponding to the electric field generated when the word line WL0 and the cell plate electrode CP0 are set to the logic voltage "H".
Is an intersection with a line l2 passing through a point N3 moved in the horizontal axis direction from. Here, the potential difference read between the bit lines BL0 and / BL0 is Vr3 which is the electric field difference between the point O3 and the point P3. Similarly, when the data to be read is "0", the bit line BL0 and the state of / BL0 are only reversed, and the potential difference to be read is Vr3. Next, when the sense amplifier control signal SAE100 is set to the logic voltage “H”, the data read to the bit lines BL0 and / BL0 is amplified and read by the sense amplifier SA0. Sense amplifier SA
When the signal is amplified by 0, the state of the bit line BL0 changes from the point O3 to the point Q3, and the state of the bit line / BL0 changes from the point P3 to the point D. Next, the cell plate electrode CP0 is set to the logic voltage “L” in a data rewriting state. At this time,
The state of bit line BL0 is from point Q3 to point A, and the state of bit line / BL0 is from point D to point E. After that, the word line WL0 and the sense amplifier control signal SAE100 are set to the logic voltage “L”. Thereafter, the bit line precharge control signal EQ101 is set to the logic voltage “H”, and the bit line BL
0 and / BL0 are set to the logic voltage "L" to bring them to the initial state. The potential difference Vr3 read to the bit lines BL0 and / BL0 by this operation must be a potential difference that can be accurately amplified by the sense amplifier SA0. In order to satisfy this, the capacitance value of the main body memory cell capacitor (curve ABDEA)
To determine. By determining the capacitance value of the main body memory cell capacitor so that the potential difference Vr3 becomes as large as possible, more accurate and high-speed amplification by the sense amplifier becomes possible.

In the case of the capacitance values of the main body memory cell capacitors shown in FIGS. 3 to 5, the data read potential difference between the memory cells of Vr3 to Vr5 is Vr4, and Vr3 and Vr5 are Vr4.
Smaller. Body memory cell capacitor capacitance Cs
Potential difference V read between bit lines BL0 and / BL0
FIG. 6 shows the relationship with r. As can be seen from FIG. 6, the potential difference Vr is represented by a curve having the maximum value with respect to the capacitance value Cs of the main body memory cell capacitor. In FIG. 6, Vrm indicates the lowest potential difference value at which data can be read by the sense amplifier accurately. Of the intersections of Vrm and the curves in the figure, the smaller one of the capacitance values of the main body memory cell capacitor is Csl, and the larger one of the capacitance values of the main body memory cell capacitor is Csh. As shown in this figure, the value Cs of the capacitance of the main body memory cell capacitor needs to be between Csl and Csh. The value of the capacitance Cs of the main body memory cell capacitor is Cs
Between l and Csh, the smaller the value, the less the deterioration of the ferroelectric film forming the main memory cell capacitor. In addition, the area of the main body memory cell capacitor is reduced, and high integration is achieved.

Method of Determining Capacitance of Semiconductor Memory Device of the Present Invention
The second embodiment showing the method will be described with reference to the circuit configuration diagram of FIG. 7, the operation timing diagram of FIG. 8, and the diagram showing the hysteresis characteristic of the ferroelectric of the memory cell capacitor and the data reading of the memory cell of FIG. explain.

In the first embodiment, one memory cell is composed of two memory cell capacitors and two MOS transistors, whereas in the second embodiment, one memory cell is composed of one memory cell capacitor. And that it is composed of one MOS transistor.

First, the circuit configuration shown in FIG. 7 will be described. WL0 to WL3 are word lines, DWL0 to DWL1
Is a dummy word line, BL0, / BL0, BL1, / BL
1 is a bit line, CP0 and CP1 are cell plate electrodes, D
CP0 and DCP1 are dummy cell plate electrodes, EQ11
Is a bit line equalize and precharge control signal, S
AE0 and SAE1 are sense amplifier control signals, VSS is a ground voltage, SA0 and SA1 are sense amplifiers, and Cs1 to Cs.
8 is a main memory cell ferroelectric capacitor, Cd1 to Cd
Reference numeral 4 denotes a dummy memory cell ferroelectric capacitor, and Qn denotes an N-channel MOS transistor. The main body memory cell is composed of a main body memory cell ferroelectric capacitor Cs1 to Cs8 and an N-channel MOS transistor Qn in which word lines WL0 to WL3 are connected to gates. The first electrodes of the main body memory cell ferroelectric capacitors Cs1 to Cs8 are connected to the source of the N-channel MOS transistor Qn, and the main body memory cell ferroelectric capacitors Cs1 to Cs
Eight second electrodes are connected to the cell plate electrodes CP0 and CP1. The drain of the N-channel MOS transistor Qn constituting the main body memory cell is connected to the bit line B
L0, / BL0, BL1, / BL1.
Similarly, the dummy memory cells also include the dummy memory cell ferroelectric capacitors Cd1 to Cd4 and the dummy word lines DWL0 to DWL0.
DWL1 comprises an N-channel MOS transistor Qn connected to the gate. The first electrodes of the dummy memory cell ferroelectric capacitors Cd1 to Cd4 are connected to the source of the N-channel MOS transistor Qn, and the dummy memory cell ferroelectric capacitors Cd1 to Cd4 are connected.
4 is a dummy cell plate electrode DCP0, D
Connected to CP1. The drains of the N-channel MOS transistors Qn forming the dummy memory cells are connected to the bit lines BL0, / BL0, BL1, / BL1. The bit lines BL0 and / BL0 and the bit lines BL1 and / BL1 are connected to sense amplifiers SA, respectively.
0, SA1. Sense amplifier SA0, S
A1 is the sense amplifier control signal SAE0, SA
The sense amplifier control signals SAE0 and SAE are controlled by E1.
It operates when all the E1s are at the logic voltage “H”. The bit lines BL0 and / BL0 and the bit lines BL1 and / BL1 are
N-channel MOS transistor Qn whose gate is bit line equalize and precharge control signal EQ11
Connected via Bit lines BL0, / BL0, BL
Each of the gates 1 and / BL1 is connected to the ground voltage VSS via an N-channel MOS transistor Qn which is a bit line equalize and precharge control signal EQ11.

Next, in FIG. 8 and FIG. 9, in order to read the data of the main memory cell, the word lines WL0 to WL3 and the dummy word lines DWL0 and DWL are initially set.
1, cell plate electrodes CP0 and CP1, dummy cell plate electrodes DCP0 and DCP1, sense amplifier control signal S
AE0 and SAE1 are set to the logic voltage "L", the bit line equalize and precharge control signal EQ11 is set to the logic voltage "H", and the bit line is set to the logic voltage "L". Thereafter, the bit line equalize and precharge control signal E
Q11 is set to the logic voltage "L", and the bit line is set in a floating state. Next, the main body memory cell capacitor Cs2
When all of the word line WL1, the dummy word line DWL1, the cell plate electrode CP0, and the dummy cell plate electrode DCP0 are set to the logical voltage “H” to read the data of the dummy memory cell, the data of the dummy memory cell is read to the bit line BL0. , Data of the main memory cell is read to bit line / BL0. At this time, when the data of the main body memory cell is “1”, the state changes from the point B in FIG. 9 to the point O9. When the data of the main body memory cell is "0", the state changes from the point E to the point P9, and the dummy memory cell
The state changes from point 9 to point S9. Thereafter, when the sense amplifier control signal SAE0 is set to the logic voltage “H” to operate the sense amplifier SA0, the bit lines BL0, / BL0
The data read out is amplified. If the data of the main memory cell is "1" in a state where the sense amplifier is operated and the data is amplified, the main memory cell changes from the state of the point O9 to the state of the point Q9, and the dummy memory cell changes to the state of the point S9. From the point D. At this time, if the data of the main memory cell is "0", the main memory cell changes from the state of point P9 to the state of point D, and the dummy memory cell changes from the state of point S9 to the state of point T9.

Next, the cell plate electrode CP0 is set to the logic voltage "L". At this time, if the data of the main memory cell is "1", the main memory cell maintains the state of point A from the state of point Q9 and the dummy memory cell maintains the state of point D. If the data of the main memory cell is "0", the main memory cell maintains the state of point E from the state of point D, and the dummy memory cell maintains the state of point T9. The word line WL1 and the dummy word line DWL1 are set to the logic voltage “L”. At this time, if the data of the main memory cell is “1”, the main memory cell changes from the state of point A to a state between points A and B, and the dummy memory cell changes from the state of point D to points D and T9. The state is between. Thereafter, the dummy memory cell is brought to the state of point T9. If the data of the main memory cell is "0", the main memory cell maintains the state at point E, and the dummy memory cell maintains point T9. Next, the dummy cell plate electrode DCP
0 is a logic voltage “L” and the sense amplifier control signal SAE
0 is a logic voltage “L”, the bit line equalize and precharge control signal EQ11 is a logic voltage “H”, and the bit line is a logic voltage “L”.

In the second embodiment, in lines 11, 12, and 13 having the slope of the parasitic capacitance of the bit line as a gradient, the read potential difference Vr9 between the data "1" and the data "0" of the main memory cell is determined by the sense amplifier. The capacitance value of the main body memory cell capacitor is determined so as to be at least twice the potential difference that can be accurately amplified. Next, in order to determine the capacitance value of the dummy memory cell, the logical voltage between the line indicating the capacitance of the dummy memory cell, that is, the line passing through the points D, S9, and T9, and the word line WL0 and the cell plate electrode CP0 is set to "H". The line l3 (lines l1, l2) passing through the point R17 shifted in the horizontal axis direction from the point T17 by the electric field generated immediately after "
Is a point S9. At this time, the potential difference between the point S9 and the point P9 is V19, and the point S9 and the point O are
The potential difference from V9 is Vh9, and V19 and Vh9 are set so that the potential difference can be accurately amplified by the sense amplifier. Ideally, V19 = Vh9 = Vr9 / 2.
By determining the main memory cell capacitor capacitance and the dummy memory cell capacitor capacitance in this manner, accurate and high-speed amplification can be performed by the sense amplifier. Here, a ferroelectric film is used for the dummy memory cell capacitor, but a normal capacitor may be used.

A third embodiment of the semiconductor memory device according to the present invention will be described with reference to the circuit diagram of FIG. 10 and the operation timing chart of FIG.

First, the circuit diagram of FIG. 10 will be described. This circuit has a configuration in which a capacitor is connected to the bit line via a MOS transistor having a switching function with respect to the circuit of the third embodiment. WL0 to WL3 are word lines, DWL0 to DWL1 are dummy word lines, BL0,
/ BL0, BL1, / BL1 are bit lines, CP0, CP
1 is a cell plate electrode, DCP0 and DCP1 are dummy cell plate electrodes, EQ11 is a bit line equalize and precharge control signal, S100 and S101 are control signals, V10 is a signal, SAE0 and SAE1 are sense amplifier control signals, VSS is a ground voltage, SA0 and SA1 are sense amplifiers, Cs1 to Cs8 are main memory cell ferroelectric capacitors, Cd1 to Cd4 are dummy memory cell ferroelectric capacitors, Cb1 to Cb4 are bit line capacitance adjusting capacitors,
Qn is an N-channel MOS transistor. The main body memory cell is composed of the main body memory cell ferroelectric capacitor Cs1.
Cs8 and word lines WL0 to WL3 are configured by N-channel MOS transistors Qn connected to the gates. Main body memory cell ferroelectric capacitor Cs1-Cs8
Is connected to the source of the N-channel MOS transistor Qn, and the second electrode of the main memory cell ferroelectric capacitors Cs1 to Cs8 is connected to the cell plate electrode CP.
0, CP1. The drains of the N-channel MOS transistors Qn constituting the main memory cell are connected to bit lines BL0, / BL0, BL1, / BL1. Similarly, the dummy memory cell is constituted by a dummy memory cell ferroelectric capacitor Cd1 to Cd4 and an N-channel MOS transistor Qn having a gate connected to dummy word lines DWL0 to DWL1. Further, the dummy memory cell ferroelectric capacitors Cd1 to Cd
4 is an N-channel MOS transistor Qn
, And the second electrodes of the dummy memory cell ferroelectric capacitors Cd1 to Cd4 are connected to the dummy cell plate electrodes DCP0 and DCP1. The drains of the N-channel MOS transistors Qn forming the dummy memory cells are connected to the bit lines BL0, / BL0, BL
1, / BL1. Also, the bit line BL
0, / BL0 and BL1, / BL1 are connected to sense amplifiers SA0, SA1, respectively. The sense amplifiers SA0 and SA1 are controlled by sense amplifier control signals SAE0 and SAE1, respectively, and operate when all of the sense amplifier control signals SAE0 and SAE1 are at the logic voltage “H”. Further, bit lines BL0, / BL0 and BL
1, / BL1 are N-channel MOS transistors whose gates are bit line equalize and precharge control signals EQ11.
Connected via transistor Qn. Bit line BL
0, / BL0, BL1, / BL1 each have a gate formed of a bit line equalize and precharge control signal EQ1.
It is connected to the ground voltage VSS via the N-channel MOS transistor Qn which is 1. Bit line BL0, /
The gates of BL0, BL1, and / BL1 are signals S, respectively.
Capacitors Cb1 and Cb via N-channel MOS transistors Qn 101, S100, S101 and S100.
2, Cb3, and Cb4 are connected, and the respective capacitances Cb
1, Cb2, Cb3, and Cb4 plate electrodes are signals V1
Connected to 0. The potential of the signal V10 is equal to the capacitance Cb1
An appropriate potential is set depending on whether Cb4 is a normal capacitor, a capacitor using a ferroelectric film, or, in the case of a ferroelectric capacitor, how to use it (which part of the hysteresis curve is used).

Next, in order to read the data of the main memory cell, the word lines WL0 to WL3, the dummy word lines DWL0 and DWL1, the cell plate electrode C
P0, CP1, dummy cell plate electrodes DCP0, DC
P1, the sense amplifier control signals SAE0 and SAE1, the control signals S100 and S101 are set to a logic voltage "L", the bit line equalize and precharge control signal EQ11 is set to a logic voltage "H", and the bit line is set to a logic voltage "L". .
Thereafter, the bit line equalize and precharge control signal EQ11 is set to the logic voltage "L", and the bit line is set in a floating state. Next, the main memory cell capacitor C
If the word line WL1, the dummy word line DWL1, the cell plate electrode CP0, the dummy cell plate electrode DCP0, and the control signal S101 are all set to the logic voltage “H” in order to read the data of s2, the data of the dummy memory cell is connected to the bit line BL0. Is read, and the data of the main memory cell is read to the bit line / BL0. Here, the reason why the capacity is increased by adding a bit line capacity adjusting capacity to the bit line from which the data of the dummy memory cell has been read out is to use a dummy memory cell of the same size as the main body memory cell capacitor, This is to obtain an appropriate reference voltage when reading from data “1” of the memory cell.
The bit line capacitance adjusting capacitor may be a ferroelectric film or a normal capacitor.

A fourth embodiment showing the semiconductor memory device of the present invention will be described with reference to the circuit configuration diagram of FIG. 10 and the operation timing diagram of FIG.

First, the circuit configuration shown in FIG.
This is the same as the embodiment. Next, in order to read the data of the main body memory cells, the word lines WL0 to WL0 are initially set.
WL3, dummy word lines DWL0, DWL1, cell plate electrodes CP0, CP1, dummy cell plate electrode DC
P0, DCP1, sense amplifier control signals SAE0, SA
E1 is set to the logic voltage "L", and the bit line equalize and precharge control signal EQ11, control signals S100, S100
101 is set to the logic voltage “H”, and the bit line is set to the logic voltage “L”. Thereafter, the bit line equalize and precharge control signal EQ11 is set to the logic voltage "L", and the bit line is set in a floating state. Next, in order to read data from the main body memory cell capacitor Cs2, all of the word line WL1, the dummy word line DWL1, the cell plate electrode CP0, and the dummy cell plate electrode DCP0 are set to the logic voltage “H”, and the control signal S101 is set to the logic voltage “L”. ", The data of the dummy memory cell is read to the bit line BL0, and the data of the main memory cell is read to the bit line / BL0. Here, the reason why the capacity for adjusting the bit line capacity of the bit line from which the data of the dummy memory cell is read out is electrically cut off to reduce the capacity is that the dummy memory cell is equivalent to the main body memory cell capacitor. Use
This is to obtain an appropriate reference voltage when reading from data “0” of the memory cell. The bit line capacitance adjusting capacitor may be a ferroelectric film or a normal capacitor.

[0039]

According to the present invention, a semiconductor memory device using a ferroelectric film as a memory cell capacitor and a method of determining the capacitance value thereof are provided.
According to the method , by setting the optimum capacitance value of the memory cell ferroelectric capacitor in accordance with the parasitic capacitance value of the bit line, the data read potential difference of the memory cell can be increased, and there is no malfunction during reading. It can be a semiconductor memory device.

[Brief description of the drawings]

FIG. 1 illustrates a method of determining a capacitance value of a semiconductor memory device according to the present invention.
Diagram illustrating a circuit configuration of the first embodiment shown

FIG. 2 illustrates a method of determining a capacitance value of a semiconductor memory device according to the present invention;
Showing the operation timing of the first embodiment shown in FIG.

FIG. 3 illustrates a method for determining a capacitance value of a semiconductor memory device according to the present invention;
Shows the first embodiment shown, the memory cell capacitor of the first capacitor value, the data reading of the hysteresis characteristic as the memory cell of the ferroelectric

FIG. 4 illustrates a method of determining a capacitance value of a semiconductor memory device according to the present invention;
Shows in the first embodiment shown, the data read notes <br/> Riseru ferroelectric hysteresis characteristics and the memory cell capacitor having a second capacitance value

FIG. 5 illustrates a method of determining a capacitance value of a semiconductor memory device according to the present invention;
Shows in the first embodiment shown, the data read notes <br/> Riseru ferroelectric hysteresis characteristics and the memory cell capacitor having a third capacitance value

FIG. 6 illustrates a method of determining a capacitance value of a semiconductor memory device according to the present invention.
Between the capacitance value of the memory cell capacitor and the data read potential difference in the first embodiment shown in FIG.

FIG. 7 illustrates a method of determining a capacitance value of a semiconductor memory device according to the present invention.
Showing the circuit configuration of the second embodiment shown in FIG.

FIG. 8 illustrates a method of determining a capacitance value of a semiconductor memory device according to the present invention.
Showing operation timing of the second embodiment shown in FIG.

FIG. 9 illustrates a method of determining a capacitance value of a semiconductor memory device according to the present invention.
Figure in the second embodiment, showing a data reading hysteresis characteristic as the memory cell of the ferroelectric memory cell capacitor shown

FIG. 10 is a diagram showing a circuit configuration of a third and a fourth embodiment showing the semiconductor memory device of the present invention;

FIG. 11 is a diagram showing the operation timing of the third embodiment showing the semiconductor memory device of the present invention;

FIG. 12 is a diagram showing operation timings of a fourth embodiment showing the semiconductor memory device of the present invention;

FIG. 13 is a diagram showing a circuit configuration of a conventional semiconductor memory device.

FIG. 14 is a diagram showing a sense amplifier unit having a circuit configuration of a conventional semiconductor memory device;

FIG. 15 is a diagram showing operation timing of a conventional semiconductor memory device;

Figure 16 is a diagram showing a data reading hysteresis characteristic as the memory cell of the ferroelectric memory cell capacitor of the conventional semiconductor memory device

DESCRIPTION OF SYMBOLS 11 to 13 lines 80a to 80d Memory cells 81a to 81d Memory cell transistors 82 Word lines (WORD) 83a to 83d Memory cell capacitors 84 Word lines (WORD) 86,88 Bit lines 90 Sense amplifiers 92,94 bits Line 96 Sense amplifier 98, 100 Cell plate electrode (PLATE) 102, 104, 106, 108 Bit line precharge transistor 110, 112 P-channel type MOS transistor 114, 116 Signal node 118, 120 N-channel type MOS transistor BL0, / BL0, BL1, / BL1 Bit line Cb1 to Cb4 Bit line capacitance adjusting capacitor S100, S101, V10 Control signal Csh, Csl Body memory cell capacitance value Cd1 to Cd4 Dummy memory cell capacitor CP0 to CP7 Cell plate electrode Cs00 to Cs17, Cs00B to Cs17B, Cs1
To Cs8 Body memory cell capacitors DCP0, DCP1 Dummy cell plate electrodes DWL0 to DWL1 Dummy word lines EQ11 to EQ101 Bit line equalize and precharge control signals Qn N-channel MOS transistors SA0, SA1 Sense amplifier SAE100, SAE101 Sense amplifier control signals V19, Vh9 , Vr3 to Vr5, Vr16 Potential difference Vrm Readable minimum potential difference VSS Ground voltage WL0 to WL7 Word line φPRECHARGE Bit line precharge control signal φSENSE Sense amplifier control signal

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-301093 (JP, A) JP-A-5-62469 (JP, A) JP-A-63-201998 (JP, A) (58) Survey Field (Int.Cl. ⁷ , DB name) G11C 11/40-11/409 G11C 11/22

Claims (6)

(57) [Claims] A first bit line and a second bit line paired with the first bit line are connected to an amplifier, and a first word line and a first ferroelectric are connected to a first MOS transistor. In a semiconductor memory device in which a body capacitor and the first bit line are connected and the first ferroelectric capacitor is connected to a first plate electrode, the first bit line and the second bit line Between the potential difference between the first ferroelectric capacitor and the capacitance value of the first ferroelectric capacitor. The capacitance of the first ferroelectric capacitor is set within a range where the potential difference is equal to or larger than the potential difference that can be accurately amplified by the amplifier. A method for determining a capacitance value of a semiconductor memory device, comprising setting a value. 2. The method according to claim 1, wherein a capacitance value of the first ferroelectric capacitor is set to be small within the range. 3. A first bit line and a second bit line paired with the first bit line are connected to the amplifier, and a first word line and a first ferroelectric are connected to the first MOS transistor. Body capacitor and the first bit line are connected, the first ferroelectric capacitor is connected to a first plate electrode, and a second MOS transistor is connected to a second word line and a first word line.
Are connected to the second bit line and the first capacitor is connected to the second plate electrode, and the second capacitor is connected to the second bit line when data is read from the first capacitor to the second bit line. The first bit line capacitance adjusting capacitance is connected to the bit line capacitance and becomes larger than the first bit line capacitance. When the logical voltage of the first ferroelectric capacitor is “H”, the first bit line capacitance is adjusted. The first bit line potential at the time of reading data to the bit line and the logic voltage "L" of the first ferroelectric capacitor, and the second bit line potential at the time of reading data to the first bit line And the capacitance of the first ferroelectric capacitor is determined such that the potential difference between the first ferroelectric capacitor and the second capacitor is equal to the first desired value.
The first bit line potential is set so that the third bit line potential at the time of reading data to the second bit line becomes a potential of a second desired value intermediate between the first bit line potential and the second bit line potential. Wherein the capacitance of the capacitor is determined. 4. The semiconductor memory device according to claim 3, wherein said first bit line capacitance adjusting capacitor is a ferroelectric capacitor. 5. A first bit line and a second bit line paired with the first bit line are connected to an amplifier, and a first word line and a first ferroelectric are connected to a first MOS transistor. Body capacitor and the first bit line are connected, the first ferroelectric capacitor is connected to a first plate electrode, and a second MOS transistor is connected to a second word line and a first word line.
Are connected to the second bit line and the first capacitor is connected to the second plate electrode, and the second capacitor is connected to the second bit line when data is read from the first capacitor to the second bit line. The first bit line capacitance adjusting capacitance is cut off from the bit line capacitance and becomes smaller than the first bit line capacitance. When the logic voltage of the first ferroelectric capacitor is “H” and the first The first bit line potential at the time of reading data to the bit line and the logic voltage "L" of the first ferroelectric capacitor, and the second bit line potential at the time of reading data to the first bit line And the capacitance of the first ferroelectric capacitor is determined so that the potential difference between the first ferroelectric capacitor and the third bit at the time of reading data to the second bit line of the first capacitor is determined. The line potential is Said to be the second desired value of the intermediate potential between the the preparative line potential second bit line potential first
Wherein the capacitance of the capacitor is determined. 6. The semiconductor memory device according to claim 5, wherein said first bit line capacitance adjusting capacitor is a ferroelectric capacitor.