JP6219060B2 - NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE DATA READING METHOD - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device that reads and writes data using memory cells, and a nonvolatile memory device data reading method that reads data stored in memory cells.

  In general, when reading data in a nonvolatile semiconductor memory using a one-transistor one-capacitor (1T1C) type memory cell, a reference for determining whether the logical value of the read data is “0” or “1” A potential is generated in the memory. As a reference potential generation method, a method using a so-called dummy cell and a method using a memory cell (hereinafter referred to as a read cell) as a data read target itself (hereinafter referred to as a self-reference method) are known. In the case of a method using a dummy cell, the characteristics of both cells may dissociate with time due to, for example, a difference in access frequency between the dummy cell and the read cell, and the determination accuracy of the read data value may be reduced. On the other hand, in the case of the self-referencing method, the reference potential is generated using the read cell itself, so that the read data value determination accuracy can be kept high even if there is a characteristic variation with time. is there.

  For example, Patent Literature 1 discloses a memory device that determines a read data value using a self-referencing method. In the device, first, stored data is read from one cell and an offset is added to this to obtain a read voltage. Next, data is read again from the one cell and used as a reference voltage. Then, the read voltage is compared with the reference voltage to determine whether the logical value of the first read storage data is “0” or “1”.

JP 11-191295 A

  By the way, the offset amount in the memory device of Patent Document 1 is determined by the wiring capacity of the bit line, and is the same when the logical value of the read data is “0” and “1”. Therefore, if the difference between the voltage level when the logical value of the read data is “0” and the voltage level when it is “1” is small, the accuracy of the logical value determination by comparison with the reference voltage is reduced. There was a problem of doing.

  The present invention has been made in view of the above-described problems, and provides a nonvolatile semiconductor memory device and a nonvolatile memory device data reading method capable of determining a read data value with high accuracy. Objective.

The nonvolatile semiconductor memory device according to the present invention reads a storage potential from a memory cell and then writes a reference potential to the memory cell, and compares the storage potential with the reference potential read from the memory cell. A non-volatile semiconductor storage device that reads the first capacitance element whose capacitance value changes according to the storage potential, and an offset command signal supply unit that supplies an offset command signal to the first capacitance element The storage potential is applied to one terminal of the first capacitive element, the potential of the offset command signal is applied to the other terminal of the first capacitive element, and the first capacitive element Exhibits a capacitance value according to the potential difference between the terminals, and the potential of the offset command signal is the first command potential at the time of reading the storage potential from the memory cell. Transition to a second command potential at the time of comparison between the memory potential and the reference potential, and a potential difference generated between the first memory potential and the first command potential when the memory potential is the first memory potential; The total capacitance value of the first capacitive element within a first potential difference range, which is a range between a potential difference generated between the first storage potential and the second command potential, and the storage potential is the first potential difference. A potential difference generated between the second memory potential and the first command potential when the second memory potential is lower than a potential, and a potential difference generated between the second memory potential and the second command potential. It is set to be smaller than the total capacitance value of the first capacitive element within the second potential difference range which is a range .

A non-volatile semiconductor memory device according to the present invention is a non-volatile semiconductor memory device of a self-reference method for reading from a memory cell using a first potential or a second potential lower than the first potential as a storage potential . A capacitive element having a first terminal and a second terminal, the capacitance value of which increases with an increase in potential difference between the first terminal and the second terminal, and the memory cell at the first terminal. And a means for changing the potential applied to the second terminal from a potential higher than the first potential to a potential lower than the second potential. A potential difference between the first potential and the second potential of the storage potential read from the cell is enlarged .

A non-volatile semiconductor memory device according to the present invention is a non-volatile semiconductor memory device of a self-reference method for reading from a memory cell using a first potential or a second potential lower than the first potential as a storage potential. A capacitor having a first terminal and a second terminal, the capacitance value of which increases in accordance with a decrease in potential difference between the first terminal and the second terminal, and the memory cell at the first terminal And changing the potential applied to the second terminal from a third potential having a potential lower than the second potential to a fourth potential lower than the third potential. And expanding the potential difference between the first potential and the second potential of the storage potential read from the memory cell.

A nonvolatile semiconductor memory device according to the present invention is a nonvolatile semiconductor memory device that reads data by comparing a storage potential read from a memory cell with a reference potential, and depends on the storage potential. A first capacitive element whose capacitance value changes, and an offset command signal supply unit that applies an offset command potential to the first capacitive element, wherein the offset command signal supply unit is applied to the capacitive element Means for switching the offset command potential from a predetermined first potential to a second potential lower than the first potential; a second capacitive element connected to the first capacitive element; A signal supply unit connected to a capacitor, and reading from the memory cell a first storage potential and a second storage potential lower than the first storage potential as the storage potential; The second potential is lower than the second storage potential, and the first capacitive element is read when reading the storage potential from the memory cell. An offset command potential is applied to a connection point between the first terminal of the second capacitor element and one terminal of the second capacitor element, and the first terminal of the first capacitor element to which the offset command potential is applied. And the second terminal of the first capacitive element to which the storage potential is applied become a potential difference corresponding to a depletion region when the storage potential is the first storage potential, and the storage potential Is set to be a potential difference corresponding to the accumulation region when the second storage potential .

  According to the nonvolatile semiconductor memory device and the nonvolatile memory device data read method according to the present invention, the read data value can be determined with high accuracy.

1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device (hereinafter referred to as a memory device) according to a first embodiment. FIG. It is a time chart which shows the signal change at the time of data reading. It is a figure which shows the relationship between the electric potential difference for every read data value, and a capacity | capacitance. It is a time chart which shows the read-out electric potential according to a memory | storage data value. It is a block diagram which shows the structure of the memory device which is a 2nd Example. It is a time chart which shows the signal change at the time of data reading. It is a figure which shows the relationship between the electric potential difference for every read data value, and a capacity | capacitance. It is a figure which shows the relationship between the electric potential difference for every read-out data value in a 1st modification, and a capacity | capacitance. It is a figure which shows the relationship between the electric potential difference for every read-out data value in a 2nd modification, and a capacity | capacitance.

  Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

<First embodiment>
FIG. 1 shows the configuration of a memory device 1A according to this embodiment.

  The memory cell M0 includes a cell capacitor 2 and a cell transistor 3. One end of the cell capacitor 2 is connected to the plate line 9, and a signal PL0 on the plate line 9 is supplied. The other end of the cell capacitor 2 is connected to the drain of the cell transistor 3. The source of the cell transistor 3 is connected to one bit line 71 of a pair of bit lines 71 and 81 adjacent to each other. The memory cell M1 includes a cell capacitor 4 and a cell transistor 5. One end of the cell capacitor 4 is connected to the plate line 10, and a signal PL1 on the plate line 10 is supplied. The other end of the cell capacitor 4 is connected to the drain of the cell transistor 5. The source of the cell transistor 5 is connected to the other bit line 81. The gates of the cell transistors 3 and 5 are connected to a common word line 6. A memory selection signal WL0 on the word line 6 is supplied to each of the gates. Each of the cell capacitors 2 and 4 is, for example, a ferroelectric capacitor. Each of the cell transistors 3 and 5 is, for example, an NMOS transistor. Hereinafter, the word line 6 and the plate lines 9 and 10 are collectively referred to as a selection line group. The selection line group intersects with the bit lines 71 and 81. The memory cells M1 and M2 are arranged at the intersection position.

  The source of the precharge transistor 11 is connected to the bit line 71, the drain is connected to a write potential such as a ground potential, and the precharge signal EQ0 is input to the gate. The source of the precharge transistor 12 is connected to the bit line 81, the drain is connected to a write potential such as a ground potential, and the precharge signal EQ1 is input to the gate. Each of the precharge transistors 11 and 12 is, for example, an NMOS transistor. The precharge transistor 11 operates as a switch that selectively connects or opens between the bit line 71 and a write potential such as a ground potential in response to the precharge signal EQ0. When the precharge transistor 11 is on, the signal PL0 is applied to the plate line 9, and the memory cell M0 is selected by the memory selection signal WL0 on the word line 6, for example, the logical value “0” is applied to the memory cell M0. Reference data such as “is written. Similarly, the precharge transistor 12 operates as a switch for selectively connecting or releasing the bit line 81 and a write potential such as the ground potential in accordance with the precharge signal EQ1. When the precharge transistor 12 is on, the signal PL1 is applied to the plate line 10, and the memory cell M1 is selected by the memory selection signal WL0 on the word line 6, the memory cell M1 has a logical value “0”, for example. Reference data such as “is written.

  The bit line 71 is connected to a potential holding line 72 via a switch (hereinafter referred to as “SW”) 13. The bit line 81 is connected to the potential holding line 82 via SW16. One end of the SW 14 is connected to the bit line 71, and the other end is connected to the potential holding line 82. One end of the SW 15 is connected to the potential holding line 72, and the other end is connected to the bit line 81. Each of the SWs 13 to 16 is turned on / off in response to an open / close signal (not shown; also referred to as a bit line selection signal). Each of the SWs 13 to 16 can also be referred to as a connection switch that selectively connects one of the bit lines 71 and 81 and one of the potential holding lines 72 and 82 in accordance with an open / close signal.

  The sense amplifier 17 amplifies the difference between the potential of the potential holding line 72 connected to one terminal and the potential of the potential holding line 82 connected to the other terminal. The potential of the potential holding line 72 is maintained by the parasitic capacitance 20. The potential of the potential holding line 82 is maintained by the parasitic capacitance 19.

  The capacitive element 21 is connected to the potential holding line 72. Hereinafter, an example in which the capacitive element 21 is an NMOS transistor will be described. The source and drain of the transistor 21 are connected to each other and connected to the potential holding line 72. The transistor 21 functions as a MOS capacitor element. An offset command potential ADa that is an output from the inverter 22 is applied to the gate of the transistor 21. An offset command signal sig0 is input to the inverter 22. The capacitance value exhibited by the transistor 21 changes according to the potential on the potential holding line 72.

  It is desirable to provide the capacitive element 40 in order to align the total capacitance value existing on the potential holding line 72 side with the total capacitance value existing on the potential holding line 82 side. One end of the capacitive element 40 is connected to the potential holding line 82, and the ground potential VSS is input to the other end. The capacitance value of the capacitive element 40 is desirably the same as or substantially the same as the capacitance value exhibited by the transistor 21. The capacitive element 40 is, for example, an NMOS transistor whose source and drain are connected to the potential holding line 82 and whose ground potential VSS is input to the gate.

  The offset command signal supply unit 50 generates an offset command signal and supplies it to the potential holding line 72 via the capacitive element 21. The offset command signal is supplied at an appropriate timing in relation to the on / off timing of SW13-16.

  Hereinafter, the data read operation of the memory device 1A will be described with reference to FIG.

  In the initial state, SW13 is on and SW14 is off.

  First, the memory cell M0 is selected by setting the signal level of the memory selection signal WL0 to “H”.

  Next, at time T0, the signal level of the signal PL0 is set to “H”, and the data stored in the memory cell M0 is read. The potential BLSA of the potential holding line 72 is determined by the storage potential corresponding to the data value read from the memory cell M0. In FIG. 2, the potential BLSA when the read data value is “0” is shown as the potential B0, and the potential BLSA when the data value is “1” is shown as the potential B1. The potential BLSA increases as the parasitic capacitance 20 is charged from the time T1. Hereinafter, this reading is referred to as “first reading”.

  Next, at time T1, the signal level of the SW1 opening / closing signal is set to “L”, and SW13 is turned off. The potential BLSA is maintained by the parasitic capacitance 20 even after the SW 13 is turned off.

  Next, at time T2, the signal level of the precharge signal EQ0 is set to “H”, and the precharge transistor 11 is turned on. As a result, the potential of the bit line 71 becomes the VSS level, and the logical value “0” is written in the memory cell M0.

  Next, at time T3, the signal level of the offset command signal Sig0 is set to “H”. As a result, the offset command potential ADa decreases from the potential VCAP1 to the potential VSS. As a result, the potential BLSA decreases. The amount of decrease is different between the potential B0 when the data value read first is “0” and the potential B1 when the data value is “1”. The lowered potential BLSA is also referred to as an offset potential.

  Next, at time T4, the signal level of the SW2 open / close signal is set to “H”, and SW14 is opened. Further, the signal level of the signal PL0 is set to “H”. As a result, the data value “0” is also read out to the potential holding line 82. The potential REF of the potential holding line 82 is determined according to the data value read from the memory cell M0. The potential REF is located between the potential B0 and the potential B1, and is maintained by the parasitic capacitance 19.

  Next, at time T5, the signal level of the SW2 open / close signal is set to “L”, and SW14 is closed. Even after the SW 14 is closed, the potential REF is maintained by the parasitic capacitance 19.

  Next, at time T6, the sense amplifier 17 amplifies the potential difference between the potential BLSA and the potential REF. As a result, when the first read data value is “0”, the potential B0 decreases, and when the first read data value is “1”, the potential B1 increases.

  Hereinafter, the capacitance value of the capacitive element 21 will be described with reference to FIG. In the case where the capacitive element 21 is formed of the transistor 21 as shown in FIG. 1, the horizontal axis represents the potential difference between the gate, source, and drain of the transistor 21, and the vertical axis represents the capacitance value between the gate, source, and drain. The potential difference is a potential difference between the offset command potential ADa applied to the gate of the transistor 21 and the potential BLSA applied to the source / drain. The offset command potential ADa is adjusted by the signal level of the offset command signal sig0 input to the inverter 22. In the depletion region of the transistor 21, the capacitance value increases as the potential difference increases. On the other hand, in the accumulation region of the transistor 21, the capacitance value is almost constant even when the potential difference is further increased. Thus, the capacitance value has a positive gradient with respect to the magnitude of the potential difference. In other words, the capacitance value exhibited by the transistor 21 changes according to the storage potential and the offset command potential ADa.

  The potential BLSA when the read data value is “1” (the potential B1 in FIG. 2) is higher than the potential BLSA when the read data value is “0” (the potential B0 in FIG. 2). The applied offset command potential ADa to the gate of the transistor 21 before the potential BLSA drops is set to be higher than the potential B1. As a result, the potential difference between the gate and the source / drain when the read data value is “0” is larger than the potential difference between the gate and the source / drain when the read data value is “1”. After the potential BLSA drops, the potential of the potential holding line 72 on the side where the potential corresponding to the data value (“0” or “1”) first read from the memory cell M0 is stabilized until the potential is stabilized. Charges need to be accumulated in the capacitive element 21 connected to the holding line 72. Due to the potential difference as described above, the total amount of charges accumulated when the read data value is “0” (hereinafter referred to as the total capacitance value) is the total capacitance value when the read data value is “1”. Bigger than.

  Specifically, when the read data value is “0”, a corresponding charge is accumulated in the section D0a. In other words, when the read data value is “0”, the transistor 21 exhibits the total capacitance value in the section D0a. Potential difference VC0a = potential VCAP1−potential B0. The section D0a is determined according to the potential VCAP1. Since the potential difference when the read data value is “0” is relatively large, the section D0a is located on the accumulation region side. On the other hand, when the read data value is “1”, a corresponding charge is accumulated in the section D1a. In other words, when the read data value is “1”, the transistor 21 exhibits the total capacitance value in the section D1a. Potential difference VC1a = potential VCAP1−potential B1. The section D1a is also determined according to the potential VCAP1. Since the potential difference when the read data value is “1” is relatively small, the section D1a is located on the depletion region side. The total capacity value in the section D0a is larger than the total capacity value in the section D1a. Therefore, when the potential BLSA is decreased at time T3 in FIG. 2, the amount of decrease in the potential B0 is greater than the amount of decrease in the potential B1.

  Hereinafter, the amount of decrease in the potentials B0 and B1 will be described with reference to FIG. The vertical axis of the time chart in FIG. 4 is the potential, and the horizontal axis is the time. The drop amount ΔV0 of the potential B0 due to the offset at time T3 is larger than the drop amount ΔV1 of the potential B1. In other words, the offset amount when the read data value is “0” is larger than the offset amount when the read data value is “1”. As a result, the potential difference ΔVd between the potential B0 and the potential B1 after the decrease is larger than the potential difference ΔVa between the potential B0 and the potential B1 before the decrease.

  With this operation, even if the potential difference between the potential B0 and the potential B1 before the drop is small, the potential difference between the potential B0 and the potential B1 after the drop can be widened. Therefore, erroneous determination can be reduced when the potential BLSA is compared with the potential REF. In other words, it is possible to improve the determination accuracy of whether the first read data value is “0” or “1”.

  As described above, in the memory device 1A of the present embodiment, the potential holding line 72 on the side where the potential BLSA corresponding to the data value (“0” or “1”) first read from the memory cell M0 is held. In addition, a capacitive element 21 whose capacitance value changes according to the potential is connected. The capacitance value of the capacitive element 21 is configured to increase as the potential BLSA decreases. The capacitive element 21 can be composed of the transistor 21 and the inverter 22 as in the above embodiment. Further, the offset command potential ADa, that is, the potential VCAP1 before the BLSA potential drop is set larger than the potential BLSA. In this case, the smaller the potential BLSA, the larger the potential difference between the gate and the source / drain of the transistor 21, so the total capacitance value of the capacitor 21 also increases. The total capacitance value is the total amount of capacitance included in the section from the storage region of the transistor 21 to the depletion layer region (section D0a in FIG. 3). On the other hand, the larger the potential BLSA, the smaller the potential difference between the gate and the source / drain of the transistor 21, so the total capacitance value of the capacitor 21 also becomes smaller. The total capacitance value is a total amount of capacitance mainly included in the depletion layer region (section D0a in FIG. 3) of the transistor 21. Therefore, the amount of decrease in the potential BLSA is greater when the data value read first is “0” than when the data value is “1”. As a result, even when the potential difference between the potential B0 and the potential B1 before the drop is small, the potential difference between the potential B0 and the potential B1 after the drop can be widened, and the first read data value is “ The determination accuracy of “0” or “1” can be improved.

<Second embodiment>
FIG. 5 shows the configuration of the memory device 1B according to this embodiment. The memory device 1B includes an offset command voltage adjusting unit. Other configurations are the same as those of the first embodiment.

  The capacitive element 31 is connected to the potential holding line 72. Hereinafter, a case where the capacitive element 31 is formed of an NMOS transistor will be described. The source and drain of the transistor 31 are connected to each other and to the potential holding line 72. The transistor 31 functions as a MOS capacitor element. The gate of the transistor 31 is connected to the node n2. Node n2 is connected to precharge potential VCAP2 via switch. The switch 34 is, for example, a PMOS transistor. In this case, the drain of the transistor is connected to the precharge potential VCAP2, the source is connected to the node n2, and the open / close signal sig1 is input to the gate. Further, the gate of the transistor 33 is connected to the node n2. The transistor 33 is, for example, an NMOS transistor. The source and drain of the transistor 33 are connected to each other and to the output of the inverter 32. The transistor 33 functions as a MOS capacitor element. An offset command signal sig2 output from the signal supply unit 51 is input to the input of the inverter 32. Here, the switch 34, the transistor 33, the inverter 32, and the signal supply unit 51 form an offset command signal supply unit 52.

  Hereinafter, the drop in the potential BLSA of the potential holding line 72 will be described with reference to FIG. The state before time T2 is the same as in the first embodiment, and the potential BLSA of the potential holding line 72 is maintained at the potential V2 by the parasitic capacitance 20.

  First, at time T2, the signal level of the precharge signal EQ0 is set to “H”, and the precharge transistor 11 is turned on. As a result, the potential of the bit line 71 becomes the VSS level, and the logical value “0” is written in the memory cell M0. At time T2, the potential of the open / close signal sig1 is changed from the ground potential VSS to the precharge potential VCAP2, and the switch 34 is turned off. Before the switch is turned off, the node n2 is fixed to the precharge potential VCAP2, but the potential of the node n2 can be changed by the switch off.

  Next, at time T3, the potential of the offset command signal sig2 input to the inverter 32 is changed from the ground potential VSS to the potential VDD.

  Along with this, the potential of the node n1 connected to the output of the inverter 32 changes from the potential VDD to the ground potential VSS.

  At this time, the potential of the node n2 decreases from the precharge potential VCAP2 by “α” to become VCAP2-α. “Α” is obtained from the following equation.

α = C1 × (C1 + C2) × VDD / (C1 × C2 + C2 × C3 + C3 × C1)
Here, C1 is the capacitance value of the transistor 33, C2 is the capacitance value of the transistor 31, and C3 is the capacitance value of the parasitic capacitance 20. The capacitance values C1 and C2 are determined according to the magnitude of the precharge potential VCAP2.

  In addition, the potential BLSA decreases by “β” to V2−β. “Β” is obtained from the following equation.

β = C1 × C2 × VDD / (C1 × C2 + C2 × C3 + C3 × C1)
Since the capacitance values C1 and C2 are determined according to the magnitude of the precharge potential VCAP2, the magnitude of the amount of decrease in the potential BLSA can be adjusted by changing the magnitude of the precharge potential VCAP2. The operation after time T4 is the same as that in the first embodiment.

  Hereinafter, the capacitance value of the capacitive element 31 will be described with reference to FIG. The horizontal axis represents the potential difference between the gate, source, and drain of the transistor 31, and the vertical axis represents the capacitance value between the gate, source, and drain. The potential difference is a potential difference between the potential applied to the gate of the transistor 31, that is, the offset command potential ADb at the node n2 and the potential BLSA applied to the source / drain. The offset command potential ADb can be adjusted by changing the magnitude of the precharge potential VCAP2. In the depletion region of the transistor 31, the capacitance value increases as the potential difference increases. On the other hand, in the accumulation region of the transistor 31, the capacitance value is substantially constant even when the potential difference is further increased. Thus, the capacitance value has a positive gradient with respect to the magnitude of the potential difference.

  The potential BLSA when the read data value is “1” (the potential B1 in FIG. 6) is higher than the potential BLSA when the read data value is “0” (the potential B0 in FIG. 6). The applied offset command potential ADb to the gate of the transistor 31 before the potential BLSA drops is set to be higher than the potential B1. As a result, the potential difference between the gate and the source / drain when the read data value is “0” is larger than the potential difference between the gate and the source / drain when the read data value is “1”. After the potential BLSA drops, the potential of the potential holding line 72 on the side where the potential corresponding to the data value (“0” or “1”) first read from the memory cell M0 is stabilized until the potential is stabilized. Charges need to be accumulated in the capacitive element 31 connected to the holding line 72.

  Specifically, when the read data value is “0”, a corresponding charge is accumulated in the section D0b. In other words, when the read data value is “0”, the transistor 31 exhibits the total capacitance value in the section D0b. Since the potential difference when the read data value is “0” is relatively large, the section D0b is located on the accumulation region side. The potential difference VC0b = VCAP2-B0 between the gate, the source and the drain of the transistor 31 when the read data value is “0”. The section D0b is VC0b-α to VC0b.

  On the other hand, when the read data value is “1”, the corresponding charge is accumulated in the section D1b. In other words, when the read data value is “1”, the transistor 31 exhibits the total capacitance value in the section D1b. Since the potential difference when the read data value is “1” is relatively small, the section D1b is located near the depletion region. The potential difference VC1b = VCAP2-B1 between the gate, the source and the drain of the transistor 31 when the read data value is “1”. The section D1b is VC1b-α to VC1b.

  The total capacity value in the section D0b is larger than the total capacity value in the section D1b. Therefore, when the potential BLSA is decreased at time T3 in FIG. 6, the amount of decrease in the potential B0 is greater than the amount of decrease in the potential B1. In other words, the offset amount when the read data value is “0” is larger than the offset amount when the read data value is “1”. As a result, as shown in FIG. 4, the potential difference ΔVd between the potential B0 and the potential B1 after the decrease is larger than the potential difference ΔVa between the potential B0 and the potential B1 before the decrease. With this operation, even if the potential difference between the potential B0 and the potential B1 before the drop is small, the potential difference between the potential B0 and the potential B1 after the drop can be widened.

  As described above, in the memory device 1B of the present embodiment, the magnitude α of the drop amount of the potential BLSA of the potential holding line 72 can be adjusted by adjusting the magnitude of the precharge potential VCAP2. That is, by adjusting the magnitude of the precharge potential VCAP2, the offset amount of the potential BLSA determined according to the first read data value can be finely adjusted. In other words, by adjusting the magnitude of the precharge potential VCAP2, the capacitance value of the capacitive element 31 connected to the potential holding line 72 can be adjusted more finely than in the first embodiment. . With this adjustment, the amount of charge accumulated in the capacitor 31 when the read data value is “0” is set as the amount of charge in the accumulation region, and the charge accumulated in the capacitor 31 when the read data value is “1”. The amount can be the charge amount of the depletion region. Therefore, the difference between the accumulated charge amount when the read data is “0” and the accumulated charge amount when the read data is “1” can be further increased, and the difference between the lowered potentials B0 and B1. Can be made larger. Thereby, the determination accuracy of the read data value can be further improved.

  Each of the memory cells M0 and M1 in the first and second embodiments is a ferroelectric memory, but is not limited to this. The memory devices 1A and 1B can be applied to all nonvolatile memories such as a FASH memory that compares a reference potential of a dummy cell and a read potential of the memory cell, for example.

  The memory devices 1A and 1B of the first and second embodiments include two bit lines and two potential holding lines, two plate lines, and one word line, but are not limited thereto. The memory devices 1A and 1B can be applied to a memory cell array including more bit lines, potential holding lines, plate lines and word lines and memory cells corresponding to the number of the memory devices.

<First Modification>
Hereinafter, with reference to FIG. 8, a modification will be described based on the first embodiment. The capacitive element 21 of the first embodiment is a transistor 21 and is an example in which the relationship between the gate-source / drain potential difference and the capacitance value is used, but is not limited thereto. For example, as shown in FIG. 8, a capacitor that exhibits a capacitance value proportional to the potential difference between the potential BLSA and the offset command potential ADa can be used instead of the transistor 21. Also in this case, the capacitance value when the read data value is “0” (capacity value within the interval D0c) is larger than the capacitance value when the read data value is “1” (capacity value within the interval D1c). Become. Therefore, the potential difference when the read data value is “0” is larger than the potential difference when the read data value is “1”. As a result, the same effects as in the above embodiment can be obtained. Further, the capacitance value is not necessarily proportional to the potential difference, and any element or circuit having a positive gradient in capacitance value can be used instead of the transistor 21.

<Second Modification>
Hereinafter, another modification will be described with reference to FIG. 9 based on the first embodiment. In the first embodiment, the offset command signal Sig0 is applied so that the offset command potential ADa applied to the gate of the transistor 21 is larger than the potential B1 generated in the potential holding line 72 when the read data value is “1”. In this example, the potential is set and the capacitance value of the capacitor 21 has a positive gradient, but the present invention is not limited to this. That is, the potential of the offset command signal sig0 is set so that the offset command potential ADa is smaller than the potential B0 generated in the potential holding line 72 when the read data value is “0”, and the capacitance value of the capacitive element 21 is An element having a negative gradient can be used.

  In this case, the potential difference between the potential B0 of the potential holding line 72 when the read data value is “0” and the offset command potential ADa before the potential BLSA drop is the potential holding line 72 when the read data value is “1”. Less than the potential difference between the potential B1 and the offset command potential ADa. In addition, since the capacitance value has a negative gradient, the amount of charge accumulated in the capacitor element 21 (capacitance in the section D0d in FIG. 9) when the read data value is “0” after the potential BLSA drops is as follows. Therefore, the accumulated charge amount (capacitance in the section D1d in FIG. 9) of the capacitive element 21 when the read data value is “0” is larger.

  Therefore, when the potential BLSA is lowered at time T3 in FIG. 2, the amount of decrease in the potential B0 is larger than the amount of decrease in the potential B1 as in the above embodiment. As a result, the same effects as in the above embodiment can be obtained. In the second embodiment, the same configuration as that of the second modification can be obtained, and the same effect can be obtained.

1A, 1B Nonvolatile semiconductor memory device (memory device)
2, 4 Cell capacitance 3, 5 Cell transistor 6 Word line 71, 81 Bit line 72, 82 Potential holding line 9, 10 Plate line 11, 12 Precharge transistor 13-16 Switch 17 Sense amplifier 19, 20 Parasitic capacitance 21, 31 33 Transistor 22, 32 Inverter 34 Switch 40 Capacitance element 50, 52 Offset command signal supply unit 51 Signal supply unit M0, M1 Memory cell

Claims (4)

A non-volatile semiconductor memory device that reads data by reading a memory potential from a memory cell and then writing a reference potential to the memory cell and comparing the memory potential with the reference potential read from the memory cell. There,
A first capacitive element whose capacitance value changes according to the storage potential;
An offset command signal supply unit for supplying an offset command signal to the first capacitive element,
The storage potential is applied to one terminal of the first capacitive element, the potential of the offset command signal is applied to the other terminal of the first capacitive element, and the first capacitive element is between the terminals. Presents a capacitance value according to the potential difference,
The potential of the offset command signal is
Transition from a first command potential at the time of reading the storage potential from the memory cell to a second command potential at the time of comparison between the storage potential and the reference potential;
Between the potential difference generated between the first memory potential and the first command potential when the memory potential is the first memory potential, and the potential difference generated between the first memory potential and the second command potential The total capacitance value of the first capacitive element in the first potential difference range that is a range of
A potential difference generated between the second memory potential and the first command potential when the memory potential is a second memory potential lower than the first potential, and the second memory potential and the second command potential A non-volatile semiconductor memory device, wherein the non-volatile semiconductor memory device is set to be smaller than a total capacitance value of the first capacitor element in a second potential difference range which is a range between potential differences generated therebetween. A non-volatile semiconductor memory device of a self-reference method for reading from a memory cell using a first potential or a second potential lower than the first potential as a storage potential,
A capacitive element comprising a first terminal and a second terminal, wherein a capacitance value increases in accordance with an increase in potential difference between the first terminal and the second terminal;
Means for applying the memory potential of the memory cell to the first terminal;
Means for changing a potential applied to the second terminal from a potential higher than the first potential to a potential lower than the second potential;
A nonvolatile semiconductor memory device, wherein a potential difference between the first potential and the second potential of the storage potential read from the memory cell is enlarged. A non-volatile semiconductor memory device of a self-reference method for reading from a memory cell using a first potential or a second potential lower than the first potential as a storage potential,
A capacitive element comprising a first terminal and a second terminal, wherein a capacitance value increases in accordance with a decrease in potential difference between the first terminal and the second terminal;
Means for applying the memory potential of the memory cell to the first terminal;
Means for changing the potential applied to the second terminal from a third potential having a potential lower than the second potential to a fourth potential lower than the third potential;
A nonvolatile semiconductor memory device, wherein a potential difference between the first potential and the second potential of the storage potential read from the memory cell is enlarged. A nonvolatile semiconductor memory device that reads data by comparing a storage potential read from a memory cell and a reference potential,
A first capacitor element whose capacitance value changes depending on the storage potential;
An offset command signal supply unit that applies an offset command potential to the first capacitive element,
The offset command signal supply unit is
Means for switching the offset command potential applied to the capacitive element from a predetermined first potential to a second potential lower than the first potential ;
A second capacitive element connected to the first capacitive element;
A signal supply unit connected to the second capacitive element;
Comprising
A first memory potential and a second memory potential lower than the first memory potential are read from the memory cell as the memory potential;
The first potential is higher than the first memory potential;
The second potential is lower than the second memory potential;
At the time of reading the storage potential from the memory cell, an offset command potential is applied to a connection point between the first terminal of the first capacitive element and one terminal of the second capacitive element;
The potential difference between the first terminal of the first capacitive element to which the offset command potential is applied and the second terminal of the first capacitive element to which the storage potential is applied is the memory. When the potential is the first memory potential, the potential difference corresponds to the depletion region,
A non-volatile semiconductor memory device, wherein the memory potential is set to be a potential difference corresponding to an accumulation region when the memory potential is the second memory potential .

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