KR20060015924A - Semiconductor memory device and bitline sense amplifier offset voltage test method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method for measuring a bit line sense amplifier offset voltage thereof, and more particularly, to fix a bit line bar voltage level to a predetermined level by using two different precharge voltages at the time of precharging. It is a technology that can easily control and improve the offset voltage characteristics by varying the voltage level so as to measure an accurate offset voltage value based on a fixed bit line bar.

To this end, the present invention provides an equalization unit for equalizing any one of adjacent bit lines or adjacent bit line bars according to an equalization control signal, and a precharge control signal to control the adjacent bit lines and the bit line bars. Precharge voltage to the same level of precharge voltage, and in the test mode, a precharge unit for precharging the bit lines and the bit line bars with different precharge voltages, and sensing and amplifying data of the bit lines. And an output control unit for outputting data of the bit line selected by the column control signal among the outputs of the sense amplifier.

Description

Semiconductor memory device and bitline sense amplifier offset voltage test method

1 is a circuit diagram of a conventional semiconductor memory device.

2A and 2B are graphs of operations in the normal mode of the semiconductor memory device.

3 is a circuit diagram of a semiconductor memory device according to an embodiment of the present invention.

4A and 4B are graphs illustrating operations of the semiconductor memory device of FIG. 3.

FIG. 5 is a graph of offset voltage measured from the semiconductor memory device of FIG. 3. FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method for measuring a bit line sense amplifier offset voltage thereof, and more particularly, to fix a bit line bar voltage level to a predetermined level by using two different precharge voltages at the time of precharging. It is a technology that can easily control and improve the offset voltage characteristics by varying the voltage level so as to measure an accurate offset voltage value based on a fixed bit line bar.

In general, a semiconductor memory device is for storing data or reading data in a plurality of memory cells, and includes a plurality of bit lines and a plurality of word lines, a circuit for selecting the bit lines and word lines, and a plurality of bit lines. Peripheral circuits such as sense amplifiers.

In particular, among the plurality of sense amplifiers, the bit line sense amplifier senses and amplifies the data on the bit line and outputs the data to the data bus, and the data bus sense amplifier senses and amplifies the data amplified by the bit line sense amplifier again and outputs the data. Output to the buffer.

Here, the sensing margin of the bit line sense amplifier is one of important factors for determining device characteristics. This sensing margin is affected by various factors, but in particular by the offset voltage, which is the lowest possible voltage of the sense amplifier.

1 is a configuration diagram of a conventional semiconductor memory device.

The conventional semiconductor memory device includes an equalization control unit 10, a separation control unit 20, a precharge unit 30, a sense amplifier 40, and an output control unit 50.

The equalization control unit 10 is controlled by the equalization control signals BLEQH and BLEQL to equalize the bit line pairs BL and BLZ. To this end, the equalization control unit 10 is provided with an equalization control signal BLEQ to the gate and has an NMOS transistor NM1 connected between the bit line pairs BL and BLZ.

The separation controller 20 is controlled by the separation control signals BISH and BISL to selectively separate the bit lines BL and BLZ of the memory cell array region and the bit lines BL and BLZ of the sense amplifier region, respectively. To this end, the separation control unit 20 is provided with the separation control signals BISH and BISL applied to the gate and includes NMOS transistors NM2 and NM3 connected to the bit lines BL and BLZ, respectively.

The precharge unit 30 is controlled by the precharge control signal BLP to precharge the bit lines BL and BLZ with the precharge voltage VBLP. To this end, the precharge unit 30 applies the precharge control signal BLP to the gate, the precharge voltage VBLP to the one terminal, and the NMOS transistors NM4 and NM5 having the other terminal connected to the bit lines BL and BLZ, respectively. Equipped.

The sense amplifier 40 is controlled by the sense amplifier control signals SZ and RTO to sense and amplify the data carried on the bit line BL. To this end, the sense amplifier 40 includes PMOS transistors PM1 and PM2 and NMOS transistors NM6 and NM7. The PMOS transistors PM1 and PM2 are connected in series between the bit line pairs BL and BLZ, a sense amplifier control signal RTO is applied to the common node, and each gate is connected to the bit line bar BLZ and the bit line BL, respectively. The NMOS transistors NM6 and NM7 are connected in series between the bit line pairs BL and BLZ, a sense amplifier control signal SZ is applied to the common node, and each gate is connected to the bit line bar BLZ and the bit line BL, respectively.

The output controller 50 selectively transmits the data amplified by the sense amplifier 40 controlled by the column select signal YI to the input / output buses SIO and SIOZ. To this end, the output controller 50 includes NMOS transistors NM8 and NM9 having a column selection signal YI applied to the gate and connected at both ends thereof to the bit line bar BLZ and the bit line BL.

Hereinafter, the operation of the bit line sense amplifier of FIG. 1 will be described with reference to FIGS. 2A and 2B.

FIG. 2A is an operation graph of a semiconductor memory device in a normal mode, and FIG. 2B is an enlarged view of portion A of FIG. 2A.

First, the precharge unit 30 precharges the bit line to the precharge voltage VBLP (for example, 1/2 of the internal power supply voltage VCC), and the equalizer 10 adjusts the equalization control signal BLEQ to a high level. When enabled, the bit line pairs BL and BLZ are equalized to eliminate the voltage difference between the bit line BL and the bit line bar BLZ connected to the selected memory cell.

A row decoder (not shown) analyzes an externally inputted row address to select a word line corresponding to the row address, and a cell transistor (not shown) connected to the selected word line is turned on so that a cell capacitor (not shown) is provided. Charge distribution occurs between the bit line capacitor (not shown) and a potential difference between the bit line BL and the bit line bar BLZ to which the selected memory cell is connected.

That is, when the data of the cell is a high level value, when the word line WL is activated, the charge stored in the cell is charged with the bit line BL. Thereafter, the bit line BL rises by the sensing voltage Vs compared to the bit line bar BLZ, and when the sensing voltage Vs becomes larger than the offset voltage, the sense amplifier 40 starts to drive and amplifies the bit line BL to the core voltage VCORE level. Amplify bit line bar BLZ to ground voltage VSS level.

At this time, the sensing voltage Vs is

Here, C _BL is a bit line capacitor value and C _S is a cell capacitor value.

That is, the sensing voltage Vs is influenced by the bit line capacitor value, the cell capacitor value, and the power supply voltage VCC.

However, in the conventional semiconductor memory device, when the sensing voltage Vs is smaller than the offset voltage during operation, the sense amplifier amplifies abnormal data so that an error occurs. Therefore, the offset voltage of the bit line sense amplifier must be accurately known.

To this end, the offset voltage of the bit line sense amplifier has been conventionally measured by using a VCP BUMP TEST method using a control of a capacitor plate voltage VCP.

The VCP bump test method measures the offset voltage of the sense amplifier by adjusting the capacitor plate voltage VCP during read / write operation by adjusting the sensing voltage of the sense amplifier according to the change amount of VCP.

However, the above-described method measures the offset voltage under the assumption that the VCP variation is equally applied to all the cells, so that the capacitance of the capacitor in the cell array, the storage node RC, and the threshold voltage of the cell change. In this case, there is a problem in that the sensing voltage Vs is changed so that an accurate offset voltage cannot be measured.

The present invention was created to solve the above problems, by using the two different bit line precharge voltage to fix the voltage level of the adjacent bit line bar to a constant level and to vary the bit line voltage level to measure the offset voltage Therefore, the purpose of the present invention is to accurately measure an offset voltage of a bit line sense amplifier regardless of a change in capacity of a cell capacitor, a storage node RC, and a change in a threshold voltage of a cell.

According to an aspect of the present invention, there is provided a semiconductor memory device including an equalizer for equalizing any one of adjacent bit lines or adjacent bit line bars according to an equalization control signal, and controlled by a precharge control signal. A precharge unit which precharges adjacent bit lines and the bit line bars with a precharge voltage having the same level, and in the test mode, precharges the bit lines and the bit line bars with different precharge voltages; And a sense amplifier for sensing and amplifying the data of the bit line, and an output control unit for outputting data of the bit line selected by the column control signal among the outputs of the sense amplifier.

The bit line sense amplifier offset voltage measuring method of the present invention includes a first step of fixing a bit line bar at a predetermined level with one of different precharge voltages in a test mode, and changing the other to precharge the bit line; A second step of outputting data by sensing a potential difference between a line and the bit line bar, a third step of repeating the first step and the second step according to the output data, and measuring the offset voltage; and the test mode It is characterized in that it comprises a fourth step of exiting to enter the read mode of the normal mode.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram of a semiconductor memory device including a sense amplifier in accordance with an embodiment of the present invention.

The conventional semiconductor memory device includes an equalization control unit 100, a separation control unit 200, precharge units 300 and 301, a sense amplifier 400, and an output control unit 500.

The equalization control unit 100 is controlled by the equalization control signals BLEQH and BLEQL to equalize adjacent bit lines BL and adjacent bit line bars BLZ. To this end, the equalization control unit 100 includes an NMOS transistor NM11 to which the equalization control signals BLEQH and BLEQL are applied to the gate, and connected between adjacent bit lines BL and adjacent bit line bars BLZ.

The separation controller 200 is controlled by the separation control signals BISH and BISL to selectively separate the bit line pairs BL and BLZ in the memory cell array region and the bit line pairs BL and BLZ in the sense amplifier region, respectively. To this end, the separation control unit 20 is provided with NMOS transistors NM12 and NM13 connected to the bit control pairs BISH and BISL and connected to the bit line pairs BL and BLZ, respectively.

In the precharge units 300 and 301, a precharge control signal BLP is applied to a gate, precharge voltages VBLP0 and VBLP1 are applied to one terminal thereof, and an NMOS connected to the bit lines BL and bitline bars BLZ, respectively. The transistors NM14 and NM15 are provided. At this time, the precharge unit 300 is controlled by the precharge control signal BLP to precharge two adjacent bit lines BL with the precharge voltage VBLP0, and the precharge unit 301 is controlled by the precharge control signal BLP to precharge the precharge unit. The two adjacent bit line bars BLZ are precharged with the charge voltage VBLP1.

Accordingly, in the offset voltage measurement mode, the bit line bar BLZ is fixed at the precharge voltage VBLP1 level, and the bit line BL may change the precharge voltage VBLP0 to change the sensing voltage Vs while measuring the offset voltage.

The sense amplifier 400 is controlled by the sense amplifier control signals SZ and RTO to sense and amplify data carried on the bit line BL. To this end, the sense amplifier 400 includes PMOS transistors PM11 and PM12 NMOS transistors NM16 and NM17. PMOS transistors PM11 and PM12 are connected in series between bit line pairs BL and BLZ, and a sense amplifier control signal RTO is applied to a common node, and each gate is connected to bit line bar BLZ and bit line BL, respectively. The NMOS transistors NM16 and NM17 are connected in series between the bit line pairs BL and BLZ, a sense amplifier control signal SZ is applied to the common node, and each gate is connected to the bit line bar BLZ and the bit line BL, respectively.

The output controller 500 selectively transmits the data amplified by the sense amplifier 400 controlled by the column select signal YI to the input / output buses SIO and SIOZ. For this purpose, the output controller 500 includes NMOS transistors NM18 and NM19 having a column select signal YI applied to a gate and a drain thereof connected to bit line pairs BL and BLZ, respectively.

Hereinafter, the operation of the bit line sense amplifier of FIG. 3 will be described with reference to FIGS. 4A and 4B.

4A is an operation graph of the semiconductor memory device in the normal mode, and FIG. 4B is an enlarged view of a portion B of FIG. 2A.

First, as in the normal mode, the precharge units 300 and 301 precharge the bit line pairs to the same level of the precharge voltages VBLP0 and VBLP1 (VCC / 2), and the equalizer 10 equalizes the control signal BLEQ. By equalizing the two bit lines to eliminate the voltage difference between the bit line and the bit line bar connected to the selected memory cell.

Thereafter, as shown in FIG. 4B, the test mode is entered to measure the offset voltage of the bit line sense amplifier. Upon entering the test mode, the bit line bar BLZ precharges to the precharge voltage VBLP1 level and the bit line BL precharges to the precharge voltage VBLP0 level. At this time, the precharge voltage VBLP1 is fixed at a constant level and the precharge voltage VBLP0 is changed.

As described above, the bit line BL voltage level is varied based on the fixed bit line bar BLZ, and the output data is determined to be correct data, thereby offsetting the cell capacitor capacity, the storage node RC, and the cell threshold voltage. The voltage can be measured.

The sensing margin is measured by fixing the precharge voltage VBLP1 and varying the precharge voltage VBLP0. However, the sensing margin may be measured by fixing the precharge voltage VBLP0 and varying the precharge voltage VBLP1.

Thereafter, the row decoder (not shown) analyzes an externally inputted row address to select a word line corresponding to the row address, and a cell transistor (not shown) connected to the selected word line is turned on to display a cell capacitor ( Charge sharing between the bit line capacitor and the bit line capacitor to generate a potential difference between the bit line and the bit line bar connected to the selected memory cell. Thereafter, the bit line BL is increased by the sensing voltage Vs compared to the bit line bar BLZ, the bit line BL is amplified to the core voltage VCORE level, and the bit line bar / BL1 is amplified to the ground voltage VSS level.

Thereafter, when the sense amplifier control signals RTO and SZ are enabled, that is, the sense amplifier control signal RTO becomes the high level VDD, and the sense amplifier control signal SZ becomes the low level VSS so that the bit line sense amplifier operates to select the selected memory cell. It senses and amplifies the potential difference between the connected bit line and the bit line bar.

Accordingly, the bit line sense amplifier 40 makes the bit line BL connected to the selected memory cell low VSS by the sense amplifier control signal SZ, and makes the bit line bar BLZ high VDD by the sense amplifier control signal RTO.

Subsequently, when the column address is analyzed by a column decoder (not shown) and the column control signal YI corresponding to the column address is enabled at a high level, the amplified data carried on the bit line by the bit line sense amplifier is transferred to the data bus. Is sent.

The external test equipment determines whether the amplified data value is the correct value, and if it is not the correct value, the offset voltage is larger than the sensing voltage Vs, so that the precharge voltage VBLP0 applied to the bit line is adjusted to a larger level. do.

In this way, it is determined whether the output data value is the correct value, and the precharge voltage VBLP0 is varied according to the result, and the above process is repeated until the correct data is obtained. Thus, the voltage of the minimum cell data capable of the normal operation of the DRAM, that is, the offset voltage is determined. You can measure accurately.

After accurately measuring the offset voltage in the same manner as described above, the test mode exits and returns to the normal mode to perform the read operation.

That is, as shown in FIG. 4, in the test mode, the bit line bar BLZ is fixed to the precharge voltage VBLP1 (VCC / 2) level, and the bit line BL is changed to the precharge voltage VBLP0, whereby the difference between the different precharge voltages (VBLP0) is obtained. -VBLP1) becomes the offset voltage Vs.

As such, by measuring the offset voltage by varying the bit line voltage level based on the fixed bit line bar BLZ, the change in the capacitance of the capacitor, the storage node RC, and the threshold voltage of the cell are performed. Regardless, since the difference between the precharge voltages VBLP0 to VBLP1 is constant, the accurate offset voltage Vs can be measured as shown in FIG. 5. As shown in FIG. 5, it can be seen that the graphs of the ideal offset voltage C and the measured offset voltage D are almost similar.

As described above, the present invention has the effect of improving the sensing capability of the sense amplifier by accurately measuring the offset voltage using two different precharge voltages to improve the offset voltage characteristics.                     

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, replacements and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (6)

An equalizer for equalizing adjacent bit lines and adjacent bit line bars according to an equalization control signal; It is controlled by a precharge control signal to precharge the adjacent bit lines and the bit line bars to the same level of precharge voltage in the normal mode, and in the test mode, the bit lines and the bit line bars are different from each other. A precharge unit for precharging with a precharge voltage; A sense amplifier for sensing and amplifying data of the bit line; And An output control unit for outputting data of a bit line selected by a column control signal among the outputs of the sense amplifiers; A semiconductor memory device comprising a. The method of claim 1, wherein the equalization unit, A first switching unit connected between the bit lines or the bit line bars and controlled by the equalization control signal; A semiconductor memory device comprising: a. The method of claim 2, wherein the precharge unit, And maintaining the bit line bar at a constant voltage level using one of different precharge voltages, and precharging the bit line by varying one of the different precharge voltages. . The method of claim 3, wherein the precharge unit, Second and third switching units connected in series between any one of the bit lines or the bit line bars and controlled by the precharge control signal. A semiconductor memory device comprising: a. The method of claim 4, wherein the first to third switching unit, A semiconductor memory device characterized in that the NMOS transistor. A first step of fixing the bit line bar to a predetermined level with one of different precharge voltages in a test mode and precharging the bit line by varying the other; A second step of outputting data by sensing a potential difference between the bit line and the bit line bar; A third step of measuring the offset voltage by repeating the first step and the second step according to the output data; And A fourth step of exiting the test mode and entering a read operation mode of the normal mode; A method of measuring a bit line sense amplifier offset voltage in a semiconductor memory device.

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