KR20060131561A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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KR20060131561A
KR20060131561A KR1020050052092A KR20050052092A KR20060131561A KR 20060131561 A KR20060131561 A KR 20060131561A KR 1020050052092 A KR1020050052092 A KR 1020050052092A KR 20050052092 A KR20050052092 A KR 20050052092A KR 20060131561 A KR20060131561 A KR 20060131561A
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South Korea
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high voltage
back bias
bias voltage
sense amplifier
voltage
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KR1020050052092A
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Korean (ko)
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우탁균
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주식회사 하이닉스반도체
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Publication of KR20060131561A publication Critical patent/KR20060131561A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

A semiconductor memory device is provided to improve accuracy of memory test process by separately controlling a high voltage, which is applied on back bias voltage terminals of PMOS(Positive Metal Oxide Semiconductor) transistors. A semiconductor memory device includes a high voltage generator(100), a sense amplifier(500), a memory cell(600), a back bias voltage controller(300), and a back bias voltage pad(400). The high voltage generator boosts up an external source voltage to generate a high voltage. The sense amplifier amplifies data of a bit line pair by using the high voltage as a back bias voltage. The memory cell uses the high voltage to store the data. The back bias voltage controller discriminates a normal mode from a test mode and selectively supplies the high voltage to the sense amplifier. The back bias voltage pad receives the back bias voltage from the outside during the test mode.

Description

반도체 메모리 장치{Semiconductor memory device}Semiconductor memory device

도 1은 종래의 반도체 메모리 장치의 구성도.1 is a block diagram of a conventional semiconductor memory device.

도 2는 본 발명의 실시예에 따른 반도체 메모리 장치의 구성도.2 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

본 발명은 반도체 메모리 장치에 관한 것으로서, 보다 상세하게는 정상모드와 테스트모드를 구별하여 고전압을 센스앰프의 피모스 트랜지스터의 백바이어스전압으로 제공함으로써, 센스앰프 특성 변화에 따른 불량셀 검출이 가능하도록 하는 기술이다.The present invention relates to a semiconductor memory device, and more particularly, to distinguish a normal mode from a test mode and to provide a high voltage as a back bias voltage of a PMOS transistor of a sense amplifier, so that a defective cell can be detected according to a change of a sense amplifier characteristic. It is a technique to do.

일반적으로, 반도체 메모리 장치는 메모리 셀 어레이와 센스앰프 등을 포함하여 데이터를 라이트 하거나 리드하기 위한 장치이다. 특히, 반도체 메모리 장치의 리드 및 라이트 동작을 위해 외부 전원 전압보다 셀 트랜지스터의 문턱 전압만큼 더 큰 전압인 고전압을 필요로 하는 경우가 있다. 그에 따라, 반도체 메모리 장치 내에서 외부 전원 전압을 승압시켜 고전압을 생성하여 사용한다. In general, a semiconductor memory device is a device for writing or reading data including a memory cell array, a sense amplifier, and the like. In particular, there is a case where a high voltage, which is a voltage larger than a threshold voltage of a cell transistor, is required for read and write operations of a semiconductor memory device. Accordingly, the external power supply voltage is boosted in the semiconductor memory device to generate and use a high voltage.

도 1은 종래의 반도체 메모리 장치의 구성도이다.1 is a configuration diagram of a conventional semiconductor memory device.

종래의 반도체 메모리 장치는 고전압 발생부(10), 고전압패드(20), 센스앰프 (30), 및 메모리 셀(40)을 구비한다.The conventional semiconductor memory device includes a high voltage generator 10, a high voltage pad 20, a sense amplifier 30, and a memory cell 40.

고전압 발생부(10)는 외부전원전압을 승압하여 고전압 VPP을 발생하고, 고전압패드(20)는 외부에서 고전압 VPP을 인가받기 위해 구비된다.The high voltage generator 10 boosts the external power supply voltage to generate a high voltage VPP, and the high voltage pad 20 is provided to receive the high voltage VPP from the outside.

센스앰프(30)는 비트라인쌍 BL, /BL에 양 출력단이 연결되어, 비트라인쌍 BL, /BL에 실린 데이터를 증폭하여 출력한다. 이를 위해, 센스앰프(30)는 피모스 트랜지스터 PM1, PM2와 엔모스 트랜지스터 NM1, NM2를 구비한다. 특히, 피모스 트랜지스터 PM1, PM2의 백바이어스전압으로서 고전압 VPP이 인가된다.The sense amplifier 30 has both output terminals connected to the bit line pairs BL and / BL, and amplifies and outputs the data carried on the bit line pairs BL and / BL. To this end, the sense amplifier 30 includes PMOS transistors PM1 and PM2 and NMOS transistors NM1 and NM2. In particular, the high voltage VPP is applied as the back bias voltage of the PMOS transistors PM1 and PM2.

메모리 셀(40)은 엔모스 트랜지스터 NM3과 셀 캐패시터 C1를 구비하고, 엔모스 트랜지스터 NM3의 게이트에 고전압 VPP이 인가된다.The memory cell 40 includes an NMOS transistor NM3 and a cell capacitor C1, and a high voltage VPP is applied to the gate of the NMOS transistor NM3.

상기와 같은 구성을 갖는 종래의 반도체 메모리 장치는 센스앰프(30)의 피모스 트랜지스터 PM1, PM2의 백바이어스전압단과 메모리 셀(40)의 엔모스 트랜지스터 NM3의 게이트에 고전압 VPP이 인가된다.In the conventional semiconductor memory device having the above configuration, the high voltage VPP is applied to the back bias voltage terminals of the PMOS transistors PM1 and PM2 of the sense amplifier 30 and the gate of the NMOS transistor NM3 of the memory cell 40.

이때, 피모스 트랜지스터 PM1, PM2의 문턱전압을 조절하여 제품의 특성을 테스트하거나 불량셀을 검출하기 위해 피모스 트랜지스터 PM1, PM2의 백바이어스전압단에 인가되는 고전압 VPP을 조절해야 하는 경우가 있는데, 종래에는 피모스 트랜지스터 PM1, PM2의 백바이어스전압단과 메모리 셀(40)의 엔모스 트랜지스터 NM3의 게이트에 동일한 고전압 VPP이 인가되므로, 피모스 트랜지스터 PM1, PM2의 백바이어스전압단에 인가되는 고전압 VPP을 조절하는 경우 메모리 셀(40)의 엔모스 트랜지스터 NM3의 게이트에 인가되는 고전압 VPP도 같이 변하게 되어 센스앰프(30)의 특성이 변할 뿐만 아니라 메모리 셀(40) 특성까지 변하게 된다. 그에 따라, 센스앰 프 특성변화에 따른 불량셀을 검출하기가 어려운 문제점이 있다.In this case, in order to test the characteristics of the product by detecting the threshold voltages of the PMOS transistors PM1 and PM2 or to detect a defective cell, it may be necessary to adjust the high voltage VPP applied to the back bias voltage terminals of the PMOS transistors PM1 and PM2. Conventionally, since the same high voltage VPP is applied to the back bias voltage terminals of the PMOS transistors PM1 and PM2 and the gate of the NMOS transistor NM3 of the memory cell 40, the high voltage VPP applied to the back bias voltage terminals of the PMOS transistors PM1 and PM2 is applied. In this case, the high voltage VPP applied to the gate of the NMOS transistor NM3 of the memory cell 40 is also changed, so that the characteristics of the sense amplifier 30 are changed as well as the characteristics of the memory cell 40. Accordingly, there is a problem in that it is difficult to detect a defective cell due to the change of the sense amplifier characteristic.

상기와 같은 문제점을 해결하기 위한 본 발명의 목적은, 테스트 모드시에 피모스 트랜지스터 PM1, PM2의 백바이어스전압단에 인가되는 고전압만 별도로 제어할 수 있도록 하여 센스앰프 특성변화에 따른 불량셀 검출이 가능하도록 하는데 있다.An object of the present invention for solving the above problems, it is possible to separately control only the high voltage applied to the back-bias voltage terminal of the PMOS transistors PM1, PM2 in the test mode to detect the defective cells according to the change of the sense amplifier characteristics. To make it possible.

상기 과제를 달성하기 위한 본 발명의 반도체 메모리 장치는, 외부전원전압을 승압시켜 고전압을 발생하는 고전압 발생부와, 상기 고전압을 백바이어스전압으로 사용하여 비트라인쌍의 데이터를 증폭하는 센스앰프와, 상기 고전압을 이용하여 상기 데이터를 저장하는 메모리 셀과, 정상모드와 테스트모드를 구별하여 상기 고전압을 선택적으로 상기 센스앰프에 인가하는 백바이어스전압 제어부와, 상기 테스트 모드시에 외부로부터 백바이어스전압을 인가받는 백바이어스전압 패드를 포함하여 구성함을 특징으로 한다.The semiconductor memory device of the present invention for achieving the above object is a high voltage generator for generating a high voltage by boosting the external power supply voltage, a sense amplifier for amplifying the data of the bit line pair using the high voltage as a back bias voltage; A memory cell for storing the data using the high voltage, a back bias voltage controller for selectively applying the high voltage to the sense amplifier by distinguishing between a normal mode and a test mode, and a back bias voltage from an external source in the test mode. It is characterized in that it comprises a back bias voltage pad applied.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 실시예에 따른 반도체 메모리 장치의 구성도이다.2 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

본 발명의 반도체 메모리 장치는 고전압 발생부(100), 고전압패드(200), 백바이어스전압 제어부(300), 백바이어스전압 패드(400), 센스앰프(500), 및 메모리셀(600)을 포함한다.The semiconductor memory device of the present invention includes a high voltage generator 100, a high voltage pad 200, a back bias voltage controller 300, a back bias voltage pad 400, a sense amplifier 500, and a memory cell 600. do.

고전압 발생부(100)는 외부전원전압을 승압하여 고전압 VPP을 발생한다. 이 를 위해, 고전압 발생부(100)는 기준전압 발생부(미도시), 전압분배부(미도시), 비교부(미도시), 오실레이터(미도시), 차지펌프(미도시), 및 승압부(미도시) 등을 포함한다.The high voltage generator 100 boosts the external power supply voltage to generate a high voltage VPP. To this end, the high voltage generator 100 may include a reference voltage generator (not shown), a voltage divider (not shown), a comparator (not shown), an oscillator (not shown), a charge pump (not shown), and a boosted voltage. And the like (not shown).

고전압패드(200)는 외부에서 고전압 VPP을 인가받는다.The high voltage pad 200 receives a high voltage VPP from the outside.

백바이어스전압 제어부(300)는 테스트모드신호 TM에 의해 제어되어 고전압 VPP을 피모스 트랜지스터 PM3의 백바이어스전압단에 인가할지를 제어하는 엔모스 트랜지스터 NM4를 구비한다. 이때, 테스트모드신호 TM는 외부로부터 인가된다.The back bias voltage control unit 300 includes an NMOS transistor NM4 that is controlled by the test mode signal TM to control whether the high voltage VPP is applied to the back bias voltage terminal of the PMOS transistor PM3. At this time, the test mode signal TM is applied from the outside.

백바이어스전압 패드(400)는 피모스 트랜지스터 PM3의 백바이어스전압으로 사용되는 고전압 VPP을 외부에서 인가받는다.The back bias voltage pad 400 is externally applied with the high voltage VPP used as the back bias voltage of the PMOS transistor PM3.

센스앰프(500)는 비트라인쌍 BL, /BL에 양 출력단이 연결되어, 비트라인쌍 BL, /BL에 실린 데이터를 증폭하여 출력한다. 이를 위해, 센스앰프(500)는 피모스 트랜지스터 PM3, PM4와 엔모스 트랜지스터 NM5, NM6를 구비한다. 이때, 피모스 트랜지스터 PM3, PM4는 그 소스에 센스앰프제어신호 RTO가 인가되고 드레인은 비트라인쌍 BL, /BL에 각각 연결되며, 게이트가 엔모스 트랜지스터 NM5, NM6의 게이트에 각각 접속되며, 피모스 트랜지스터 PM3, PM4의 백바이어스전압으로서 고전압 VPP이 인가된다. 또한, 엔모스 트랜지스터 NM5, NM6는 드레인이 비트라인쌍 BL, /BL에 접속되고 소스에 센스앰프 제어신호 SB가 인가된다.The sense amplifier 500 is connected to both output terminals of the bit line pairs BL and / BL, and amplifies and outputs data loaded on the bit line pairs BL and / BL. To this end, the sense amplifier 500 includes PMOS transistors PM3 and PM4 and NMOS transistors NM5 and NM6. At this time, the sense amplifier control signal RTO is applied to the PMOS transistors PM3 and PM4, the drain is connected to the bit line pairs BL and / BL, respectively, and the gate is connected to the gates of the NMOS transistors NM5 and NM6, respectively. The high voltage VPP is applied as the back bias voltages of the MOS transistors PM3 and PM4. In addition, the NMOS transistors NM5 and NM6 have drains connected to the bit line pairs BL and / BL, and a sense amplifier control signal SB is applied to the source.

메모리 셀(600)은 엔모스 트랜지스터 NM7과 셀캐패시터 C2를 구비한다. 엔모스 트랜지스터 NM7는 게이트에 워드라인 WL이 접속되고 드레인에 비트라인바 /BL가 접속되고 소스에 캐패시터 C2의 일측이 접속된다. 캐패시터 C2는 일측이 엔모스 트 랜지스터 NM7에 접속되고 타측이 접지전압단에 접속된다. The memory cell 600 includes an NMOS transistor NM7 and a cell capacitor C2. In the NMOS transistor NM7, a word line WL is connected to a gate, a bit line bar / BL is connected to a drain, and one side of the capacitor C2 is connected to a source. One side of the capacitor C2 is connected to the NMOS transistor NM7 and the other side is connected to the ground voltage terminal.

상기와 같은 구성을 갖는 반도체 메모리 장치는 정상 모드시에는 엔모스 트랜지스터 NM4를 턴온시켜 피모스 트랜지스터 PM3의 백바이어스전압단과 메모리 셀(600)의 엔모스 트랜지스터 NM7의 게이트에 고전압 VPP이 그대로 인가된다.In the semiconductor memory device having the above configuration, in the normal mode, the NMOS transistor NM4 is turned on so that the high voltage VPP is applied to the back bias voltage terminal of the PMOS transistor PM3 and the gate of the NMOS transistor NM7 of the memory cell 600 as it is.

한편, 테스트 모드시에는 엔모스 트랜지스터 NM4를 턴오프시켜 메모리 셀(600)의 엔모스 트랜지스터 NM7의 게이트에는 고전압 VPP이 그대로 인가되고 피모스 트랜지스터 PM3의 백바이어스전압단에는 고전압 VPP의 인가를 차단한 후, 백바이어스전압패드(400)를 통해 외부에서 백바이어스전압 VBB을 조절하여 인가한다.Meanwhile, in the test mode, the NMOS transistor NM4 is turned off, and the high voltage VPP is applied to the gate of the NMOS transistor NM7 of the memory cell 600 as it is, and the application of the high voltage VPP is blocked to the back bias voltage terminal of the PMOS transistor PM3. Thereafter, the back bias voltage VBB is controlled and applied from the outside through the back bias voltage pad 400.

이와같이, 정상 모드와 테스트 모드를 구별하여 피모스 트랜지스터 PM3의 백바이어스전압을 조절하여 인가함으로써 센스앰프 특성 변화에 따른 불량셀을 검출할 수 있는 테스트가 가능하다.As described above, a test capable of detecting a defective cell according to a change in the sense amplifier characteristic is possible by distinguishing the normal mode from the test mode and applying and controlling the back bias voltage of the PMOS transistor PM3.

이상에서 살펴본 바와 같이, 본 발명은 테스트 모드시에 피모스 트랜지스터 PM1, PM2의 백바이어스전압단에 인가되는 고전압만 별도로 제어할 수 있도록 하여 정확한 테스트를 가능하게 하여 반도체 메모리 장치의 개발시간을 단축시키고 수율을 향상시키는 효과가 있다.As described above, in the test mode, only the high voltage applied to the back bias voltage terminals of the PMOS transistors PM1 and PM2 can be controlled separately, thereby enabling accurate testing to shorten the development time of the semiconductor memory device. There is an effect of improving the yield.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허 청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허 청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, replacements and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (3)

외부전원전압을 승압시켜 고전압을 발생하는 고전압 발생부;A high voltage generating unit generating a high voltage by boosting an external power supply voltage; 상기 고전압을 백바이어스전압으로 사용하여 비트라인쌍의 데이터를 증폭하는 센스앰프;A sense amplifier for amplifying data of a bit line pair using the high voltage as a back bias voltage; 상기 고전압을 이용하여 상기 데이터를 저장하는 메모리 셀;A memory cell storing the data using the high voltage; 정상모드와 테스트모드를 구별하여 상기 고전압을 선택적으로 상기 센스앰프에 인가하는 백바이어스전압 제어부; 및A back bias voltage controller for discriminating the normal mode from the test mode and selectively applying the high voltage to the sense amplifier; And 상기 테스트 모드시에 외부로부터 백바이어스전압을 인가받는 백바이어스전압 패드를 포함하여 구성하는 것을 특징으로 하는 반도체 메모리 장치.And a back bias voltage pad receiving a back bias voltage from the outside in the test mode. 제 1항에 있어서, 상기 백바이어스전압 제어부는,The method of claim 1, wherein the back bias voltage control unit, 상기 정상모드시에는 턴온되고 상기 테스트모드시에는 턴오프되는 것을 특징으로 하는 반도체 메모리 장치.And turn off in the normal mode and turn off in the test mode. 제 2항에 있어서, 상기 백바이어스전압 제어부는,The method of claim 2, wherein the back bias voltage control unit, 테스트 모드신호에 의해 제어되어 상기 고전압을 상기 센스앰프에 인가하는 엔모스 트랜지스터를 구비함을 특징으로 하는 반도체 메모리 장치.And an NMOS transistor controlled by a test mode signal to apply the high voltage to the sense amplifier.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100806141B1 (en) * 2006-09-04 2008-02-22 주식회사 하이닉스반도체 Semiconductor memory device and driving method thereof
EP4102505A4 (en) * 2020-08-27 2023-10-04 Changxin Memory Technologies, Inc. Memory adjustment method and adjustment system, and semiconductor device
US11886721B2 (en) 2020-08-27 2024-01-30 Changxin Memory Technologies, Inc. Method and system for adjusting memory, and semiconductor device
US11984190B2 (en) 2020-08-27 2024-05-14 Changxin Memory Technologies, Inc. Method and system for adjusting memory, and semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100806141B1 (en) * 2006-09-04 2008-02-22 주식회사 하이닉스반도체 Semiconductor memory device and driving method thereof
EP4102505A4 (en) * 2020-08-27 2023-10-04 Changxin Memory Technologies, Inc. Memory adjustment method and adjustment system, and semiconductor device
US11886721B2 (en) 2020-08-27 2024-01-30 Changxin Memory Technologies, Inc. Method and system for adjusting memory, and semiconductor device
US11928357B2 (en) 2020-08-27 2024-03-12 Changxin Memory Technologies, Inc. Method and system for adjusting memory, and semiconductor device
US11984190B2 (en) 2020-08-27 2024-05-14 Changxin Memory Technologies, Inc. Method and system for adjusting memory, and semiconductor device

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