JP3665701B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device that is useful for manufacturing a trench capacitor structure DRAM or the like.
[0002]
[Prior art]
Conventionally known processes for manufacturing a DRAM having a memory cell of 1 transistor / 1 capacitor and a trench capacitor structure are as follows. First, a hard mask made of a laminated film of a silicon nitride film (SiN film) and a silicon oxide film (SiO ₂ film) is patterned on a silicon substrate, and the substrate is etched using the hard mask to form an island shape that is formed later. The capacitor groove is processed so as to be located at the end of the element formation region. The trench is filled with polysilicon or the like to be a capacitor node after a capacitor insulating film is formed on the side wall.
[0003]
FIG. 14 shows a state in which the capacitor groove 103 is formed in the silicon substrate 101 in this way, and the polysilicon 104 is buried in the groove 103. An isolation silicon oxide film 105 is formed in the upper part of the trench, and a capacitor insulating film is formed in a portion omitted from the silicon oxide film 105 in the figure below. Of the silicon nitride film / silicon oxide film laminated film used as the hard mask, the silicon oxide film is removed, leaving only the silicon nitride film 102.
[0004]
Thereafter, with the silicon nitride film 102 left, a photoresist 107 is applied via an antireflection film 106 as shown in FIG. Then, this photoresist 107 is exposed, a resist pattern is formed so as to cover the island-shaped element formation region, and the silicon nitride film 102 and the silicon substrate 101 in the element isolation region are etched as shown in FIG. The element isolation groove 108 is processed.
[0005]
Thereafter, an element isolation insulating film is embedded in the element isolation trench 108 formed. In this way, a MOS transistor is formed in each element formation region separated from each other. The gate electrode of the MOS transistor is continuously arranged across a plurality of element formation regions, and this becomes a word line. Thereafter, an interlayer insulating film is deposited, contact holes are formed, and bit lines are provided.
[0006]
[Problems to be solved by the invention]
In the conventional trench capacitor structure DRAM manufacturing process described above, when microfabrication is performed using the submicron rule or sub-quarter micron rule, a thin film of about 0.6 μm is used in order to increase the margin of lithography technology. It is necessary to use a photoresist. In general, when trying to obtain a high resolution using an ultraviolet exposure apparatus having a large NA, the depth of focus becomes small, so that a fine resist pattern can be patterned with a sufficient resolution with a thick photoresist of 0.8 μm or more. Because it is difficult.
[0007]
However, since there is a step due to the silicon nitride film 102 on the substrate surface after the trench capacitor is formed as shown in FIG. 14, the thickness of the photoresist 107 applied flatly in the subsequent resist coating process is as follows. Even if it is 0.6 μm above, it is thicker at the stepped portion. For example, if the silicon nitride film 102 has a thickness of 0.15 μm and the surface position of the polysilicon 104 embedded in the trench 103 is 0.05 μm lower than the substrate surface, the photoresist 107 has a thickness of 0.8 μm at the step portion. . Since the margin of lithography is rate-determined by the thickness of the photoresist, the margin does not increase as much as the thin film photoresist is used.
[0008]
If the photoresist 107 is as thin as about 0.6 μm, when dry etching is used in the next substrate etching step shown in FIG. 16, the photoresist 107 is interposed between the silicon substrate 101 or the silicon nitride film 102. Since a large selection ratio cannot be obtained, a situation in which a desired element separation process cannot be performed occurs.
[0009]
The present invention has been made in consideration of the above circumstances, and is intended to increase the margin by performing lithography on a flat substrate on a flat surface, and to form a silicon oxide film / silicon nitride film using a thin film photoresist. It is an object of the present invention to provide a method for manufacturing a semiconductor device that enables microfabrication by performing the etching of the laminated film by dry etching under a predetermined gas condition.
[0010]
[Means for Solving the Problems]
A method of manufacturing a semiconductor device according to the present invention includes a step of patterning a first hard mask formed of a laminated film of a silicon nitride film and a first silicon oxide film on a semiconductor substrate, and using the first hard mask. Etching the semiconductor substrate to form a groove; and removing a first silicon oxide film from the first hard mask and then leaving a step due to the silicon nitride film, a predetermined material film in the groove A step of embedding, a step of forming a second silicon oxide film on the semiconductor substrate so as to have a flat surface, and applying a photoresist on the second silicon oxide film with a uniform thickness and exposing the photoresist. A step of forming a photoresist pattern; and anisotropic drying using an etching gas containing at least a CF-based gas and an Ar gas, using the photoresist pattern. Patterning a second hard mask by continuously etching the second silicon oxide film and the underlying silicon nitride film by etching, and processing the semiconductor substrate using the second hard mask And a process of
It is characterized by having.
[0011]
The method for manufacturing a semiconductor device according to the present invention also includes a step of patterning a first hard mask made of a laminated film of a silicon nitride film and a first silicon oxide film on a semiconductor substrate, and using the first hard mask. Etching the semiconductor substrate to form a capacitor groove, and removing the first silicon oxide film from the first hard mask and then leaving a step due to the silicon nitride film. A step of forming a trench capacitor of a DRAM cell by embedding a conductive material serving as a capacitor node through a capacitor insulating film therein; a step of forming a second silicon oxide film on the semiconductor substrate so that the surface is flat; A photoresist is coated on the second silicon oxide film with a uniform thickness and exposed to form a photoresist pattern. And etching the second silicon oxide film and the underlying silicon nitride film by anisotropic dry etching using an etching gas containing at least a CF-based gas and Ar gas, using the photoresist pattern. Forming a pattern of the second hard mask, etching the semiconductor substrate using the second hard mask to form an element isolation groove, and isolating the element isolation groove in the element isolation groove A step of embedding a film; and a step of forming a MOS transistor of a DRAM cell in an element formation region of the semiconductor substrate exposed by removing the second hard mask.
[0012]
Preferably, in the present invention, as the second silicon oxide film, at least one of a silicon oxide film by a low pressure CVD method using organooxysilane as a raw material and a boron-doped silicon oxide film by a low pressure CVD method are used. As the gas, a mixed gas containing CHF ₃ , CF ₄ and Ar gas is used.
[0013]
According to the present invention, in the case where a trench capacitor or the like is formed in the opening of the silicon nitride film in a state where there is a step due to the silicon nitride film, and then the substrate processing is further performed, The photoresist is flattened and applied with a uniform thickness. Accordingly, it is possible to expand the lithography margin with the thin film photoresist. Also, using the obtained photoresist pattern, the laminated film of the silicon oxide film used for planarization and the underlying silicon nitride film is etched by anisotropic dry etching using an etching gas containing CF-based gas and Ar gas. Then, the next substrate processing such as element isolation groove formation is performed using the hard mask formed thereby. This makes it possible to manufacture a DRAM or the like having an element formation region with a fine dimension.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment in which the present invention is applied to a DRAM having a trench capacitor structure using a deep trench will be described below with reference to the drawings.
FIG. 1 is a cross-sectional view of a capacitor groove forming process. In this example, the silicon substrate 10 includes a p-type layer 11, an n − -type layer 12, and a p-type layer 13. A thermal oxide film 21 having a thickness of about 6 nm is formed on the silicon substrate 10. A silicon nitride film 22 having a thickness of about 0.22 .mu.m is formed thereon by low pressure CVD or sputtering, and a silicon oxide film 23 having a thickness of about 0.7 .mu.m is formed by CVD. Are sequentially stacked. A photoresist (not shown) is applied on the laminated film and a lithography process is performed. Using the formed resist pattern, the silicon oxide film 23, the silicon nitride film 22 and the thermal oxide film 21 are sequentially etched away. As a result, a first hard mask made of a laminated film of the silicon nitride film 22 and the silicon oxide film 23 is obtained. After the patterning of the hard mask, the photoresist is removed, and the silicon substrate 10 is etched by the RIE method using the obtained hard mask to process the capacitor groove 31 as shown. The grooves 31 are assumed to be deep, for example, about 7 μm.
[0015]
Next, as shown in FIG. 2, first, arsenic-doped polysilicon is buried in the groove 31 to a predetermined depth by CVD and dry etching, and this is used as a solid phase diffusion source to form a plate electrode along the groove 31. A mold layer 33 is formed. Once the arsenic doped polysilicon is removed, a capacitor insulating film 32 is formed on the sidewall of the trench 31. The capacitor insulating film 32 is, for example, a silicon oxynitride film (NO film) composed of a silicon nitride film formed by a low pressure CVD method and an oxide film formed on the surface thereof. Then, arsenic-doped polysilicon is again buried in the groove 31 to a predetermined depth by low-pressure CVD and dry etching, the capacitor insulating film on the top is removed, and then the silicon oxide film 35 to be a collar is formed by CVD and dry etching. Form. Further, arsenic-doped polysilicon is buried in the groove 31 to a depth of about 0.12 μm from the substrate surface by CVD and dry etching, and the silicon oxide film 35 exposed on the groove 31 is about 0.18 μm by HF wet etching. Remove to depth. The portion where the silicon oxide film 35 is removed becomes a portion where a buried strap for connecting the diffusion layer of the MOS transistor and the capacitor is formed by solid phase diffusion from the polysilicon 34 in the trench 31 in the future. Controlling its depth is important. Thereafter, high resistance polysilicon is buried in the groove 31 to a depth of 0.4 μm from the substrate surface by CVD and dry etching. This is to reliably prevent a short circuit between the passing word line and the capacitor node when the element isolation insulating film is embedded and a passing word line is provided thereon as will be described later.
[0016]
In this manner, as shown in FIG. 2, the capacitor node 34 is embedded and the trench capacitor 20 is obtained. During the trench capacitor 20 formation process described above, the silicon nitride film 22 covers the substrate surface outside the capacitor region, and functions as an etching stopper in a plurality of filling steps of polysilicon or other trenches 31. After the trench capacitor 20 is formed, a lithography process for processing the next element isolation trench is performed with the silicon nitride film 22 left as shown in FIG.
[0017]
The plan view of the substrate at the stage of FIG. 2 is as shown in FIG. A region surrounded by a broken line is used as an element formation region 30 (active region), but at this stage, the element is not yet separated. A trench capacitor 20 is formed in an opening located at an end portion of the element forming region 30 of the silicon nitride film 22 shown by hatching. FIG. 2 shows a cross-section at the position AA ′ in FIG.
[0018]
As described above, since the step where the trench capacitor 20 is formed has a step of about 0.2 μm, which is substantially determined by the thickness of the silicon nitride film 22, before entering the lithography process, as shown in FIG. A silicon oxide film 24 is deposited to flatten the surface. The silicon oxide film 24 is, for example, a silicon oxide film (hereinafter referred to as a TEOS film) by a low pressure CVD method using organooxysilane as a raw material or a boron-doped silicon oxide film (hereinafter referred to as a BSG film) by a low pressure CVD method. Is about 0.3 μm.
[0019]
On the thus flattened substrate, as shown in FIG. 3, an antireflection film 25 made of an organic insulating film is formed, and a photoresist 26 is applied thereon by 0.6 μm. Then, the photoresist 26 is exposed and developed to form a resist pattern covering the element formation region as shown in FIG. Since the thin film photoresist 26 has a uniform thickness on the substrate, this lithography is performed with high resolution. FIG. 12 is a plan view at this stage, and FIG. 4 corresponds to a cross-section at the position AA ′ in FIG.
[0020]
Then, as shown in FIG. 5, reflection of the element isolation region is performed by anisotropic dry etching using a mixed gas containing at least CF gas and Ar gas using the patterned photoresist 26 as a mask. The prevention film 25, the silicon oxide film 24, and the silicon nitride film 22 are sequentially removed by etching. Specifically, when the silicon oxide film 24 is a TEOS film, a mixed gas of CHF ₃ / CF ₄ / Ar / O ₂ is used as an etching gas, and when the silicon oxide film 24 is a BSG film, CHF ₃ / CF ₄ / Ar mixed gas is used as an etching gas.
[0021]
The preferable etching gas conditions are CHF ₃ / CF ₄ / Ar / O ₂ = 56/14/70/5 [SCCM] when the silicon oxide film 24 is a TEOS film, and the silicon oxide film 24 is a BSG film. In this case, CHF ₃ / CF ₄ / Ar = 56/14/70 [SCCM]. By using this condition, even if the photoresist 26 is a thin film of 0.6 μm, the laminated film of the silicon nitride film 22 and the silicon oxide film 24 can be etched simultaneously.
[0022]
In the etching process of the silicon oxide film 24 and the silicon nitride film 22 using the above-described etching gas, at the same time as the etching progresses, a certain polymer containing a Si—C bond is generated, and the surface and side surfaces of the photoresist 26 are further formed. A reaction of depositing on the side surfaces of the etched silicon oxide film 24 and silicon nitride film 22 occurs, and this serves to suppress the progress of etching of the photoresist 26 itself. This enables etching of the laminated film of the thick silicon oxide film 24 and the silicon nitride film 22 with a thin film photoresist. In particular, the polymer adhering to the side surfaces of the photoresist 26 and the etched silicon oxide film 24 suppresses the receding of the side surfaces due to the lateral etching, thereby enabling highly accurate pattern transfer.
[0023]
The photoresist 26 remaining in the above etching process is then peeled off.
Subsequently, using the second hard mask composed of the patterned silicon oxide film 24 and silicon nitride film 22, the silicon substrate 10 is etched by RIE using an NF ₃ / Ar mixed gas as an etching gas, and FIG. As shown in FIG. 4, an element isolation groove 27 having a depth of about 0.35 μm is formed. In this embodiment, the photoresist 26 is stripped before etching the silicon substrate, but the substrate may be etched without stripping it. The silicon oxide film 24 remaining on the silicon nitride film 22 in this substrate etching process is about 0.2 μm. The remaining silicon oxide film 24 is removed by HF wet etching.
[0024]
In this HF-based wet etching process, lateral etching of the thermal oxide film 21 underlying the silicon nitride film 22 exposed on the side surface in the direction perpendicular to the paper surface occurs, and if this lateral etching is large, an element to be formed later Cause deterioration of characteristics. For this measure, it is preferable to use a BSG film as the silicon oxide film 24. This is because the BSG film has a high wet etching selectivity with respect to the thermal oxide film and can suppress lateral etching.
[0025]
Then, after forming a thermal oxide film on the surface of the silicon substrate, a silicon oxide film is deposited by a low pressure CVD method, and planarized by CMP treatment using the silicon nitride film 22 as an etching stopper, as shown in FIG. An STI (Shllow Trench Isolation) film 28 which is an element isolation insulating film is buried and formed so as to be substantially the same surface position as the nitride film 22. In this state, well formation of each element region is performed by ion implantation (not shown).
[0026]
Thereafter, the silicon nitride film 22 is removed by etching with phosphoric acid to expose the substrate surface in the element forming region, and the MOS transistor forming process is started. When the silicon nitride film 22 is removed by etching from the state shown in FIG. 7, the STI film 28 in the element isolation region becomes convex. In order to reduce this convexity, the surface of the STI film 28 may be recessed in advance. preferable. The drawings after FIG. 8 are shown in a reduced scale compared with the drawings so far. First, as shown in FIG. 8, after forming a gate oxide film 41, a gate electrode 42 made of a laminated film of a polysilicon film 42a and a WSi film 42b is patterned using the silicon nitride film 43 as a mask, and sidewall insulation by the silicon nitride film is performed. After the film 44 is formed, source and drain n + type diffusion layers 46 and 47 are formed by ion implantation. One diffusion layer 47 is connected to the capacitor node 34 via a diffusion layer 48 formed by lateral diffusion from the capacitor node 34.
[0027]
The gate electrode 42 is continuously arranged in a direction perpendicular to the paper surface across a plurality of element regions to form a word line. The plan view is shown in FIG. FIG. 8 corresponds to a cross-section at the position AA ′ in FIG. 13.
[0028]
Thereafter, as shown in FIG. 9, an interlayer insulating film 51 is formed, a bit line contact hole is processed therein, and polysilicon 52 is buried in the contact hole so that the surface is flat, and then a bit formed of a W film is formed. Line 53 is formed.
[0029]
Thereafter, as shown in FIG. 10, an interlayer insulating film 54 is deposited, a first layer Al wiring 55 is formed on the word line, and an interlayer insulating film 56 is further deposited to form a second layer Al wiring. 57 is formed and finally a passivation film 58 is formed to complete the DRAM.
[0030]
As described above, in this embodiment, the lithography using the thin film photoresist for the next element isolation groove processing is performed in the state where there is a step due to the silicon nitride film 22 after the trench capacitor is formed, as described in FIG. Further, the substrate is planarized by the silicon oxide film 24. As a result, the thin film photoresist 26 can have a uniform thickness on the substrate surface, and high-resolution lithography is possible. In the etching process of the silicon oxide film 24 and the silicon nitride film 22 using the patterned photoresist 26, RIE using an etching gas containing CHF ₃ / CF ₄ / Ar is used. By optimally setting, even if the photoresist 26 is as thin as 0.6 μm, it is possible to pattern a hard mask with a silicon oxide film / silicon nitride film laminated film with high accuracy for processing an element isolation groove. it can. Then, by performing substrate isolation for element isolation using this hard mask, the substrate etching selectivity can be made sufficiently large, and highly accurate substrate processing can be performed.
[0031]
As described above, a trench capacitor structure DRAM can be manufactured with high accuracy by a sub-micron or sub-quarter micron design rule.
The present invention is not limited to the manufacture of DRAMs, but can be similarly applied to the manufacture of other semiconductor devices that require similar substrate processing steps.
[0032]
【The invention's effect】
As described above, according to the present invention, the lithography process is performed on the substrate surface flattened with the silicon oxide film, and the etching of the silicon oxide film / silicon nitride film with the photoresist pattern is performed under the predetermined gas condition. By performing this anisotropic dry etching and forming a hard mask for the subsequent substrate processing, the subsequent substrate processing can be performed with high accuracy. In particular, if the present invention is applied to the manufacture of a DRAM having a trench capacitor structure, the DRAM can be manufactured with a fine design rule.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a capacitor trench forming step of a DRAM according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view of a capacitor node embedding process according to the same embodiment;
FIG. 3 is a cross-sectional view of a state where the substrate is flattened and a photoresist is applied in the embodiment.
FIG. 4 is a cross-sectional view showing a state in which a photoresist is patterned in the embodiment.
FIG. 5 is a cross-sectional view showing a state in which a silicon oxide film / silicon nitride film is etched using a resist pattern in the embodiment.
6 is a cross-sectional view showing a state where an element isolation trench is formed using a silicon oxide film / silicon nitride film hard mask in the same example. FIG.
FIG. 7 is a cross-sectional view showing a state where an element isolation insulating film is embedded in the embodiment.
FIG. 8 is a cross-sectional view of a state where a MOS transistor is formed in the same embodiment.
FIG. 9 is a cross-sectional view of a state where bit lines are formed in the same embodiment.
FIG. 10 is a cross-sectional view after the completion of the DRAM in the embodiment.
FIG. 11 is a plan view of the substrate corresponding to the process of FIG. 2;
12 is a plan view of the substrate corresponding to the process of FIG. 4; FIG.
13 is a plan view of the substrate corresponding to the process of FIG. 8. FIG.
FIG. 14 is a cross-sectional view of a capacitor node embedding process in a conventional DRAM manufacturing process.
FIG. 15 is a cross-sectional view showing a lithography process for element isolation groove processing in a conventional DRAM manufacturing process.
FIG. 16 is a cross-sectional view showing a lithography process for element isolation groove processing in a conventional DRAM manufacturing process.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Silicon substrate, 22 ... Silicon nitride film, 23 ... Silicon oxide film, 31 ... Capacitor groove, 32 ... Capacitor insulating film, 33 ... N-type layer, 34 ... Capacitor node, 20 ... Trench capacitor, 26 ... Photoresist, 27... Element isolation trench 28. STI film 40. MOS transistor

Claims (3)

Patterning a first hard mask comprising a laminated film of a silicon nitride film and a first silicon oxide film on a semiconductor substrate;
Etching the semiconductor substrate using the first hard mask to form a groove;
Burying a predetermined material film in the trench in a state where a step due to the silicon nitride film remains after removing the first silicon oxide film of the first hard mask;
Forming a second silicon oxide film on the semiconductor substrate so as to have a flat surface;
Applying a photoresist with a uniform thickness on the second silicon oxide film and exposing it to form a photoresist pattern;
Using the photoresist pattern, the second silicon oxide film and the underlying silicon nitride film are continuously etched by anisotropic dry etching using an etching gas containing at least CF gas and Ar gas. Forming a hard mask pattern,
Processing the semiconductor substrate using the second hard mask;
A method for manufacturing a semiconductor device, comprising: Patterning a first hard mask comprising a laminated film of a silicon nitride film and a first silicon oxide film on a semiconductor substrate;
Etching the semiconductor substrate using the first hard mask to form a capacitor trench;
After removing the first silicon oxide film from the first hard mask, a conductive material to be a capacitor node is embedded in the capacitor trench with a capacitor insulating film in a state where a step due to the silicon nitride film remains. Forming a DRAM cell trench capacitor;
Forming a second silicon oxide film on the semiconductor substrate so as to have a flat surface;
Applying a photoresist with a uniform thickness on the second silicon oxide film and exposing it to form a photoresist pattern;
Using the photoresist pattern, the second silicon oxide film and the underlying silicon nitride film are continuously etched by anisotropic dry etching using an etching gas containing at least CF gas and Ar gas. Forming a hard mask pattern,
Etching the semiconductor substrate using the second hard mask to form an element isolation trench;
Embedding and forming an element isolation insulating film in the element isolation trench;
Forming a MOS transistor of a DRAM cell in an element formation region of the semiconductor substrate exposed by removing the second hard mask. The second silicon oxide film is at least one of a silicon oxide film by a low pressure CVD method using organooxysilane as a raw material and a boron-doped silicon oxide film by a low pressure CVD method,
The method for manufacturing a semiconductor device according to claim 1, wherein the etching gas is a mixed gas containing CHF ₃ , CF _4, and Ar gas.

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