JP3632806B2 - Performance information storage device and medium on which performance information storage program is recorded - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a performance information storage device, a performance information storage method, and a medium recording a performance information storage program suitable for use in a performance recording / playback device such as a sequencer.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a sequencer (performance recording / playback device) is known that stores performance information including the pitch of each note and the sounding timing for each note of a desired music piece and plays it at the tempo at which it was played or at a specified tempo. It has been. In this sequencer, step information for inputting performance information representing pitches, note lengths, etc., one step at a time, and performance information generated in response to actual performance operation (for example, keyboard operation) are stored and held in real time. A performance information storage device is provided.
[0003]
[Problems to be solved by the invention]
In such a performance information storage device, in order to store performance information by real-time input, the start switch for instructing the storage start is operated after specifying the song number to be stored, and when the storage is finished, the stop is stopped. Various switch operations such as operating switches are required.
[0004]
For this reason, for example, when it is desired to immediately write down a fragmentary phrase that comes to mind during composition performance, the operation becomes unsuitable. In other words, there is no consciousness of “recording a performance” in the middle of expressing the phrase drawn in the mind, and if the various switch operations described above are performed in such a state, the flow of thought in the creation process There is a problem that the operation is obstructed and the operation becomes troublesome.
[0005]
Accordingly, the present invention has been made in view of the above-described circumstances, and a performance information storage device and performance information that can be stored and stored with one touch of a phrase that has been input for performance or that can be automatically stored and stored without any switch operation. It is an object to provide a storage method and a medium on which a performance information storage program is recorded.
[0009]
[Means for Solving the Problems]
To achieve the above objective,Claim1In the performance information storage device described in 1), a storage means comprising a buffer area for temporarily storing performance information generated in response to a performance operation, and a bank area for storing and storing the performance information;thisThe performance information is sequentially temporarily stored in the buffer area of the storage means,Previous performance operationMore than a certain time sincedidlaterNewWhen a performance operation is performed, the data stored in the buffer areaSaidPrevious performance operationFor up toStorage control means for transferring performance information to the bank area for storage and storage;Means for instructing performance information stored in the buffer area not to be transferred to and stored in the bank area, and in the designated state, a new performance operation is performed after a predetermined time has elapsed since the previous performance operation. Transfer prevention means for controlling the storage control means so as not to transfer and store the performance information stored in the buffer area to the bank area even ifIt is characterized by comprising.
[0011]
Claim2In the medium recorded with the performance information storage program described in 1., the performance information generated in response to the performance operation is stored.,Buffer area of storage meansIn orderNext temporary storageTemporary storage procedure and previous performance operationMore than a certain time sincedidlaterNewWhen a performance operation is performed, the data stored in the buffer areaSaidPrevious performance operationFor up toPerformance information,SaidStorage meansTransfer to bank area and saveIn a state where the transfer storage procedure and the performance information stored in the buffer area are instructed not to be transferred and stored in the bank area, a new performance operation is performed after a predetermined time has elapsed since the previous performance operation. Even so, the transfer prevention procedure for controlling the performance information stored in the buffer area so as not to be transferred and stored in the bank area is recorded so as to be readable and executable by the computer.It is characterized by that.
[0013]
BookAccording to the invention, when a performance operation is performed again after a predetermined time has elapsed after completion of the performance operation, the performance information corresponding to the previous performance operation stored in the buffer area of the storage means is automatically transferred to the bank area. And saveOn the other hand, when transfer prevention is instructed, the performance information stored in the buffer area is discarded without being transferred to the bank area even if a performance operation is performed again after a certain period of time has elapsed.To do. As a result, it is possible to automatically store and save a phrase that has been input without performing any operation.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
The medium storing the performance information storage device, performance information storage method, and performance information storage program according to the present invention can be applied to a computer music device using an electronic musical instrument or a personal computer in addition to a sequencer. Hereinafter, an electronic musical instrument according to an embodiment of the present invention will be described as an example with reference to the drawings.
[0015]
A. First embodiment
(1) Overall configuration
FIG. 1 is a block diagram showing a configuration of an electronic musical instrument according to a first embodiment of the present invention. In this figure, reference numeral 1 denotes a keyboard, which generates performance information such as a key-on / key-off signal corresponding to a pressed / released key operation (performance operation), a key code, and velocity information corresponding to a key pressing speed (strength).
[0016]
Reference numeral 2 denotes a panel switch group disposed on the front surface of the musical instrument panel. For this panel switch group 2, in addition to an on / off switch for turning on the power and a tone color selection switch, a bank switch BS and a phrase bank (to be described later) which are operated when recording performance information of the phrase inputted by the performance are selected. A bank select switch BSEL and the like are provided. Reference numeral 3 denotes a display unit composed of an LCD panel or the like, which displays an operation mode and various setting states of the entire musical instrument in accordance with a display control signal supplied from a CPU 4 described later.
[0017]
The CPU 4 has a function of storing and reproducing the performance information in addition to instructing the tone generator 7 (described later) to generate a musical sound according to the performance information output from the keyboard 1. The operation of the CPU 4 according to the gist of the present invention will be described later. Reference numeral 5 denotes a ROM that stores various parameters and tables for tone control in addition to various control programs loaded into the CPU 4.
[0018]
The program and data stored in the ROM 5 may be stored in the storage device 10 including a recording medium. The recording medium may be a magnetic recording, magneto-optical recording, optical recording on a fixed or removable medium. In addition to recording, it is also possible to use a rewritable nonvolatile semiconductor memory such as a flash memory such as an IC card.
The program and data stored in the ROM 5 can be received from other devices connected via a communication line or the like and stored in the recording medium described above. A configuration may be adopted in which the data is downloaded to a rewritable nonvolatile memory such as a flash memory provided in place of the ROM 3.
[0019]
A RAM 6 is used as a work area for the CPU 4 and includes a phrase area for storing and holding performance information in accordance with the on operation of the bank switch BS, in addition to various calculation results and registers / flags. Although the configuration of the phrase area will be described later, the phrase area is not limited to the RAM 6, and an electrically rewritable nonvolatile memory may be separately provided and assigned to the memory.
[0020]
The sound source 7 is configured by a well-known waveform memory reading method and includes a plurality of sound generation channels that perform time-division operation. The sound source 7 stores waveform data of various timbres, and reads waveform data of timbres designated in advance according to performance information supplied from the CPU 4 to generate a musical sound waveform W.
A D / A conversion circuit 8 converts the musical sound waveform W output from the sound source 7 into an analog waveform signal and supplies the analog waveform signal to the next sound system 9. For example, the sound system 9 performs filtering, such as removing unnecessary noise, on the analog waveform signal supplied from the previous stage, and then amplifies this to generate sound from the speaker.
[0021]
(2) Configuration of RAM 6
Next, the configuration of the phrase area provided in the RAM 6 will be described with reference to FIGS.
In FIG. 2, Rp is a read pointer that designates a read address of a temporary buffer TB described later. Wp is a write pointer that designates a write address of the temporary buffer PB. That is, the read pointer Rp and the write pointer Wp manage the read / write position of the temporary buffer TB.
[0022]
The temporary buffer TB temporarily stores performance information generated in response to key pressing / release operations on the keyboard 1. PB is a phrase bank area formed from the phrase banks PB (0) to P (n). Each of the phrase banks PB (0) to PB (n) is selected in response to the operation of the bank select switch BSEL described above, and is updated and specified when storing and holding performance information. The performance information temporarily stored in the temporary buffer TB is stored and saved for the designated phrase banks PB (0) to PB (n).
[0023]
DIR is a directory area that stores data for managing the head addresses and data sizes of the phrase banks PB (0) to PB (n). That is, as shown in FIG. 3, the directory area DIR includes a phrase address PAD and a phrase data size PDS.
The phrase address PAD is composed of address areas PAD (0) to PAD (n) for storing the head addresses of the respective phrase banks PB (0) to PB (n). On the other hand, the phrase data size PDS is formed from size areas PDS (0) to PDS (n) for storing data sizes for the respective phrase banks PB (0) to PB (n).
[0024]
(3) Operation
Next, the operation of the first embodiment having the above configuration will be described with reference to FIGS. Here, in particular, an operation for storing and saving performance information generated by a key release operation of the keyboard 1 in accordance with an ON operation of the bank switch BS will be referred to.
[0025]
(1) Overall operation (main routine)
First, when the electronic musical instrument according to the present embodiment is turned on, the CPU 4 loads the control program stored in the ROM 5 and then executes the main routine shown in FIG. Performs initialization to reset flags or set initial values. Thereafter, the CPU 4 advances the process to step SA2 to perform various switch processes according to the switch operation of the panel switch group 2. In this switch process, as will be described later, the performance information temporarily stored in the temporary buffer TB in response to the ON operation of the bank switch BS is automatically saved and saved in the phrase bank PB.
[0026]
In step SA3, performance information is generated in response to a key release operation on the keyboard 1, or a keyboard process is performed to temporarily store the performance information in the temporary buffer TB. Next, in step SA4, a sound generation process for instructing sound generation to the sound source 7 is performed in accordance with the performance information generated by the keyboard process, and in step SA5, an operation state or the like is displayed in response to the switch process. Other processing such as display processing is executed. Thereafter, the CPU 4 repeats the processes at steps SA2 to SA5.
[0027]
(2) Timer interrupt processing
The CPU 4 executes the timer interrupt process shown in FIG. 5 at regular intervals in order to measure the blank time during which the performance operation (press / release key operation) is not performed. When the interrupt timing comes, the CPU 4 advances the process to step SB1 shown in FIG. 5, and increments the counter value stored in the register BC by one. In the next step SB2, it is determined whether or not the incremented counter value has reached the maximum value MAX. Here, when the maximum value MAX has not been reached, the determination result is “NO”, and this process is temporarily terminated and the process returns to the main routine.
On the other hand, when the counter value reaches the maximum value MAX, the determination result is “YES”, the process proceeds to the next step SB3, the value is decremented by 1, and the counter value is clipped at the maximum value MAX. finish.
[0028]
(3) Keyboard processing routine operation
When the keyboard processing routine shown in FIG. 6 is executed via step SA3 described above, the CPU 4 advances the process to step SC1, and determines whether or not there is a key-on event. Here, when a key-on event occurs in response to a key pressing operation, the determination result in step SC1 is “YES”, and the process proceeds to the next step SC2. In step SC2, performance information representing the key code and velocity of the depressed key is generated, and key-on processing is performed to send this to the sound source 7.
[0029]
On the other hand, when a key-off event occurs in response to the key release operation, the process proceeds to step SC3 via step SC1, and the determination result here is “YES”, and the process proceeds to step SC4. In step SC4, a key-on process for instructing the sound source 7 to mute corresponding to the key code of the key released from the sound source 7 is performed.
If no key release operation is performed, the determination results in steps SC1 and SC2 are both “NO”, and this routine is completed without performing any processing.
[0030]
When the composer plays a fragmented phrase, after the key-on process of step SC2 is performed in response to the key pressing operation, the CPU 4 proceeds to step SC5, while corresponding to the key release operation. Then, the process proceeds to step SC8.
First, when the process proceeds to step SC5 in response to the key depression operation, the CPU 4 determines whether or not the counter value of the register BC that is advanced in the above-described timer interrupt process (see FIG. 5) is equal to or greater than a certain value BTIME. To do. Here, if the value is equal to or greater than the predetermined value BTIME, the determination result is “YES”, and the flow proceeds to the next Step SC6. In step SC6, it is determined whether or not the number of keys currently on is “0”. If there is no key being keyed on, the determination result is “YES”, the process proceeds to step SC7, and the value of the read pointer Rp is rewritten to the write pointer Wp.
[0031]
As described above, in steps SC5 to SC7, it is determined whether or not there is a blank time during which no key pressing operation is performed until the current key-on event occurs, and when there is a blank time represented by a constant value BTIME, In order to clear the temporary buffer TB, the value of the read pointer Rp is rewritten to the write pointer Wp, and the addresses indicated by both pointers Rp and Wp are made coincident.
When there is no blank time, the determination result in steps SC5 and SC6 is “NO”, and the process proceeds to step SC8. In this case, the temporary buffer TB is not cleared.
[0032]
In step SC8, the CPU 4 sequentially writes performance information in the temporary buffer TB in accordance with the write address indicated by the write pointer Wp. The performance information to be written includes a key-on / key-off event interval (event time difference), a key code, and a velocity.
When the performance information is written in the temporary buffer TB in this way, the process proceeds to step SC9 to update the write pointer Wp, and in the subsequent step SC10, the counter value of the register BC is cleared to zero and this routine is completed.
[0033]
As described above, in the keyboard processing routine, performance information (event time difference, key code, and velocity) generated in response to the key pressing operation is sequentially written in the temporary buffer TB, and the key pressing operation is not performed for a certain time or more. In this case, the read pointer Rp and the write pointer Wp are matched to clear the temporary buffer TB.
[0034]
(4) Switch processing (operation when bank switch BS is turned on)
Assume that the bank switch BS is turned on in a state where the piece of the phrase that has been played is temporarily stored in the temporary buffer TB as described above.
When the CPU 4 executes the switch processing routine shown in FIG. 6 through step SA2 and proceeds to step SD1, the CPU 4 first scans various switches forming the panel switch group 2 in step SD1 to change the setting state. To detect.
[0035]
Next, in step SD2, it is determined whether or not the bank switch BS is set to ON. In this case, since the switch BS is turned on, the determination result is “YES”, and the process proceeds to the next step SD3. When the bank switch BS is not turned on, the determination result is “NO”, and the process proceeds to step SD8 to perform other switch processing.
[0036]
In step SD3, it is determined whether or not the read pointer Rp and the write pointer Wp indicate different addresses, that is, whether or not performance information is temporarily stored in the temporary buffer TB. Here, when the read pointer Rp and the write pointer Wp specify the same address, that is, when the temporary buffer TB is empty, the determination result is “NO”, and this routine is completed.
[0037]
On the other hand, if performance information is temporarily stored in the temporary buffer TB by the keyboard processing routine described above, the determination result is “YES”, and the process proceeds to step SD4. In step SD4, the read start address indicated by the read pointer Rp is set in the address area PAD [BNUM]. BNUM is a bank number designated by the operation of the bank select switch BSEL described above. Next, at step SD5, the data size of the performance information represented by the difference between the write pointer Wp and the read pointer Rp is set in the size area PDS [BNUM].
[0038]
Then, when proceeding to the next step SD6, the CPU 4 reads the performance information for the data size set in the size area PDS [BNUM] from the temporary buffer TB based on the read start address set in the address area PAD [BNUM]. This is written and saved in the phrase bank PB [BNUM].
Next, in step SD7, the address value of the write pointer Wp is stored in the read pointer Rp, the temporary buffer TB is cleared again, and the bank number BNUM stored in the register BNUM is incremented to avoid duplication of the bank number BNUM. To complete this routine.
[0039]
As described above, according to the first embodiment, when the composer starts to play a phrase, the performance information (event time difference, key code, and velocity) generated in response to the key press / release operation is sequentially stored in the temporary buffer TB. If the bank switch BS is turned on before a certain time has elapsed since the end of playing, the performance information sequence written in the temporary buffer TB is automatically written and saved in the phrase bank PB. The entered phrase can be recorded with one touch.
On the other hand, if you don't like the phrase you played and you don't want to save it in the bank, if you leave it as it is, the temporary buffer TB is automatically cleared after a certain period of time has elapsed since you finished playing.
[0040]
B. Second embodiment
In the first embodiment described above, when the bank switch BS is turned on after the phrase has been played and until a predetermined time has elapsed, the phrase performance information string temporarily stored in the temporary buffer TB is automatically stored in the phrase bank PB. When the bank switch BS is not turned on, the performance information string of the phrase temporarily stored in the temporary buffer TB is automatically cleared.
[0041]
On the other hand, in the second embodiment, as will be described later, when a key is pressed again after a certain time has elapsed since the end of playing a phrase, the performance information sequence already stored in the temporary buffer TB is stored. Is automatically stored in the phrase bank PB, and when a cancel switch CS (described later) for instructing deletion is turned on, the temporary buffer TB is cleared to avoid automatic storage.
[0042]
Therefore, the difference in configuration between the second embodiment and the first embodiment described above is that a cancel switch CS that is operated when preventing the saving of unnecessary phrases is provided in place of the bank switch BS. Since the configuration other than the above is the same as that of the first embodiment, the description of the configuration is omitted.
In the second embodiment, only the keyboard processing routine and the switch processing routine are different from those in the first embodiment. Therefore, the operations of these routines will be described below.
[0043]
(1) Keyboard processing routine operation
As in the first embodiment described above, when the keyboard processing routine shown in FIG. 8 is executed via step SA3, the CPU 4 advances the process to step SE1 to determine whether there is a key-on event. Here, when a key-on event occurs in response to a key pressing operation, the determination result in step SE1 is “YES”, and the process proceeds to the next step SE2. In step SE2, performance information representing the key code and velocity of the depressed key is generated, and a key-on process is performed to send it to the sound source 7.
[0044]
On the other hand, when a key-off event occurs in response to the key release operation, the process proceeds to step SE3 via step SE1, and the determination result here is “YES”, and the process proceeds to step SE4. In step SE4, a key-on process is performed to instruct the sound source 7 to mute the musical sound corresponding to the key code of the key released.
If no key release operation is performed, the determination results in steps SE1 and SE2 are both “NO”, and this routine is completed without performing any processing.
[0045]
When the composer plays a fragmented phrase, after the key-on process of step SE2 is performed in response to the key pressing operation, the CPU 4 advances the process to step SE5, while corresponding to the key release operation. Then, the process proceeds to step SE11.
First, when the process proceeds to step SE5 in response to the key depression operation, the CPU 4 determines whether or not the counter value of the register BC advanced by the above-described timer interrupt process (see FIG. 5) is equal to or greater than a certain value BTIME. To do. Here, if it is greater than or equal to the constant value BTIME, the determination result is “YES”, and the flow proceeds to the next Step SE6. In step SE6, it is determined whether or not the number of keys currently on is “0”. If there is no key being turned on, the determination result is “YES”, and the process proceeds to step SE7.
[0046]
In step SE7, it is determined whether or not the read pointer Rp and the write pointer Wp indicate different addresses, that is, whether or not the performance information is temporarily stored in the temporary buffer TB. Here, when the read pointer Rp and the write pointer Wp specify the same address, that is, when the temporary buffer TB is empty, the determination result is “NO”, and the process proceeds to step SE11 described later.
[0047]
On the other hand, if the performance information has already been temporarily stored in the temporary buffer TB, the determination result here is “YES”, and the process proceeds to step SE8. In step SE8, the read start address indicated by the read pointer Rp is set in the address area PAD [BNUM], and the performance information data size represented by the difference between the write pointer Wp and the read pointer Rp is set in the size area PDS [BNUM]. ] Is set. BNUM is a bank number designated by the operation of the bank select switch BSEL described above.
[0048]
Next, when proceeding to step SE9, the CPU 4 reads the performance information sequence from the temporary buffer TB according to the read start address set in the address area PAD [BNUM] and the data size set in the size area PDS [BNUM]. To the phrase bank PB [BNUM]. Thereafter, the process proceeds to step SE10, where the address value of the write pointer Wp is stored in the read pointer Rp, and the temporary buffer TB is cleared.
[0049]
As described above, in steps SE5 to SE10, if a key is pressed by the next performance operation after a predetermined time has elapsed since the completion of the previous performance operation, the temporary buffer TB corresponding to the previous performance operation is stored. The performance information sequence temporarily stored is automatically saved in the phrase bank PB. By doing so, it is possible to automatically store and save phrases that have been input for performance, and prevent forgetting to save them.
[0050]
When there is no blank time longer than a certain time, or when the temporary buffer TB is empty, the determination results of the above steps SE5, SE6, and SE7 are all “NO”. In these cases, the process returns to step SE11. Since the process proceeds, the above-described automatic saving is not executed.
[0051]
In step SE11, the CPU 4 sequentially writes performance information in the temporary buffer TB according to the write address indicated by the write pointer Wp. The performance information to be written includes a key-on / key-off event interval (event time difference), a key code, and a velocity.
When the performance information is thus written to the temporary buffer TB, the process proceeds to step SE12, the counter value of the register BC is cleared to zero, and this routine is completed.
[0052]
As described above, in the keyboard processing routine, when a key is pressed by the next performance operation after a predetermined time has elapsed since the completion of the previous performance operation, the key is temporarily stored in the temporary buffer TB corresponding to the previous performance operation. On the other hand, when the previous performance operation is not performed, performance information (event time difference, key code and velocity) generated corresponding to the current performance operation is automatically stored in the phrase bank PB. ) Are sequentially written in the temporary buffer TB.
[0053]
(4) Switch processing (operation when cancel switch CS is turned on)
When the cancel switch CS is turned on while the phrase played in this manner is temporarily stored in the temporary buffer TB, the CPU 4 executes a switch processing routine shown in FIG. 9 and proceeds to step SF1 to scan the switch. In subsequent step SF2, based on the switch scanning result, it is determined whether or not the cancel switch CS is set to ON.
[0054]
In this case, since the switch CS is turned on, the determination result is “YES”, and the process proceeds to the next step SF3. When the cancel switch CS is not turned on, the determination result is “NO”, the process proceeds to step SF4, and other switch processing is performed.
In step SF3, the value of the read pointer Rp is reset to the write pointer Wp to clear the temporary buffer TB. This prevents the performance information string of unnecessary phrases temporarily stored in the temporary buffer TB from being automatically saved.
[0055]
As described above, according to the second embodiment, when a performance operation is performed again after a predetermined time has elapsed since the previous performance operation was performed, the performance by the previous performance operation stored in the temporary buffer TB is performed. The information string is automatically saved in the phrase bank PB, and if a cancel switch CS (described later) for instructing the deletion is turned on before that, the temporary buffer TB is cleared and automatic saving is avoided. Can be automatically stored and saved without any switch operation, and phrases that do not need to be saved can be deleted.
[0056]
In the first and second embodiments described above, performance information generated in response to the key release operation of the keyboard 1 is stored and stored, but the gist of the present invention is not limited to this. Of course, the present invention is also applicable to storing and storing performance information generated by other performance forms.
In each of the above-described embodiments, the presence / absence of a blank time during which no key pressing operation is performed is determined based on a fixed value BTIME. Also good. In other words, a desired interval time may be set so that phrase breaks can be recognized.
[0057]
Further, in each of the above-described embodiments, the phrase bank PB for storing and saving is selected by a switch operation. Instead, an empty phrase bank PB is automatically selected or all phrase banks are selected. When the PB is occupied, the latest phrase may be overwritten and saved in the bank where the oldest phrase is stored and saved. Alternatively, an overwrite prohibition flag can be provided, and a new phrase can be overwritten and stored in a bank in which the flag is not set.
[0058]
【The invention's effect】
BookAccording to the invention, when a performance operation is performed again after a predetermined time has elapsed after completion of the performance operation, performance information corresponding to the previous performance operation stored in the buffer area of the storage means is automatically stored in the bank area. Transfer to and saveOn the other hand, when transfer prevention is instructed, the performance information stored in the buffer area is discarded without being transferred to the bank area even if a performance operation is performed again after a certain period of time has elapsed.Therefore, it is possible to automatically store and save a phrase that has been input without performing any operation.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a first embodiment according to the present invention.
FIG. 2 is a memory map showing a memory configuration of a RAM 6;
FIG. 3 is a memory map showing a memory configuration of a RAM 6;
FIG. 4 is a flowchart showing an operation of a main routine in the first embodiment.
FIG. 5 is a flowchart showing the operation of a timer interrupt processing routine in the first embodiment.
FIG. 6 is a flowchart showing the operation of a keyboard processing routine in the first embodiment.
FIG. 7 is a flowchart showing an operation of a switch processing routine in the first embodiment.
FIG. 8 is a flowchart showing the operation of a keyboard processing routine in the second embodiment.
FIG. 9 is a flowchart showing an operation of a switch processing routine in the second embodiment.
[Explanation of symbols]
1 keyboard
2 Panel switch group (instruction means)
3 Display section
4 CPU (instruction means, storage control means)
5 ROM
6 RAM (storage means)
7 Sound source
8 D / A converter circuit
9 Sound system
10 Storage device

Claims (2)

A storage means comprising a bank area for storing storage buffer area and the performance information for temporarily storing performance information generated in response to a performance operation,
Continue to sequentially temporarily stores the performance information in the buffer area of the storage means, when a new performance operation after a lapse from a previous performance operation a predetermined time or more is situations, Stored the destination to the buffer area a storage control unit that Sons storage coercive transfers the performance data to the performance operation to the bank areas,
Means for instructing performance information stored in the buffer area not to be transferred to and stored in the bank area, and in the instructed state, a new performance operation is performed after a predetermined time has elapsed since the previous performance operation; A transfer preventing means for controlling the storage control means so as not to transfer and store the performance information stored in the buffer area to the bank area even if it is made. Performance information storage device. On the computer,
The performance information generated in response to the performance operation, and temporary storage procedure for storing at sequential one in the buffer area of the storage means,
When new performance operation after a lapse from a previous performance operation a predetermined time or more is situations, the performance information to the stored said previous performance operation in the buffer area is transferred to the bank area of the storage means Transfer storage procedure to store and save,
In the state in which the performance information stored in the buffer area is instructed not to be transferred and stored in the bank area, even if a new performance operation is performed after a predetermined time or more has elapsed since the previous performance operation, A transfer prevention procedure for controlling performance information stored in the buffer area so as not to be transferred and stored in the bank area;
The computer-readable recording medium which recorded the performance information storage program for performing this.

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