JP3629855B2 - Manufacturing method of semiconductor memory element - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory element, a method for manufacturing the semiconductor memory element, and a semiconductor memory device suitable for application to, for example, a nonvolatile semiconductor memory element as a redundant switching element.
[0002]
[Prior art]
Conventionally, a redundancy circuit of a nonvolatile semiconductor memory device is defective by using a so-called laser fusing fuse in which a fuse formed of polycrystalline silicon or the like is formed and a fuse corresponding to a defective bit to be redundant is blown by a laser. Switching between bits and spare bits has been performed.
[0003]
In this case, the sequence for switching to the redundant circuit is as follows.
(1) UV erasure at wafer level (2) Chip operation confirmation at wafer level (function test)
(3) Determining whether redundancy is possible and checking redundant chips (4) Fusing a fuse as a redundant selection switch by laser (5) UV erasure at wafer level (6) Chip assembly (7) Chip operation check (function test)
[0004]
In such a sequence, the steps (2), (3), and (4) must be performed by different devices, for example, a tester and a laser cutter. It had become a strange thing.
[0005]
As a method for avoiding such complications, there is a method of using a nonvolatile semiconductor memory element as a redundant switching element instead of the above-described laser blown fuse.
In this case, when checking the operation of the chip, first, electrons are sufficiently extracted from the non-volatile semiconductor memory element to be depleted so that the element becomes conductive, and when redundancy is possible, electrons are injected. What is necessary is just to interrupt conduction.
[0006]
As described above, when the nonvolatile semiconductor memory element is used as a redundant switching element, the information of the nonvolatile semiconductor memory element is changed on the spot at the time of chip operation confirmation at the wafer level using the tester (2). By doing so, redundancy can be performed, so that the steps (3) and (4) described above can be eliminated.
Furthermore, since redundancy can be electrically switched even for a chip that has become defective after chip assembly and can be repaired by a redundant circuit, the repair efficiency by the redundant circuit can be increased.
[0007]
[Problems to be solved by the invention]
However, if the nonvolatile semiconductor memory element is simply used as the redundancy switching element and the information of the nonvolatile semiconductor memory element is changed on the spot at the time of the chip operation confirmation at the wafer level (2) using the tester, In the ultraviolet erasing step (5) before assembly, information on the nonvolatile semiconductor memory element used as the redundant switching element is also changed at the same time, so that it cannot be put into practical use as a redundant switching element.
[0008]
In order to avoid this problem, as shown in FIG. 5, a nonvolatile semiconductor memory element for redundant switching is covered with a film that does not transmit ultraviolet light such as aluminum wiring, in this example, a wiring layer 59, so that the memory element by ultraviolet irradiation is used. A technology for preventing fluctuations in information has been proposed.
[0009]
In the semiconductor memory element 50 of FIG. 5, a floating gate 53 is formed on the surface of a semiconductor substrate 51 via a tunnel gate insulating film 52, and a control gate 55 is formed on the floating gate 53 via an intergate insulating layer 54. Stack gate structure.
A thick interlayer insulating layer 58 is formed so as to cover the floating gate 53 and the control gate 55 having a stack structure, and a wiring layer 59 serving as a light shielding film is formed so as to cover the surface.
On the surface of the semiconductor substrate 51, an impurity diffusion layer 56 serving as a source part and a drain part is formed.
[0010]
However, according to this technique, as shown in FIG. 5, ultraviolet rays UV enter from the gap a of the interlayer insulating layer 58 between the wiring layer 59 and the substrate 51. There is a demerit that it is necessary to cover the wiring layer 59 to be sufficiently wide, resulting in an increase in the element area.
[0011]
In order to solve the above-described problem, in the present invention, a semiconductor memory element is used as a redundant switching element so that ultraviolet rays are not incident on the floating gate, thereby simplifying complicated redundant switching work and ultraviolet erasing. The present invention provides a non-volatile semiconductor memory element that can prevent the redundant information from fluctuating and can be downsized, a method for manufacturing the same, and a semiconductor memory device using the semiconductor memory element.
[0012]
[Means for Solving the Problems]
[0014]
According to the method of manufacturing a semiconductor memory element of the present invention, a first electrode layer is formed on a semiconductor substrate via a gate insulating film, the first electrode layer is patterned to form a floating gate, and then the floating gate is formed. A second electrode layer made of a material that does not transmit ultraviolet rays is formed so as to cover the insulating layer between the gates, and a control gate that covers the floating gate is formed by patterning the second electrode layer. Further, when patterning the second electrode layer, the semiconductor substrate is dug to form a recess, and a source region and a drain region are formed in the recess.
[0015]
According to the method of manufacturing a semiconductor memory element of the present invention described above, the control gate made of a material that does not transmit ultraviolet rays is formed by covering the floating gate with the inter-gate insulating layer interposed therebetween, thereby shielding the ultraviolet rays. A semiconductor memory element that can be manufactured can be manufactured. In addition, since the control gate is formed to form the light shielding film, the semiconductor memory element can be manufactured by a normal manufacturing process of the semiconductor memory element, and the ultraviolet light can be blocked without increasing the manufacturing process.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
The present invention includes a step of forming a first electrode layer on a semiconductor substrate through a gate insulating film, patterning the first electrode layer to form a floating gate, and an intergate insulating layer so as to cover the floating gate. Forming a second electrode layer made of a material that does not transmit ultraviolet light, and patterning the second electrode layer to form a control gate covering the floating gate, and patterning the second electrode layer In addition, a semiconductor memory device manufacturing method includes forming a recess by digging a semiconductor substrate and forming a source region and a drain region in the recess.
[0021]
Hereinafter, embodiments of a semiconductor memory element, a method for manufacturing the same, and a semiconductor memory device according to the present invention will be described with reference to the drawings.
1 and 2 are schematic configuration diagrams of a region corresponding to one memory cell of a semiconductor memory element, in this example, a nonvolatile semiconductor memory element. 1 is a plan view, FIG. 2A is a cross-sectional view taken along the line AA ′ of FIG. 1, and FIG. 2B is a cross-sectional view taken along the line BB ′ of FIG.
[0022]
In this semiconductor memory element, a floating gate 3 made of, for example, a polycrystalline silicon layer doped with phosphorus as an impurity is formed on a semiconductor substrate 1 made of, for example, silicon via a tunnel gate insulating film 2. An intergate insulating layer 4 made of, for example, a laminated film of SiO ₂ / SiN / SiO ₂ is formed, and a control gate 5 made of, for example, a laminated film of silicide WSi and polycrystalline silicon is formed thereon, A memory cell 10 is configured.
[0023]
As shown in FIG. 2A, a source region 6S and a drain region 6D are formed of diffusion layers at positions on both sides of the control gate 5 in the semiconductor substrate 1.
On the other hand, as shown in FIG. 2B, the floating gate 3 is formed over the tunnel gate insulating film 2 and a part of the element isolation layer 7 that performs element isolation around the tunnel gate insulating film 2.
The element isolation layer 7 isolates the active region 8 of the memory cell 10 shown in FIG. 1 from surrounding memory cells. In the active region 8, the aforementioned thin tunnel gate insulating film 2 is formed on the semiconductor substrate 1. Reference numeral 9 denotes a contact portion between the source region 6S and the drain region 6D and the upper layer wiring.
[0024]
In this example, the control gate 5 is formed of a material that does not transmit ultraviolet light, for example, a so-called metal polycide in which a WSi layer is formed on a polysilicon layer.
The control gate 5 made of a material that does not transmit ultraviolet rays covers the upper surface and side surfaces of the floating gate 3 as shown in FIGS. 2A and 2B, so that the ultraviolet rays can be efficiently blocked.
Further, since the control gate 5 also covers the side surface of the floating gate 3, it is possible to prevent the incidence of ultraviolet rays from the side, which is a problem in the example of FIG.
[0025]
According to the semiconductor memory element of the above-described example , since the floating gate 3 is covered with the control gate 5 made of a material that does not transmit ultraviolet rays, it is possible to prevent ultraviolet rays from entering from above and from the side of the floating gate 3. In addition, it is possible to prevent changes in the memory content of the semiconductor memory element due to the incidence of ultraviolet rays.
[0026]
In addition, a separate light shielding film is not provided on the memory element, and the light can be shielded by the control gate 5 covering the floating gate 3, so that it is not necessary to form a wide light shielding film. Restrictions are reduced. Therefore, it is possible to reduce the size of the semiconductor memory element and to shield light.
[0027]
For example, the operation method of the nonvolatile semiconductor memory element is as follows.
By applying a negative voltage to the control gate 5 and a positive voltage to the source region 6S and a well region (not shown) formed in the semiconductor substrate 1, electrons are extracted from the floating gate 3 to make the memory element conductive. Can do.
On the other hand, by applying a positive voltage to the control gate 5 and a negative voltage to the source region 6S and the well region, electrons can be injected into the floating gate 3 and the storage element can be made non-conductive.
[0028]
Further, when the semiconductor memory device is configured by using the above-described semiconductor memory element as a redundant selection switch, the semiconductor memory element of the redundant selection switch can be used even if ultraviolet rays for erasing information of the main body semiconductor memory element are incident. Since the floating gate is covered with the control gate made of a material that does not transmit ultraviolet rays, the redundant information is retained without being rewritten, so that an efficient redundancy system can be realized.
In addition, since the semiconductor memory element is used as a redundant selection switch, it can be programmed to provide switching information, so that a complicated process as in the case of using a conventional laser fusing fuse as a redundant selection switch is not required. Redundant switching can be performed with.
[0029]
Next, a method for manufacturing the nonvolatile semiconductor memory element will be described with reference to the drawings.
First, as shown in FIG. 3A, a tunnel gate insulating film 2 is formed on a semiconductor substrate 1 made of, for example, silicon. Further, a first electrode layer 11 made of polycrystalline silicon doped with phosphorus as an impurity, which will later become the floating gate 3, is deposited.
Next, as shown in FIG. 3B, the first electrode layer 11 is patterned to form the floating gate 3.
[0030]
Subsequently, as shown in FIG. 3C, an intergate insulating layer 4 made of, for example, a laminated film of SiO ₂ / SiN / SiO ₂ is formed on the entire surface covering the floating gate 3.
Further, a second electrode layer 12 made of a laminated film of silicide WSi and polycrystalline silicon is formed on the intergate insulating layer 4 as a material that does not transmit ultraviolet light, for example.
[0031]
Next, as shown in FIG. 3D, the control gate 5 is formed by patterning the second electrode layer 12 in the gate portion simultaneously with the processing of the gate portion of the peripheral transistor. Further, the source region 6S and the drain region 6D are formed in the semiconductor substrate 1.
In this way, a semiconductor memory element including the memory cell 10 having the structure shown in FIG. 1 is obtained.
[0032]
According to the method of manufacturing the nonvolatile semiconductor memory element of the above-described example, the control gate 5 made of a material that does not transmit ultraviolet rays is formed by covering the floating gate 3 with the inter-gate insulating layer 4 interposed therebetween. A semiconductor memory element that can be shielded from light can be manufactured.
Further, since the control gate 5 is formed to form a light shielding film, it can be manufactured by a normal semiconductor memory element manufacturing process, and a semiconductor memory element capable of shielding ultraviolet rays can be manufactured without increasing the manufacturing process. .
[0033]
By the way, as the structure of the current memory, similarly to the example shown in FIG. 5, a so-called stack gate in which two layers of control gates and floating gates are stacked in the same pattern via an inter-gate insulating layer. What has a structure is used.
In the case of this structure, it is common to process the gate portions of peripheral transistors and the like and the processing of the stack gate of each memory cell of the memory array separately.
[0034]
On the other hand, in the method for manufacturing the semiconductor memory element of the above-described example , the gate portion of the nonvolatile semiconductor memory element that is shielded from ultraviolet rays is processed simultaneously with the processing of the gate portion of the peripheral transistor.
[0035]
On the other hand, as an embodiment of the method for manufacturing a semiconductor memory element of the present invention, simultaneously with processing of the memory cell, that is, the processing of the stack gate of each memory cell of the main body semiconductor memory element other than the redundant selection switch, which is not shielded from ultraviolet rays, The gate portion of the nonvolatile semiconductor memory element that is shielded from ultraviolet rays may be processed.
In this case, as shown in a process diagram of the manufacturing process in FIG. 4, after processing the stack gate of each memory cell of the memory array, the semiconductor substrate 1 is dug to form a recess 1a. Even if the 6S and the drain region 6D are formed, there is no significant problem in the characteristics of the semiconductor memory element.
[0036]
The present invention is not limited to the above-described examples, and various other configurations can be taken without departing from the gist of the present invention.
[0037]
【The invention's effect】
[0038]
According to the method for manufacturing a semiconductor memory element of the present invention, a control gate made of a material that does not transmit ultraviolet rays is formed by covering a floating gate with an inter-gate insulating layer therebetween, so that the semiconductor can block ultraviolet rays. A memory element can be manufactured. In addition, since the control gate is formed to form the light shielding film, the semiconductor memory element can be manufactured by a normal manufacturing process of the semiconductor memory element, and the ultraviolet light can be blocked without increasing the manufacturing process.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram (plan view) of a memory cell as an example of a semiconductor memory element .
FIG. 2A is a cross-sectional view taken along the line AA ′ of the memory cell of FIG.
B is a cross-sectional view taken along the line BB 'of the memory cell of FIG.
FIG. 3 is a manufacturing process diagram illustrating an example of a manufacturing method of an AD semiconductor memory element ;
FIG. 4 is a manufacturing process diagram of an embodiment of the method for manufacturing a semiconductor memory element of the present invention.
FIG. 5 is a schematic configuration diagram of an example of a semiconductor memory element that blocks ultraviolet rays.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 1a Concave part, 2 Tunnel gate insulating film, 3 Floating gate, 4 Gate insulating layer, 5 Control gate, 6S source region, 6D Drain region, 7 Element isolation layer, 8 Active region, 9 Contact part, 10 Memory Cell, 11 first electrode layer, 12 second electrode layer, 50 semiconductor memory element, 51 semiconductor substrate, 52 tunnel gate insulating film, 53 floating gate, 54 inter-gate insulating layer, 55 control gate, 56 diffusion layer, 58
Inter-gate insulating layer, 59 wiring layer, UV UV

Claims (1)

Forming a first electrode layer on a semiconductor substrate via a gate insulating film, patterning the first electrode layer to form a floating gate;
Forming a second electrode layer made of a material that does not transmit ultraviolet light through an inter-gate insulating layer so as to cover the floating gate, and patterning the second electrode layer to form a control gate covering the floating gate And
When patterning the second electrode layer, the semiconductor substrate is dug to form a recess,
A method of manufacturing a semiconductor memory element, wherein a source region and a drain region are formed in the recess.

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