JP3621303B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a memory cell and its peripheral circuit (core) are provided on the same substrate, and a method for manufacturing the same, and more particularly to a semiconductor device that reduces the occupied area of the core and speeds up the operation thereof. It relates to a manufacturing method.
[0002]
[Prior art]
Recently, high integration of semiconductor devices has been promoted. In a system-on-chip (SOC), a peripheral circuit (core) such as a central processing unit (CPU) for controlling a memory cell and its operation on the same substrate. And are formed. In such an SOC, the memory cell is required to stabilize data even when alpha rays are incident, that is, soft error resistance is required, and the core operates the logic circuit constituting it faster. It is required to do. Therefore, when the memory cell is an SRAM, in the SRAM portion, the source / drain junction capacitance of the CMOS transistor constituting it is increased, and in the core portion, the source / drain junction capacitance of the CMOS transistor constituting it is lowered. There is a need.
[0003]
However, if the impurity concentration of the wells incorporated in the circuit constituting the core part is lowered in order to reduce the junction capacitance of the core part, the following problems occur. FIGS. 50A and 50B are cross-sectional views showing punch-through under the element isolation region in a conventional CMOS transistor. As shown in FIGS. 50A and 50B, in the CMOS transistor, a p-well 83 and an n-well 84 separated by an element isolation film 82 are formed on the surface of a semiconductor substrate 81. Then, n formed on the surface of the p-well 83 ⁺ Source diffusion layers 85a and n ⁺ N channel MOS transistor 87 having drain diffusion layer 85b and p formed on the surface of n well 84. ⁺ Source diffusion layers 86a and p ⁺ A p-channel MOS transistor 88 having a drain diffusion layer 86b is provided.
[0004]
Furthermore, the p-well 83 is n ⁺ P insulated from source diffusion layer 85a ⁺ A well contact layer 91 is formed, and the n well 84 is formed of p by an insulating film 90. ⁺ N insulated from the source diffusion layer 86a ⁺ A well contact layer 92 is formed.
[0005]
In the thus configured CMOS transistor, as shown in FIG. 50A, the gate electrodes 93 and 94 have 0 (V), n ⁺ Drain diffusion layers 85b and p ⁺ The drain diffusion layer 86b has 1.8 (V), n ⁺ Source diffusion layers 85a and p ⁺ The well contact layer 91 has 0 (V), p ⁺ Source diffusion layers 86a and n ⁺ When 1.8 (V) is applied to the well contact layer 92, p passing through the n-well 84 and the p-well 83 under the element isolation film 82 and the insulating film 89. ⁺ Drain diffusion layer 86b and p ⁺ Punch-through between the well contact layer 91 is likely to occur.
[0006]
Further, as shown in FIG. 50B, the gate electrodes 93 and 94 have 1.8 (V), n ⁺ Drain diffusion layers 85b and p ⁺ 0 (V), n is applied to the drain diffusion layer 86b. ⁺ Source diffusion layers 85a and p ⁺ The well contact layer 91 has 0 (V), p ⁺ Source diffusion layers 86a and n ⁺ When 1.8 (V) is applied to the well contact layer 92, n passes through the n well 84 and the p well 83 under the element isolation film 82 and the insulating film 90. ⁺ Well contact layer 92 and n ⁺ Punch-through between the drain diffusion layer 85b is likely to occur. Hereinafter, such punch-through is referred to as inter-well punch-through.
[0007]
On the other hand, when the impurity concentration around the source / drain diffusion layer of the CMOS transistor such as a well is low in order to reduce the junction capacitance, punch-through under the element isolation region is likely to occur.
[0008]
Therefore, conventionally, in the core portion, the above-described requirements are met by reducing the impurity concentration in the well and increasing the width of the element isolation film between the pMOS and nMOS constituting the CMOS. FIGS. 39A and 39B to FIGS. 49A and 49B are cross-sectional views showing a conventional method of manufacturing a semiconductor device in the order of steps. In these drawings, (a) shows a region corresponding to the core portion of the semiconductor device, and (b) shows a region corresponding to the SRAM portion of the semiconductor device.
[0009]
First, as shown in FIGS. 39A and 39B, p is formed on the p-type silicon substrate 51 in both the core portion and the SRAM portion. ⁻ An epitaxial layer 52 is formed. Next, p at the core ⁻ An element isolation film 53a is formed in a predetermined region on the surface of the epitaxial layer 52, and p in the SRAM portion. ⁻ An element isolation film 53 b is formed in a predetermined region on the surface of the epitaxial layer 52. As a result, the nMOS region 111, which is the region where the n-channel MOS transistor is formed, and the pMOS region 112, where the p-channel MOS transistor is formed, are partitioned in the core portion. An nMOS region 113 which is a region to be formed and a pMOS region 114 which is a region where a p-channel MOS transistor is formed are partitioned. The width of the element isolation film 53a is, for example, 1.2 μm, and the width of the element isolation film 53b is, for example, 0.4 μm. Thereafter, a sacrificial oxide film (not shown) is formed on the entire surface.
[0010]
Next, FIG. And (b) As shown, a resist 54 having an opening 54a on the nMOS region 111 side of the nMOS region 111 and the element isolation film 53a and completely covering the SRAM portion is formed. On element isolation film 53a The size of the opening 54a is about half that of the element isolation film 53a. Next, using the resist 54 as a mask, for example, an acceleration voltage of 300 keV, 1.5 × 10 ¹³ The dose amount of B ⁺ In the core portion, p ⁻ A p-type well 55 deeper than the element isolation film 53 a is formed in the epitaxial layer 52.
[0011]
After the resist 54 is removed, as shown in FIGS. 41A and 41B, a resist 56 having an opening 56a at the center of the nMOS region 111 and completely covering the SRAM portion is newly formed. Next, using the resist 56 as a mask, for example, an acceleration voltage of 30 keV, 8 × 10 ¹² The dose amount of B ⁺ By ion implantation of p ⁻ A p-type channel 57 is formed at an intermediate depth of the epitaxial layer 52.
[0012]
After the resist 56 is removed, as shown in FIGS. 42A and 42B, the resist 58 has an opening 58a on the nMOS region 113 side of the nMOS region 113 and the element isolation film 53b and completely covers the core portion. Form. Next, using the resist 58 as a mask, for example, an acceleration voltage of 150 keV, 2 × 10 ¹³ The dose amount of B ⁺ Is implanted in the SRAM portion by p. ⁻ A p-type well 59 is formed in the epitaxial layer 52. Further, using the resist 58 as a mask, for example, an acceleration voltage of 30 keV, 1.5 × 10 5 ¹³ The dose amount of B ⁺ As a result, a p-type channel 60 is formed in the p-type well 59.
[0013]
After the resist 58 is removed, as shown in FIGS. 43A and 43B, the resist 61 which has an opening 61a on the pMOS region 112 side of the pMOS region 112 and the element isolation film 53a and completely covers the SRAM portion. Form. Next, using the resist 61 as a mask, for example, an acceleration voltage of 600 keV, 1.5 × 10 5 ¹³ P at the dose amount ⁺ In the core portion, p ⁻ An n-type well 62 is formed in the epitaxial layer 52.
[0014]
After the resist 61 is removed, as shown in FIGS. 44A and 44B, a resist 63 having an opening 63a at the center of the pMOS region 112 and completely covering the SRAM portion is newly formed. Next, using the resist 63 as a mask, for example, an acceleration voltage of 100 keV, 3 × 10 ¹² As of dose amount ⁺ Are ion-implanted to form an n-type channel 64 at an intermediate depth of the n-type well 62 in the core.
[0015]
After the resist 63 is removed, as shown in FIGS. 45A and 45B, the resist 65 has an opening 65a on the pMOS region 114 side of the pMOS region 114 and the element isolation film 53b and completely covers the core portion. Form. Next, using the resist 65 as a mask, for example, an acceleration voltage of 350 keV, 2 × 10 ¹³ P at the dose amount ⁺ Is implanted in the SRAM portion by p. ⁻ An n-type well 66 is formed in the epitaxial layer 52. Further, for example, an acceleration voltage of 100 keV, 1.4 × 10 ¹³ As of dose amount ⁺ Are ion-implanted to form an n-type channel 67 at an intermediate depth of the n-type well 66.
[0016]
After the resist 65 is removed, a gate oxide film 68 and a gate electrode 69 are formed in the nMOS region 111, the pMOS region 112, the nMOS region 113, and the pMOS region 114, as shown in FIGS. 46 (a) and 46 (b).
[0017]
Next, as shown in FIGS. 47A and 47B, sidewalls 70 are formed on the sides of the gate oxide film 68 and the gate electrode 69.
[0018]
Next, as shown in FIGS. 48A and 48B, a resist 71 having openings 71a and 71b is formed in the nMOS region 111 and the nMOS region 113, respectively. Next, using the resist 71 as a mask, for example, an acceleration voltage of 20 keV, 5 × 10 ¹⁵ As of dose amount ⁺ Are implanted into the nMOS region 111 and the nMOS region 113 by ion implantation. ⁺ A source / drain diffusion layer 72 is formed.
[0019]
After the resist 71 is removed, as shown in FIGS. 49A and 49B, a resist 73 having openings 73a and 73b is formed in the pMOS region 112 and the pMOS region 114, respectively. Next, using the resist 73 as a mask, for example, an acceleration voltage of 4 keV, 5 × 10 ¹⁵ The dose amount of B ⁺ Is implanted into the pMOS region 112 and the pMOS region 114 by ion implantation. ⁺ A source / drain diffusion layer 74 is formed.
[0020]
Thereafter, the ions implanted by annealing are activated, and then a wiring or the like is formed to complete the semiconductor device.
[0021]
Also, a semiconductor device has been proposed in which a region having a high impurity concentration is formed below the element isolation film in order to prevent punch-through under the element isolation region (Japanese Patent Laid-Open No. 8-97378). In the semiconductor device described in this proposal, a high-concentration impurity concentration region is provided in a well in which a MOS transistor is formed, extending to a lower portion of an element isolation film formed around the transistor.
[0022]
[Problems to be solved by the invention]
However, in the SOC, when the occupied area of the memory cell part (SRAM part) and the occupied area of the core part are compared, that of the core part is significantly larger. In the semiconductor device manufactured by the conventional method shown in the figure, Since the width of the element isolation film 53a is widened at the portion, there is a problem in that the area of the entire chip becomes large.
[0023]
Further, in the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 8-97378, since the high concentration impurity concentration region exists below the MOS transistor, the influence on the threshold voltage of the MOS transistor can be considered. This effect becomes significant when the integration is higher. Furthermore, application to SOC is not considered, and when applied to SOC, the number of processes may increase. Furthermore, when applied to the core portion of the SOC, the junction capacitance increases due to the high-concentration impurity region, and the operation may be delayed.
[0024]
These problems are conspicuous in the SOC, but similar problems exist in the memory chip itself if the core portion is a peripheral region such as a decoder.
[0025]
The present invention has been made in view of such a problem, and can occupy a high-speed operation of a core portion on which a logic circuit is formed, and can reduce the occupied area of the core portion. An object of the present invention is to provide a semiconductor device capable of preventing punch-through under the separation region and a manufacturing method thereof.
[0026]
[Means for Solving the Problems]
A semiconductor device according to the present invention includes: A semiconductor layer of a first conductivity type formed by epitaxial growth on the surface and having an impurity concentration lower than that of the base portion is provided. A semiconductor device having a semiconductor substrate of a first conductivity type and a complementary transistor for a core portion and a complementary transistor for a memory cell portion formed on the semiconductor substrate, wherein the complementary transistor for a core portion is the first transistor A first second conductivity type well formed on a conductive type semiconductor substrate, and a first core portion formed in the first second conductivity type well and having a source / drain conductivity type of the first conductivity type MOS transistor and semiconductor substrate of the first conductivity type First conductivity type semiconductor layer A second core-portion MOS transistor having a source / drain conductivity type of the second-conductivity type, an element isolation film for isolating the first and second core-portion MOS transistors from each other, and And a first conductivity type well formed at the second core portion MOS transistor side under the element isolation film and having a higher impurity concentration than the first conductivity type semiconductor substrate.
[0027]
In the present invention, since the first conductivity type well having an impurity concentration higher than that of the semiconductor substrate is formed on the second core portion MOS transistor side under the element isolation film in the core portion, punch-through under the element isolation region is formed. Resistance is improved. For this reason, the width of the element isolation film in the core portion can be reduced, and the area occupied by the core portion can be reduced. Further, since the second core portion MOS transistor is formed on the semiconductor substrate, the junction capacitance is reduced as compared with the conventional one formed in the well. As a result, high speed operation is possible.
[0028]
In the present invention, the complementary transistor for the memory cell portion includes a second first conductivity type well and a second second conductivity type well formed on the first conductivity type semiconductor substrate, and the second conductivity type well. A first MOS transistor for the memory cell portion formed in the second conductivity type well and having a source / drain conductivity type of the first conductivity type; and a source / drain conductivity type formed in the second first conductivity type well. And the second conductivity type well, and the impurity concentration of the first and second conductivity type wells may be equal to each other.
[0029]
In addition, it is preferable that the semiconductor device has a third second conductivity type well that is formed on the first core portion MOS transistor side under the element isolation film and has an impurity concentration higher than that of the first second conductivity type well. In this case, the impurity concentrations of the second and third second conductivity type wells may be equal to each other. By providing the third second conductivity type well, the punch-through resistance under the element isolation region is further improved, so that the occupation area can be further reduced.
[0031]
A method for manufacturing a semiconductor device according to the present invention includes: A semiconductor layer of a first conductivity type formed by epitaxial growth on the surface and having an impurity concentration lower than that of the base portion is provided. In the method of manufacturing a semiconductor device, comprising: forming a complementary transistor for a core portion and a complementary transistor for a memory cell portion on a first conductivity type semiconductor substrate, the complementary transistor for the core portion and the complementary type for the memory cell portion The step of forming a transistor comprises: a first core portion MOS transistor that constitutes the core portion complementary transistor, the source / drain conductivity type being the first conductivity type; Formed in the first conductivity type semiconductor layer of the first conductivity type semiconductor substrate; A first element isolation film for element isolation from a second core part MOS transistor having a source / drain conductivity type of the second conductivity type and a complementary transistor for the memory cell part are formed. A second memory cell portion MOS transistor having a first conductivity type and a second memory cell portion MOS transistor having a source / drain conductivity type of a second conductivity type is isolated from each other. Forming an element isolation film on the first conductivity type semiconductor substrate, and forming an impurity from the first conductivity type semiconductor substrate below the first element isolation film on the second core portion MOS transistor side. A first conductivity type well having a high concentration is formed, and the first conductivity type is formed on the first conductivity type semiconductor substrate in a region where the second memory cell MOS transistor is to be formed. A step of impurity concentration than the semiconductor substrate to form a high second first-conductivity-type well, and having a.
[0032]
In the present invention, since the first first conductivity type well is formed at the same time as the second first conductivity type well, it is possible to improve the punch-through resistance under the element isolation region without increasing the number of steps. is there.
[0033]
In the present invention, the step of forming the complementary transistor for the core portion and the complementary transistor for the memory cell portion includes the step of forming the first conductivity type in the region where the first memory cell portion MOS transistor is to be formed. Forming a second second conductivity type well on the semiconductor substrate and forming a third second conductivity type well on the first core portion MOS transistor side under the first element isolation film; It is desirable to have.
[0034]
The step of forming the complementary transistor for the core portion and the complementary transistor for the memory cell portion includes the step of forming the first memory cell portion after the step of forming the first and second first conductivity type wells. Forming a first second conductivity type well and a second conductivity type channel sequentially on the first conductivity type semiconductor substrate in the region where the MOS transistor is to be formed using the same mask. The step of implanting second conductivity type ions into the first conductivity type semiconductor substrate in the region where the first memory cell portion MOS transistor is to be formed, and the first memory cell portion MOS And implanting the first conductivity type ions into the first conductivity type semiconductor substrate in a region where a transistor is to be formed at a lower dose than the second conductivity type ions.
[0035]
By implanting the first conductivity type ions at a low dose after implanting the second conductivity type ions, the impurity concentration of the well in the first core portion MOS transistor is substantially decreased, so that the junction capacitance is decreased. . As a result, high speed operation is possible.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. In the following description, the well contact layer provided in the CMOS transistor is the same as the conventional one, and its illustration and description are omitted for the sake of simplicity. In the first embodiment, a complementary transistor (CMOS) constituting an SRAM and a CMOS constituting a peripheral circuit (core) such as a CPU are formed on the same substrate. That is, a system on chip (SOC) is manufactured. FIGS. 1A and 1B to FIGS. 10A and 10B are cross-sectional views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps. In these drawings, (a) shows a region corresponding to the core portion of the semiconductor device, and (b) shows a region corresponding to the SRAM portion of the semiconductor device.
[0038]
First, as shown in FIGS. 1A and 1B, in both regions of the core portion and the SRAM portion, p is formed on the p-type silicon substrate 1. ⁻ Epitaxial layer 2 is formed. Next, p at the core ⁻ The first element isolation film 3a is formed in a predetermined region on the surface of the epitaxial layer 2, and p-type in the SRAM portion. ⁻ A second element isolation film 3 b is formed in a predetermined region on the surface of the epitaxial layer 2. As a result, the nMOS region 101 and the p-channel MOS transistor (first core portion MOS transistor), which are regions where the n-channel MOS transistor (second core portion MOS transistor) is formed, are formed in the core portion. The pMOS region 102 which is a region is partitioned, and in the SRAM portion, an nMOS region 103 which is a region where an n-channel MOS transistor (second memory cell portion MOS transistor) is formed and a p-channel MOS transistor (first memory) A pMOS region 104, which is a region where a cell portion MOS transistor) is formed, is partitioned. The width of the element isolation film 3a is, for example, 0.9 μm, and the width of the element isolation film 3b is, for example, 0.4 μm. The element isolation films 3a and 3b may be formed by LOCOS oxidation or by adopting a trench structure. Thereafter, a sacrificial oxide film (not shown) is formed on the entire surface.
[0039]
Next, as shown in FIG. 2A, a resist 4 having an opening 4a is formed on the nMOS region 101 side of the element isolation film 3a. The size of the opening 4a is smaller than half that of the element isolation film 3a. In other words, the region that matches the opening 4 a of the element isolation film 3 a is narrower than the region under the resist 4. Further, as shown in FIG. 2B, an opening 4b is formed in the resist 4 on the nMOS region 103 side of the nMOS region 103 and the element isolation film 3b. The size of the opening 4b on the element isolation film 3b is about half that of the element isolation film 3b. Next, using the resist 4 as a mask, for example, an acceleration voltage of 150 keV, 2 × 10 ¹³ The dose amount of B ⁺ In the core portion, a p-type well (first first conductivity type well) 5a is formed below the region matching the opening 4a of the element isolation film 3a. In the SRAM portion, p-type well is formed. ⁻ A p-type well (second first conductivity type well) 5 b deeper than the element isolation film 3 b is formed in the epitaxial layer 2. Further, using the resist 4 as a mask, for example, an acceleration voltage of 30 keV, 1.5 × 10 5 ¹³ The dose amount of B ⁺ To form a p-type channel 6 at an intermediate depth of the p-type well 5b.
[0040]
After the resist 4 is removed, as shown in FIGS. 3A and 3B, a resist 7 having an opening 7a at the center of the nMOS region 101 and completely covering the SRAM portion is newly formed. Next, using the resist 7 as a mask, for example, an acceleration voltage of 30 keV, 8 × 10 ¹² The dose amount of B ⁺ By ion implantation of p ⁻ A p-type channel 8 is formed at an intermediate depth of the epitaxial layer 2.
[0041]
After the resist 7 is removed, as shown in FIGS. 4A and 4B, the resist 9 has an opening 9a on the pMOS region 102 side of the pMOS region 102 and the element isolation film 3a and completely covers the SRAM portion. Form. The region covered with the resist 9 of the element isolation film 3a is substantially the same as the region aligned with the opening 4a. Next, using the resist 9 as a mask, for example, an acceleration voltage of 600 keV, 1.5 × 10 ¹³ P at the dose amount ⁺ By ion implantation of p ⁻ An n-type well (first second conductivity type well) 10 is formed in the epitaxial layer 2.
[0042]
After removing the resist 9, as shown in FIGS. 5A and 5B, a resist 11 having an opening 11a in the center of the pMOS region 102 and completely covering the SRAM portion is newly formed. Next, using the resist 11 as a mask, for example, an acceleration voltage of 100 keV, 3 × 10 ¹² As of dose amount ⁺ To form an n-type channel 12 at an intermediate depth of the n-type well 10.
[0043]
After the resist 11 is removed, as shown in FIGS. 6A and 6B, the resist 13 has an opening 13a on the pMOS region 104 side of the pMOS region 104 and the element isolation film 3b and completely covers the core portion. Form. Next, using the resist 13 as a mask, for example, an acceleration voltage of 350 keV, 2 × 10 ¹³ P at the dose amount ⁺ Is implanted in the SRAM portion by p. ⁻ An n-type well (second second conductivity type well) 14 deeper than the element isolation film 3 b is formed in the epitaxial layer 2. Further, using the resist 13 as a mask, for example, an acceleration voltage of 100 keV, 1.4 × 10 ¹³ As of dose amount ⁺ Are ion-implanted to form an n-type channel 15 at an intermediate depth of the n-type well 14.
[0044]
After the resist 13 is peeled off, a gate oxide film 16 and a gate electrode 17 are formed in the nMOS region 101, the pMOS region 102, the nMOS region 103, and the pMOS region 104, as shown in FIGS. The thickness of the gate oxide film 16 is, for example, 2.5 nm, and the thickness of the gate electrode 17 is, for example, 150 nm.
[0045]
Next, as shown in FIGS. 8A and 8B, sidewalls 18 are formed on the sides of the gate oxide film 16 and the gate electrode 17. The sidewall 18 is made of, for example, a silicon oxide film and / or a silicon nitride film, and the width thereof is, for example, 70 nm.
[0046]
Next, as shown in FIGS. 9A and 9B, a resist 19 having openings 19a and 19b in the nMOS region 101 and the nMOS region 103 is formed. Next, using the resist 19 as a mask, for example, an acceleration voltage of 20 keV, 5 × 10 ¹⁵ As of dose amount ⁺ Is implanted into the nMOS region 101 and the nMOS region 103 by ion implantation. ⁺ A source / drain diffusion layer 20 is formed.
[0047]
After the resist 19 is removed, as shown in FIGS. 10A and 10B, a resist 21 having openings 21a and 21b is formed in the pMOS region 102 and the pMOS region 104, respectively. Next, using the resist 21 as a mask, for example, an acceleration voltage of 4 keV, 5 × 10 ¹⁵ The dose amount of B ⁺ Is implanted into the pMOS region 102 and the pMOS region 104 by ion implantation. ⁺ A source / drain diffusion layer 22 is formed.
[0048]
Thereafter, the ions implanted into each well and the source / drain diffusion layer are activated by annealing at, for example, 1000 ° C. for 10 seconds, and then a wiring or the like is formed by a normal method to complete the semiconductor device.
[0049]
Thus, in the semiconductor device manufactured according to the first embodiment, as shown in FIGS. 10A and 10B, the impurity concentration is p on the nMOS region 101 side under the element isolation film 3a. ⁻ Since the p-type well 5a higher than that of the epitaxial layer 2 is formed, punch-through between the n-type source / drain diffusion layer 20 and the n-type well 10 is sufficiently suppressed. For this reason, since the width of the element isolation film 3a can be made narrower than the conventional one, the chip area can be reduced.
[0050]
N ⁺ Source / drain diffusion layer 20 is p ⁻ Since it is formed directly on the epitaxial layer 2, the junction capacitance Cj in the core portion is reduced. Accordingly, high speed operation is possible.
[0051]
Furthermore, since the p-type well 5a can be formed simultaneously with the formation of the p-type well 5b of the SRAM portion, it is possible to prevent an increase in the number of manufacturing steps.
[0052]
Next, a second embodiment of the present invention will be described. In the second embodiment, the area is further reduced as compared with the first embodiment. FIGS. 11A and 11B to FIGS. 20A and 20B are cross-sectional views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps. In these drawings, (a) shows a region corresponding to the core portion of the semiconductor device, and (b) shows a region corresponding to the SRAM portion of the semiconductor device. Further, in the second embodiment shown in FIGS. 11 (a) and 11 (b) to 20 (a) and (b), FIGS. 1 (a) and (b) to FIGS. 10 (a) and (b) are used. The same components as those of the first embodiment shown are denoted by the same reference numerals, and detailed description thereof is omitted.
[0053]
First, as shown in FIGS. 11A and 11B, p is formed on the p-type silicon substrate 1 in both the core portion and the SRAM portion. ⁻ Epitaxial layer 2 is formed. Next, p at the core ⁻ An element isolation film 31 is formed in a predetermined region on the surface of the epitaxial layer 2, and p-type in the SRAM portion. ⁻ An element isolation film 3 b is formed in a predetermined region on the surface of the epitaxial layer 2. As a result, the nMOS region 101 and the pMOS region 102 are partitioned, and the nMOS region 103 and the pMOS region 104 are partitioned. The width of the element isolation film 31 is narrower than that of the element isolation film 3a in the first embodiment, for example, 0.6 μm. Thereafter, a sacrificial oxide film (not shown) is formed on the entire surface.
[0054]
Next, as shown in FIG. 12A, a resist 4 having an opening 4a is formed on the element isolation film 31 on the nMOS region 101 side. The size of the opening 4 a is about half that of the element isolation film 31. Further, as shown in FIG. 12B, an opening 4b is formed in the resist 4 on the nMOS region 103 side of the nMOS region 103 and the element isolation film 3b. On element isolation film 3b The size of the opening 4b is about half that of the element isolation film 3b. Next, using the resist 4 as a mask, for example, an acceleration voltage of 150 keV, 2 × 10 ¹³ The dose amount of B ⁺ In the core portion, a p-type well 5a is formed under the region matching the opening 4a of the element isolation film 31, and p-type well 5a is formed in the SRAM portion. ⁻ A p-type well 5b deeper than the element isolation film 3b is formed in the epitaxial layer 2. Further, using the resist 4 as a mask, for example, an acceleration voltage of 30 keV, 1.5 × 10 5 ¹³ The dose amount of B ⁺ To form a p-type channel 6 at an intermediate depth of the p-type well 5b.
[0055]
After the resist 4 is removed, as shown in FIGS. 13A and 13B, a resist 7 having an opening 7a in the center of the nMOS region 101 and completely covering the SRAM portion is newly formed. Next, using the resist 7 as a mask, for example, an acceleration voltage of 30 keV, 8 × 10 ¹² The dose amount of B ⁺ By ion implantation of p ⁻ A p-type channel 8 is formed at an intermediate depth of the epitaxial layer 2.
[0056]
After removing the resist 7, as shown in FIGS. 14A and 14B, a resist 32 having an opening 32a in the pMOS region 102 and completely covering the SRAM portion is formed. Next, using the resist 32 as a mask, for example, an acceleration voltage of 600 keV, 1.5 × 10 5 ¹³ P at the dose amount ⁺ And, for example, an acceleration voltage of 170 keV, 3 × 10 ¹² The dose amount of B ⁺ By ion implantation of p ⁻ An n-type well (first second conductivity type well) 33 is formed in the epitaxial layer 2. At this time, since the size of the opening 32a is narrower than that of the opening 9a in the first embodiment, the n-type well 33 is formed away from the p-type well 5a. P ⁺ B after ion implantation ⁺ By ion implantation of P ⁺ Therefore, the substantial impurity concentration of the n-type well 33 from the n-type is lowered. B ⁺ There is no need for ion implantation.
[0057]
After removing the resist 32, as shown in FIGS. 15A and 15B, a resist 11 having an opening 11a at the center of the pMOS region 102 and completely covering the SRAM portion is newly formed. Next, using the resist 11 as a mask, for example, an acceleration voltage of 240 keV, 5 × 10 ¹² P at the dose amount ⁺ And, for example, an acceleration voltage of 100 keV, 3 × 10 ¹² As of dose amount ⁺ Are ion-implanted to form an n-type channel 34 at an intermediate depth of the n-type well 33. The height of the n-type channel 34 is higher than that of the n-type channel 12 in the first embodiment.
[0058]
After the resist 11 is removed, a resist 35 having an opening 35a on the pMOS region 102 side of the element isolation film 31 is formed as shown in FIG. The size of the opening 35 a is about half that of the element isolation film 31. Further, as shown in FIG. 16B, an opening 35b is formed in the resist 35 on the pMOS region 104 side of the pMOS region 104 and the element isolation film 3b. The size of the opening 35b on the element isolation film 3b is about half that of the element isolation film 3b. Next, using the resist 35 as a mask, for example, an acceleration voltage of 350 keV, 2 × 10 ¹³ P at the dose amount ⁺ In the core portion, an n-type well (third second conductive layer) is formed under the region aligned with the opening 35a of the element isolation film 31. Type Well) 36a, and in the SRAM portion, p ⁻ An n-type well 36b deeper than the element isolation film 3b is formed in the epitaxial layer 2. Further, using the resist 35 as a mask, for example, an acceleration voltage of 100 keV, 1.4 × 10 ¹³ As of dose amount ⁺ Are ion-implanted to form an n-type channel 37 at an intermediate depth of the n-type well 36b.
[0059]
After the resist 35 is removed, the gate oxide film 16 and the gate electrode 17 are formed in the nMOS region 101, the pMOS region 102, the nMOS region 103, and the pMOS region 104 as shown in FIGS. 17 (a) and 17 (b).
[0060]
Next, as shown in FIGS. 18A and 18B, sidewalls 18 are formed on the sides of the gate oxide film 16 and the gate electrode 17. The sidewall 18 is made of, for example, a silicon oxide film and / or a silicon nitride film.
[0061]
Next, as shown in FIGS. 19A and 19B, a resist 19 having openings 19a and 19b in the nMOS region 101 and the nMOS region 103 is formed. Next, using the resist 19 as a mask, for example, an acceleration voltage of 20 keV, 5 × 10 ¹⁵ As of dose amount ⁺ Is implanted into the nMOS region 101 and the nMOS region 103 by ion implantation. ⁺ A source / drain diffusion layer 20 is formed.
[0062]
After the resist 19 is removed, as shown in FIGS. 20A and 20B, a resist 21 having openings 21a and 21b is formed in the pMOS region 102 and the pMOS region 104, respectively. Next, using the resist 21 as a mask, for example, an acceleration voltage of 4 keV, 5 × 10 ¹⁵ The dose amount of B ⁺ Is implanted into the pMOS region 102 and the pMOS region 104 by ion implantation. ⁺ A source / drain diffusion layer 22 is formed.
[0063]
Thereafter, ions implanted into each well and the source / drain diffusion layer are activated by annealing, and then a wiring or the like is formed by a normal method to complete the semiconductor device.
[0064]
As described above, in the semiconductor device manufactured according to the second embodiment, the p-type well 5a is formed on the nMOS region 101 side under the element isolation film 31, as shown in FIGS. In addition, since the n-type well 36 a having an impurity concentration higher than that of the n-type well 33 is formed on the pMOS region 102 side, the n-type source / drain diffusion layer 20 and the n-type well 33 are interposed between them. Punch-through and punch-through between the p-type source / drain diffusion layer 22 and the p-type epitaxial layer 2 are sufficiently suppressed. For this reason, since the width of the element isolation film 31 can be further reduced, the chip area can be further reduced.
[0065]
Further, since the substantial impurity concentration in the n-type well 33 is lower than that in the n-type well 10 in the first embodiment, the junction capacitance Cj in the core portion is further reduced. Therefore, higher speed operation is possible.
[0066]
Further, since the n-type well 36a can be formed simultaneously with the formation of the n-type well 36b of the SRAM portion, it is possible to prevent an increase in the number of manufacturing steps.
[0067]
Next, a third embodiment of the present invention will be described. In the third embodiment, the number of steps is reduced from that of the first embodiment. FIGS. 21A and 21B to 29A and 29B are cross-sectional views showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention in the order of steps. In these drawings, (a) shows a region corresponding to the core portion of the semiconductor device, and (b) shows a region corresponding to the SRAM portion of the semiconductor device. Further, in the third embodiment shown in FIGS. 21A and 21B to FIGS. 29A and 29B, FIGS. 1A and 1B to FIG. 10A and FIG. The same components as those of the first embodiment shown are denoted by the same reference numerals, and detailed description thereof is omitted.
[0068]
First, as shown in FIGS. 21A and 21B, p is formed on the p-type silicon substrate 1 in both the core portion and the SRAM portion. ⁻ Epitaxial layer 2 is formed. Next, p at the core ⁻ The element isolation film 3a is formed in a predetermined region on the surface of the epitaxial layer 2, and p is formed in the SRAM portion. ⁻ An element isolation film 3 b is formed in a predetermined region on the surface of the epitaxial layer 2. As a result, the nMOS region 101 and the pMOS region 102 are partitioned, and the nMOS region 103 and the pMOS region 104 are partitioned. Thereafter, a sacrificial oxide film (not shown) is formed on the entire surface.
[0069]
Next, as shown in FIG. 22A, a resist 4 having an opening 4a on the nMOS region 101 side of the element isolation film 3a is formed. Further, as shown in FIG. 22B, an opening 4b is formed in the resist 4 on the nMOS region 103 side of the nMOS region 103 and the element isolation film 3b. Next, using the resist 4 as a mask, for example, an acceleration voltage of 150 keV, 2 × 10 ¹³ The dose amount of B ⁺ In the core portion, a p-type well 5a is formed under the region matching the opening 4a of the element isolation film 3a, and p-type well 5a is formed in the SRAM portion. ⁻ A p-type well 5b deeper than the element isolation film 3b is formed in the epitaxial layer 2. Further, using the resist 4 as a mask, for example, an acceleration voltage of 30 keV, 1.5 × 10 5 ¹³ The dose amount of B ⁺ To form a p-type channel 6 at an intermediate depth of the p-type well 5b.
[0070]
After the resist 4 is peeled off, as shown in FIGS. 23A and 23B, a resist 7 having an opening 7a at the center of the nMOS region 101 and completely covering the SRAM portion is newly formed. Next, using the resist 7 as a mask, for example, an acceleration voltage of 30 keV, 8 × 10 ¹² The dose amount of B ⁺ By ion implantation of p ⁻ A p-type channel 8 is formed at an intermediate depth of the epitaxial layer 2.
[0071]
After the resist 7 is removed, as shown in FIGS. 24A and 24B, the resist 9 has an opening 9a on the pMOS region 102 side of the pMOS region 102 and the element isolation film 3a and completely covers the SRAM portion. Form. The region covered with the resist 9 of the element isolation film 3a is substantially the same as the region aligned with the opening 4a. Next, using the resist 9 as a mask, for example, an acceleration voltage of 600 keV, 1.5 × 10 ¹³ P at the dose amount ⁺ In the core portion, p ⁻ An n-type well 10 deeper than the p-type well 5a is formed in the epitaxial layer 2. Further, using the resist 9 as a mask, for example, an acceleration voltage of 100 keV, 3 × 10 ¹² As of dose amount ⁺ Are ion-implanted to form an n-type channel 41 at an intermediate depth of the n-type well 10.
[0072]
After stripping the resist 9, as shown in FIGS. 25A and 25B, the resist 13 has an opening 13a on the pMOS region 104 side of the pMOS region 104 and the element isolation film 3b and completely covers the core portion. Form. Next, using the resist 13 as a mask, for example, an acceleration voltage of 350 keV, 2 × 10 ¹³ P at the dose amount ⁺ Is implanted in the SRAM portion by p. ⁻ An n-type well 14 deeper than the element isolation film 3 b is formed in the epitaxial layer 2. Further, using the resist 13 as a mask, for example, an acceleration voltage of 100 keV, 1.4 × 10 ¹³ As of dose amount ⁺ Are ion-implanted to form an n-type channel 15 at an intermediate depth of the n-type well 14.
[0073]
After the resist 13 is peeled off, a gate oxide film 16 and a gate electrode 17 are formed in the nMOS region 101, the pMOS region 102, the nMOS region 103, and the pMOS region 104, as shown in FIGS.
[0074]
Next, as shown in FIGS. 27A and 27B, sidewalls 18 are formed on the sides of the gate oxide film 16 and the gate electrode 17. The sidewall 18 is made of, for example, a silicon oxide film and / or a silicon nitride film.
[0075]
Next, as shown in FIGS. 28A and 28B, a resist 19 having openings 19a and 19b is formed in the nMOS region 101 and the nMOS region 103, respectively. Next, using the resist 19 as a mask, for example, an acceleration voltage of 20 keV, 5 × 10 ¹⁵ As of dose amount ⁺ Is implanted into the nMOS region 101 and the nMOS region 103 by ion implantation. ⁺ A source / drain diffusion layer 20 is formed.
[0076]
After the resist 19 is removed, as shown in FIGS. 29A and 29B, a resist 21 having openings 21a and 21b is formed in the pMOS region 102 and the pMOS region 104, respectively. Next, using the resist 21 as a mask, for example, an acceleration voltage of 4 keV, 5 × 10 ¹⁵ The dose amount of B ⁺ Is implanted into the pMOS region 102 and the pMOS region 104 by ion implantation. ⁺ A source / drain diffusion layer 22 is formed.
[0077]
Thereafter, ions implanted into each well and the source / drain diffusion layer are activated by annealing, and then a wiring or the like is formed by a normal method to complete the semiconductor device.
[0078]
As described above, according to the third embodiment, since the n-type well 10 and the n-type channel 41 are formed using the resist 9, the number of steps can be reduced as compared with the first embodiment.
[0079]
In the semiconductor device manufactured according to the third embodiment, as shown in FIGS. 29A and 29B, the p-type well 5a is formed on the nMOS region 101 side under the element isolation film 3a. Therefore, as in the first embodiment, punch-through between the n-type source / drain diffusion layer 20 and the n-type well 10 is sufficiently suppressed. For this reason, it is possible to reduce a chip area. However, as shown in FIG. 29A, since the n-type channel 41 extends between the element isolation films, a slight increase in the junction capacitance Cj can be considered as compared with the first embodiment.
[0080]
Next, a fourth embodiment of the present invention will be described. In the fourth embodiment, the number of steps is reduced as compared with the second embodiment. 30A and 30B to 38A and 38B are cross-sectional views showing a method of manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps. In these drawings, (a) shows a region corresponding to the core portion of the semiconductor device, and (b) shows a region corresponding to the SRAM portion of the semiconductor device. Further, in the fourth embodiment shown in FIGS. 30A and 30B to FIGS. 38A and 38B, FIGS. 11A and 11B to FIGS. 20A and 20B are used. The same components as those of the second embodiment shown are denoted by the same reference numerals, and detailed description thereof is omitted.
[0081]
First, as shown in FIGS. 30A and 30B, in both regions of the core portion and the SRAM portion, p is formed on the p-type silicon substrate 1. ⁻ Epitaxial layer 2 is formed. Next, p at the core ⁻ An element isolation film 31 is formed in a predetermined region on the surface of the epitaxial layer 2, and p-type in the SRAM portion. ⁻ An element isolation film 3 b is formed in a predetermined region on the surface of the epitaxial layer 2. As a result, the nMOS region 101 and the pMOS region 102 are partitioned, and the nMOS region 103 and the pMOS region 104 are partitioned. Thereafter, a sacrificial oxide film (not shown) is formed on the entire surface.
[0082]
Next, as shown in FIG. 31A, a resist 4 having an opening 4a is formed on the element isolation film 31 on the nMOS region 101 side. Further, as shown in FIG. 31B, an opening 4b is formed in the resist 4 on the nMOS region 103 side of the nMOS region 103 and the element isolation film 3b. Next, using the resist 4 as a mask, for example, an acceleration voltage of 150 keV, 2 × 10 ¹³ The dose amount of B ⁺ In the core portion, a p-type well 5a is formed under the region matching the opening 4a of the element isolation film 31, and p-type well 5a is formed in the SRAM portion. ⁻ A p-type well 5b deeper than the element isolation film 3b is formed in the epitaxial layer 2. Further, using the resist 4 as a mask, for example, an acceleration voltage of 30 keV, 1.5 × 10 5 ¹³ The dose amount of B ⁺ To form a p-type channel 6 at an intermediate depth of the p-type well 5b.
[0083]
After the resist 4 is peeled off, as shown in FIGS. 32A and 32B, a resist 7 having an opening 7a at the center of the nMOS region 101 and completely covering the SRAM portion is newly formed. Next, using the resist 7 as a mask, for example, an acceleration voltage of 30 keV, 8 × 10 ¹² The dose amount of B ⁺ By ion implantation of p ⁻ A p-type channel 8 is formed at an intermediate depth of the epitaxial layer 2.
[0084]
After removing the resist 7, as shown in FIGS. 33A and 33B, a resist 32 having an opening 32a in the pMOS region 102 and completely covering the SRAM portion is formed. Next, using the resist 32 as a mask, for example, an acceleration voltage of 600 keV, 1.5 × 10 5 ¹³ P at the dose amount ⁺ In the core portion, p ⁻ An n-type well 33 deeper than the p-type well 5 a is formed in the epitaxial layer 2. In addition, resist 32 For example, an acceleration voltage of 100 keV, 3 × 10 ¹² As of dose amount ⁺ Are ion-implanted to form an n-type channel 42 at an intermediate depth of the n-type well 33.
[0085]
After the resist 32 is removed, as shown in FIGS. 34A and 34B, a resist 35 having an opening 35a is formed on the element isolation film 31 on the pMOS region 102 side. Further, as shown in FIG. 34B, an opening 35b is formed in the resist 35 on the pMOS region 104 side of the pMOS region 104 and the element isolation film 3b. Next, using the resist 35 as a mask, for example, an acceleration voltage of 350 keV, 2 × 10 ¹³ P at the dose amount ⁺ In the core portion, an n-type well 36a is formed under the region matching the opening 35a of the element isolation film 31, and in the SRAM portion, p-type is implanted. ⁻ An n-type well 36b deeper than the element isolation film 3b is formed in the epitaxial layer 2. Further, using the resist 35 as a mask, for example, an acceleration voltage of 100 keV, 1.4 × 10 ¹³ As of dose amount ⁺ Are ion-implanted to form an n-type channel 37 at an intermediate depth of the n-type well 36b.
[0086]
After the resist 35 is removed, the gate oxide film 16 and the gate electrode 17 are formed in the nMOS region 101, the pMOS region 102, the nMOS region 103, and the pMOS region 104 as shown in FIGS. 35 (a) and 35 (b).
[0087]
Next, as shown in FIGS. 36A and 36B, sidewalls 18 are formed on the sides of the gate oxide film 16 and the gate electrode 17. The sidewall 18 is made of, for example, a silicon oxide film and / or a silicon nitride film.
[0088]
Next, as shown in FIGS. 37A and 37B, a resist 19 having openings 19a and 19b is formed in the nMOS region 101 and the nMOS region 103, respectively. Next, using the resist 19 as a mask, for example, an acceleration voltage of 20 keV, 5 × 10 ¹⁵ As of dose amount ⁺ Is implanted into the nMOS region 101 and the nMOS region 103 by ion implantation. ⁺ A source / drain diffusion layer 20 is formed.
[0089]
After removing the resist 19, as shown in FIGS. 38A and 38B, a resist 21 having openings 21a and 21b is formed in the pMOS region 102 and the pMOS region 104, respectively. Next, using the resist 21 as a mask, for example, an acceleration voltage of 4 keV, 5 × 10 ¹⁵ The dose amount of B ⁺ Is implanted into the pMOS region 102 and the pMOS region 104 by ion implantation. ⁺ A source / drain diffusion layer 22 is formed.
[0090]
Thereafter, ions implanted into each well and the source / drain diffusion layer are activated by annealing, and then a wiring or the like is formed by a normal method to complete the semiconductor device.
[0091]
Thus, according to the fourth embodiment, since the n-type well 33 and the n-type channel 42 are formed using the resist 32, the number of steps can be reduced as compared with the second embodiment.
[0092]
In the semiconductor device manufactured according to the fourth embodiment, the p-type well 5a is formed on the nMOS region 101 side under the element isolation film 31, as shown in FIGS. In addition, since the n-type well 36 a having an impurity concentration higher than that of the n-type well 33 is formed on the pMOS region 102 side, the gap between the n-type source / drain diffusion layer 20 and the n-type well 33 is formed. Punch-through and punch-through between the p-type source / drain diffusion layer 22 and the p-type epitaxial layer 2 are sufficiently suppressed. For this reason, since the width of the element isolation film 31 can be further reduced, the chip area can be further reduced. However, as shown in FIG. 38A, since the n-type channel 42 extends between the element isolation films, a slight increase in the junction capacitance Cj is conceivable as compared with the second embodiment.
[0093]
Note that the conductivity type of the semiconductor substrate is not limited to the p-type, but may be an n-type. In this case, the conductivity type of each well, diffusion layer, etc. may be set to a conductivity type opposite to that of the previous embodiment.
[0094]
【The invention's effect】
As described above in detail, according to the present invention, the first conductivity type well having a higher impurity concentration than that of the semiconductor substrate is provided on the second core portion MOS transistor side under the element isolation film in the core portion. Therefore, the punch-through resistance under the element isolation region can be improved. For this reason, the width of the element isolation film in the core portion can be reduced, and the occupied area of the core portion can be reduced. Further, since the second core portion MOS transistor is formed on the semiconductor substrate, the junction capacitance can be reduced and the operation of the core portion can be speeded up as compared with the conventional one formed in the well. .
[0095]
By providing the third second conductivity type well on the first core portion MOS transistor side under the element isolation film, the punch-through resistance under the element isolation region can be further improved. Can be reduced.
[0096]
Furthermore, since the first first conductivity type well is formed at the same time as the second first conductivity type well, punch-through resistance under the element isolation region can be improved without increasing the number of steps. Further, in producing the well of the first core portion MOS transistor, the second conductivity type ions are implanted into the semiconductor substrate, and then the first conductivity type ions are implanted at a low dose, thereby substantially reducing the impurity concentration of the well. Thus, the junction capacity can be reduced. As a result, higher speed operation is possible.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the invention.
FIG. 2 is also a view showing the first embodiment of the present invention, and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 1 (a) and (b).
FIG. 3 is a view similarly showing the first embodiment of the present invention, and is a cross-sectional view showing the next step of the step shown in FIGS. 2 (a) and (b).
FIG. 4 is also a view showing the first embodiment of the present invention, and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 3 (a) and 3 (b).
FIG. 5 is a view similarly showing the first embodiment of the present invention, and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 4 (a) and 4 (b).
FIG. 6 is a view similarly showing the first embodiment of the present invention, and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 5 (a) and 5 (b).
FIG. 7 is also a view showing the first embodiment of the present invention and a cross-sectional view showing a step subsequent to the step shown in FIGS. 6 (a) and (b).
FIG. 8 is a view similarly showing the first embodiment of the present invention, and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 7 (a) and (b).
FIG. 9 is also a view showing the first embodiment of the present invention and a sectional view showing a step subsequent to the steps shown in FIGS. 8 (a) and 8 (b).
FIG. 10 is a view similarly showing the first embodiment of the present invention, and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 9 (a) and (b).
FIG. 11 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a second example of the present invention.
FIG. 12 is a view showing a second embodiment of the present invention, and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 11 (a) and (b).
FIG. 13 is a view showing a second embodiment of the present invention and a sectional view showing a step subsequent to the step shown in FIGS. 12 (a) and 12 (b).
14 is a cross-sectional view showing a second embodiment of the present invention and showing a step subsequent to the step shown in FIGS. 13 (a) and (b). FIG.
FIG. 15 is also a view showing a second embodiment of the present invention, and a sectional view showing a step subsequent to the steps shown in FIGS. 14 (a) and 14 (b).
FIG. 16 is a view showing a second embodiment of the present invention, and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 15 (a) and 15 (b).
FIG. 17 is also a view showing a second embodiment of the present invention and a cross-sectional view showing a step subsequent to the step shown in FIGS. 16 (a) and (b).
FIG. 18 is a cross-sectional view showing a second step of the step shown in FIGS. 17A and 17B, similarly showing the second embodiment of the present invention.
FIG. 19 is a cross-sectional view showing a second step of the step shown in FIGS. 18A and 18B, similarly showing the second embodiment of the present invention.
FIG. 20 is a view similarly showing the second embodiment of the present invention, and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 19 (a) and 19 (b).
FIG. 21 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the third example of the present invention.
FIG. 22 is a view showing a third embodiment of the present invention and is a cross-sectional view showing a step subsequent to the steps shown in FIGS. 21 (a) and (b).
23 is also a view showing a third embodiment of the present invention, and a sectional view showing a step subsequent to the steps shown in FIGS. 22 (a) and (b). FIG.
FIG. 24 is a view similarly showing the third embodiment of the present invention, and is a cross-sectional view showing the next step of the step shown in FIGS. 23 (a) and (b).
FIG. 25 is a view showing a third embodiment of the present invention, and a sectional view showing a step subsequent to the steps shown in FIGS. 24 (a) and 24 (b).
FIG. 26 is a view of the third embodiment of the present invention, and is a cross-sectional view showing the next step of the steps shown in FIGS. 25 (a) and 25 (b).
FIG. 27 is a view showing the third embodiment of the present invention and a sectional view showing a step subsequent to the step shown in FIGS. 26 (a) and (b).
FIG. 28 is a view showing the third embodiment of the present invention and a sectional view showing a step subsequent to the step shown in FIGS. 27 (a) and (b).
FIG. 29 is a view showing the third embodiment of the present invention and a sectional view showing a step subsequent to the step shown in FIGS. 28 (a) and (b).
30 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a fourth example of the invention. FIG.
FIG. 31 is a cross-sectional view showing a step subsequent to the step shown in FIGS. 30A and 30B, similarly showing the fourth embodiment of the present invention.
FIG. 32 is a cross-sectional view showing a step subsequent to the step shown in FIGS. 31A and 31B, similarly showing the fourth embodiment of the present invention.
FIG. 33 is a cross-sectional view showing a step subsequent to the step shown in FIGS. 32A and 32B, similarly showing the fourth embodiment of the present invention.
FIG. 34 is a cross-sectional view showing a step subsequent to the step shown in FIGS. 33A and 33B, similarly showing the fourth embodiment of the present invention.
FIG. 35 is a cross-sectional view showing a step subsequent to the step shown in FIGS. 34 (a) and 34 (b), similarly showing the fourth embodiment of the present invention.
FIG. 36 is a cross-sectional view showing a step subsequent to the step shown in FIGS. 35 (a) and 35 (b), similarly showing the fourth embodiment of the present invention.
FIG. 37 is a cross-sectional view showing a step subsequent to the step shown in FIGS. 36A and 36B, similarly showing the fourth embodiment of the present invention.
FIG. 38 is a view similarly showing a fourth embodiment of the present invention, and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 37 (a) and (b).
FIG. 39 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device.
FIG. 40 is a view similarly showing the conventional manufacturing method, and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 39 (a) and (b).
FIG. 41 is a view similarly showing the conventional manufacturing method, and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 40 (a) and (b).
42 is also a view showing the conventional manufacturing method and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 41 (a) and 41 (b). FIG.
43 is also a view showing a conventional manufacturing method and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 42 (a) and (b). FIG.
44 is also a view showing a conventional manufacturing method and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 43 (a) and 43 (b). FIG.
45 is also a view showing the conventional manufacturing method and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 44 (a) and 44 (b). FIG.
46 is also a view showing a conventional manufacturing method and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 45 (a) and 45 (b). FIG.
47 is also a view showing a conventional manufacturing method and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 46 (a) and 46 (b). FIG.
FIG. 48 is a view similarly showing the conventional manufacturing method and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 47 (a) and 47 (b).
FIG. 49 is a view similarly showing the conventional manufacturing method and is a cross-sectional view showing a step subsequent to the step shown in FIGS. 48 (a) and 48 (b).
50A and 50B are cross-sectional views showing punch-through under an element isolation region in a conventional CMOS transistor.
[Explanation of symbols]
1: Semiconductor substrate
2; Epitaxial layer
3a, 3b, 31; element isolation film
4, 7, 9, 11, 13, 19, 21, 32, 35; resist
4a, 4b, 7a, 9a, 11a, 13a, 19a, 19b, 21a, 21b, 32a, 35a, 35b: opening
5a, 5b; p-type well
6, 8; p-type channel
10, 14, 33, 36a, 36b; n-type well
12, 15, 34, 37, 41, 42; n-type channel
16: Gate oxide film
17; gate electrode
18; sidewall
20, 22: Source / drain diffusion layers
101, 103; nMOS region
102, 104; pMOS region
51; Semiconductor substrate
52; epitaxial layer
53a, 53b; element isolation film
54, 56, 58, 61, 63, 65, 71, 73; resist
54a, 56a, 58a, 61a, 63a, 65a, 71a, 71b, 73a, 73b: opening
55, 59; p-type well
57, 60; p-type channel
62, 66; n-type well
64, 67; n-type channel
68; Gate oxide film
69; gate electrode
70; sidewall
72, 74: Source / drain diffusion layers
81; Semiconductor substrate
82; Element isolation film
83, 84; well
85a, 86a; source diffusion layer
85b, 86b; drain diffusion layer
87; n-channel MOS transistor
88; p-channel MOS transistor
89, 90; insulating film
91, 92; well contact
93, 94; gate electrode
111, 113; nMOS region
112, 114; pMOS region

Claims (7)

A first conductive type semiconductor substrate; a first conductive type epitaxial film formed on a surface of the first conductive type semiconductor substrate; and having an impurity concentration lower than that of the first conductive type semiconductor substrate; and the first conductive type In the semiconductor device having the complementary transistor for the core portion and the complementary transistor for the memory cell portion formed in the epitaxial film,
The complementary transistor for the core part is
A first second conductivity type well formed in the first conductivity type epitaxial film;
A first core part MOS transistor formed in the first second conductivity type well and having a source / drain conductivity type of the first conductivity type;
A second core portion MOS transistor formed in the first conductivity type epitaxial film and having a source / drain conductivity type of the second conductivity type;
An element isolation film having a thickness smaller than that of the epitaxial film by isolating the first and second core MOS transistors from each other;
A first first conductivity type well having an impurity concentration higher than that of the first conductivity type epitaxial film formed on the second core portion MOS transistor side under the element isolation film;
A second conductivity type channel impurity region provided in the first second conductivity type well, extending to the element isolation film, and having an impurity concentration peak at a position spaced from the surface of the epitaxial film;
A first conductivity type channel provided in the first conductivity type epitaxial film, localized under the gate electrode of the second core portion MOS transistor, and having an impurity concentration peak at a position separated from the surface of the epitaxial film An impurity region;
Have
The complementary transistor for the memory cell portion is
A second first conductivity type well and a second second conductivity type well formed in the first conductivity type epitaxial film;
A first MOS transistor for a memory cell portion formed in the second second conductivity type well and having a source / drain conductivity type of the first conductivity type;
A second MOS transistor for the memory cell portion formed in the second first conductivity type well and having a source / drain conductivity type of the second conductivity type;
Have
The semiconductor device according to claim 1, wherein impurity concentrations of the first and second first conductivity type wells are equal to each other. 3. The semiconductor device according to claim 1, further comprising a third second conductivity type well that is formed on the first core portion MOS transistor side under the element isolation film and has an impurity concentration higher than that of the first second conductivity type well. Item 14. The semiconductor device according to Item 1. 3. The semiconductor device according to claim 2, wherein impurity concentrations of the second and third second conductivity type wells are equal to each other. Forming a first conductivity type epitaxial film having a lower impurity concentration than the semiconductor substrate on a first conductivity type semiconductor substrate;
The epitaxial film of the core part is thinner than the epitaxial film, and the core part is formed with regions and source / drains in which the first core part transistor whose source / drain is of the first conductivity type is to be formed. Forming a first element isolation film that is separated from a region where a second core part transistor of the second conductivity type is to be formed;
The epitaxial film of the memory cell portion is thinner than the epitaxial film, and the memory cell portion includes a region where a first memory cell portion transistor having a source / drain of the first conductivity type is to be formed. A step of forming a second element isolation film that is separated from a region where a second memory cell transistor for a source / drain of the second conductivity type is to be formed;
Of the regions separated by the first element isolation film of the core portion, the epitaxial film in the region where the first core portion transistor whose source and drain are of the first conductivity type is to be formed Forming a second conductivity type well of 1;
Forming a first first conductivity type well having an impurity concentration higher than that of the epitaxial film below the first element isolation film and on a region where the second core portion transistor is to be formed; At the same time, forming a second first conductivity type well having an impurity concentration higher than that of the epitaxial film in the epitaxial film in a region where the second memory cell transistor is to be formed;
Forming a second conductivity type channel provided in the first second conductivity type well, extending to the first element isolation film, and having an impurity concentration peak at a position separated from the surface of the epitaxial film; ,
A first conductivity type channel provided in the first conductivity type epitaxial film, localized under the gate electrode of the second core portion MOS transistor, and having an impurity concentration peak at a position separated from the surface of the epitaxial film Forming a step ;
By pre-Symbol the first core portion transistor is formed in the first second conductivity-type well, forming the second core portion transistor without forming a well in said epitaxial layer, the core Forming a complementary transistor for a portion;
Forming a complementary transistor for a memory cell portion in the memory cell portion;
A method for manufacturing a semiconductor device, comprising: Below the previous SL to form a second second conductivity type wells in the epitaxial layer of the first conductivity type region in the MOS transistor for the first memory cell unit is formed, the first isolation layer 5. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of forming a third second conductivity type well on the first core portion MOS transistor side. After the step of forming a pre-Symbol first and second first-conductivity-type well, the epitaxial layer to a first of said first conductivity type region in which the first memory cell section MOS transistor is formed 6. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of sequentially forming the second conductivity type well and the second conductivity type channel using the same mask. After the step of forming a pre-Symbol first and second first-conductivity-type well, a second conductivity type in the epitaxial layer of the first conductivity type region in which the MOS transistor for the first core portion is formed Forming a first second conductivity type well by implanting ions and implanting a first conductivity type ion at a lower dose than the second conductivity type ions;
The method of manufacturing a semiconductor device according to claim 4, wherein:

Images