JP3583086B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP3583086B2
JP3583086B2 JP2001211950A JP2001211950A JP3583086B2 JP 3583086 B2 JP3583086 B2 JP 3583086B2 JP 2001211950 A JP2001211950 A JP 2001211950A JP 2001211950 A JP2001211950 A JP 2001211950A JP 3583086 B2 JP3583086 B2 JP 3583086B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
thermoplastic resin
mold
sealing material
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001211950A
Other languages
Japanese (ja)
Other versions
JP2002083833A (en
Inventor
文彦 大岡
康子 二野宮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP2001211950A priority Critical patent/JP3583086B2/en
Publication of JP2002083833A publication Critical patent/JP2002083833A/en
Application granted granted Critical
Publication of JP3583086B2 publication Critical patent/JP3583086B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

【０００１】
【産業上の利用分野】
この発明は半導体装置及びその製造方法に関する。
【０００２】
【従来の技術】
従来より、半導体チップを搭載したパッケージ（半導体パッケージ）として種々の構造のものが提案されている。図３１は従来の半導体パッケージの構造を概略的に示す断面図である。一例としてリードフレームを用いた樹脂モールドタイプの半導体パッケージの構造を、図３１に示した。
【０００３】
図３１に示す半導体パッケージは、リードフレーム１０に搭載した半導体チップ１２を封止樹脂１４で封止して成る。
【０００４】
リードフレーム１０はダイパッド部１０ａ及びリード部１０ｂを有する。半導体チップ１２を導電体１６を介してダイパッド部１０ａに固定する。また所定個数のリード部１０ｂをダイパッド部１０ａの周囲に配置し、リード部１０ｂ及び半導体チップ１２をボンディングワイヤ１８を介して電気接続する。そしてダイパッド部１０ａ、その近傍のリード部１０ｂの一部、半導体チップ１２、及びボンディングワイヤ１８を、封止樹脂１４で覆う。
【０００５】
リード部１０ｂを半導体チップ１２と電気接続するための内部リード端子を、リード部１０ｂの封止樹脂１４で封止する部分に設ける。またリード部１２を図示しない配線板と電気接続するための外部リード端子を、リード部１０ｂの封止樹脂１４で封止しない部分に設ける。
【０００６】
次に上述の従来パッケージの製造方法につき説明する。図３２及び図３３は図３１に示す従来パッケージの製造工程を概略的に示す断面図である。
【０００７】
まず、半導体チップ１２をフェースアップで導電体１６を介してダイパッド部１０ａに固定する（図３２（Ａ））。次に、半導体チップ１２に既に形成してある回路素子（図示せず）をボンディングワイヤ１８を介してリード部１０ｂと電気接続する（図３２（Ｂ））。次に、ダイパッド部１０ａ、その近傍のリード部１０ｂの一部、半導体チップ１２、及びボンディングワイヤ１８を、封止樹脂１４で封止する（図３３）。次に図３１にも示すように、リード部１０ｂの封止樹脂１４で封止していない部分を折り曲げ、半導体パッケージを完成する。
【０００８】
【発明が解決しようとする課題】
しかしながら上述した従来パッケージでは、半導体チップをボンディングワイヤ及びリード部を介し配線板と接続する構造となっているため、半導体パッケージの外形サイズ（パッケージサイズ）を小さくすることに限界がある。
【０００９】
近年は半導体チップ１個当たりに形成される電気回路素子の集積度が増加する傾向が強く、その結果、半導体チップの外形サイズ（チップサイズ）はますます大きく成りつつある。一方、配線板への実装密度を高めるためには、パッケージサイズを小さくすることが必要である。従ってチップサイズが大きくなる中でパッケージサイズを小さくするには、ボンディングワイヤの長さを短くしたり、半導体パッケージから突出するボンディングワイヤの高さを低くしたりすることが望まれる。しかし長さを短くし過ぎたり高さを低くし過ぎたりすると半導体チップとリード部とをボンディングワイヤで電気接続することが出来なくなるため、パッケージサイズを必ずしも充分に満足できる程度まで小さく出来ない。
【００１０】
この発明の目的は上述した従来の問題点を解決し、サイズをより小さく出来る半導体装置とその製造に適した半導体装置の製造方法とを提供することにある。
【００１１】
【課題を解決するための手段】
この目的の達成を図るため、この出願に係る半導体装置の製造方法の発明によれば、集積回路が形成された半導体チップの第１主表面上に、集積回路に一端が接続された突起電極を形成する工程と、半導体チップを凹部を有する型の第１の部分の凹部内に第１主表面を上側にして配置する工程と、半導体チップの第１主表面上に、固化させた状態の熱可塑性樹脂を配置する工程と、熱可塑性樹脂を可塑性を示す温度に加熱する工程と、型の第１の部分と第１の部分に対向する型の第２の部分とにより、流動化した熱可塑性樹脂を押圧して半導体チップの第１主表面に形成されている突起電極を熱可塑性樹脂で覆う工程とを含んでいる。
【００１２】
また、この発明の製造方法によれば、固化させた状態の熱可塑性樹脂を凹部を有する型の第１の部分の凹部内に配置する工程と、熱可塑性樹脂の表面上に、集積回路を具え、集積回路に一端が接続された突起電極が第１主表面上に形成されている半導体チップを第１主表面を上側にして配置する工程と、固化させた状態の熱可塑性樹脂を可塑性を示す温度に加熱する工程と、型の第１の部分とこの第１の部分に対向する型の第２の部分とにより、流動化した熱可塑性樹脂を押圧して半導体チップの第１主表面に対向する第２主表面を熱可塑性樹脂で覆う工程とを含んでいる。なお、以下において、この発明の半導体装置自体に関する発明を第一発明と称し、これらの製造方法に関する発明を第二発明と総称することがある。
【００１３】
また、この発明の半導体装置の製造方法によれば、凹部を有する第１の型の当該凹部内に、表面に突起電極が形成された半導体基板を配置する工程と、第１の型内に配置された半導体基板の表面上に熱可塑性樹脂を配置する工程と、熱可塑性樹脂が流動化する温度に加熱する工程と、第１の型とこの第１の型に対向する第２の型とで熱可塑性樹脂を押圧することで、半導体基板を流動化した樹脂にて覆う工程とを含むことを特徴とする。
【００１４】
また、この出願で外部端子とは、突起電極と外部との電気的接続を補助するための導体であって、突起電極の第２端部に形成される導体を意味する。そのため、以下では、外部端子を補助導体と称することがある。
【００１５】
また、第一発明又は第二発明の実施に当たっては、半導体チップの第２主表面をセラミックス板で封止するのがよい。
【００１６】
さらに第一発明又は第二発明の実施に当たっては、集積回路部を封止する封止材が熱硬化型樹脂および熱可塑性樹脂のいずれか一方を含むのが好ましい。また第二発明は第一発明の半導体装置を製造するのに適した方法のひとつであって、従って第一発明を第二発明によって製造したものに限定するものではない。
【００１７】
【作用】
第一発明によれば、突起電極を集積回路部から突出させて形成するので、突起電極の突出方向から見た半導体装置の長さ及び幅を、半導体チップと同程度まで小さくできる。また突起電極の突出方向における半導体装置の高さを、突起電極の突出高さを低くすることによって低くできる。特に、第一発明のうちの特に外部端子を備える発明によれば、この外部端子を備えることにより、半導体装置を配線基板等に搭載する際に、半導体装置と配線基板とを電気的に確実に接続させることができる。また第一発明のうちの封止材の厚さを考慮した発明によれば、封止材の厚さを第１端部および第２端部間の距離と実質的に同じにしてあるので、突起電極を封止材によって保護することができる。
【００１８】
さらに少なくとも集積回路部を封止しているので、半導体装置を保管し或は運搬し或は実装するときに集積回路部が損傷するのを防止出来る。
【００１９】
また、第二発明によれば、小型であって、しかも保管や運搬や実装に便利な半導体装置を提供出来る。また、第二発明の好適例によれば、少なくとも突起電極及び集積回路部を封止材で覆った後に封止材を削って露出させると、集積回路部の封止と突起電極の露出とを簡略に行なえる。
【００２０】
【実施例】
以下、図面を参照し、発明の実施例につき説明する。尚、図面はこの発明が理解できる程度に概略的に示してあるにすぎず、従ってこの発明を図示例に限定するものではない。
【００２１】
図１は第一発明の第一実施例の構成を概略的に示す断面図である。この実施例の半導体装置（この実施例では半導体パッケージと称する。）３４は半導体チップ２２と、半導体チップ２２の集積回路部２２ａに突出させて設けた接続導体（突起電極）２０と、接続導体２０の突出端部（第２端部）を露出させて集積回路部２２ａを封止する封止材２８とを備える。図１に示すように、接続導体２０は、第１端部及び第２端部を両端に有しており、この第１端部が集積回路に接続されてかつこの第２端部が封止材２８から露出するように設けられている。また、半導体チップ２２の表面のうち集積回路が設けられている主表面を第１主表面と称し、集積回路が設けられていない第１主表面と反対側の主表面を第２主表面と称し、それ以外の半導体チップ２２の表面を側面と称する。この集積回路は、上述した集積回路部２２ａと等しい。
【００２２】
図示せずも、集積回路部２２ａは電気回路素子例えばトランジスタや容量や配線を有し、所望の電気回路素子の端子部分に接続導体２０を設ける。封止材２８は半導体チップ２２の集積回路部２２ａを覆いそれ以外の半導体チップ２２部分を覆わない。すなわち、半導体チップ２２の側面及び第２主表面は露出されている。また接続導体２０及び封止材２８が集積回路部２２ａから突出する高さをほぼ等しくしている。すなわち、封止材２８の表面が、接続導体２０の第２端部と略同一面に形成されている。
【００２３】
第一発明の第一実施例の半導体パッケージ３４と従来のリードフレームを用いた半導体パッケージ（図３３参照）とを比較すると、この実施例では、リードフレーム及びボンディングワイヤを用いないのでリードフレーム厚約０．２ｍｍ及びボンディングワイヤの結線時の突出高さ約０．２ｍｍが不要となり、従って半導体パッケージ３４の厚さを、従来よりも薄く出来る。従来パッケージでは厚さが例えば約１．０ｍｍであったのに対しこの実施例パッケージでは厚さを例えば半導体チップ２２の厚さ約０．３５ｍｍ及び封止材２８の厚さ約０．０２ｍｍとして合計約０．４ｍｍとすることが出来る。さらにこの実施例では、リードフレームを用いないので外部リード端子部が不要となり、従って半導体パッケージ３４の幅を、従来よりも狭く出来る。
【００２４】
図２〜図１１は第二発明の第一実施例の説明に供する製造工程図である。この実施例は、図１に示す半導体パッケージ３４を製造する例である。
【００２５】
まず、接続導体２０を、半導体チップ２２の集積回路部２２ａから突出させて集積回路部２２ａの所望の端子部分に形成する（図２）。この実施例では、接続導体２０の形成材料として、半田、金或はそのほかの導電性材料、好ましくはろう付けを行なえる導電性材料を用いる。接続導体２０の形成には任意好適な技術を用いることができ、例えば、厚膜印刷技術を用いて形成する。或はフォトリソ及びエッチング技術と蒸着そのほかの薄膜形成技術とを組み合わせて用いて形成する。或はフォトリソ及びエッチング技術と無電解めっき技術とを組み合わせて用いて形成する。或は球状又は半球状の接続導体２０を集積回路部２２ａの端子部分に圧着して形成する。また、接続導体２０の形成を、半導体ウエハから個々の半導体チップ２２を分離する前にウエハ状態で行ないその後個々の半導体チップ２２に分離しても良いし、半導体チップ２２を半導体ウエハから分離した状態で行なっても良い。
【００２６】
次に、接続導体２０及び集積回路部２２ａを封止材２８で覆う（図３〜図７）。この実施例では、封止材２８を熱硬化型樹脂とし、型の第１の部分２４（以下、単に型２４と称する。）及び型の第２の部分（以下、単に型２６と称する。）を用いて型成形技術により封止材２８で覆う。型２４は半導体チップ２２を入れる凹部２４ａを有する。凹部２４ａの深さＨを、半導体チップ２２を凹部２４ａ内に載置したときの凹部２４ａ下面から接続導体２０の突出端に至る高さｈよりも長くする（図４参照）。そして半導体チップ２２を凹部２４ａに入れた状態で半導体チップ２２が実質的に位置ずれしないように凹部２４ａの側壁面で半導体チップを支持し、しかも半導体チップ２２を凹部２４ａ内へ入れ或は凹部２４ａ外へ出す作業が自在に行なえるように凹部２４ａを形成する。また型２６は封止材流路２６ａと凹部２４ａを開閉自在に閉じる蓋部分２６ｂとを有する（図５参照）。そして凹部２４ａを閉じたとき凹部２４ａ内の気体を凹部２４ａ外へ抜き出すための気体流路（図示せず）を、型成形技術で通常行なわれている如く、型２４及び又は２６に設ける。型２４及び２６の形成材料は例えば金属であり、すなわち金型２４及び２６とできる。
【００２７】
封止材２８で覆うに当っては、まず、型２４、２６を封止材２８が流動しやすい温度に予め加熱しておく。そして半導体チップ２２を、集積回路部２２ａが凹部２４ａの外側へ向くようにして型２４の凹部２４ａ内に入れる（図３〜図４）。次いで、凹部２４ａを型２６の蓋部分２６ｂで閉じる（図５）。凹部２４ａを閉じた状態で蓋部分２６ｂと接続導体２０とを離間させる。蓋部分２６ｂと集積回路部２２ａとの離間距離は例えば５０μｍである。次いで、流動性を有し硬化させていない状態の封止材２８を封止材流路２６ａを介して凹部２４ａ内に注入し、凹部２４ａ及び蓋部分２６ｂが囲む空間内に封止材２８を充満させ、接続導体２０及び集積回路部２２ａを封止材２８中に埋め込む（図５〜図６）。好ましくは、接続導体２０及び集積回路部２２ａ特に集積回路部２２ａと封止材２８との間に気泡を残存させないようにする。次いで、封止材２８を加熱して硬化させ、その後、半導体チップ２２を型２４及び２６から取り外して接続導体２０及び集積回路部２２ａを封止材２８中に埋め込んだ半導体チップ２２を得る（図７）。封止材２８を硬化させる際には、例えば、型２４を封止材２８が硬化する温度に加熱し、型２６を封止材２８が硬化しない温度に加熱し、これら型２４、２６の加熱温度の差を小さくして封止材２８の熱応力を小さくするようにするのが良い。また、半導体チップ２２を型２４から取り外すのを容易にするため、例えば、突き棒ｐ（この棒ｐを図３（Ｂ）中に一点鎖線で示した）が凹部２４ａの底から凹部２４ａの高さ方向ｑに突出する高さの調整自在に、突き棒ｐを型２４に摺動自在に設け、半導体チップ２２を凹部２４ａから突き棒ｐで突き出して取り外すのが良い。或は、型２４の底を形成する部分ｒ（この部分ｒを図３（Ｂ）中に点線で示した）を凹部２４ａの高さの調整を自在に行なえるように構成しても良い。
【００２８】
次に、接続導体２０及び集積回路部２２ａを覆う封止材２８を、研磨、研削、切削或はそのほかの任意好適な削り取り装置を用いて削って接続導体２０の突出端部を露出させる（図８〜図１１）。この実施例で用いる削り取り装置は固定部３０（図８参照）及び削り部３２を備える。固定部３０は半導体チップ２２を位置決め固定するための位置決め部３０ａを有し、削り部３２は半導体チップ２２を削るための削り面３２ａを有する。例えば、位置決め部３０ａは凹部であって半導体チップ２２をこの位置決め部３０ａに嵌め込むことによって位置決めする。また削り面３２ａには例えば研磨材、砥粒、或は切削刃を設ける。
【００２９】
接続導体２０を露出させるに当っては、まず、接続導体２０とは反対側の半導体チップ２２部分を固定部３０に取り付けて、半導体チップ２２を固定部３０に位置決め固定する（図８〜図９）。次いで、接続導体２０上の封止材２８部分を削り部３２の削り面３２ａに当接させる（図１０）。次いで、封止材２８を削り面３２ａに押し付けた状態で封止材２８及び削り面３２ａを相対的に動かして、接続導体２０の突出端部が削り面３２ａと接触するまで封止材２８を削り、これにより接続導体２０の突出端部を封止材２８から露出させる（図１１）。
【００３０】
次に、半導体チップ２２を固定部３０から取り外し、集積回路部２２ａを封止材２８で封じ込んで成る半導体パッケージ３４を得る（図１）。半導体チップ２を固定部３０から取り外すのを容易にするため、型２４と同様の突き棒ｐや部分ｒを固定部３０に設けるようにしても良い。
【００３１】
第二発明の第一実施例の製造方法と従来のリードフレームを用いた半導体パッケージの製造方法とを比較すれば、この実施例ではボンディングワイヤ及びリードフレームを用いないので、ボンディング工程及びリードフレームのめっき工程が不要であり従って従来よりもＴＡＴ（Ｔｕｒｎ Ａｒｏｕｎｄ Ｔｉｍｅ）を大幅に短縮出来、しかも製造設備に対する投資を低減出来る。またこの実施例では従来よりも工程が簡略になるので、不良品検出のためのチェック項目を従来よりも少なく出来る。
【００３２】
図１２は半導体チップの実装状態を概略的に示す断面図である。同図に示す配線板３６は基板３６ａと基板３６ａに設けた配線パターン３６ｂと配線パターン３６ｂの端子部分に設けた接続導体３６ｃとを備える。接続導体３６の形成材料を半田、金、導電性接着材或はそのほかの導電性材料、好ましくはろう付けを行なえる導電性材料とする。半導体パッケージ３４の接続導体２０及び配線板３６の接続導体３６ｃの少なくとも一方をろう付けを行なえる導電性材料とする。
【００３３】
上述のようにして製造した半導体パッケージ３４を配線板３６に実装するに当っては、半導体パッケージ３４の接続導体２０及び配線板３６の接続導体３６ｃを位置合わせして、接続導体２０を接続導体３６ｃ上に位置させる。次いで接続導体２０及び又は３６ｃを加熱溶融し然る後に冷却凝固させて、集積回路部２２ａと配線パターン３６ｂとを接続導体２０、３６ｃを介して電気接続する。
【００３４】
尚、半導体パッケージ３４の接続導体２０がろう付けを行なえる導電性材料である場合には、配線板３６の接続導体３６ｃを必ずしも設けなくとも良い。
【００３５】
図１３は第一及び第二発明の第一実施例の変形例の説明に供する図である。
【００３６】
この変形例の半導体パッケージ３７は、図１３にも示すように、第一実施例の半導体パッケージ３４に補助導体３８を設けて成る。補助導体３８を接続導体２０上及び当該導体２０近傍の封止材２８上に突出させて設けている。この補助導体３８は、接続導体２０の露出した第２端部上に形成されており、従って、この第２端部と電気的に接続されている。接続導体２０の突出方向から見て補助導体３８を接続導体２０よりも広く形成する。図１３に示すように、接続導体２０が突出した方向から見た接続導体２０の最大幅よりも広い最大幅を有するように、補助導体３８が設けられている。
【００３７】
さらに第二発明の変形例は半導体パッケージ３７を製造する例であって、この例では、まず、半導体パッケージ３４を上述した第一実施例と同様の工程を経て完成する（図２〜図１１及び図１）。
【００３８】
次に、補助導体３８を接続導体２０の突出方向から見て接続導体２０よりも広く成るように接続導体２０上及び当該導体２０近傍の封止材２８上に形成し、補助導体３８を有する半導体パッケージ３７を得る（図１３）。
【００３９】
補助導体３８の形成材料は半田、金或はそのほかの導電性材料、好ましくはろう付けを行なえる導電性材料である。補助導体３８の形成には任意好適な技術を用いることができ、例えば、厚膜印刷技術を用いて形成する。或はフォトリソ及びエッチング技術と蒸着そのほかの薄膜形成技術とを組み合わせて用いて形成する。或はフォトリソ及びエッチング技術と無電解めっき技術とを組み合わせて用いて形成する。或は球状又は半球状の補助導体３８を接続導体２０に圧着して形成する。第二発明の第一実施例の変形例でも、第二発明の第一実施例と同様の効果が得られる。
【００４０】
図１４は第一発明の第二実施例の構成を概略的に示す断面図である。尚、上述した第一実施例の構成成分に対応する構成成分については同一の符号を付して示し、第一実施例と同様の点についてはその詳細な説明を省略する。
【００４１】
この実施例の半導体パッケージ４４は半導体チップ２２、接続導体２０、封止材２８、４０を備える。この実施例では、接続導体２０を設けた半導体チップ２２の全体を封止材２８、４０で覆う。封止材４０例えばセラミック板で半導体チップ２２の集積回路部２２ａとは反対側の部分を覆うと共に、封止材２８例えば熱硬化型の樹脂で接続導体２０を露出させるようにしながら残りの半導体チップ２２部分を覆う。
【００４２】
第一発明の第二実施例でも、半導体パッケージ４４の厚さを、第一実施例よりは厚いが従来パッケージよりも薄くすることが出来る。また半導体パッケージ４４の幅を従来パッケージよりも狭く出来る。
【００４３】
図１５〜図２１はこの発明の第二実施例の説明に供する製造工程図である。この実施例は半導体パッケージ４４を製造する例である。尚、第一実施例の構成成分に対応する構成成分を同一の符号を付して示し、第一実施例と同様の点についてはその詳細な説明を省略する。
【００４４】
まず、接続導体２０を半導体チップ２２の集積回路部２２ａから突出させて集積回路部２２ａに形成する。
【００４５】
次に、接続導体２０を設けた半導体チップ２２の全体を、封止材２８、４０で覆う（図１５〜図１９）。この実施例では、半導体チップ２２を型２４の凹部２４ａ内に入れた状態で半導体チップ２２の側壁と凹部２４ａの側壁との間にこれら側壁の全周にわたり封止材を流し込むための間隙ｔが出来るように、凹部２４ａを半導体チップ２２よりも幅広く形成する（図１６参照）。
【００４６】
封止材２８、４０で覆うに当っては、まず、集積回路部２２ａとは反対側の半導体チップ２２部分に板状の封止材４０例えばセラミック板を接着剤４２を介して固着する（図１５）。そして型２４、２６を封止材２８が流動しやすい温度に予め加熱しておく。次いで、半導体チップ２２を凹部２４ａ内に入れ、半導体チップ２２及び凹部２４ａの側壁の間にこれら側壁の全周にわたり間隙ｔが出来るように、任意好適な手段を用いて半導体チップ２２を位置決めする（図１６）。次いで、凹部２４ａを型２６の蓋部分２６ｂで閉じる（図１７）。次いで、流動性を有し硬化していない状態の封止材２８を型２６の封止材流路２６ａを介して凹部２４ａ内に注入し、接続導体２０、集積回路部２２ａ及び半導体チップ２２の側壁を封止材２８中に埋め込む（図１８）。好ましくは、接続導体２０及び集積回路部２２ａ特に集積回路部２２ａと封止材２８との間に気泡を残存させないようにする。次いで、封止材２８を加熱して硬化させ、その後、半導体チップ２２を型２４及び２６から取り外す（図１９）。封止材２８を硬化させる際には、例えば、型２４を封止材２８が硬化する温度に加熱し、型２６を封止材２８が硬化しない温度に加熱し、型２４、２６の加熱温度の差を小さくして封止材２８の熱応力を小さくするようにするのが良い。
【００４７】
次に、図２０〜図２１にも示すように、封止材２８を削って接続導体２０を露出させる（図２０〜図２１）。
【００４８】
接続導体２０を露出させるに当っては、まず、接続導体２０とは反対側の半導体チップ２２部分を封止材２８、４０を介して固定部３０に取り付け、接続導体２０上の封止材２８を削り部３２の削り面３２ａに当接させる（図２０）。次いで、封止材２８を削り面３２ａに圧接した状態で封止材２８及び削り面３２ａを相対的に動かし、接続導体２０が露出するまで封止材２８を削る（図２１）。
【００４９】
次に、半導体チップ２２を固定部３０から取り外し、半導体チップ２２を封止材２８、４０で封じ込んで成る半導体パッケージ４４を得る（図１４）。第二発明の第二実施例でも、第一実施例と同様の効果が得られる。
【００５０】
図２２は第一発明の第三実施例の構成を概略的に示す断面図である。尚、第一実施例の構成成分に対応する構成成分については同一の符号を付して示し、第一実施例と同様の点についてはその詳細な説明を省略する。
【００５１】
この実施例の半導体パッケージ４８は接続導体２０、半導体チップ２２及び封止材４６、４７を備える。この実施例では、接続導体２０を設けた半導体チップ２２の全体を封止材４６、４７で覆う。封止材４６例えば熱可塑性樹脂で半導体チップ２２の集積回路部２２ａとは反対側の部分を覆うと共に封止材４７例えば熱可塑性樹脂で接続導体２０を露出させるようにしながら残りの半導体チップ２２部分を覆う。
【００５２】
第一発明の第三実施例でも、半導体パッケージ４８の厚さを、第一実施例よりは厚いが従来パッケージよりも薄く出来る。また半導体パッケージ４８の幅を従来パッケージよりも狭く出来る。
【００５３】
図２３〜図３０は第二発明の第三実施例の説明に供する製造工程図である。この実施例は図２２に示す半導体パッケージ４８を製造する例である。尚、第一実施例の構成成分に対応する構成成分については同一の符号を付して示し、第一実施例と同様の点についてはその詳細な説明を省略する。
【００５４】
まず、第一実施例と同様にして、半導体チップ２２及び接続導体２０を形成する。
【００５５】
次に、接続導体２０を設けた半導体チップ２２の全体を、封止材４６、４７で覆う（図２３〜図２８）。
【００５６】
封止材４６、４７で覆うに当っては、まず、封止材４６例えば熱可塑性樹脂を固化させた状態で型２４の凹部２４ａ内に嵌め込み、封止材４６を凹部２４ａで支持して位置決めする（図２３）。封止材４６は固化させた状態でその中央部に凹部４６ａを備え、従って封止材４６の周辺部の高さをその中央部の高さよりも高くしてある。次いで、集積回路部２２ａとは反対側の半導体チップ２２部分を封止材４６の凹部４６ａ内に嵌め込み、封止材４７の周辺部を半導体チップ２２及び凹部２４ａの側壁の間に挿入すると共に半導体チップ２２を凹部４６ａで支持して位置決めする（図２４）。次いで、封止材４７例えば熱可塑性樹脂を固化させた状態で、型２４の凹部２４ａ内に嵌め込み、半導体チップ２２の接続導電体２０上に載置する（図２５）。封止材４７は固化させた状態でその中央部に凹部４７ａを備え、従って封止材４６の周辺部の高さをその中央部の高さよりも高くしてある。この凹部４７ａ内に接続導体２０を入れるようにして封止材４７を型２４の凹部２４ａ内に嵌め込み、封止材４７の周辺部を半導体チップ２２及び凹部２４ａの側壁の間に挿入する。次いで、型２６の蓋部分２６ｂを摺動自在に型２４の凹部２４ａ内に嵌め込み、蓋部分２６ｂを封止材４７に当接させる（図２６）。尚、この例では封止材流路２６ａを型２６に設けていない。次いで、封止材４６、４７を、これらが可塑性を示す、すなわち流動化する温度に型２４、２６を介して加熱しながら型２４、２６の間に押圧し、この押圧により、封止材４６、４７の周辺部を互いに圧接させると共に接続導体２０を設けた半導体チップ２２全体を封止材４６、４７中に埋め込む。好ましくは、接続導体２０及び集積回路部２２ａ特に集積回路部２２ａと封止材４７との間に気泡を残存させないようにする。次いで、封止材４６、４７の周辺部を圧接したまま封止材４６、４７を型２４、２６を介し冷却して固化させ、これにより封止材４６、４７の周辺部を互いに接着する（図２７）。次いで、半導体チップ２２を型２４、２６から取り外し、封止材４６、４７で覆われた半導体チップ２２及び接続導体２０を得る（図２８）。
【００５７】
次に、接続導体２０及び集積回路部２２ａを覆う封止材４７を削って接続導体２０を露出させる（図２９〜図３０）。
【００５８】
接続導体２０を露出させるに当っては、まず半導体チップ２２を固定部３０に取り付けて位置決め固定し、然る後、接続導体２０上の封止材４７部分を削り部３２の削り面３２ａに当接させる（図２９）。次いで、削り面３２ａにより、接続導体２０が露出するまで封止材４７を削る（図３０）。
【００５９】
次に、半導体チップ２２を固定部３０から取り外し、接続導体２０を設けた半導体チップ２２全体を封止材４６、４７で封じ込んで成る半導体パッケージ４８を得る（図２２）。第二発明の第三実施例でも、第一実施例と同様の効果を得られる。
【００６０】
発明は上述した実施例にのみ限定されるものではなく、従って各構成成分の形状、配設位置、形成材料、数値的条件及びそのほかを任意好適に変更出来る。
【００６１】
【発明の効果】
上述した説明からも明らかなように、第一発明の半導体装置によれば、半導体チップをこれとは別の電気回路に接続するための突起電極を半導体チップの集積回路部から突出させて形成するので、突起電極の突出方向から見た半導体装置の長さ及び幅を小さく出来る。また突起電極の突出方向における半導体装置の高さを、突起電極の突出高さを低くすることによって低く出来る。従って従来のリードフレームを用いた半導体装置に比較して、半導体装置自体のサイズを小さく出来る。さらに少なくとも集積回路部を封止しているので、半導体装置を保管し或は運搬し或は実装するときに集積回路部が破損するのを防止出来る。従来周知のフリップチップと比較すれば、フリップチップでは集積回路部を保護膜で保護しているものの保護膜のみでは湿気や衝撃から集積回路部を必ずしも充分に保護することが出来ず従ってフリップチップを封止材で封止しない状態ではその保管や運搬や実装に注意を要し不便である。これに対しこの発明の半導体装置は封止材により集積回路部を湿気や衝撃から保護しているので、この半導体装置の保管や運搬や実装を行なうときに損傷が生じにくく便利である。
【００６２】
従って第一発明の半導体装置によれば、小型であって、しかも保管や運搬や実装に便利な半導体装置を提供出来る。
【００６３】
さらに第二発明の半導体装置の製造方法によれば、小型であって、しかも保管や運搬や実装に便利な半導体装置を提供できる。また第二発明の好適例によれば、少なくとも突起電極及び集積回路部を封止材で覆ったのちに封止材を削って突起電極を露出させるので、集積回路部の封止と突起電極の露出とを簡略に行なえ、従って第一発明の半導体装置を簡略に製造出来る。
【図面の簡単な説明】
【図１】第一発明の第一実施例の構成を概略的に示す断面図である。
【図２】第二発明の第一実施例における製造工程の一段階を概略的に示す断面図である。
【図３】（Ａ）及び（Ｂ）は第二発明の第一実施例における製造工程の同一工程段階を概略的に示す上面図及び断面図である。
【図４】（Ａ）及び（Ｂ）は第二発明の第一実施例における製造工程の同一工程段階を概略的に示す上面図及び断面図である。
【図５】（Ａ）及び（Ｂ）は第二発明の第一実施例における製造工程の同一工程段階を概略的に示す上面図及び断面図である。
【図６】第二発明の第一実施例における製造工程の一段階を概略的に示す断面図である。
【図７】第二発明の第一実施例における製造工程の一段階を概略的に示す断面図である。
【図８】（Ａ）及び（Ｂ）は第二発明の第一実施例における製造工程の同一工程段階を概略的に示す下面図及び断面図である。
【図９】（Ａ）及び（Ｂ）は第二発明の第一実施例における製造工程の同一工程段階を概略的に示す下面図及び断面図である。
【図１０】第二発明の第一実施例における製造工程の一段階を概略的に示す断面図である。
【図１１】第二発明の第一実施例における製造工程の一段階を概略的に示す断面図である。
【図１２】半導体パッケージの実装状態を概略的に示す断面図である。
【図１３】（Ａ）及び（Ｂ）は第一発明の第一実施例の変形例の構成を概略的に示す上面及び断面図である。
【図１４】第一発明の第二実施例の構成を概略的に示す断面図である。
【図１５】第二発明の第二実施例における製造工程の一段階を概略的に示す断面図である。
【図１６】（Ａ）及び（Ｂ）は第二発明の第二実施例における製造工程の同一工程段階を概略的に示す上面図及び断面図である。
【図１７】（Ａ）及び（Ｂ）は第二発明の第二実施例における製造工程の同一工程段階を概略的に示す上面図及び断面図である。
【図１８】第二発明の第二実施例における製造工程の一段階を概略的に示す断面図である。
【図１９】第二発明の第二実施例における製造工程の一段階を概略的に示す断面図である。
【図２０】第二発明の第二実施例における製造工程の一段階を概略的に示す断面図である。
【図２１】第二発明の第二実施例における製造工程の一段階を概略的に示す断面図である。
【図２２】第一発明の第三実施例の構成を概略的に示す断面図である。
【図２３】（Ａ）及び（Ｂ）は第二発明の第三実施例における製造工程の同一工程段階を概略的に示す上面図及び断面図である。
【図２４】（Ａ）及び（Ｂ）は第二発明の第三実施例における製造工程の同一工程段階を概略的に示す上面図及び断面図である。
【図２５】（Ａ）及び（Ｂ）は第二発明の第三実施例における製造工程の同一工程段階を概略的に示す上面図及び断面図である。
【図２６】（Ａ）及び（Ｂ）は第二発明の第三実施例における製造工程の一段階を概略的に示す断面図である。
【図２７】第二発明の第三実施例における製造工程の一段階を概略的に示す断面図である。
【図２８】第二発明の第三実施例における製造工程の一段階を概略的に示す断面図である。
【図２９】第二発明の第三実施例における製造工程の一段階を概略的に示す断面図である。
【図３０】第二発明の第三実施例における製造工程の一段階を概略的に示す断面図である。
【図３１】従来の半導体パッケージの構成を概略的に示す断面図である。
【図３２】（Ａ）及び（Ｂ）は従来の半導体パッケージの製造工程における異なる一段階を概略的に示す断面図である。
【図３３】従来の半導体パッケージの製造工程における一段階を概略的に示す断面図である。
【符号の説明】
２０：接続導体
２２：半導体チップ
２２ａ：集積回路部
２８：封止材
３４、３７、４４、４８：半導体パッケージ
３８：補助導体[0001]
[Industrial applications]
The present invention relates to a semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, packages having various structures have been proposed as packages (semiconductor packages) on which semiconductor chips are mounted. FIG. 31 is a sectional view schematically showing a structure of a conventional semiconductor package. As an example, the structure of a resin-molded semiconductor package using a lead frame is shown in FIG.
[0003]
The semiconductor package shown in FIG. 31 is formed by sealing a semiconductor chip 12 mounted on a lead frame 10 with a sealing resin 14.
[0004]
The lead frame 10 has a die pad portion 10a and a lead portion 10b. The semiconductor chip 12 is fixed to the die pad portion 10a via the conductor 16. A predetermined number of leads 10b are arranged around the die pad 10a, and the leads 10b and the semiconductor chip 12 are electrically connected via the bonding wires 18. Then, the die pad portion 10a, a part of the lead portion 10b near the die pad portion 10a, the semiconductor chip 12, and the bonding wires 18 are covered with the sealing resin 14.
[0005]
An internal lead terminal for electrically connecting the lead portion 10b to the semiconductor chip 12 is provided at a portion of the lead portion 10b to be sealed with the sealing resin. An external lead terminal for electrically connecting the lead portion 12 to a wiring board (not shown) is provided in a portion of the lead portion 10b which is not sealed with the sealing resin 14.
[0006]
Next, a method of manufacturing the above-described conventional package will be described. 32 and 33 are cross-sectional views schematically showing manufacturing steps of the conventional package shown in FIG.
[0007]
First, the semiconductor chip 12 is fixed face up to the die pad portion 10a via the conductor 16 (FIG. 32A). Next, a circuit element (not shown) already formed on the semiconductor chip 12 is electrically connected to the lead portion 10b via the bonding wire 18 (FIG. 32B). Next, the die pad portion 10a, a part of the lead portion 10b near the die pad portion 10a, the semiconductor chip 12, and the bonding wires 18 are sealed with the sealing resin 14 (FIG. 33). Next, as shown in FIG. 31, a portion of the lead portion 10b that is not sealed with the sealing resin 14 is bent to complete a semiconductor package.
[0008]
[Problems to be solved by the invention]
However, the conventional package described above has a structure in which a semiconductor chip is connected to a wiring board via bonding wires and leads, and thus there is a limit to reducing the external size (package size) of the semiconductor package.
[0009]
In recent years, the degree of integration of electric circuit elements formed per semiconductor chip tends to increase, and as a result, the outer size (chip size) of the semiconductor chip is becoming larger. On the other hand, in order to increase the mounting density on the wiring board, it is necessary to reduce the package size. Therefore, in order to reduce the package size as the chip size increases, it is desirable to reduce the length of the bonding wires or to reduce the height of the bonding wires protruding from the semiconductor package. However, if the length is too short or the height is too low, the semiconductor chip and the lead portion cannot be electrically connected with the bonding wires, so that the package size cannot always be reduced to a sufficiently satisfactory level.
[0010]
An object of the present invention is to solve the above-mentioned conventional problems and to provide a semiconductor device that can be reduced in size and a method of manufacturing a semiconductor device suitable for manufacturing the semiconductor device.
[0011]
[Means for Solving the Problems]
In order to achieve this object, according to the invention of a method for manufacturing a semiconductor device according to the present application, a projecting electrode having one end connected to an integrated circuit is formed on a first main surface of a semiconductor chip on which the integrated circuit is formed. Forming a first part of a mold having a recess in a semiconductor chip Concave Inside the department With the first main surface up The process of placing and the semiconductor chip First lord A step of disposing a solidified thermoplastic resin on the surface; ,heat Heating the plastic resin to a temperature that indicates plasticity; and a first part of the mold. And the second The semiconductor chip is pressed by pressing the fluidized thermoplastic resin with the second part of the mold opposite to the first part. Electrode formed on the first main surface of the semiconductor device Covering with a thermoplastic resin.
[0012]
Further, according to the manufacturing method of the present invention, the first portion of the mold having the concave portion is formed by solidifying the thermoplastic resin. Concave Disposing a semiconductor chip having an integrated circuit on a surface of a thermoplastic resin and having a protruding electrode having one end connected to the integrated circuit formed on a first main surface. With the first main surface up Placement process and solidified State of A step of heating the thermoplastic resin to a temperature showing plasticity, and pressing the fluidized thermoplastic resin by the first portion of the mold and the second portion of the mold opposite to the first portion to press the semiconductor chip. The second main surface facing the first main surface of Covering with a thermoplastic resin. In the following, the invention relating to the semiconductor device itself of the present invention may be referred to as a first invention, and the invention relating to these manufacturing methods may be collectively referred to as a second invention.
[0013]
According to the method of manufacturing a semiconductor device of the present invention, a step of arranging a semiconductor substrate having a projection electrode formed on a surface thereof in the concave portion of the first mold having the concave portion; Disposing a thermoplastic resin on the surface of the semiconductor substrate, heating the thermoplastic resin to a temperature at which the thermoplastic resin is fluidized, and using a first mold and a second mold opposed to the first mold. Pressing the thermoplastic resin to cover the semiconductor substrate with the fluidized resin.
[0014]
In this application, the external terminal is a conductor for assisting the electrical connection between the protruding electrode and the outside, and means a conductor formed at the second end of the protruding electrode. Therefore, hereinafter, the external terminal may be referred to as an auxiliary conductor.
[0015]
Further, in carrying out the first invention or the second invention, it is preferable to seal the second main surface of the semiconductor chip with a ceramic plate.
[0016]
Further, in the implementation of the first invention or the second invention, it is preferable that the sealing material for sealing the integrated circuit portion includes one of a thermosetting resin and a thermoplastic resin. Further, the second invention is one of the methods suitable for manufacturing the semiconductor device of the first invention, and thus the first invention is not limited to the method manufactured by the second invention.
[0017]
[Action]
According to the first aspect, since the protruding electrodes are formed so as to protrude from the integrated circuit portion, the length and width of the semiconductor device viewed from the protruding direction of the protruding electrodes can be reduced to about the same as the semiconductor chip. Further, the height of the semiconductor device in the projecting direction of the projecting electrode can be reduced by reducing the projecting height of the projecting electrode. In particular, according to the first aspect of the invention having an external terminal, by providing the external terminal, when the semiconductor device is mounted on a wiring board or the like, the semiconductor device and the wiring board can be electrically reliably connected. Can be connected. According to the first aspect of the present invention in which the thickness of the sealing material is considered, the thickness of the sealing material is substantially equal to the distance between the first end and the second end. The projecting electrode can be protected by the sealing material.
[0018]
Further, since at least the integrated circuit portion is sealed, it is possible to prevent the integrated circuit portion from being damaged when storing, transporting or mounting the semiconductor device.
[0019]
Further, according to the second invention, it is possible to provide a small-sized semiconductor device which is convenient for storage, transportation and mounting. Further, according to the preferred embodiment of the second invention, when at least the projecting electrode and the integrated circuit portion are covered with the sealing material and then the sealing material is shaved and exposed, the sealing of the integrated circuit portion and the exposure of the projecting electrode are performed. It can be done simply.
[0020]
【Example】
Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that the drawings are only schematically shown to the extent that the present invention can be understood, and thus the present invention is not limited to the illustrated examples.
[0021]
FIG. 1 is a sectional view schematically showing the configuration of the first embodiment of the first invention. The semiconductor device (referred to as a semiconductor package in this embodiment) 34 of this embodiment includes a semiconductor chip 22, a connection conductor (projection electrode) 20 protruding from an integrated circuit portion 22 a of the semiconductor chip 22, and a connection conductor 20. And a sealing material 28 for exposing the protruding end portion (second end portion) of the integrated circuit portion 22a by exposing the same. As shown in FIG. 1, the connection conductor 20 has a first end and a second end at both ends, the first end being connected to the integrated circuit and the second end being sealed. It is provided so as to be exposed from the material 28. The main surface of the semiconductor chip 22 on which the integrated circuit is provided is referred to as a first main surface, and the main surface opposite to the first main surface on which the integrated circuit is not provided is referred to as a second main surface. The other surface of the semiconductor chip 22 is referred to as a side surface. This integrated circuit is equivalent to the above-described integrated circuit section 22a.
[0022]
Although not shown, the integrated circuit portion 22a has an electric circuit element such as a transistor, a capacitor, and a wiring, and the connection conductor 20 is provided at a terminal portion of a desired electric circuit element. The sealing material 28 covers the integrated circuit portion 22a of the semiconductor chip 22 and does not cover other portions of the semiconductor chip 22. That is, the side surface and the second main surface of the semiconductor chip 22 are exposed. The heights at which the connection conductor 20 and the sealing material 28 protrude from the integrated circuit portion 22a are made substantially equal. That is, the surface of the sealing material 28 is formed on substantially the same plane as the second end of the connection conductor 20.
[0023]
A comparison between the semiconductor package 34 of the first embodiment of the first invention and a semiconductor package using a conventional lead frame (see FIG. 33) shows that in this embodiment, since the lead frame and the bonding wires are not used, the lead frame thickness is reduced. 0.2 mm and a protruding height of about 0.2 mm at the time of connection of the bonding wire are not required, so that the thickness of the semiconductor package 34 can be made smaller than before. In contrast to the conventional package having a thickness of, for example, about 1.0 mm, the package of this embodiment has a total thickness of, for example, about 0.35 mm for the semiconductor chip 22 and about 0.02 mm for the sealing material 28. It can be about 0.4 mm. Further, in this embodiment, since a lead frame is not used, an external lead terminal portion is not required, so that the width of the semiconductor package 34 can be made narrower than before.
[0024]
2 to 11 are manufacturing process diagrams for explaining the first embodiment of the second invention. This embodiment is an example of manufacturing the semiconductor package 34 shown in FIG.
[0025]
First, the connection conductor 20 is formed at a desired terminal portion of the integrated circuit portion 22a by protruding from the integrated circuit portion 22a of the semiconductor chip 22 (FIG. 2). In this embodiment, as a material for forming the connection conductor 20, solder, gold or another conductive material, preferably a conductive material capable of brazing is used. Any suitable technique can be used for forming the connection conductor 20, for example, using a thick-film printing technique. Alternatively, it is formed using a combination of photolithography and etching techniques and vapor deposition and other thin film forming techniques. Alternatively, it is formed using a combination of a photolithography and etching technique and an electroless plating technique. Alternatively, the connection conductor 20 may be formed by crimping the spherical or hemispherical connection conductor 20 to the terminal portion of the integrated circuit portion 22a. The connection conductors 20 may be formed in a wafer state before separating the individual semiconductor chips 22 from the semiconductor wafer, and then separated into individual semiconductor chips 22 or in a state where the semiconductor chips 22 are separated from the semiconductor wafer. May be performed.
[0026]
Next, the connection conductor 20 and the integrated circuit portion 22a are covered with a sealing material 28 (FIGS. 3 to 7). In this embodiment, the sealing material 28 is a thermosetting resin, and the first portion 24 of the mold (hereinafter simply referred to as the mold 24) and the second portion of the mold (hereinafter simply referred to as the mold 26). And is covered with a sealing material 28 by a molding technique. The mold 24 has a concave portion 24 a for receiving the semiconductor chip 22. The depth H of the concave portion 24a is longer than the height h from the lower surface of the concave portion 24a to the protruding end of the connection conductor 20 when the semiconductor chip 22 is placed in the concave portion 24a (see FIG. 4). With the semiconductor chip 22 placed in the concave portion 24a, the semiconductor chip is supported on the side wall surface of the concave portion 24a so that the semiconductor chip 22 is not substantially displaced. The recess 24a is formed so that the work of taking out can be performed freely. The mold 26 has a sealing material channel 26a and a lid portion 26b that closes the concave portion 24a so as to be openable and closable (see FIG. 5). Then, a gas flow path (not shown) for extracting gas in the concave portion 24a to the outside of the concave portion 24a when the concave portion 24a is closed is provided in the molds 24 and / or 26, as is generally performed by a molding technique. The forming material of the dies 24 and 26 is, for example, metal, that is, the dies 24 and 26 can be used.
[0027]
Before covering with the sealing material 28, first, the molds 24 and 26 are heated in advance to a temperature at which the sealing material 28 easily flows. Then, the semiconductor chip 22 is inserted into the concave portion 24a of the mold 24 so that the integrated circuit portion 22a faces the outside of the concave portion 24a (FIGS. 3 and 4). Next, the concave portion 24a is closed by the lid portion 26b of the mold 26 (FIG. 5). With the concave portion 24a closed, the lid portion 26b is separated from the connection conductor 20. The distance between the lid portion 26b and the integrated circuit portion 22a is, for example, 50 μm. Next, the sealing material 28 having fluidity and not being cured is injected into the recess 24a through the sealing material channel 26a, and the sealing material 28 is placed in a space surrounded by the recess 24a and the lid portion 26b. After filling, the connection conductor 20 and the integrated circuit portion 22a are embedded in the sealing material 28 (FIGS. 5 to 6). Preferably, air bubbles are not left between the connection conductor 20 and the integrated circuit portion 22a, particularly between the integrated circuit portion 22a and the sealing material. Next, the sealing material 28 is heated and cured, and then the semiconductor chip 22 is removed from the molds 24 and 26 to obtain the semiconductor chip 22 in which the connection conductor 20 and the integrated circuit portion 22a are embedded in the sealing material 28 (FIG. 7). When the sealing material 28 is cured, for example, the mold 24 is heated to a temperature at which the sealing material 28 is cured, and the mold 26 is heated to a temperature at which the sealing material 28 is not cured. It is preferable to reduce the temperature difference so as to reduce the thermal stress of the sealing material 28. In addition, in order to make it easy to remove the semiconductor chip 22 from the mold 24, for example, a push rod p (this rod p is indicated by a dashed line in FIG. 3B) is raised from the bottom of the concave portion 24a to the height of the concave portion 24a. It is preferable that the push rod p is slidably provided on the mold 24 so that the height projecting in the height direction q can be adjusted, and the semiconductor chip 22 is protruded from the recess 24a by the push rod p and removed. Alternatively, a portion r that forms the bottom of the mold 24 (this portion r is indicated by a dotted line in FIG. 3B) may be configured so that the height of the concave portion 24a can be freely adjusted.
[0028]
Next, the sealing material 28 covering the connection conductor 20 and the integrated circuit portion 22a is ground using a polishing, grinding, cutting, or any other suitable shaving device to expose the protruding end of the connection conductor 20 (FIG. 8 to FIG. 11). The shaving device used in this embodiment includes a fixing portion 30 (see FIG. 8) and a shaving portion 32. The fixing portion 30 has a positioning portion 30a for positioning and fixing the semiconductor chip 22, and the shaving portion 32 has a shaving surface 32a for shaving the semiconductor chip 22. For example, the positioning portion 30a is a concave portion, and is positioned by fitting the semiconductor chip 22 into the positioning portion 30a. For example, abrasives, abrasive grains, or cutting blades are provided on the shaving surface 32a.
[0029]
In exposing the connection conductor 20, first, the part of the semiconductor chip 22 opposite to the connection conductor 20 is attached to the fixing part 30, and the semiconductor chip 22 is positioned and fixed to the fixing part 30 (FIGS. 8 to 9). ). Next, the sealing material 28 on the connection conductor 20 is brought into contact with the shaved surface 32a of the shaved portion 32 (FIG. 10). Next, the sealing material 28 and the shaved surface 32a are relatively moved while the sealing material 28 is pressed against the shaved surface 32a, and the sealing material 28 is moved until the protruding end of the connection conductor 20 contacts the shaved surface 32a. Then, the projecting end of the connection conductor 20 is exposed from the sealing material 28 (FIG. 11).
[0030]
Next, the semiconductor chip 22 is removed from the fixing part 30, and a semiconductor package 34 in which the integrated circuit part 22a is sealed with the sealing material 28 is obtained (FIG. 1). In order to facilitate removal of the semiconductor chip 2 from the fixing part 30, a push rod p or a part r similar to the mold 24 may be provided on the fixing part 30.
[0031]
Comparing the manufacturing method of the first embodiment of the second invention with the conventional method of manufacturing a semiconductor package using a lead frame, this embodiment does not use a bonding wire and a lead frame. Since a plating step is not required, the TAT (Turn Around Time) can be significantly reduced as compared with the related art, and the investment in manufacturing equipment can be reduced. Further, in this embodiment, since the process is simpler than in the related art, the number of check items for detecting a defective product can be reduced as compared with the related art.
[0032]
FIG. 12 is a sectional view schematically showing a mounting state of a semiconductor chip. The wiring board 36 shown in the figure includes a substrate 36a, a wiring pattern 36b provided on the substrate 36a, and a connection conductor 36c provided at a terminal portion of the wiring pattern 36b. The material for forming the connection conductor 36 is solder, gold, a conductive adhesive or another conductive material, preferably a conductive material that can be brazed. At least one of the connection conductor 20 of the semiconductor package 34 and the connection conductor 36c of the wiring board 36 is made of a conductive material that can be brazed.
[0033]
In mounting the semiconductor package 34 manufactured as described above on the wiring board 36, the connection conductor 20 of the semiconductor package 34 and the connection conductor 36c of the wiring board 36 are aligned, and the connection conductor 20 is connected to the connection conductor 36c. On top. Next, the connection conductors 20 and / or 36c are heated and melted, and then cooled and solidified to electrically connect the integrated circuit portion 22a and the wiring pattern 36b via the connection conductors 20 and 36c.
[0034]
When the connection conductor 20 of the semiconductor package 34 is made of a conductive material that can be brazed, the connection conductor 36c of the wiring board 36 may not necessarily be provided.
[0035]
FIG. 13 is a diagram for explaining a modification of the first embodiment of the first and second inventions.
[0036]
As shown in FIG. 13, a semiconductor package 37 of this modification is configured by providing an auxiliary conductor 38 to the semiconductor package 34 of the first embodiment. The auxiliary conductor 38 is provided so as to protrude on the connection conductor 20 and on the sealing material 28 near the conductor 20. The auxiliary conductor 38 is formed on the exposed second end of the connection conductor 20, and is therefore electrically connected to the second end. The auxiliary conductor 38 is formed wider than the connection conductor 20 when viewed from the projecting direction of the connection conductor 20. As shown in FIG. 13, the auxiliary conductor 38 is provided such that the connection conductor 20 has a maximum width that is wider than the maximum width of the connection conductor 20 when viewed from the direction in which the connection conductor 20 protrudes.
[0037]
Further, a modified example of the second invention is an example of manufacturing a semiconductor package 37. In this example, first, the semiconductor package 34 is completed through the same steps as those of the above-described first embodiment (FIGS. 2 to 11 and FIG. (Fig. 1).
[0038]
Next, the auxiliary conductor 38 is formed on the connection conductor 20 and on the sealing material 28 near the conductor 20 so as to be wider than the connection conductor 20 when viewed from the projecting direction of the connection conductor 20. A package 37 is obtained (FIG. 13).
[0039]
The material for forming the auxiliary conductor 38 is solder, gold, or another conductive material, preferably a brazing conductive material. The auxiliary conductor 38 can be formed by any suitable technique, for example, by using a thick-film printing technique. Alternatively, it is formed using a combination of photolithography and etching techniques and vapor deposition and other thin film forming techniques. Alternatively, it is formed using a combination of a photolithography and etching technique and an electroless plating technique. Alternatively, a spherical or hemispherical auxiliary conductor 38 is formed by crimping on the connection conductor 20. In the modification of the first embodiment of the second invention, the same effect as that of the first embodiment of the second invention can be obtained.
[0040]
FIG. 14 is a sectional view schematically showing the configuration of the second embodiment of the first invention. The components corresponding to the components of the above-described first embodiment are denoted by the same reference numerals, and detailed descriptions of the same points as those of the first embodiment will be omitted.
[0041]
The semiconductor package 44 of this embodiment includes a semiconductor chip 22, connection conductors 20, and sealing materials 28 and 40. In this embodiment, the entirety of the semiconductor chip 22 provided with the connection conductor 20 is covered with sealing materials 28 and 40. The sealing material 40, for example, a ceramic plate covers the part of the semiconductor chip 22 on the side opposite to the integrated circuit portion 22a, and the remaining semiconductor chip while exposing the connection conductor 20 with the sealing material 28, for example, a thermosetting resin. Cover 22 parts.
[0042]
Also in the second embodiment of the first invention, the thickness of the semiconductor package 44 can be thicker than the first embodiment but smaller than the conventional package. Further, the width of the semiconductor package 44 can be made smaller than that of the conventional package.
[0043]
15 to 21 are manufacturing process diagrams for explaining a second embodiment of the present invention. This embodiment is an example of manufacturing a semiconductor package 44. The components corresponding to the components of the first embodiment are denoted by the same reference numerals, and detailed description of the same points as those of the first embodiment will be omitted.
[0044]
First, the connection conductor 20 is formed on the integrated circuit portion 22a by protruding from the integrated circuit portion 22a of the semiconductor chip 22.
[0045]
Next, the entire semiconductor chip 22 provided with the connection conductors 20 is covered with sealing materials 28 and 40 (FIGS. 15 to 19). In this embodiment, a gap t is formed between the side wall of the semiconductor chip 22 and the side wall of the concave portion 24a in the state where the semiconductor chip 22 is placed in the concave portion 24a of the mold 24 to flow the sealing material over the entire periphery of the side wall. The recess 24a is formed wider than the semiconductor chip 22 so that it can be formed (see FIG. 16).
[0046]
When covering with the sealing materials 28 and 40, first, a plate-shaped sealing material 40, for example, a ceramic plate is fixed to the portion of the semiconductor chip 22 opposite to the integrated circuit portion 22a via an adhesive 42 (FIG. 15). Then, the molds 24 and 26 are heated in advance to a temperature at which the sealing material 28 easily flows. Next, the semiconductor chip 22 is placed in the concave portion 24a, and the semiconductor chip 22 is positioned using any suitable means so that a gap t is formed between the side walls of the semiconductor chip 22 and the concave portion 24a over the entire periphery of these side walls ( (FIG. 16). Next, the concave portion 24a is closed by the lid portion 26b of the mold 26 (FIG. 17). Next, the sealing material 28 in a fluid and uncured state is injected into the recess 24 a through the sealing material flow path 26 a of the mold 26, and the connection conductor 20, the integrated circuit portion 22 a, and the semiconductor chip 22 are removed. The side walls are embedded in the sealing material 28 (FIG. 18). Preferably, air bubbles are not left between the connection conductor 20 and the integrated circuit portion 22a, particularly between the integrated circuit portion 22a and the sealing material. Next, the sealing material 28 is heated and cured, and then the semiconductor chip 22 is removed from the molds 24 and 26 (FIG. 19). When the sealing material 28 is cured, for example, the mold 24 is heated to a temperature at which the sealing material 28 is cured, and the mold 26 is heated to a temperature at which the sealing material 28 is not cured. It is preferable to reduce the difference in the thermal stress of the sealing material 28 by reducing the difference.
[0047]
Next, as shown in FIGS. 20 to 21, the sealing material 28 is shaved to expose the connection conductor 20 (FIGS. 20 to 21).
[0048]
In exposing the connection conductor 20, first, the portion of the semiconductor chip 22 opposite to the connection conductor 20 is attached to the fixing portion 30 via the sealing materials 28 and 40, and the sealing material 28 on the connection conductor 20 is formed. Is brought into contact with the shaved surface 32a of the shaved portion 32 (FIG. 20). Next, the sealing material 28 and the shaved surface 32a are relatively moved while the sealing material 28 is pressed against the shaved surface 32a, and the sealing material 28 is shaved until the connection conductor 20 is exposed (FIG. 21).
[0049]
Next, the semiconductor chip 22 is removed from the fixing portion 30, and a semiconductor package 44 in which the semiconductor chip 22 is sealed with sealing materials 28 and 40 is obtained (FIG. 14). In the second embodiment of the second invention, the same effect as in the first embodiment can be obtained.
[0050]
FIG. 22 is a sectional view schematically showing the configuration of the third embodiment of the first invention. The components corresponding to the components of the first embodiment are denoted by the same reference numerals, and detailed description of the same points as those of the first embodiment will be omitted.
[0051]
The semiconductor package 48 of this embodiment includes the connection conductor 20, the semiconductor chip 22, and the sealing materials 46 and 47. In this embodiment, the whole of the semiconductor chip 22 provided with the connection conductor 20 is covered with sealing materials 46 and 47. The sealing material 46 covers the portion of the semiconductor chip 22 on the side opposite to the integrated circuit portion 22a with a thermoplastic resin, for example, and the sealing material 47 covers the remaining semiconductor chip 22 while exposing the connection conductor 20 with the thermoplastic resin. Cover.
[0052]
Also in the third embodiment of the first invention, the thickness of the semiconductor package 48 can be thicker than the first embodiment but smaller than the conventional package. Further, the width of the semiconductor package 48 can be made smaller than that of the conventional package.
[0053]
FIGS. 23 to 30 are manufacturing process diagrams for explaining the third embodiment of the second invention. This embodiment is an example of manufacturing the semiconductor package 48 shown in FIG. The components corresponding to the components of the first embodiment are denoted by the same reference numerals, and detailed description of the same points as those of the first embodiment will be omitted.
[0054]
First, the semiconductor chip 22 and the connection conductor 20 are formed in the same manner as in the first embodiment.
[0055]
Next, the entire semiconductor chip 22 provided with the connection conductor 20 is covered with sealing materials 46 and 47 (FIGS. 23 to 28).
[0056]
When covering with the sealing materials 46 and 47, first, the sealing material 46, for example, a thermoplastic resin is solidified and fitted into the concave portion 24a of the mold 24, and the sealing material 46 is supported and positioned by the concave portion 24a. (FIG. 23). The sealing material 46 is provided with a concave portion 46a at the center thereof in a solidified state, so that the height of the peripheral portion of the sealing material 46 is higher than the height of the center portion. Next, the portion of the semiconductor chip 22 opposite to the integrated circuit portion 22a is fitted into the concave portion 46a of the sealing material 46, and the peripheral portion of the sealing material 47 is inserted between the semiconductor chip 22 and the side wall of the concave portion 24a. The chip 22 is positioned and supported by the recess 46a (FIG. 24). Next, with the sealing material 47, for example, a thermoplastic resin solidified, it is fitted into the concave portion 24a of the mold 24 and mounted on the connecting conductor 20 of the semiconductor chip 22 (FIG. 25). The sealing material 47 is provided with a concave portion 47a at the center thereof in a solidified state, so that the height of the peripheral portion of the sealing material 46 is higher than the height of the center portion. The sealing material 47 is fitted into the concave portion 24a of the mold 24 so that the connection conductor 20 is inserted into the concave portion 47a, and the peripheral portion of the sealing material 47 is inserted between the semiconductor chip 22 and the side wall of the concave portion 24a. Next, the lid 26b of the mold 26 is slidably fitted into the recess 24a of the mold 24, and the lid 26b is brought into contact with the sealing material 47 (FIG. 26). Note that, in this example, the sealing material channel 26a is not provided in the mold 26. The seals 46, 47 are then pressed between the dies 24, 26 while heating through the dies 24, 26 to a temperature at which they exhibit plasticity, ie, fluidize, and the pressing causes , 47 are pressed against each other, and the entire semiconductor chip 22 provided with the connection conductor 20 is embedded in the sealing materials 46, 47. Preferably, air bubbles are not left between the connection conductor 20 and the integrated circuit portion 22a, particularly between the integrated circuit portion 22a and the sealing material 47. Next, the sealing members 46 and 47 are cooled and solidified through the molds 24 and 26 while the peripheral portions of the sealing members 46 and 47 are pressed against each other, whereby the peripheral portions of the sealing members 46 and 47 are bonded to each other ( (FIG. 27). Next, the semiconductor chip 22 is removed from the molds 24 and 26 to obtain the semiconductor chip 22 and the connection conductor 20 covered with the sealing materials 46 and 47 (FIG. 28).
[0057]
Next, the sealing material 47 covering the connection conductor 20 and the integrated circuit portion 22a is shaved to expose the connection conductor 20 (FIGS. 29 to 30).
[0058]
In exposing the connection conductor 20, first, the semiconductor chip 22 is mounted and fixed on the fixing portion 30, and then the sealing material 47 on the connection conductor 20 is brought into contact with the shaved surface 32 a of the shaved portion 32. (FIG. 29). Next, the sealing material 47 is shaved by the shaved surface 32a until the connection conductor 20 is exposed (FIG. 30).
[0059]
Next, the semiconductor chip 22 is removed from the fixing portion 30, and a semiconductor package 48 is obtained in which the entire semiconductor chip 22 provided with the connection conductors 20 is sealed with sealing materials 46 and 47 (FIG. 22). In the third embodiment of the second invention, the same effect as in the first embodiment can be obtained.
[0060]
The present invention is not limited only to the above-described embodiment, and accordingly, the shapes, arrangement positions, forming materials, numerical conditions, and others of the components can be arbitrarily and suitably changed.
[0061]
【The invention's effect】
As is apparent from the above description, according to the semiconductor device of the first invention, the protruding electrodes for connecting the semiconductor chip to another electric circuit are formed so as to protrude from the integrated circuit portion of the semiconductor chip. Therefore, the length and width of the semiconductor device viewed from the direction in which the protruding electrodes project can be reduced. Further, the height of the semiconductor device in the direction in which the protruding electrodes protrude can be reduced by reducing the protruding height of the protruding electrodes. Therefore, the size of the semiconductor device itself can be reduced as compared with a semiconductor device using a conventional lead frame. Further, since at least the integrated circuit portion is sealed, it is possible to prevent the integrated circuit portion from being damaged when the semiconductor device is stored, transported, or mounted. Compared with the conventionally known flip chip, the flip chip protects the integrated circuit portion with a protective film, but the protective film alone cannot always sufficiently protect the integrated circuit portion from moisture and impact, so the flip chip is If not sealed with a sealing material, care must be taken for storage, transportation, and mounting, which is inconvenient. On the other hand, since the semiconductor device of the present invention protects the integrated circuit portion from moisture and impact by the sealing material, it is convenient that the semiconductor device is hardly damaged when it is stored, transported or mounted.
[0062]
Therefore, according to the semiconductor device of the first invention, it is possible to provide a small-sized semiconductor device which is convenient for storage, transportation, and mounting.
[0063]
Further, according to the method of manufacturing a semiconductor device of the second invention, it is possible to provide a small-sized semiconductor device which is convenient for storage, transportation, and mounting. According to the preferred embodiment of the second invention, at least the protruding electrode and the integrated circuit portion are covered with the sealing material, and then the sealing material is shaved to expose the protruding electrode. Exposure can be performed simply, so that the semiconductor device of the first invention can be manufactured simply.
[Brief description of the drawings]
FIG. 1 is a sectional view schematically showing a configuration of a first embodiment of the first invention.
FIG. 2 is a sectional view schematically showing one stage of a manufacturing process in the first embodiment of the second invention.
FIGS. 3A and 3B are a top view and a sectional view schematically showing the same process steps of a manufacturing process in the first embodiment of the second invention.
FIGS. 4A and 4B are a top view and a sectional view schematically showing the same process steps of the manufacturing process in the first embodiment of the second invention.
FIGS. 5A and 5B are a top view and a cross-sectional view schematically showing the same process steps of a manufacturing process in the first embodiment of the second invention.
FIG. 6 is a sectional view schematically showing one stage of a manufacturing process in the first embodiment of the second invention.
FIG. 7 is a sectional view schematically showing one stage of a manufacturing process in the first embodiment of the second invention.
FIGS. 8A and 8B are a bottom view and a sectional view schematically showing the same process steps of the manufacturing process in the first embodiment of the second invention.
FIGS. 9A and 9B are a bottom view and a sectional view schematically showing the same process steps of the manufacturing process in the first embodiment of the second invention.
FIG. 10 is a sectional view schematically showing one stage of a manufacturing process in the first embodiment of the second invention.
FIG. 11 is a sectional view schematically showing one stage of a manufacturing process in the first embodiment of the second invention.
FIG. 12 is a sectional view schematically showing a mounting state of a semiconductor package.
FIGS. 13A and 13B are a top view and a sectional view schematically showing a configuration of a modification of the first embodiment of the first invention.
FIG. 14 is a sectional view schematically showing a configuration of a second embodiment of the first invention.
FIG. 15 is a sectional view schematically showing one stage of a manufacturing process in the second embodiment of the second invention.
FIGS. 16 (A) and (B) are a top view and a cross-sectional view schematically showing the same process step of the manufacturing process in the second embodiment of the second invention.
17A and 17B are a top view and a cross-sectional view schematically showing the same process steps of a manufacturing process in the second embodiment of the second invention.
FIG. 18 is a sectional view schematically showing one stage of a manufacturing process in the second embodiment of the second invention.
FIG. 19 is a cross-sectional view schematically showing one stage of a manufacturing process in the second embodiment of the second invention.
FIG. 20 is a cross-sectional view schematically showing one stage of a manufacturing process in the second embodiment of the second invention.
FIG. 21 is a cross sectional view schematically showing one stage of a manufacturing process in the second embodiment of the second invention.
FIG. 22 is a sectional view schematically showing a configuration of a third embodiment of the first invention.
FIGS. 23A and 23B are a top view and a cross-sectional view schematically showing the same process step of the manufacturing process in the third embodiment of the second invention.
FIGS. 24A and 24B are a top view and a cross-sectional view schematically showing the same process steps of a manufacturing process in a third embodiment of the second invention.
FIGS. 25A and 25B are a top view and a cross-sectional view schematically showing the same process step of the manufacturing process in the third embodiment of the second invention.
FIGS. 26A and 26B are cross-sectional views schematically showing one stage of the manufacturing process in the third embodiment of the second invention.
FIG. 27 is a cross sectional view schematically showing one stage of a manufacturing process in the third embodiment of the second invention.
FIG. 28 is a cross sectional view schematically showing one step of a manufacturing process in the third embodiment of the second invention.
FIG. 29 is a cross sectional view schematically showing one stage of a manufacturing process in the third embodiment of the second invention.
FIG. 30 is a sectional view schematically showing one stage of a manufacturing process in a third embodiment of the second invention.
FIG. 31 is a cross-sectional view schematically showing a configuration of a conventional semiconductor package.
FIGS. 32A and 32B are cross-sectional views schematically showing different stages in a conventional semiconductor package manufacturing process.
FIG. 33 is a cross-sectional view schematically showing one stage in a conventional semiconductor package manufacturing process.
[Explanation of symbols]
20: Connection conductor
22: Semiconductor chip
22a: integrated circuit section
28: Sealant
34, 37, 44, 48: Semiconductor package
38: Auxiliary conductor

Claims (6)

集積回路が形成された半導体チップの第１主表面上に、前記集積回路に一端が接続された突起電極を形成する工程と、
前記半導体チップを凹部を有する型の第１の部分の当該凹部内に前記第１主表面を上側にして配置する工程と、
前記半導体チップの前記第１主表面上に、固化させた状態の熱可塑性樹脂を配置する工程と、
前記熱可塑性樹脂を可塑性を示す温度に加熱する工程と、
前記型の第１の部分と該第１の部分に対向する型の第２の部分とにより、流動化した熱可塑性樹脂を押圧して前記半導体チップの前記第１主表面に形成されている前記突起電極を熱可塑性樹脂で覆う工程とを含むこと
を特徴とする半導体装置の製造方法。Forming a protruding electrode having one end connected to the integrated circuit on a first main surface of the semiconductor chip on which the integrated circuit is formed;
Arranging the semiconductor chip in the concave portion of the first portion of the mold having the concave portion with the first main surface facing upward ;
Disposing a solidified thermoplastic resin on the first main surface of the semiconductor chip;
Heating the thermoplastic resin to a temperature showing plasticity,
The first part of the mold and the second part of the mold facing the first part press the fluidized thermoplastic resin to form the semiconductor chip on the first main surface of the semiconductor chip . Covering the protruding electrode with a thermoplastic resin. 固化させた状態の熱可塑性樹脂を凹部を有する型の第１の部分の当該凹部内に配置する工程と、
前記熱可塑性樹脂の表面上に、集積回路を具え、当該集積回路に一端が接続された突起電極が第１主表面上に形成されている半導体チップを前記第１主表面を上側にして配置する工程と、
前記固化させた状態の熱可塑性樹脂を可塑性を示す温度に加熱する工程と、
前記型の第１の部分と該第１の部分に対向する型の第２の部分とにより、流動化した熱可塑性樹脂を押圧して前記半導体チップの前記第１主表面に対向する第２主表面を熱可塑性樹脂で覆う工程とを含むこと
を特徴とする半導体装置の製造方法。Disposing a thermoplastic resin in a state in which is solid-reduction in the concave portion of the first portion of the mold having a concave portion,
A semiconductor chip having an integrated circuit on the surface of the thermoplastic resin and having a protruding electrode having one end connected to the integrated circuit formed on the first main surface is disposed with the first main surface facing upward. Process and
Heating the thermoplastic resin in a state of being the solidifying temperature indicating plasticity,
The first part of the mold and the second part of the mold facing the first part press the fluidized thermoplastic resin to form a second main part facing the first main surface of the semiconductor chip. Covering the surface with a thermoplastic resin. 前記固化させた状態の熱可塑性樹脂の表面上に、集積回路を具え、当該集積回路に一端が接続された突起電極が第１主表面上に形成されている半導体チップを配置する工程の後に、
さらに前記半導体チップ表面上に固化させた状態の熱可塑性樹脂を配置する工程を含むこと
を特徴とする請求項２に記載の半導体装置の製造方法。After the step of arranging a semiconductor chip having an integrated circuit on the surface of the solidified thermoplastic resin and having a protruding electrode having one end connected to the integrated circuit formed on the first main surface,
3. The method according to claim 2, further comprising the step of arranging a solidified thermoplastic resin on the surface of the semiconductor chip. 前記突起電極の他端を覆うように前記半導体チップを封止材により封止した後に、当該封止材を前記突起電極の他端が露出するまで研磨する工程を含むこと
を特徴とする請求項１〜３のいずれか一項に記載の半導体装置の製造方法。After sealing the semiconductor chip with a sealing material so as to cover the other end of the projecting electrode, a step of polishing the sealing material until the other end of the projecting electrode is exposed is included. The method of manufacturing a semiconductor device according to any one of claims 1 to 3. 凹部を有する第１の型の当該凹部内に、表面に突起電極が形成された半導体基板を配置する工程と、
前記第１の型内に配置された半導体基板の前記表面上に熱可塑性樹脂を配置する工程と、
前記熱可塑性樹脂が流動化する温度に加熱する工程と、
前記第１の型と当該第１の型に対向する第２の型とで前記熱可塑性樹脂を押圧することで、前記半導体基板を流動化した前記樹脂にて覆う工程とを含むこと
を特徴とする半導体装置の製造方法。Arranging a semiconductor substrate having a projecting electrode formed on the surface thereof in the concave portion of the first type having the concave portion;
Disposing a thermoplastic resin on the surface of the semiconductor substrate disposed in the first mold;
Heating to a temperature at which the thermoplastic resin is fluidized,
Pressing the thermoplastic resin with the first mold and a second mold facing the first mold to cover the semiconductor substrate with the fluidized resin. Semiconductor device manufacturing method. 前記半導体基板の表面を樹脂で覆う工程の後、前記樹脂の表面を研磨する工程を含むこと
を特徴とする請求項５に記載の半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 5, further comprising: after the step of covering the surface of the semiconductor substrate with a resin, polishing the surface of the resin.
JP2001211950A 2001-07-12 2001-07-12 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3583086B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001211950A JP3583086B2 (en) 2001-07-12 2001-07-12 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001211950A JP3583086B2 (en) 2001-07-12 2001-07-12 Semiconductor device and manufacturing method thereof

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP19111692A Division JP3233990B2 (en) 1992-07-17 1992-07-17 Semiconductor device and manufacturing method thereof

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2004179320A Division JP2004260222A (en) 2004-06-17 2004-06-17 Semiconductor device and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JP2002083833A JP2002083833A (en) 2002-03-22
JP3583086B2 true JP3583086B2 (en) 2004-10-27

Family

ID=19047188

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001211950A Expired - Fee Related JP3583086B2 (en) 2001-07-12 2001-07-12 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3583086B2 (en)

Also Published As

Publication number Publication date
JP2002083833A (en) 2002-03-22

Similar Documents

Publication Publication Date Title
US6410979B2 (en) Ball-grid-array semiconductor device with protruding terminals
US6983537B2 (en) Method of making a plastic package with an air cavity
JP3362530B2 (en) Resin-sealed semiconductor device and method of manufacturing the same
US6008074A (en) Method of forming a synchronous-link dynamic random access memory edge-mounted device
JP3155741B2 (en) Semiconductor package with CSP BGA structure
TWI316740B (en) Package having exposed integrated circuit device
TWI540315B (en) Pressure sensor and method of assembling same
US6918178B2 (en) Method of attaching a heat sink to an IC package
US5834835A (en) Semiconductor device having an improved structure for storing a semiconductor chip
JPH08255860A (en) Lead frame, and method for forming lead frame
JPH05226564A (en) Semiconductor device
US5963796A (en) Fabrication method for semiconductor package substrate and semiconductor package
JP3514101B2 (en) Semiconductor device, method of manufacturing the same, and electronic equipment
JP2003170465A (en) Method for manufacturing semiconductor package and sealing mold therefor
JP3583086B2 (en) Semiconductor device and manufacturing method thereof
JP2005191147A (en) Method for manufacturing hybrid integrated circuit device
JPH0473297B2 (en)
JP3233990B2 (en) Semiconductor device and manufacturing method thereof
JP2004260222A (en) Semiconductor device and method of manufacturing the same
JP2002270627A (en) Semiconductor device manufacturing method
JP5308107B2 (en) Circuit device manufacturing method
EP0430204B1 (en) Plastic mould type semiconductor device
EP0999586A2 (en) Semiconductor device and method of producing same
KR100262811B1 (en) A plastic package having air cavity and method for manufacturing it
JP3495566B2 (en) Semiconductor device

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040420

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040617

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20040727

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20040727

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070806

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080806

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080806

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090806

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090806

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100806

Year of fee payment: 6

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100806

Year of fee payment: 6

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100806

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110806

Year of fee payment: 7

LAPS Cancellation because of no payment of annual fees