JP2002083833A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small-sized semiconductor device obtained by simple manufacturing; and its manufacturing method. SOLUTION: A connection semiconductor 20 is formed in an integrated circuit part 22a of a semiconductor chip 22 so as to project, and next the connection semiconductor 20 and the integrated circuit 22a are buried in a resin 28. After that, the resin 28 is polished, and the connection semiconductor 20 is exposed from the resin.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Hitherto, packages having various structures have been proposed as packages (semiconductor packages) on which semiconductor chips are mounted. FIG. 31 is a sectional view schematically showing a structure of a conventional semiconductor package. As an example, the structure of a resin-molded semiconductor package using a lead frame is shown in FIG.

[0003] A semiconductor package shown in FIG.
4 sealed.

The lead frame 10 has a die pad portion 10a.
And a lead portion 10b. The semiconductor chip 12 is fixed to the die pad 10a via the conductor 16. A predetermined number of leads 10b are arranged around the die pad 10a, and the leads 10b and the semiconductor chip 12 are electrically connected via the bonding wires 18. Then, the die pad portion 10a, a part of the lead portion 10b near the die pad portion 10a, the semiconductor chip 12, and the bonding wire 18 are covered with the sealing resin 14.

An internal lead terminal for electrically connecting the lead portion 10b to the semiconductor chip 12 is provided at a portion of the lead portion 10b which is sealed with the sealing resin 14. Also, the lead portion 12
Is provided in a portion of the lead portion 10b which is not sealed with the sealing resin 14 for electrical connection to a wiring board (not shown).

Next, a method of manufacturing the above-mentioned conventional package will be described. 32 and 33 are cross-sectional views schematically showing manufacturing steps of the conventional package shown in FIG.

First, the semiconductor chip 12 is fixed face up to the die pad portion 10a via the conductor 16 (FIG. 32A). Next, a circuit element (not shown) already formed on the semiconductor chip 12 is connected to the bonding wire 1.
32 and is electrically connected to the lead 10b (FIG. 32).
(B)). Next, the die pad portion 10a, a part of the lead portion 10b near the die pad portion 10a, the semiconductor chip 12, and the bonding wires 18 are sealed with the sealing resin 14 (FIG. 33).
Next, as shown in FIG. 31, a portion of the lead portion 10b that is not sealed with the sealing resin 14 is bent to complete a semiconductor package.

[0008]

However, the conventional package described above has a structure in which the semiconductor chip is connected to the wiring board via bonding wires and lead portions, so that the external size (package size) of the semiconductor package is reduced. There are limitations.

In recent years, the degree of integration of electric circuit elements formed per semiconductor chip tends to increase, and as a result, the outer size (chip size) of the semiconductor chip is becoming larger. On the other hand, in order to increase the mounting density on the wiring board, it is necessary to reduce the package size. Therefore, in order to reduce the package size as the chip size increases, it is desirable to reduce the length of the bonding wires or to reduce the height of the bonding wires protruding from the semiconductor package. However, if the length is too short or the height is too low, the semiconductor chip and the lead cannot be electrically connected with the bonding wires, so that the package size cannot always be reduced to a sufficiently satisfactory level.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a semiconductor device which can be reduced in size and a method of manufacturing a semiconductor device suitable for manufacturing the same.

[0011]

According to the invention of a method of manufacturing a semiconductor device according to the present invention, an integrated circuit is provided on a first main surface of a semiconductor chip on which an integrated circuit is formed. Forming a protruding electrode having one end connected to the semiconductor chip, arranging the semiconductor chip in the concave portion of the first portion of the mold having the concave portion,
Arranging the solidified thermoplastic resin, heating the solidified thermoplastic resin to a temperature indicating plasticity, forming a first part of the mold and a second part of the mold facing the first part.
And pressing the fluidized thermoplastic resin to cover the semiconductor chip with the thermoplastic resin.

According to the manufacturing method of the present invention, the step of arranging the solidified thermoplastic resin in the concave portion of the first portion of the mold having the concave portion includes the steps of: A step of disposing a semiconductor chip having an integrated circuit and a protruding electrode having one end connected to the integrated circuit formed on the first main surface; and a step of heating the solidified thermoplastic resin to a temperature indicating plasticity. , A first part of the mold and this first part
And pressing the fluidized thermoplastic resin with the second portion of the mold facing the portion to cover the semiconductor chip with the thermoplastic resin. In the following, the invention relating to the semiconductor device itself of the present invention may be referred to as a first invention, and the invention relating to these manufacturing methods may be collectively referred to as a second invention.

According to the method of manufacturing a semiconductor device of the present invention, a step of arranging a semiconductor substrate having a projection electrode formed on the surface thereof in the first mold having a recess, Disposing a thermoplastic resin on the surface of a semiconductor substrate disposed therein; heating the thermoplastic resin to a temperature at which the thermoplastic resin fluidizes; a first mold and a second mold facing the first mold. Pressing the thermoplastic resin with the mold to cover the semiconductor substrate with the fluidized resin.

In this application, the external terminal is a conductor for assisting the electrical connection between the protruding electrode and the outside.
It means a conductor formed at the second end of the protruding electrode. Therefore, in the following, the external terminal may be referred to as an auxiliary conductor.

In practicing the first invention or the second invention, the second main surface of the semiconductor chip is preferably sealed with a ceramic plate.

Further, in the implementation of the first invention or the second invention, it is preferable that the sealing material for sealing the integrated circuit portion contains one of a thermosetting resin and a thermoplastic resin.
Further, the second invention is one of the methods suitable for manufacturing the semiconductor device of the first invention, and thus the first invention is not limited to the method manufactured by the second invention.

[0017]

According to the first aspect of the present invention, since the protruding electrodes are formed so as to protrude from the integrated circuit portion, the length and width of the semiconductor device viewed from the protruding direction of the protruding electrodes can be reduced to the same extent as the semiconductor chip. Further, the height of the semiconductor device in the projecting direction of the projecting electrode can be reduced by reducing the projecting height of the projecting electrode. In particular, according to the first aspect of the invention having an external terminal, by providing the external terminal, when the semiconductor device is mounted on a wiring board or the like, the semiconductor device and the wiring board can be electrically reliably connected. Can be connected. According to the first aspect of the invention in which the thickness of the sealing material is taken into account, the thickness of the sealing material is substantially the same as the distance between the first end and the second end. The projecting electrodes can be protected by the sealing material.

Further, since at least the integrated circuit portion is sealed, it is possible to prevent the integrated circuit portion from being damaged when storing, transporting or mounting the semiconductor device.

Further, according to the second invention, it is small and
Moreover, a semiconductor device that is convenient for storage, transportation, and mounting can be provided. Further, according to the preferred embodiment of the second invention, when at least the projecting electrode and the integrated circuit portion are covered with the sealing material and then the sealing material is shaved and exposed, the sealing of the integrated circuit portion and the exposure of the projecting electrode are performed. It can be done simply.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. The drawings are only schematically shown to the extent that the present invention can be understood, and thus the present invention is not limited to the illustrated examples.

FIG. 1 is a sectional view schematically showing the structure of the first embodiment of the first invention. The semiconductor device (referred to as a semiconductor package in this embodiment) 34 of this embodiment includes a semiconductor chip 22, a connection conductor (projection electrode) 20 protruding from an integrated circuit portion 22 a of the semiconductor chip 22, and a connection conductor 20. And a sealing material 28 for exposing the protruding end portion (second end portion) and sealing the integrated circuit portion 22a. As shown in FIG. 1, the connection conductor 20 has a first end and a second end at both ends, the first end being connected to the integrated circuit and the second end being sealed. It is provided so as to be exposed from the material 28. The main surface of the semiconductor chip 22 on which the integrated circuit is provided is referred to as a first main surface, and the main surface opposite to the first main surface on which the integrated circuit is not provided is a second main surface.
The surface of the semiconductor chip 22 other than the main surface is referred to as a side surface. This integrated circuit corresponds to the integrated circuit unit 22 described above.
equal to a.

Although not shown, the integrated circuit section 22a has an electric circuit element such as a transistor, a capacitor, and a wiring, and a connection conductor 20 is provided at a terminal portion of a desired electric circuit element. The sealing material 28 covers the integrated circuit portion 22a of the semiconductor chip 22 and does not cover other portions of the semiconductor chip 22. That is, the side surface and the second main surface of the semiconductor chip 22 are exposed. Further, the connection conductor 20 and the sealing material 28 are
The height protruding from a is almost equal. That is,
The surface of the sealing material 28 is formed on substantially the same plane as the second end of the connection conductor 20.

A comparison between the semiconductor package 34 of the first embodiment of the first invention and a semiconductor package using a conventional lead frame (see FIG. 33) shows that the lead frame and the bonding wires are not used in this embodiment, A frame thickness of about 0.2 mm and a protruding height of about 0.2 mm at the time of connection of the bonding wires are not required, so that the thickness of the semiconductor package 34 can be made smaller than before. In contrast to the conventional package having a thickness of, for example, about 1.0 mm, in the package of this embodiment, the thickness is, for example, about 0.35 mm for the semiconductor chip 22 and about 0.02 mm for the sealing material 28. It can be about 0.4 mm. Further, in this embodiment, since a lead frame is not used, an external lead terminal is not required, so that the width of the semiconductor package 34 can be made smaller than in the conventional case.

FIGS. 2 to 11 are manufacturing process diagrams for explaining the first embodiment of the second invention. This embodiment is an example of manufacturing the semiconductor package 34 shown in FIG.

First, the connection conductor 20 is connected to the semiconductor chip 22.
And formed at desired terminal portions of the integrated circuit portion 22a by protruding from the integrated circuit portion 22a (FIG. 2). In this example,
As a material for forming the connection conductor 20, solder, gold, or another conductive material, preferably a conductive material that can be brazed, is used. Any suitable technique can be used for forming the connection conductor 20, for example, using a thick film printing technique. Alternatively, it is formed using a combination of photolithography and etching techniques and vapor deposition and other thin film forming techniques. Alternatively, it is formed using a combination of a photolithography and etching technique and an electroless plating technique. Alternatively, the connection conductor 20 may be formed by crimping the spherical or hemispherical connection conductor 20 to the terminal portion of the integrated circuit portion 22a. Further, the connection conductor 20 may be formed in a wafer state before separating the individual semiconductor chips 22 from the semiconductor wafer, and thereafter may be separated into the individual semiconductor chips 22 or in a state where the semiconductor chips 22 are separated from the semiconductor wafer. May be performed.

Next, the connecting conductor 20 and the integrated circuit section 22a
Is covered with a sealing material 28 (FIGS. 3 to 7). In this example,
The sealing material 28 is a thermosetting resin, and the first portion 24 of the mold is used.
(Hereinafter, simply referred to as a mold 24) and a second portion of the mold (hereinafter, simply referred to as a mold 26) are covered with a sealing material 28 by a molding technique. The mold 24 has a concave portion 24a for receiving the semiconductor chip 22. The depth H of the concave portion 24a is determined by setting the concave portion 24 when the semiconductor chip 22 is placed in the concave portion 24a.
(a) It is longer than the height h from the lower surface to the protruding end of the connection conductor 20 (see FIG. 4). Then, the semiconductor chip 22 is inserted into the recess 2.
The semiconductor chip is supported on the side wall surface of the concave portion 24a so that the semiconductor chip 22 is not substantially displaced in the state where the semiconductor chip 22 is placed in the concave portion 4a. The recess 24a is formed so as to perform The mold 26 has a sealing material channel 26a and a lid portion 26b that closes the concave portion 24a so as to be openable and closable (see FIG. 5). When the recess 24a is closed, the recess 24 is closed.
A gas flow path (not shown) for extracting the gas in a to the outside of the concave portion 24a is provided in the molds 24 and / or 26 as is usually performed by a molding technique. The forming material of the molds 24 and 26 is, for example, metal, that is, the molds 24 and 26
And can be.

In covering with the sealing material 28, first, the mold 2
4 and 26 are heated in advance to a temperature at which the sealing material 28 easily flows. Then, the semiconductor chip 22 is moved to the integrated circuit section 22a.
Of the mold 24 so as to face the outside of the recess 24a.
a (FIGS. 3 and 4). Next, the concave portion 24a is closed with the lid portion 26b of the mold 26 (FIG. 5). With the concave portion 24a closed, the lid portion 26b and the connection conductor 20 are separated from each other. The distance between the lid portion 26b and the integrated circuit portion 22a is, for example, 50 μm. Next, the sealing material 28 having fluidity and not being cured is injected into the recess 24a through the sealing material channel 26a, and the sealing material 28 is placed in a space surrounded by the recess 24a and the lid portion 26b. After filling, the connection conductor 20 and the integrated circuit portion 22a are embedded in the sealing material 28 (FIGS. 5 to 6). Preferably, the connection conductor 20 and the integrated circuit portion 22a
In particular, no air bubbles are left between the integrated circuit portion 22a and the sealing material. Next, the sealing material 28 is heated and cured, and then the semiconductor chip 22 is removed from the molds 24 and 26 to obtain the semiconductor chip 22 in which the connection conductor 20 and the integrated circuit portion 22a are embedded in the sealing material 28 (FIG. 7). When the sealing material 28 is cured, for example, the mold 24
Is heated to a temperature at which the sealing material 28 is cured, the mold 26 is heated to a temperature at which the sealing material 28 is not cured, and the difference between the heating temperatures of the dies 24 and 26 is reduced to reduce the thermal stress of the sealing material 28. It is better to make it smaller. In addition, in order to facilitate removal of the semiconductor chip 22 from the mold 24, for example, a push rod p (this rod p is indicated by a dashed line in FIG. 3B) is raised from the bottom of the concave portion 24a to the height of the concave portion 24a. The protruding rod p is slidably provided on the mold 24 so that the height protruding in the height direction q is adjustable.
It is preferable that the semiconductor chip 22 is protruded from the concave portion 24a with a push rod p and removed. Alternatively, a portion r that forms the bottom of the mold 24 (this portion r is indicated by a dotted line in FIG. 3B) may be configured so that the height of the concave portion 24a can be adjusted freely.

Next, the connection conductor 20 and the integrated circuit section 22a
Of the connecting conductor 20 is exposed by polishing, sealing, grinding, cutting or any other suitable shaving device to cover the sealing material 28 (FIGS. 8 to 11). The shaving device used in this embodiment includes a fixing portion 30 (see FIG. 8) and a shaving portion 32. The fixing part 30 has a positioning part 30 a for positioning and fixing the semiconductor chip 22.
2 has a shaved surface 32 a for shaving the semiconductor chip 22. For example, the positioning portion 30a is a concave portion, and is positioned by fitting the semiconductor chip 22 into the positioning portion 30a. Further, for example, an abrasive,
An abrasive or cutting blade is provided.

In exposing the connection conductor 20, first, the portion of the semiconductor chip 22 opposite to the connection conductor 20 is attached to the fixing portion 30, and the semiconductor chip 22 is attached to the fixing portion 3.
0 (FIGS. 8 and 9). Next, the portion of the sealing material 28 on the connection conductor 20 is shaved by the shaved surface 32 a of the shaved portion 32.
(FIG. 10). Next, the sealing material 28 and the shaved surface 32a are pressed while the sealing material 28 is pressed against the shaved surface 32a.
, The sealing material 28 is shaved until the protruding end of the connection conductor 20 comes into contact with the shaved surface 32a, thereby exposing the protruding end of the connection conductor 20 from the sealing material 28 (FIG. 11). .

Next, the semiconductor chip 22 is removed from the fixing portion 30, and a semiconductor package 34 in which the integrated circuit portion 22a is sealed with the sealing material 28 is obtained (FIG. 1). In order to facilitate removal of the semiconductor chip 2 from the fixing part 30, a push rod p or a part r similar to the mold 24 may be provided on the fixing part 30.

Comparing the manufacturing method of the first embodiment of the second invention with the conventional method of manufacturing a semiconductor package using a lead frame, the bonding process and the lead frame are not used in this embodiment. Since a lead frame plating step is not required, the TAT (Turn Around Time) can be greatly reduced as compared with the related art, and the investment in manufacturing equipment can be reduced. Further, in this embodiment, since the process is simpler than in the related art, the number of check items for detecting a defective product can be reduced as compared with the related art.

FIG. 12 is a sectional view schematically showing a mounted state of a semiconductor chip. The wiring board 36 shown in FIG.
a, a wiring pattern 36b provided on the substrate 36a, and a connection conductor 36c provided on a terminal portion of the wiring pattern 36b. The material for forming the connection conductor 36 is solder, gold, a conductive adhesive or another conductive material, preferably a conductive material that can be brazed. At least one of the connection conductor 20 of the semiconductor package 34 and the connection conductor 36c of the wiring board 36 is made of a conductive material that can be brazed.

In mounting the semiconductor package 34 manufactured as described above on the wiring board 36, the connection conductors 20 of the semiconductor package 34 and the connection conductors 3 of the wiring board 36 are mounted.
6c, and the connecting conductor 20 is connected to the connecting conductor 36c.
On top. Next, after the connection conductors 20 and / or 36c are heated and melted, they are cooled and solidified to form the integrated circuit portion 22a.
And the wiring pattern 36b are electrically connected via the connection conductors 20 and 36c.

The connection conductor 20 of the semiconductor package 34
When is a conductive material that can be brazed, the connection conductor 36c of the wiring board 36 may not necessarily be provided.

FIG. 13 is a view for explaining a modification of the first embodiment of the first and second inventions.

As shown in FIG. 13, the semiconductor package 37 of this modification is similar to the semiconductor package 3 of the first embodiment.
4 is provided with an auxiliary conductor 38. The auxiliary conductor 38 is provided so as to protrude on the connection conductor 20 and on the sealing material 28 near the conductor 20. The auxiliary conductor 38 is formed on the exposed second end of the connection conductor 20, and is therefore electrically connected to the second end. The auxiliary conductor 38 is formed wider than the connection conductor 20 when viewed from the projecting direction of the connection conductor 20. As shown in FIG. 13, the auxiliary conductor 38 is provided such that the connection conductor 20 has a maximum width that is wider than the maximum width of the connection conductor 20 when viewed from the direction in which the connection conductor 20 protrudes.

Further, a modified example of the second invention is an example in which a semiconductor package 37 is manufactured. In this example, first, a semiconductor package 34 is completed through the same steps as those in the above-described first embodiment (FIG. 2). 11 and 1).

Next, the auxiliary conductor 38 is formed on the connection conductor 20 and on the sealing material 28 near the conductor 20 so as to be wider than the connection conductor 20 when viewed from the projecting direction of the connection conductor 20. Is obtained (FIG. 13).

The material for forming the auxiliary conductor 38 is solder, gold or another conductive material, preferably a conductive material capable of being brazed. The auxiliary conductor 38 can be formed by any suitable technique, for example, by using a thick-film printing technique. Alternatively, it is formed using a combination of photolithography and etching techniques and vapor deposition and other thin film forming techniques. Alternatively, it is formed using a combination of a photolithography and etching technique and an electroless plating technique. Alternatively, a spherical or hemispherical auxiliary conductor 38 is formed by crimping on the connection conductor 20. In the modified example of the first embodiment of the second invention, the same effect as that of the first embodiment of the second invention can be obtained.

FIG. 14 is a sectional view schematically showing the configuration of the second embodiment of the first invention. The components corresponding to the components of the first embodiment described above are denoted by the same reference numerals, and detailed description of the same points as in the first embodiment will be omitted.

The semiconductor package 44 of this embodiment includes the semiconductor chip 22, the connection conductor 20, and the encapsulating materials 28 and 40. In this embodiment, the entirety of the semiconductor chip 22 provided with the connection conductor 20 is covered with sealing materials 28 and 40. The sealing member 40, for example, an integrated circuit portion 22 of the semiconductor chip 22 using a ceramic plate
In addition to covering the portion on the opposite side to the portion a, the remaining semiconductor chip 22 is covered while exposing the connection conductor 20 with a sealing material 28, for example, a thermosetting resin.

Also in the second embodiment of the first invention, the thickness of the semiconductor package 44 can be made thicker than the first embodiment but thinner than the conventional package. Further, the width of the semiconductor package 44 can be made smaller than that of the conventional package.

FIGS. 15 to 21 are manufacturing process diagrams for explaining the second embodiment of the present invention. This embodiment is an example of manufacturing a semiconductor package 44. The components corresponding to the components of the first embodiment are denoted by the same reference numerals,
Detailed description of the same points as in the first embodiment will be omitted.

First, the connection conductor 20 is formed on the integrated circuit portion 22a by protruding from the integrated circuit portion 22a of the semiconductor chip 22.

Next, the entire semiconductor chip 22 provided with the connection conductors 20 is covered with sealing materials 28 and 40 (FIGS. 15 to 1).
9). In this embodiment, a gap t is formed between the side wall of the semiconductor chip 22 and the side wall of the concave portion 24a in the state where the semiconductor chip 22 is placed in the concave portion 24a of the mold 24 for flowing the sealing material over the entire periphery of these side walls. So that the recess 24a
Is formed wider than the semiconductor chip 22 (see FIG. 16).

When covering with the sealing materials 28 and 40, first, a plate-shaped sealing material 40, for example, a ceramic plate is attached to the semiconductor chip 22 on the side opposite to the integrated circuit portion 22 a with an adhesive 42.
(FIG. 15). Then, the molds 24 and 26 are heated in advance to a temperature at which the sealing material 28 easily flows. Next, the semiconductor chip 22 is placed in the concave portion 24a, and the semiconductor chip 22 is positioned using any suitable means so that a gap t is formed between the side walls of the semiconductor chip 22 and the concave portion 24a over the entire periphery of these side walls ( (FIG. 16). Next, the concave portion 24a is closed by the lid portion 26b of the mold 26 (FIG. 1).
7). Next, the sealing material 28 having fluidity and being uncured is removed through the sealing material flow path 26a of the mold 26 to form the recess 24a.
And bury the connection conductor 20, the integrated circuit portion 22a, and the side wall of the semiconductor chip 22 in the sealing material 28 (FIG. 1).
8). Preferably, the connection conductor 20 and the integrated circuit portion 22a
In particular, no air bubbles are left between the integrated circuit portion 22a and the sealing material. Next, the sealing material 28 is heated and cured, and then the semiconductor chip 22 is removed from the molds 24 and 26 (FIG. 19). When the sealing material 28 is cured, for example, the mold 24 is heated to a temperature at which the sealing material 28 is cured, and the mold 26 is heated to a temperature at which the sealing material 28 is not cured. It is preferable to reduce the difference in the thermal stress of the sealing material 28 by reducing the difference in the thermal stress.

Next, as shown in FIGS. 20 to 21, the sealing material 28 is shaved to expose the connection conductor 20 (see FIGS. 20 to 20).
(FIG. 21).

In exposing the connection conductor 20, first, a portion of the semiconductor chip 22 opposite to the connection conductor 20 is attached to the fixing portion 30 via sealing materials 28 and 40, and the sealing on the connection conductor 20 is performed. The stopper 28 is brought into contact with the shaved surface 32a of the shaved portion 32 (FIG. 20). Next, the sealing material 28 is
The sealing material 28 and the shaved surface 32a are relatively moved while being pressed against the sealing material 2a until the connecting conductor 20 is exposed.
(FIG. 21).

Next, the semiconductor chip 22 is removed from the fixing portion 30, and a semiconductor package 44 in which the semiconductor chip 22 is sealed with sealing materials 28 and 40 is obtained (FIG. 14). In the second embodiment of the second invention, the same effect as in the first embodiment can be obtained.

FIG. 22 is a sectional view schematically showing the structure of the third embodiment of the first invention. The components corresponding to the components of the first embodiment are denoted by the same reference numerals,
Detailed description of the same points as in the first embodiment will be omitted.

The semiconductor package 48 of this embodiment includes the connection conductor 20, the semiconductor chip 22, and the sealing members 46 and 47. In this embodiment, the entire semiconductor chip 22 provided with the connection conductor 20 is covered with sealing materials 46 and 47. Sealing material 46
For example, the integrated circuit portion 2 of the semiconductor chip 22 is made of a thermoplastic resin.
The remaining semiconductor chip 22 is covered while covering the portion opposite to 2a and exposing the connection conductor 20 with a sealing material 47, for example, a thermoplastic resin.

Also in the third embodiment of the first invention, the thickness of the semiconductor package 48 can be larger than that of the first embodiment but smaller than that of the conventional package. Further, the width of the semiconductor package 48 can be made smaller than that of the conventional package.

FIGS. 23 to 30 are manufacturing process diagrams for explaining the third embodiment of the second invention. This embodiment is an example of manufacturing the semiconductor package 48 shown in FIG. The components corresponding to the components of the first embodiment are denoted by the same reference numerals, and detailed description of the same points as those of the first embodiment will be omitted.

First, the semiconductor chip 22 and the connection conductor 20 are formed in the same manner as in the first embodiment.

Next, the entire semiconductor chip 22 provided with the connection conductor 20 is covered with sealing materials 46 and 47 (FIGS. 23 to 2).
8).

When covering with the sealing materials 46 and 47, first, the sealing material 46, for example, a thermoplastic resin is solidified and fitted into the concave portion 24a of the mold 24, and the sealing material 46 is
Positioning is supported by 4a (FIG. 23). The sealing material 46 is provided with a concave portion 46a at the center thereof in a solidified state, so that the height of the peripheral portion of the sealing material 46 is higher than the height of the center portion. Next, the portion of the semiconductor chip 22 opposite to the integrated circuit portion 22a is fitted into the concave portion 46a of the sealing material 46, and the peripheral portion of the sealing material 47 is inserted between the semiconductor chip 22 and the side wall of the concave portion 24a. Chip 22
Is supported and positioned by the concave portion 46a (FIG. 24). Next, in a state where the sealing material 47, for example, a thermoplastic resin is solidified, the semiconductor chip 2 is fitted into the concave portion 24 a of the mold 24.
It is mounted on the second connection conductor 20 (FIG. 25). Sealing material 4
7 is provided with a concave portion 47a at the center thereof in a solidified state,
Therefore, the height of the peripheral portion of the sealing material 46 is higher than the height of the central portion. The sealing material 47 is fitted into the concave portion 24a of the mold 24 so that the connection conductor 20 is inserted into the concave portion 47a, and the peripheral portion of the sealing material 47 is inserted between the semiconductor chip 22 and the side wall of the concave portion 24a. Next, the lid 26b of the mold 26 is slidably fitted into the recess 24a of the mold 24, and the lid 26b is brought into contact with the sealing material 47 (FIG. 2).
6). Note that, in this example, the mold material 26 is not provided with the sealing material channel 26a. The seals 46, 47 are then pressed between the dies 24, 26 while being heated via the dies 24, 26 to a temperature at which they exhibit plasticity, ie, fluidize, and this pressure causes the seals 46, 47 to be pressed. , 47 are pressed against each other, and the entire semiconductor chip 22 provided with the connection conductor 20 is embedded in the sealing materials 46, 47. Preferably, the connecting conductor 2
0 and the integrated circuit portion 22a, particularly, no air bubbles remain between the integrated circuit portion 22a and the sealing material 47. Then
With the peripheral portions of the sealing materials 46 and 47 pressed against each other,
47 is cooled and solidified through the molds 24 and 26, whereby the peripheral portions of the sealing materials 46 and 47 are bonded to each other (FIG. 2).
7). Next, the semiconductor chip 22 is removed from the molds 24 and 26, and the semiconductor chip 22 covered with the sealing materials 46 and 47 is formed.
And the connection conductor 20 is obtained (FIG. 28).

Next, the connection conductor 20 and the integrated circuit section 22a
Is removed to expose the connection conductor 20 (FIGS. 29 to 30).

To expose the connection conductor 20, first, the semiconductor chip 22 is mounted and fixed on the fixing portion 30, and then the sealing material 47 on the connection conductor 20 is cut off by the shaving surface of the shaving portion 32. 32a (FIG. 29). Next, the sealing material 47 is shaved by the shaved surface 32a until the connection conductor 20 is exposed (FIG. 30).

Next, the semiconductor chip 22 is removed from the fixing portion 30, and a semiconductor package 48 in which the entire semiconductor chip 22 provided with the connection conductor 20 is sealed with sealing materials 46 and 47 is obtained (FIG. 22). In the third embodiment of the second invention, the same effect as in the first embodiment can be obtained.

The present invention is not limited only to the above-described embodiment, and accordingly, the shapes, arrangement positions, forming materials, numerical conditions, and others of the components can be arbitrarily and suitably changed.

[0061]

As is apparent from the above description, according to the semiconductor device of the first invention, the protruding electrodes for connecting the semiconductor chip to another electric circuit are formed from the integrated circuit portion of the semiconductor chip. Since the semiconductor device is formed to protrude, the length and width of the semiconductor device viewed from the protruding direction of the protruding electrode can be reduced. Further, the height of the semiconductor device in the direction in which the projecting electrodes project can be reduced by reducing the projecting height of the projecting electrodes. Therefore, the size of the semiconductor device itself can be reduced as compared with a semiconductor device using a conventional lead frame.
Further, since at least the integrated circuit portion is sealed, it is possible to prevent the integrated circuit portion from being damaged when storing, transporting, or mounting the semiconductor device. Compared with the conventionally known flip chip, the flip chip protects the integrated circuit portion with a protective film, but the protective film alone cannot always sufficiently protect the integrated circuit portion from moisture and impact, so the flip chip is If not sealed with a sealing material, care must be taken in storage, transportation and mounting, which is inconvenient. On the other hand, since the semiconductor device of the present invention protects the integrated circuit portion from moisture and impact by the sealing material, it is convenient that the semiconductor device is hardly damaged when it is stored, transported, or mounted.

Therefore, according to the semiconductor device of the first invention, it is possible to provide a semiconductor device which is small and which is convenient for storage, transportation and mounting.

Further, according to the method of manufacturing a semiconductor device of the second invention, it is possible to provide a small-sized semiconductor device which is convenient for storage, transportation, and mounting. According to the preferred embodiment of the second invention, since at least the protruding electrode and the integrated circuit portion are covered with the sealing material, the sealing material is shaved to expose the protruding electrode,
The sealing of the integrated circuit portion and the exposure of the protruding electrodes can be easily performed,
Therefore, the semiconductor device of the first invention can be manufactured simply.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing a configuration of a first embodiment of the first invention.

FIG. 2 is a sectional view schematically showing one stage of a manufacturing process in the first embodiment of the second invention.

FIGS. 3A and 3B are a top view and a sectional view schematically showing the same process steps of a manufacturing process in the first embodiment of the second invention.

FIGS. 4A and 4B are a top view and a cross-sectional view schematically showing the same process steps of a manufacturing process in the first embodiment of the second invention.

FIGS. 5A and 5B are a top view and a sectional view schematically showing the same process steps of the manufacturing process in the first embodiment of the second invention.

FIG. 6 is a sectional view schematically showing one stage of a manufacturing process in the first embodiment of the second invention.

FIG. 7 is a sectional view schematically showing one stage of a manufacturing process in the first embodiment of the second invention.

FIGS. 8A and 8B are a bottom view and a sectional view schematically showing the same process steps of the manufacturing process in the first embodiment of the second invention.

FIGS. 9A and 9B are a bottom view and a sectional view schematically showing the same process step of the manufacturing process in the first embodiment of the second invention.

FIG. 10 is a sectional view schematically showing one stage of a manufacturing process in the first embodiment of the second invention.

FIG. 11 is a sectional view schematically showing one stage of a manufacturing process in the first embodiment of the second invention.

FIG. 12 is a sectional view schematically showing a mounting state of a semiconductor package.

FIGS. 13A and 13B are a top view and a sectional view schematically showing a configuration of a modification of the first embodiment of the first invention.

FIG. 14 is a sectional view schematically showing a configuration of a second embodiment of the first invention.

FIG. 15 is a sectional view schematically showing one stage of a manufacturing process in the second embodiment of the second invention.

16 (A) and (B) are a top view and a cross-sectional view schematically showing the same process step of the manufacturing process in the second embodiment of the second invention.

17A and 17B are a top view and a cross-sectional view schematically showing the same process steps of a manufacturing process in the second embodiment of the second invention.

FIG. 18 is a sectional view schematically showing one stage of a manufacturing process in the second embodiment of the second invention.

FIG. 19 is a sectional view schematically showing one stage of a manufacturing process in the second embodiment of the second invention.

FIG. 20 is a sectional view schematically showing one stage of a manufacturing process in the second embodiment of the second invention.

FIG. 21 is a sectional view schematically showing one stage of a manufacturing process in the second embodiment of the second invention.

FIG. 22 is a sectional view schematically showing a configuration of a third embodiment of the first invention.

FIGS. 23A and 23B are a top view and a cross-sectional view schematically showing the same process steps of a manufacturing process in a third embodiment of the second invention.

FIGS. 24A and 24B are a top view and a cross-sectional view schematically showing the same process steps of a manufacturing process in a third embodiment of the second invention.

FIGS. 25A and 25B are a top view and a cross-sectional view schematically showing the same process step of the manufacturing process in the third embodiment of the second invention.

FIGS. 26A and 26B are cross-sectional views schematically showing one stage of a manufacturing process in a third embodiment of the second invention.

FIG. 27 is a cross sectional view schematically showing one stage of a manufacturing process in the third embodiment of the second invention.

FIG. 28 is a sectional view schematically showing one stage of a manufacturing process in a third embodiment of the second invention.

FIG. 29 is a cross sectional view schematically showing one stage of a manufacturing process in the third embodiment of the second invention.

FIG. 30 is a sectional view schematically showing one stage of a manufacturing process in a third embodiment of the second invention.

FIG. 31 is a sectional view schematically showing a configuration of a conventional semiconductor package.

FIGS. 32A and 32B are cross-sectional views schematically showing different stages in a conventional semiconductor package manufacturing process.

FIG. 33 is a cross-sectional view schematically showing one stage in a conventional semiconductor package manufacturing process.

[Explanation of symbols]

 Reference Signs List 20: connecting conductor 22: semiconductor chip 22a: integrated circuit part 28: sealing material 34, 37, 44, 48: semiconductor package 38: auxiliary conductor

Claims (6)

[Claims] A step of forming, on a first main surface of a semiconductor chip on which an integrated circuit is formed, a protruding electrode having one end connected to the integrated circuit; Arranging the solidified thermoplastic resin on the surface of the semiconductor chip; heating the thermoplastic resin to a temperature showing plasticity; and A first part and a second part of a mold facing the first part
And pressing the fluidized thermoplastic resin to cover the semiconductor chip with the thermoplastic resin. 2. a step of disposing the solidified thermoplastic resin in the concave portion of the first portion of the mold having the concave portion; and providing an integrated circuit on the surface of the thermoplastic resin. Disposing a semiconductor chip having a protruding electrode having one end connected to an integrated circuit formed on a first main surface; heating the solidified thermoplastic resin to a temperature indicating plasticity; A first part and a second part of a mold facing the first part;
And pressing the fluidized thermoplastic resin with the portion to cover the semiconductor chip with the thermoplastic resin. 3. A semiconductor chip having an integrated circuit and having a protruding electrode having one end connected to the integrated circuit formed on a first main surface is disposed on the surface of the solidified thermoplastic resin. 3. The method according to claim 2, further comprising, after the step (b), arranging a solidified thermoplastic resin on the surface of the semiconductor chip. 4. The method according to claim 1, further comprising the step of: after sealing the semiconductor chip with a sealing material so as to cover the other end of the projecting electrode, polishing the sealing material until the other end of the projecting electrode is exposed. The method for manufacturing a semiconductor device according to claim 1, wherein: 5. A method according to claim 1, wherein the first mold has a recess.
Arranging a semiconductor substrate having projecting electrodes formed on the surface thereof; arranging a thermoplastic resin on the surface of the semiconductor substrate arranged in the first mold; and fluidizing the thermoplastic resin. Heating to a temperature, and covering the semiconductor substrate with the fluidized resin by pressing the thermoplastic resin with the first mold and a second mold facing the first mold. And a method of manufacturing a semiconductor device. 6. The method according to claim 5, further comprising, after the step of covering the surface of the semiconductor substrate with a resin, a step of polishing the surface of the resin.