JP3577259B2

JP3577259B2 - Differential ring oscillator circuit and multi-phase clock oscillator using the same

Info

Publication number: JP3577259B2
Application number: JP2000153861A
Authority: JP
Inventors: 淳一岡村
Original assignee: THine Electronics Inc
Current assignee: THine Electronics Inc
Priority date: 2000-05-24
Filing date: 2000-05-24
Publication date: 2004-10-13
Anticipated expiration: 2020-05-24
Also published as: JP2001332698A

Description

【０００１】
【発明の属する技術分野】
本発明は、多相クロック信号を発生するための差動リング発振回路及び多相クロック発振器に関するものである。
【０００２】
【従来の技術】
最近、装置間の信号伝送には高速の小振幅シリアル信号を使うようになっている。これはディジタル信号をパラレルに転送するのに対し、僅かなケーブル数で済むのに加えてディジタル信号の転送で発生するＥＭＩを抑制することが近年より重要になってきていることによる。このような、高速のシリアル通信を実現する際には、装置内部でのパラレル−シリアル変換の為にベースクロックと等しく位相がずれた多相の副クロックの発生が必須である。多段の遅延差動反転増幅回路をリング状に接続した電圧または電流制御差動リング発振回路は、等位相の多相副クロックを多段のリング発振回路から容易に引き出すことが出来る為、この応用に最適な回路であるが、高速のリング発振回路から正確に同じく位相がずれた副クロックを発生させる為には、各段の遅延差動反転増幅回路の負荷と副クロック配線の寄生容量を均等にする必要がある。
【０００３】
従来は、各段の遅延差動反転増幅回路の負荷を均等にする為に、電圧または電流制御差動リング発振回路を構成するＮ段の遅延差動反転増幅回路を半導体基板上に２列に配置し、それぞれの列において連続する遅延差動反転増幅回路が隣り合うように配置していた。このように配置することで、差動リング発振回路を構成するＮ段の遅延差動反転増幅回路の出力と入力との間の配線における遅延を最小にして、高周波で発振可能な差動リング発振回路を実現することができる。
【０００４】
しかしながら、高速のシリアル通信を実現する為に必要とされる等間隔の位相差を有する多相クロック信号を出力する差動リング発振回路においては、一般に、１つおきの遅延差動反転増幅回路の出力から多相クロック信号を引き出すので、２列に配置された遅延差動反転増幅回路のそれぞれの列から信号を引き出すことが必要である。そのため、従来の配置及び配線によれば、一方の列については多相クロック信号の配線の引き回しが長くなり、多相クロック信号配線の寄生容量を均等に揃えることが困難となっていた。また、この多相クロック信号配線の引き回しは、差動リング発振回路の周囲における比較的広範囲な領域で行わなくてはならないため、半導体基板の面積が大きくなってしまうという問題があった。
【０００５】
【発明が解決しようとする課題】
そこで、上記の点に鑑み、本発明は、高周波で発振可能なリング発振回路から多相クロック信号配線を引き出す場合において、多相クロック信号配線の寄生容量の不均等に起因するクロック位相精度の劣化や基板面積の増加を抑えた差動リング発振回路及び多相クロック発振器を実現することを目的とする。
【０００６】
【課題を解決するための手段】
本発明に係る差動リング発振回路は、リング発振回路を構成する複数段の増幅回路を、回路上では隣合う前段と後段の増幅回路を半導体基板上では隣合わないように、それぞれを２列に互い違いに半導体基板上に配置することを特徴とし、さらに、本発明に係る多相クロック発振器は、多相クロック信号が引き出される増幅回路の全てを、どちらか一方の列に配置することを特徴とする。
【０００７】
【発明の実施の形態】
以下、図面を参照して本発明の実施の形態を詳細に説明する。
【０００８】
図１は、この発明の実施形態に係る多相クロック発振器に含まれている電圧制御差動リング発振回路の回路図であり、Ｎ＝８段の電圧制御差動リング発振回路の例を示している。
【０００９】
図１に示す電圧制御差動リング発振回路において、１０１ａ−１０１ｈは遅延差動反転増幅回路であり、１０２は遅延時間の制御電圧の外部入力端子であり、１０３は遅延時間の制御電圧源である。
【００１０】
それぞれの遅延差動反転増幅回路１０１ａ−１０１ｈは、差動入力端子対１１１と差動出力端子対１１２を持っており、８個の遅延差動反転増幅回路１０１ａ−１０１ｈの内、１番目の遅延差動反転増幅回路１０１ａの差動出力端子１１２を２番目の遅延差動反転増幅回路１０１ｂの差動入力端子１１１へ接続し、２番目の遅延差動反転増幅回路１０１ｂの差動出力端子１１２を３番目の遅延差動反転増幅回路１０１ｃの差動入力端子１１１へと順番に接続していき、最後に８番目の遅延差動反転増幅回路１０１ｈの差動出力端子１１２を１番目の遅延差動反転増幅回路１０１ａの差動入力端子１１１へ交差接続している。
【００１１】
このように接続することで、各段の遅延差動反転増幅回路１０１ａ−１０１ｈはその差動出力端子対１１２に便宜上付けられたΦ１からΦ１６までの名前のクロックを持つ電圧制御差動リング発振回路を構成することができる。
【００１２】
図２には、図１に示された８段の電圧制御差動リング発振回路から得られるΦ１からΦ１６まで名前を付けられたクロックの電圧波形が示されている。尚、図２においては、横軸が時間、縦軸が電圧を示している。
【００１３】
図１に示す、電圧制御差動リング発振回路において、１０１ａ−１０１ｈは遅延差動反転増幅回路であるので、図２に示されているように、各段の信号は外部からの制御電圧１０３で決まる単位遅延時間２０１だけ遅れてそれぞれ反転出力される。この場合電圧制御差動リング発振回路の発振周波数の逆数であるサイクル時間２０２は、
ｔ_{ｃｌｏｃｋ} ＝ｔ_{ｄｅｌａｙ}×２×Ｎ＝１６×ｔ_{ｄｅｌａｙ}
となる。
【００１４】
前記式から明らかなように、電圧制御差動リング発振回路のサイクル時間の最小値は、各段の単位遅延時間２０１と段数で決まる。遅延時間が最小になる制御電圧を加えた場合に高い発振周波数を得る為には必要最小限の遅延差動反転増幅回路の段数を選択することに加えて、各段を接続する配線の寄生容量をなるべく小さくし、単位遅延時間２０１を出来るだけ小さくするような設計が求められる。
【００１５】
従来、図１に示されたような電圧制御差動リング発振回路を半導体基板上に形成する際には、図１に示された回路図と同じように、全体を２列配置し両端を除き各段の遅延差動増幅回路が隣り合うように配置することで、各段を結ぶ配線の長さを最小にして、遅延差動反転増幅回路の負荷である配線容量を均等に且つ最小にする設計が行なわれている。
【００１６】
一方、高速のシリアル通信を実現する為には、等間隔で位相がずれた多相クロック信号が必要である。多相クロック信号の相数は、シリアル数で決定され、一般に４〜１０相の多相クロック信号が必要とされる。図２には、本実施形態における電圧制御差動リング発振回路の各段の出力波形が示されている。図に示された、Φ１からΦ１６までの名前を付けられたクロックの内、高速のシリアル通信を実現する為に必要なクロックを選択する方法に関して説明する。
【００１７】
本実施形態では、Ｎ＝８相のクロックを選択する為に、Ｎ＝８段の構成を取っている。一般に、Ｍ相のクロックに対してｎ・Ｍ段の構成（ただしｎは正の整数）が可能であるが、前述したように、電圧制御差動リング発振回路のサイクル時間の最小値は、各段の単位遅延時間２０１と段数で決まるので、シリアル通信で必要とされる高い発振周波数を得る為に必要最小限の段数であるｎ＝１が一般に選択されているが、ｎ＞１の場合でも本願の効果は有効である。
【００１８】
等間隔で位相がずれた多相クロック信号が必要であるので、サイクル時間２０２を８で割った時間だけ位相時間がずれたクロックを選択することになる。その結果、Φ１、Φ３、Φ５、．．．、Φ１５の奇数番目のクロックを多相クロック信号として選択する方法と、Φ２、Φ４、Φ６、．．．、Φ１６の偶数番目のクロックを選択する方法の二通りの方法の内のどちらかを選択することになるが、以下本実施形態においては、Φ１、Φ３、Φ５、．．．、Φ１５の奇数番目のクロックを多相クロック信号として選択する例に関して説明する。もちろん偶数番目のクロックを選択した場合でも、本実施形態と同様の効果を得ることが出来る。
【００１９】
図３は、８相の多相クロック信号を出力する増幅回路を備えた電圧制御差動リング発振回路を含む多相クロック発振器の例を示す。図１に示された電圧制御差動リング発振回路に加えて、選択されたΦ１、Φ３、Φ５、．．．、Φ１５の奇数番目のクロックを多相クロック信号として出力する為に必要な増幅回路３０１ａ−３０１ｈが付加されている。
【００２０】
前述したように、電圧制御差動リング発振回路の各段を接続する配線の寄生容量をなるべく小さくしなければならない。従って、図３の回路を半導体基板上に配置する際には、多相クロック信号の増幅回路３０１ａ−３０１ｈまでの引出し線３０２がなるべく短くなるように全体を配置することが求められる。
【００２１】
従来例の半導体基板上の配置を図４に示す。図４においては、電圧制御差動リング発振回路を全体に２列に配置し、両端を除き各段の遅延差動増幅回路が隣り合うように配置している。次に、従来例の問題点に関して説明する。
【００２２】
図４では、図３の回路図と同じように、全体を２列に配置し、両端を除き各段の遅延差動増幅回路が隣り合うように配置している。さらに、多相クロック信号の増幅回路３０１ａ−３０１ｈまでの引出し線３０２がなるべく短くなるように、遅延差動増幅回路１０１ａ−１０１ｈの脇に多相クロック信号の増幅回路３０１ａ−３０１ｈを配置している。以上の配慮をすることで、各段を結ぶ配線に関わる配線寄生を均等に且つ最小にしているのだが、一方、多相クロック信号自体は電圧制御差動リング発振回路の上下に別々に出力される為に、その配線である４０１ａと４０２ｂの間には大きな寄生容量の差が生じることになる。
【００２３】
多相クロック信号の位相が正確に等間隔であることが高速シリアル通信においては非常に重要であることから、多相クロック信号配線の半導体基板上での引き回しに関しても細心の注意を払う必要がある。つまり、それぞれの多相クロック信号の電磁／容量結合が、多相クロック信号間でそれぞれ均等になるよう常に注意を払わねばならない。一般に、多相クロック信号配線と電磁／容量結合するような別の信号線を走らせたり、半導体活性素子を配線下に配置することはない。従って、図４のように、多相クロック信号線を電圧制御差動リング発振回路の周りの比較的広範囲な領域に引き回すことは、大きな半導体基板面積を必要とすると言う別の問題引き起こすことになる。
【００２４】
図５は、上記問題点を克服する為に考案された、本願の実施形態に係る多相クロック発振器の半導体基板での配置の例を示す。
【００２５】
図５では、図３の回路図と同じように全体を２列に配置しているが、遅延差動増幅回路の各段が隣り合うことはなく、段毎に配置列を交換している。こうすることで、多相クロック信号の増幅回路３０１ａ−３０１ｈまでの引出し線３０２を常に列の一方の遅延差動増幅回路の出力から引き出せば良くなり、多相クロック信号の全てを電圧制御差動リング発振回路の一方からのみ出力させることが可能で、その引き回し線である４０１の寄生容量の差を容易に均等にすることが可能である。
【００２６】
従来例との比較の為に、図６のａには本願の電圧制御差動リング発振回路に各段の配置を示し、図６のｂには従来例の電圧制御差動リング発振回路の各段の配置を並べて示している。
【００２７】
従来例と比較して、各段を接続する配線長が長くなっているが、それは従来例の場合の両端の遅延差動反転増幅回路間の配線と同程度のものであり、従来例の配置を使った電圧制御差動リング発振回路の高周波特性に対して本願の配置によりその特性が劣ることはない。
【００２８】
図７は、Ｎ＝１０段の電圧制御差動リング発振回路の例を示している。
【００２９】
図８は、電圧制御差動リング発振回路１００を構成している遅延差動反転増幅回路の一例を示している。ここで、８０１、８０２は電圧可変抵抗器、８０３、８０４はＭＯＳトランジスタ、８０５は低電流源である。８０６、８０７はそれぞれ第１、第２の差動入力端子であり、８０８、８０９はそれぞれ第１、第２の差動出力端子である。８１０は遅延時間制御電圧入力端子である。本例はＭＯＳトランジスタを用いた遅延差動反転増幅回路であるが、本例以外の半導体集積素子を用いた遅延差動反転増幅回路に対しても本発明は有効かつ実現可能である。
【００３０】
なお、以上の実施形態においては、電圧制御された遅延差動反転増幅回路を使った電圧制御差動リング発振回路に関して説明されているが、本発明は、電流制御された遅延差動反転増幅回路を使った電流制御差動リング発振回路においても有効且つ実現可能なものであり、電圧制御差動リング発振回路に限定されることなく、特許請求の範囲に記載される範囲内で自由に変形・変更可能である。
【００３１】
【発明の効果】
本発明によれば、高速のシリアル通信を実現する為に必要な等間隔の多相クロック信号を、半導体基板上に形成された２列の遅延差動反転増幅回路の内、一方の列のみから引き出すことが可能になるので、多相クロック信号配線の寄生容量の不均等を押えることが出来る。また、従来例と同様に各段の配線遅延を小さく保ったままに出来るので、高周波数で発振可能な電圧または電流制御差動リング発振回路及び多相クロック発振器を実現できる。
【図面の簡単な説明】
【図１】本発明に係る多相クロック発振器に含まれている電圧制御差動リング発振回路を示す回路図である。
【図２】図１に示す電圧制御差動リング発振回路の出力波形を示す図である。
【図３】本発明に係る多相クロック発振器に含まれている電圧制御差動リング発振回路と増幅回路を示す回路図である。
【図４】従来方式に基づく図３の回路の配置例を示す図である。
【図５】本発明に基づく図３の回路の配置例を示す図である。
【図６】本発明と従来例との比較を示す図である。
【図７】Ｎ＝１０段の場合の本発明の実施形態を示す図である。
【図８】本発明の実施形態において用いる遅延差動反転増幅回路の一例を示す回路図である。
【符号の説明】
１００電圧制御差動リング発振回路
１０１遅延差動増幅回路
１０２遅延時間の制御電圧の入力端子
１０３制御電圧源
１１１遅延差動増幅回路の入力端子対
１１２遅延差動増幅回路の出力端子対
２０１遅延差動増幅回路の単位遅延時間
２０２電圧制御差動リング発振回路のサイクル時間
３０１多相クロック信号用増幅回路
３０２多相クロック信号引出し線
４０１多相クロック信号配線
８０１電圧可変抵抗器
８０２電圧可変抵抗器
８０３第１のＭＯＳトランジスタ
８０４第２のＭＯＳトランジスタ
８０５低電流源
８０６第１の差動入力端子
８０７第２の差動入力端子
８０８第１の差動出力端子
８０９第２の差動出力端子
８１０遅延時間の制御電圧の入力端子[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a differential ring oscillation circuit for generating a multi-phase clock signal and a multi-phase clock oscillator.
[0002]
[Prior art]
Recently, high-speed small-amplitude serial signals have been used for signal transmission between devices. This is because digital signals are transferred in parallel, whereas a small number of cables are required, and suppression of EMI generated by digital signal transfer has become more important in recent years. When realizing such high-speed serial communication, it is necessary to generate a multi-phase sub-clock having the same phase shift as the base clock for parallel-serial conversion inside the device. A voltage or current control differential ring oscillator circuit in which a multi-stage delayed differential inverting amplifier circuit is connected in a ring shape can easily derive an equal-phase multi-phase sub-clock from the multi-stage ring oscillator circuit. Although it is an optimal circuit, in order to generate a sub-clock with the same phase shift from the high-speed ring oscillator, the load of the delay differential inverting amplifier circuit of each stage and the parasitic capacitance of the sub-clock wiring must be equal. There is a need to.
[0003]
Conventionally, in order to balance the load of the delay differential inverting amplifier circuit of each stage, voltage or current controlled differential ring 2 rows of delay differential inverting amplifier circuit of N stages on a semiconductor substrate constituting the oscillation circuit placed in the delay differential inverting amplifier circuit successive was placed next to each other in each column. With this arrangement, by the delay in wiring between the input and output of the delay differential inverting amplifier circuit of N stages constituting the differential ring oscillator circuit to a minimum, it can oscillate difference in high-frequency it is possible to realize the dynamic ring oscillator circuit.
[0004]
However, in the differential ring oscillator circuit that outputs multi Ike lock signal having a phase difference of such spacing required to achieve a high-speed serial communication is generally every other delay differential inverting amplifier circuit since the output elicit a multi-phase clock signal, Ru required der is Succoth pull out the respective signals from the row of arranged delay differential inverting amplifier circuit in two rows. Therefore, according to the conventional arrangement and wiring, wire routing of multi-phase clock signals result in longer, it has been difficult to align uniformly the parasitic capacitance of the multiphase clock signal distribution lines for one row. Also, wiring of the multi-phase clock signal wirings, because that must be performed at a relatively wide region around the differential ring oscillator circuit, the area of the semiconductor substrate has a problem that it has the increased.
[0005]
[Problems to be solved by the invention]
Therefore, in view of the above, the present invention provides a method of extracting a multi-phase clock signal line from a ring oscillation circuit capable of oscillating at a high frequency, thereby deteriorating clock phase accuracy due to uneven parasitic capacitance of the multi-phase clock signal line. It is an object to realize a differential ring oscillation circuit and a multi-phase clock oscillator in which an increase in the substrate area is suppressed.
[0006]
[Means for Solving the Problems]
In the differential ring oscillation circuit according to the present invention, a plurality of stages of amplifier circuits constituting the ring oscillation circuit are arranged in two rows so that adjacent front and rear amplification circuits on the circuit are not adjacent on the semiconductor substrate. Further, the multi-phase clock oscillator according to the present invention is characterized in that all of the amplifier circuits from which the multi-phase clock signal is extracted are arranged in one of the columns. And
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0008]
FIG. 1 is a circuit diagram of a voltage-controlled differential ring oscillation circuit included in a multiphase clock oscillator according to an embodiment of the present invention, and shows an example of a voltage-controlled differential ring oscillation circuit with N = 8 stages. I have.
[0009]
In shown to voltage control differential ring oscillator circuit in FIG. 1, 101a-101h is the delay differential inverting amplifier circuit, 102 is an external input terminal of the control voltage of the delay time, 103 a control voltage source of the delay time It is.
[0010]
Each of the delayed differential inverting amplifier circuits 101a-101h has a differential input terminal pair 111 and a differential output terminal pair 112 , and the first delay differential inverting amplifier circuit 101a-101h has the first delay. The differential output terminal 112 of the differential inverting amplifier circuit 101a is connected to the differential input terminal 111 of the second delayed differential inverting amplifier circuit 101b, and the differential output terminal 112 of the second delayed differential inverting amplifier circuit 101b is connected. The differential output terminal 112 of the eighth delayed differential inverting amplifier circuit 101h is connected to the differential input terminal 111 of the third delayed differential inverting amplifier circuit 101c in order. It is cross-connected to the differential input terminal 111 of the inverting amplifier circuit 101a.
[0011]
By connecting in this manner, the delay differential inverting amplifier circuits 101a to 101h at each stage are provided with voltage controlled differential ring oscillator circuits having clocks from Φ1 to Φ16 attached to the differential output terminal pair 112 for convenience. Can be configured.
[0012]
Figure 2 shows the clock voltage waveform named from Φ1 obtained from the voltage controlled differential ring oscillator circuit 8 stages shown in Figure 1 to .phi.16. In FIG. 2, the horizontal axis represents time, and the vertical axis represents voltage.
[0013]
In the voltage-controlled differential ring oscillation circuit shown in FIG. 1 , 101a to 101h are delay differential inverting amplifier circuits . Therefore, as shown in FIG. The output is inverted with a delay of the determined unit delay time 201. In this case, the cycle time 202, which is the reciprocal of the oscillation frequency of the voltage-controlled differential ring oscillation circuit, is:
t _clock = t _delay × 2 × N = 16 × t _delay
It becomes.
[0014]
As is apparent from the above equation, the minimum value of the cycle time of the voltage controlled differential ring oscillator is determined by the unit delay time 201 of each stage and the number of stages. In order to obtain a high oscillation frequency when a control voltage that minimizes the delay time is applied, in addition to selecting the minimum number of stages of the delay differential inverting amplifier circuit required, in addition to the parasitic capacitance of the wiring connecting each stage Is required to be as small as possible and the unit delay time 201 is made as small as possible.
[0015]
Conventionally, when forming the voltage controlled differential ring oscillator circuit as shown in Figure 1 on a semiconductor substrate, like the circuit diagram shown in FIG. 1, except for the ends to place the entire two rows By arranging the delay differential amplifier circuits of each stage so as to be adjacent to each other, the length of the wiring connecting the stages is minimized, and the wiring capacitance as the load of the delay differential inverting amplifier circuit is evenly and minimized. Is designed.
[0016]
On the other hand, in order to realize high-speed serial communication, a multi-phase clock signal whose phases are shifted at equal intervals is required. The number of phases of the multiphase clock signal is determined by the serial number, the multi-phase clock signals generally 4-10 phase is required. Figure 2 is an output waveform of each stage of the put that voltage control differential ring oscillator circuit in this embodiment. Shown in the figure, among the clocks named from Φ1 to .phi.16, it will be described a method of selecting a clock necessary for high-speed serial communication.
[0017]
In this embodiment, in order to select the clock of N = 8 phase, taking a configuration of N = 8 stages. In general, an n-M stage configuration (where n is a positive integer) is possible for an M-phase clock, but as described above, the minimum value of the cycle time of the voltage-controlled differential ring oscillator circuit is since determined by the unit delay time 201 and number of stages, but n = 1 is a minimum necessary number of stages are generally selected to obtain a high oscillation frequency required by the serial communication, n> for 1 However, the effect of the present application is effective.
[0018]
Since equal intervals are required multi-phase clock signals whose phases are shifted, it will select the clock shift by the phase time period divided by the cycle time 202 at 8. As a result, Φ1, Φ 3, Φ 5 ,. . . , A method of selecting a multi-phase clock signal to odd-numbered clocks Φ 15, Φ2, Φ 4, Φ 6 ,. . . , Becomes to select either of the two ways of how to select the even-numbered clock [Phi 16, in the following the present embodiment, Φ1, Φ 3, Φ 5 ,. . . , Φ 15 will be described as a multi-phase clock signal . Of course, even if you select the even-numbered clock, it is possible to obtain the same effect as this embodiment.
[0019]
FIG. 3 shows an example of a multi-phase clock oscillator including a voltage-controlled differential ring oscillation circuit including an amplifier circuit for outputting an 8-phase multi-phase clock signal. In addition to the voltage controlled differential ring oscillator circuit shown in FIG. 1, selected Φ1, Φ3, Φ5,. . . , .PHI.15 are added as amplification circuits 301a to 301h necessary to output the odd-numbered clocks as multiphase clock signals.
[0020]
As described above, the parasitic capacitance of the wiring connecting each stage of the voltage controlled differential ring oscillation circuit must be as small as possible. Therefore, when arranging the circuit of FIG. 3 on a semiconductor substrate, it is required to arrange the whole circuit so that the lead line 302 to the amplifier circuits 301a to 301h of the multiphase clock signal is as short as possible.
[0021]
FIG. 4 shows a conventional arrangement on a semiconductor substrate. In Figure 4, disposed in two rows a voltage controlled differential ring oscillator circuit in the whole, the delay differential amplifier circuits of each stage, except the ends are arranged so as to be adjacent. Next , problems of the conventional example will be described.
[0022]
In Figure 4, like the circuit diagram of FIG. 3, arranged overall in two rows, the delay differential amplifier circuits of each stage, except the ends are arranged so as to be adjacent. In addition, as lead lines 302 to the amplifier circuit 301a-301h of the multi-phase clock signal is as short as possible, are arranged amplifying circuit 301a-301h of the multiphase clock signal on the side of the delay differential amplifier circuits 101a-101h . By taking the above into consideration, the wiring parasitics related to the wiring connecting each stage are evenly and minimized, but the polyphase clock signal itself is output separately above and below the voltage controlled differential ring oscillator. Therefore, a large parasitic capacitance difference occurs between the wirings 401a and 402b.
[0023]
Since it phases of the multiphase clock signal is equal intervals accurately is very important in high-speed serial communication, it is necessary to pay close attention with regard routed on a semiconductor substrate of a multi-phase clock signal wirings . In other words, electromagnetic / capacitive coupling of the respective multiphase clock signals, must always pay attention so as to be equal, respectively between the multiphase clock signals. In general, there is no need to run another signal line which is electromagnetically / capacitively coupled to the multi-phase clock signal wiring, or to arrange a semiconductor active element below the wiring. Therefore, as shown in FIG. 4, the routing of the multi-phase clock signal line to a relatively wide area around the voltage-controlled differential ring oscillation circuit causes another problem that a large semiconductor substrate area is required. .
[0024]
FIG. 5 shows an example of an arrangement on a semiconductor substrate of the multi-phase clock oscillator according to the embodiment of the present invention, which has been devised to overcome the above problem.
[0025]
In FIG. 5 , as in the circuit diagram of FIG. 3 , the whole is arranged in two columns , but the stages of the differential differential amplifier circuit are not adjacent to each other, and the arrangement columns are exchanged for each stage. In this way, the lead line 302 to the amplifier circuit 301a-301h of the multiphase clock signals always well if pulled out from the output of one of the delay differential amplifier circuit of a column, the voltage control transistor all multi-phase clock signal It is possible to output from only one of the ring oscillation circuits, and it is possible to easily equalize the difference in the parasitic capacitance of the routing line 401.
[0026]
For comparison with the conventional example, FIG. 6A shows the arrangement of each stage in the voltage-controlled differential ring oscillation circuit of the present application, and FIG. The arrangement of the columns is shown side by side.
[0027]
Compared with the conventional example, the wiring length connecting each stage is longer, but it is almost the same as the wiring between the delay differential inverting amplifier circuits at both ends in the conventional example. The arrangement of the present invention does not degrade the high-frequency characteristics of the voltage-controlled differential ring oscillation circuit using the circuit.
[0028]
Figure 7 shows an example of a voltage-controlled differential ring oscillator circuit N = 10 stages.
[0029]
FIG. 8 shows an example of the delayed differential inverting amplifier circuit constituting the voltage controlled differential ring oscillator circuit 100. Here , 801 and 802 are voltage variable resistors, 803 and 804 are MOS transistors, and 805 is a low current source. 806 and 807 are first and second differential input terminals, respectively, and 808 and 809 are first and second differential output terminals, respectively. 810 is a delay time control voltage input terminal. Although the present example is a delayed differential inverting amplifier circuit using MOS transistors, the present invention is effective and feasible for a delayed differential inverting amplifier circuit using a semiconductor integrated device other than this example.
[0030]
In the above embodiments, the voltage-controlled differential ring oscillator circuit using the voltage-controlled delayed differential inverting amplifier circuit has been described. However, the present invention relates to a current-controlled delayed differential inverting amplifier circuit. is intended also feasible effective and the current control transistor ring oscillator circuit using a voltage control differential ring oscillator circuit without being limited to, freely within the range described in the claims Deformable and changeable.
[0031]
【The invention's effect】
According to the present invention, a multi-phase clock signal at equal intervals necessary for realizing high-speed serial communication is transmitted from only one of the two columns of the delay differential inversion amplifier circuits formed on the semiconductor substrate. Since it is possible to draw out, it is possible to suppress the unevenness of the parasitic capacitance of the multi-phase clock signal wiring. Further, since the wiring delay of each stage can be kept small as in the conventional example, a voltage or current control differential ring oscillation circuit and a multiphase clock oscillator capable of oscillating at a high frequency can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a voltage-controlled differential ring oscillation circuit included in a multi-phase clock oscillator according to the present invention.
FIG. 2 is a diagram showing an output waveform of the voltage controlled differential ring oscillation circuit shown in FIG.
FIG. 3 is a circuit diagram showing a voltage-controlled differential ring oscillator and an amplifier included in the multi-phase clock oscillator according to the present invention.
FIG. 4 is a diagram showing an example of arrangement of the circuit of FIG. 3 based on a conventional method.
FIG. 5 is a diagram showing an example of arrangement of the circuit of FIG. 3 according to the present invention.
FIG. 6 is a diagram showing a comparison between the present invention and a conventional example.
FIG. 7 is a diagram showing an embodiment of the present invention when N = 10 stages.
FIG. 8 is a circuit diagram showing an example of a delayed differential inverting amplifier circuit used in an embodiment of the present invention.
[Explanation of symbols]
100 voltage controlled differential ring oscillator circuit 101 output terminal pair of the input terminal pair 112 delay difference Dozo width circuit input terminal 103 a control voltage source 111 delay difference Dozo width circuit of the control voltage of the delay difference Dozo width circuit 102 delay 201 delay difference Dozo width circuit cycle time 301 multiphase clock signal amplifier circuit of the unit delay time 202 the voltage controlled differential ring oscillator circuit 302 multiphase clock signal lead lines 401 multiphase clock signal wiring 801 voltage variable resistor 802 voltage Variable resistor 803 First MOS transistor 804 Second MOS transistor 805 Low current source 806 First differential input terminal 807 Second differential input terminal 808 First differential output terminal 809 Second differential output Terminal 810 Input terminal for control voltage of delay time

Claims

A differential ring oscillator circuit that have a delayed differential amplifier circuit of N stages performing an oscillation operation are connected in a ring shape (N is an integer of 4 or more), each of the delay differential amplifier circuit of the N-stage , A set of differential signal input terminals for inputting differential signals, and a set of differential signal output terminals for outputting differential signals , wherein the N-stage delayed differential amplifier circuit is provided in a semiconductor substrate. divided into the first row and the second row is parallel to the predetermined direction are arranged, the delay differential amplifier circuits each disposed in the second row, arranged in the first column is a differential signal input terminal connected to the differential signal output terminals of Taso respectively one delay differential amplifier circuit, the first are arranged in columns of one of the other delay differential amplifier circuit Having a differential signal output terminal connected to a differential signal input terminal , the differential ring oscillator circuit,
A plurality of amplifier circuits, each connected to a differential signal output terminal of a delay differential amplifier circuit arranged in the first column, and the delay differential amplifier circuit arranged in the first column, A plurality of outgoing lines respectively arranged in a plurality of amplifying circuits, the plurality of amplifying circuits,
A multi-phase clock oscillator comprising:

A differential ring oscillation circuit including an N-stage delayed differential amplifier circuit connected in a ring shape and performing an oscillation operation (where N / 2 is an even number of 2 or more),
Each of the N-stage delayed differential amplifier circuits has a set of differential signal input terminals for inputting a differential signal, and a set of differential signal output terminals for outputting a differential signal ,
The N-stage delayed differential amplifier circuits are arranged in a first column and a second column parallel to a predetermined direction in the semiconductor substrate;
For m = 1,..., (N / 2-1),
When m is an odd number, the differential signal output terminal of the m-th delayed differential amplifier circuit of the first group of delayed differential amplifier circuits arranged in the first column is connected to the second column. the of the delay differential amplifier circuit arranged second groups (m + 1) th delay differential while being connected to the differential signal input terminal of the amplifier circuit, the first group of delay differential amplifier circuit (m + 1) -th delayed differential differential signal output terminal of the amplifier circuit, the differential signal input terminal of the m-th delay differential amplifier circuit of the delay differential amplifier circuit of the second group of the It is connected to,
When m is an even number, the differential signal output terminal of the m-th delayed differential amplifier circuit of the second group of differential differential amplifier circuits is connected to the differential signal output terminal of the first group of delayed differential amplifier circuits. (m + 1) -th while being connected to the differential signal input terminal of the delay differential amplifier circuit, the difference between the (m + 1) -th delayed differential amplifier circuit of the delay differential amplifier circuit of the second group Doshingo output terminals are connected to differential signal input terminals of the m-th delay differential amplifier circuit of the delay differential amplifier circuit of the first group,
The differential signal output terminal of the N / 2th delay differential amplifier circuit of the second group of delay differential amplifier circuits is connected to the N / 2th delay differential amplifier circuit of the first group of delay differential amplifier circuits. against the differential signal input terminal of the delay differential amplifier circuit are continued,
A differential signal output terminal of a first delay differential amplifier circuit of the second group of differential differential amplifier circuits is connected to a first delay differential amplifier circuit of the first group of differential differential amplifier circuits. is connected to the differential signal input terminal of the amplifier circuit comprising,
Differential ring oscillation circuit.

A differential ring oscillation circuit including an N-stage delay differential amplifier circuit connected in a ring shape and performing an oscillation operation (where N / 2 is an odd number of 3 or more),
Each of the N-stage delayed differential amplifier circuits has a set of differential signal input terminals for inputting a differential signal, and a set of differential signal output terminals for outputting a differential signal ,
The N-stage delayed differential amplifier circuits are arranged in a first column and a second column parallel to a predetermined direction in the semiconductor substrate;
For m = 1,..., (N / 2-1),
When m is an odd number, the differential signal output terminal of the m-th delayed differential amplifier circuit of the first group of delayed differential amplifier circuits arranged in the first column is connected to the second column. the of the delay differential amplifier circuit arranged second groups (m + 1) th delay differential while being connected to the differential signal input terminal of the amplifier circuit, the first group of delay differential amplifier circuit (m + 1) -th delayed differential difference Doshingo output terminal of the amplifier circuit, the differential signal input terminal of the m-th delay differential amplifier circuit of the delay differential amplifier circuit of the second group of the It is connected to,
When m is an even number, the differential signal output terminal of the m-th delayed differential amplifier circuit of the second group of differential differential amplifier circuits is connected to the differential signal output terminal of the first group of delayed differential amplifier circuits. (m + 1) -th while being connected to the differential signal input terminal of the delay differential amplifier circuit, the difference between the (m + 1) -th delayed differential amplifier circuit of the delay differential amplifier circuit of the second group Doshingo output terminals are connected to differential signal input terminals of the m-th delay differential amplifier circuit of the delay differential amplifier circuit of the first group,
The differential signal output terminal of the N / 2th delay differential amplifier circuit of the first group of delay differential amplifier circuits is connected to the N / 2th delay differential amplifier circuit of the second group of delay differential amplifier circuits. against the differential signal input terminal of the delay differential amplifier circuit are continued,
A differential signal output terminal of a first delay differential amplifier circuit of the second group of differential differential amplifier circuits is connected to a first delay differential amplifier circuit of the first group of differential differential amplifier circuits. is connected to the differential signal input terminal of the amplifier circuit comprising,
Differential ring oscillation circuit.

A multi-phase clock oscillator comprising the differential ring oscillator circuit according to claim 2 and a plurality of amplifier circuits,
The plurality of amplifier circuits are connected to differential signal output terminals of a first group of delay differential amplifier circuits arranged in the first column, respectively, and a first group of delay circuits arranged in the first column. A plurality of lead lines are respectively provided from the differential amplifier circuit side to the plurality of amplifier circuits,
Polyphase clock oscillator.