522549 A7 __ B7 五、發明説明（1 ) 【技術領域】 (請先閱讀背面之注意事項再填寫本頁) 本發明爲關於一般性半導體積體電路.，尤其關於產生 多相時脈訊號所用包含環形振盪電路之半導體積體電路。 【背景技術】 近年，於裝置間之訊號傳送，採用高速之小振幅串聯 訊號之方式。若依據此方式，將數位訊號並聯傳輸時比較 ’除了些許電纜即可之外，可抑制在數位訊號之傳輸所發 生之 Ε Μ I ( electromagnetic interference :電磁妨礙雜訊） 〇 欲實現高速串聯通信時，於發送側，裝設不僅同步於 基礎時脈訊號並且使用具有等間隔相位差之多相副時脈訊 號（於本申請書稱爲多相時脈訊號）將並聯資料變換爲串 聯資料之並聯-串聯變換電路。爲此裝設產生多相時脈訊 號之多相時脈產生電路，必須將此多相時脈訊號供給於並 聯—串聯變換電路。 丨 經濟部智慧財產局員工消費合作社印製 作爲多相時脈產生電路，例如，使用將多段之延遲差 動反轉放大電路連接成環狀所構成之電壓或電流控制之差 動環形振盪電路。依據此差動環形振盪電路，將具有等間 隔相位差之多相時脈訊號就可容易從多段之延遲差動反轉 放大電路拉出。欲從高速差動環形振盪電路正確地產生具 有等間隔相位差之多相時脈訊號時，不僅將多段之延遲差 動反轉放大電路之負荷成爲均等，並且，必須將多相時脈 訊號配線之浮遊電容成爲均等。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -4- 522549 A7 B7 五、發明説明（2 ) (請先閲讀背面之注意事項再填寫本頁) 以往，欲使各段之延遲差動反轉放大電路之負荷變成 均等時，就將構成差動環形振盪電路之N段延遲差動反轉 放大電路在半導體基板上排列成2列，於各列使所連續之 延遲差動反轉放大電路相鄰。藉其，使N段延遲差動反轉 放大電路之輸出與輸入間之配線之延遲成爲最小，就可實 現以高周波可振盪之差動環形振盪電路。 然而’欲實現局速串聯通信，輸出所需具有等間隔相 位差之多相時脈訊號之差動環形振盪電路，一般爲從相隔 一個之延遲差動反轉放大電路之輸出拉出多相時脈訊號， 所以，從配置成2列之延遲差動反轉放大電路各列拉出訊 號。因此，依據以往之配置及配線時，關於一方之列係多 相時脈訊號之繞拉配線就變長，欲使多相時脈訊號配線之 浮遊電容保持爲均等將變成困難。又，此多相時脈訊號配 線之繞拉，因必須在差動環形振盪電路周圍之較廣寬領域 進行，所以發生半導體基板之面積有變大的問題。 【發明之揭示】 經濟部智慧財產局員工消費合作社印製 於是，鑑於上述諸問題，本發明之目的係從可使用高 周波振盪之環形振盪電路拉出多相時脈訊號配線時，提供 一種可抑制起因於多相時脈訊號配線之浮遊電容不均等之 時脈相位精度劣化或增加基板面積之半導體積體電路。 爲了解決以上問題，關於本發明之第1觀點之半導體積體 電路，係一種連接成環形進行振盪動作之N段放大電路（ N係自然數），在半導體基板分爲複數列配置有N段之放 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) 一 " -5- 522549 A7 B7_ 五、發明説明（3 ) (請先閱讀背面之注意事項再填寫本頁) 大電路，將m視爲2以上N以下之任意整數時，具有：於 各列第（m — 1 )段之放大電路與第m段之放大電路被配 置成不相鄰接之N段放大電路，與從配置於複數列中之1 列放大電路分別取出複數輸出訊號所用之複數配線。 又，關於本發明之第2觀點之半導體積體電路，因被 連接成環狀而藉進行振盪動作，屬於輸出等相位間隔之Μ 相時脈訊號之Ν段放大電路（Μ、Ν係自然數，M S Ν ) ，而具有：於半導體基板分爲2列所配置之Ν段放大電路 ，與只從配置於2列中一方列之放大電路分別取出Μ相時 脈訊號所需之Μ個配線。 依據本發明，於半導體基板分爲複數列所配置之Ν段 放大電路之1列能夠取出複數輸出訊號（多相時脈訊號） 形成有複數配線，所以，將多相時脈訊號配線之浮遊電容 成爲均等，就可抑制時脈相位精度之劣化或增加基板面櫝 【實施發明之最佳形態】 經濟部智慧財產局員工消費合作社印製 第1圖係表示關於包含本發明第1實施形態之半導體 積體電路之電壓控制差動環形振盪電路之電路圖。 如第1圖所示，電壓控制差動環形振盪電路1 0〇， 係包括Ν段（於本實施形態定爲8段）之延遲差動反轉放 大電路1 0 1 a〜1 〇 1 h，與控制在各段延遲差動反轉 放大電路之延遲時間所用之控制端子1 0 2。對於控制端 子1 0 2連接有控制電壓源1 0 3。 本紙張尺度適用中國國家標準（ CNS ) A4規格（210X297公釐） ' _6_ 522549 A7 B7 五、發明説明（4 ) (請先閲讀背面之注意事項再填寫本頁) 如第2 A圖所示，各段之延遲差動反轉放大電路 1〇1 ’係具有：非反轉輸入端子2 〇 6與反轉輸入端子 2〇7 ’及非反轉輸出端子2 〇 8，與反轉輸出端子 2 〇 9，於延遲差動反轉放大電路1 〇 1之延遲時間·爲 由施加於控制電壓輸入端子2 1 〇之控制電壓V C所控制 。按，於延遲差動反轉放大電路1 0 1之延遲時間，也可 以由控制電流加以控制。 於第2 B圖表不各段之延遲差動反轉放大電路1〇1 之內部電路。延遲差動反轉放大電路1 〇 1係包含可變電 壓用之電阻器2〇1 、202 ，與MOS電晶體203、 經濟部智慧財產局員工消費合作社印製 2 0 4，與恒電流源2 〇 5。延遲差動反轉放大電路 1〇1係將放大施加於非反轉輸入端子2 〇 6之訊號與施 加於反轉輸入端子2 0 7之訊號差値所得到之差動訊號， 供給於非反轉輸出端子2 〇 8與反轉輸出端子2 0 9。藉 由施加於控制電壓輸入端子2 1 0之控制電壓V C，使 Μ〇S電晶體2 0 3、2 0 4之汲極·源極間電壓就發生 變化，藉此控制在延遲差動反轉放大電路1 〇 1之延遲時 間。按，於本實施例作爲放大元件使用Μ〇S電晶體，但 是，本發明也可適用於使用除此之外之放大元件之情形。 再參照第1圖時，電壓控制差動環形振盪電路1 〇〇 ，係將8段延遲差動反轉放大電路1 〇 1 a〜1 〇 1 h連 接成環狀者。各段之延遲差動反轉放大電路，係具有差動 輸入端子對1 0 4與差動輸出端子對1 〇 5。第1段延遲 差動反轉放大電路1 0 1 a之差動輸出端子對1 〇 5爲連 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -7- 522549 A7 B7 五、發明説明（5 ) ' ~~~ (請先閲讀背面之注意事項再填寫本頁) 接於第2段之延遲差動反轉放大電路1 〇 1 b之差動輸入 έ而子1 〇 4 ’弟2段延遲差動反轉放大電路1 q 1 ^之产 動_出端子對1 0 5爲連接於第3段之延遲差動反轉放大 電路1 0 1 c之差動輸入端子1 〇 4。以下同樣地連接， 最後之第8段延遲差動反轉放大電路1 〇 1 h之差動輸出 端子對1 0 5爲交叉連接於第1段之延遲差動反轉放大電 路1 0 1 a之差動輸入端子1 〇 4。似此，連接成環狀之 8段延遲差動反轉放大電路1 〇 1 a〜1 〇 1卜，係從各 個差動輸出端子對1 0 5輸出時脈訊號φ 1〜φ 1 6 ^ 於第3圖表示時脈訊號Φ 1〜φ 1 6之電壓波形。於 第3圖，橫軸係表示時間，縱軸係表示電壓。各段之延遲 差動反轉放大電路係對於所輸入之訊號，只延遲由所施加 .之控制電壓V C而定之單位延遲時間T DELAY，而反轉輸出 訊號。此時’於由N段之延遲差動反轉放大電路所構成之 差動環形振盪電路，屬於振盪頻率逆數之周期期間 T CLOCK，係以下式表不。 經濟部智慧財產局員工消費合作社印製522549 A7 __ B7 V. Description of the Invention (1) [Technical Field] (Please read the precautions on the back before filling out this page) The present invention relates to general semiconductor integrated circuits. In particular, it is used to generate multi-phase clock signals. Semiconductor integrated circuit of ring oscillator circuit. [Background Art] In recent years, high-speed, small-amplitude serial signals are used for signal transmission between devices. According to this method, when digital signals are transmitted in parallel, it can be compared to 'except for a few cables, and EMI (electromagnetic interference: electromagnetic interference noise) which occurs in the transmission of digital signals can be suppressed. 〇 When high-speed serial communication is desired On the transmitting side, a parallel connection that converts parallel data to serial data using a multi-phase sub-clock signal (referred to as a multi-phase clock signal in this application) not only synchronized with the basic clock signal but also with an equally spaced phase difference is installed. -Series conversion circuit. For this purpose, a multi-phase clock generating circuit for generating a multi-phase clock signal is installed. This multi-phase clock signal must be supplied to a parallel-series conversion circuit.丨 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs As a multi-phase clock generation circuit, for example, a voltage or current controlled differential ring oscillation circuit formed by connecting multiple stages of delayed differential inversion amplifier circuits into a loop. According to this differential ring oscillator circuit, a multi-phase clock signal having an equally spaced phase difference can be easily pulled out from a multi-stage delayed differential inversion amplifier circuit. To correctly generate multi-phase clock signals with equally spaced phase differences from a high-speed differential ring oscillator circuit, not only the load of the multi-stage delay differential inversion amplifier circuit is equalized, but also the multi-phase clock signals must be wired. The floating capacitance becomes equal. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -4- 522549 A7 B7 V. Description of the invention (2) (Please read the precautions on the back before filling this page) In the past, the When the load of the delay differential inversion amplifier circuit becomes equal, the N-stage delay differential inversion amplifier circuits constituting the differential ring oscillation circuit are arranged in two rows on the semiconductor substrate, and the successive delay differentials are arranged in each row. Inverting amplifier circuits are adjacent. By using this, the delay of the wiring between the output and the input of the N-stage delay differential inversion amplifier circuit is minimized, and a differential ring oscillator circuit that can oscillate with a high frequency can be realized. However, in order to achieve local-speed serial communication, the differential ring oscillator circuit required to output multi-phase clock signals with equally spaced phase differences is generally when the multi-phase is pulled from the output of a delay differential inversion amplifier circuit separated by one. The pulse signal, so, the signal is pulled out from each column of the delayed differential inversion amplifier circuit arranged in two columns. Therefore, according to the previous configuration and wiring, the winding wiring of one series of multi-phase clock signals becomes longer, and it will become difficult to keep the floating capacitance of the multi-phase clock signal wiring equal. In addition, since the winding of the multi-phase clock signal wiring must be performed in a relatively wide area around the differential ring oscillator circuit, there is a problem that the area of the semiconductor substrate becomes large. [Disclosure of Invention] Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics. In view of the above problems, the object of the present invention is to provide a multi-phase clock signal wiring that can suppress the This is a semiconductor integrated circuit that is caused by uneven clock phase accuracy due to uneven floating capacitance of multi-phase clock signal wiring or increased substrate area. In order to solve the above problems, the semiconductor integrated circuit according to the first aspect of the present invention is an N-segment amplifier circuit (N is a natural number) connected in a ring to perform an oscillating operation. The paper size of this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm)-"-5- 522549 A7 B7_ V. Description of the invention (3) (Please read the precautions on the back before filling this page) Large circuit, When m is regarded as any integer from 2 to N, it has: the amplifier circuits in the (m-1) th stage and the amplifier circuits in the mth stage are arranged as non-adjacent N-stage amplifier circuits, and One column of amplifying circuits arranged in the plurality of columns respectively takes out the plural wirings for the plural output signals. In addition, the semiconductor integrated circuit according to the second aspect of the present invention is an N-stage amplifier circuit (M and N are natural numbers) that output an M-phase clock signal having an equal phase interval by performing an oscillating operation by being connected in a ring shape. , MS Ν), and has: N segment amplifier circuits arranged in two rows on the semiconductor substrate, and M wirings required for extracting phase M clock signals from amplifier circuits arranged in only one of the two rows. According to the present invention, a plurality of output signals (multi-phase clock signals) can be taken out in one column of the N-segment amplifying circuit configured by dividing the semiconductor substrate into a plurality of columns, and a plurality of wirings are formed. Therefore, the floating capacitors of the multi-phase clock signals are wired. If it is equal, the degradation of clock phase accuracy can be suppressed or the substrate surface can be increased. [The best form of implementing the invention] Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The first picture shows the semiconductor including the first embodiment of the present invention. Circuit diagram of voltage control differential ring oscillator circuit of integrated circuit. As shown in FIG. 1, the voltage-controlled differential ring oscillation circuit 100 is a delay differential inversion amplifier circuit including an N segment (determined as 8 segments in this embodiment) 1 0 1 a to 1 〇1 h, The control terminal is used to control the delay time of the differential inversion amplifier circuit at each stage. A control voltage source 103 is connected to the control terminal 1 102. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) '_6_ 522549 A7 B7 V. Description of the invention (4) (Please read the precautions on the back before filling this page) As shown in Figure 2A, The delay differential inversion amplifying circuit 1001 'of each stage includes: non-inverting input terminal 2 〇6 and inverting input terminal 207' and non-inverting output terminal 2 〇8, and inverting output terminal 2 〇9, the delay time of the delay differential inversion amplifier circuit 1 〇1 is controlled by the control voltage VC applied to the control voltage input terminal 2 1 〇. Pressing, the delay time of the delay differential inversion amplifier circuit 101 can also be controlled by the control current. The internal circuit of the delay differential inverting amplifier circuit 101 in each stage of the second B diagram. The delayed differential inverting amplifier circuit 101 is composed of resistors 201 and 202 for variable voltage. It is printed with MOS transistor 203, the Intellectual Property Bureau of the Ministry of Economic Affairs, the Consumer Cooperatives, and the constant current source. 〇5. The delayed differential inversion amplifier circuit 101 is a differential signal obtained by amplifying the difference between the signal applied to the non-inverting input terminal 2 and the signal applied to the inverting input terminal 207, and supplying it to the non-inverting input terminal. The rotation output terminal 2 〇8 and the reverse output terminal 209. The control voltage VC applied to the control voltage input terminal 2 10 causes the voltage between the drain and the source of the MOS transistor 2 0 3, 2 0 4 to change, thereby controlling the delay differential inversion Delay time of amplifier circuit 〇1. According to this embodiment, a MOS transistor is used as an amplification element in this embodiment. However, the present invention can also be applied to a case where other amplification elements are used. Referring again to Fig. 1, the voltage-controlled differential ring oscillator circuit 100 is a circuit in which an 8-stage delay differential inversion amplifier circuit 1 〇 1 a to 1 〇 1 h is connected. The delay differential inversion amplifier circuit of each stage has a differential input terminal pair 104 and a differential output terminal pair 105. The differential output terminal pair 1 of the first stage delayed differential inversion amplifier circuit 1 0 1 a is connected to the paper size and applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -7- 522549 A7 B7 V. Description of the invention (5) '~~~ (Please read the notes on the back before filling in this page) The differential input of the delayed differential inversion amplifier circuit 1 〇1 b followed by the second paragraph 1 〇4 ′ The 2nd stage delay differential inversion amplifier circuit 1 q 1 ^ output_output terminal pair 1 0 5 is the differential input terminal 1 0 1 c connected to the 3rd stage delay differential inversion amplifier circuit 1 〇4 . Connect the same in the following. The differential output terminal pair 1 0 of the 8th stage delay differential inversion amplifier circuit 1 0 1 is the delay differential inversion amplifier circuit 1 0 1 a that is cross-connected to the 1st stage. Differential input terminal 1 〇4. Similarly, an 8-stage delayed differential inversion amplifier circuit connected in a loop 1 〇1 a ~ 1 〇1 Bu, is to output a clock signal φ 1 ~ φ 1 6 ^ from each differential output terminal pair 105. Figure 3 shows the voltage waveforms of the clock signals Φ 1 to φ 16. In Fig. 3, the horizontal axis represents time and the vertical axis represents voltage. Delay of each stage The differential inversion amplifier circuit only delays the unit delay time T DELAY determined by the applied control voltage V C for the input signal, and inverts the output signal. At this time, the differential ring oscillation circuit composed of the N-stage delay differential inversion amplifier circuit belongs to the period T CLOCK of the inverse period of the oscillation frequency, which is expressed by the following formula. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
Tclock = 2 XNXTdelay = 1 6 XTdelay · ( 1 ) 如.（1 )式所示，差動環形振盪電路之周期期間 T CLOCK ，係由延遲差動反轉放大電路之段數N，與於各段 之單位延遲時間所決定。於這種差動環形振盪電路，施加 控制電壓使延遲時間變成最小時欲得到高振盪頻率時，不 僅將延遲差動反轉放大電路之段數成爲所需之最小限度， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） " -8 - 522549 A7 B7 五、發明説明（6 ) 並且’要求設計成使延遲差動反轉放大電路之輸出配線之 浮遊電容變小，單位延遲時間T DELAY變小。 (請先閱讀背面之注意事項再填寫本頁) 然而，欲實現高速串聯通信時，就需要具有等間隔相 位差之多相時脈訊號。多相時脈訊號之相數，係由對應於 一個並聯資料之串聯資料數所決定，一般爲需要4〜1 〇 相之多相時脈訊號。因而，從第3圖所示時脈訊號φ 1〜 Φ 1 6之中，選擇具有進行高速串聯通信所需等間隔相位 差之多相時脈訊號之方法說明如下。 一般，欲製作Μ相之時脈時，可使用具有n = η X Μ 段之延遲差動反轉放大電路之差動環形振盪電路（η係自 然數）◦然而，如上述，於差動環形振盪電路之周期期間 T cueK之最小値，因由延遲差動反轉放大電路之段數與各 段之單位延遲時間T DELAY所決定，所以，欲得到於串聯通 信所需之高振盪頻率時，段數爲所需最小限度較佳。因此 ，一般爲選擇η = 1之條件，但是本發明也可適用於η > 經濟部智慧財產局員工消費合作社印製 1之情形。於本實施形態，η = 1，亦即成爲N = Μ，爲 了製作8相之時脈訊號所需成爲具有8段之延遲差動反轉 放大電路之構成。 從這些延遲差動反轉放大電路所輸出之時脈訊號之中 ，爲了獲得具有等間隔相位差之8相多相時脈訊號，選擇 只有周期期間丁 u〇ck除以8之時間之相位不同之時脈訊號 。如第3圖所示，作爲這種時脈訊號可列舉Φ 1、Φ 3、 Φ 5.....Φ 1 5之第奇數時脈訊號，或Φ 2、Φ 4 、Φ 6.....Φ 1 6第偶數時脈訊號之任一。於本實 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -9- 522549 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（7) 施形態，雖然選擇第奇數之時脈訊號，但是選擇第偶數之 時脈訊號時也可得到同樣之效果。 第4圖係表示包含關於本發明之第1實施形態之半導 體積體電路之電壓控制差動環形振盪電路及緩衝電路之電 路圖。於此，在第1圖所示電壓差動環形振盪電路1〇0 ，爲了將第奇數之時脈訊號Φ 1、Φ 3、Φ 5..... Φ 1 5作爲多相時脈訊號輸出所需附加有8個緩衝電路 3〇la〜3〇lh。 欲減少延遲差動反轉放大電路之輸出配線之浮遊電容 ，將第4圖所示電路，形成於半導體基板上時，需要進行 配置及配線，使自延遲差動反轉放大電路1 0 1 a〜 1〇1 h到緩衝電路3 0 1 a〜3 0 1 h之多相時脈訊號 之拉出線3 0 2 a〜3 0 2 d儘量能夠變短，。 爲此，可想到如第5圖所示之配置及配線。如第5圖 所示，配置有2列延遲差動反轉放大電路1 0 1 a〜 1 0 1 h。於各例，除去兩端而連續之延遲反轉放大電路 爲配置成相鄰接。又，緩衝電路3 0 1 a〜3 0 1 h係使 拉出線3 0 2 a〜3 0 2 d儘量變短，配線於延遲差動反 轉放大電路1 0 1 a〜1 0 1 h之附近。因配置及配線成 這樣，連結各段之配線長度就變成最短，可將因連結各段 之配線所發生之配線寄生均等，且，變成最小。然而，依 據這種配線時，從緩衝電路3 0 1 a〜3 0 1 h對於並聯 一串聯變換電路4 0 2供給時脈訊號Φ 1、Φ 3、Φ 5、 • ··、Φ 1 5所用之配線，因分爲電壓控制差動環形振 (請先閲讀背面之注意事項再填寫本頁) 衣·Tclock = 2 XNXTdelay = 1 6 XTdelay · (1) As shown in equation (1), the period T CLOCK of the differential ring oscillation circuit is the number of segments N of the delay inversion amplifier circuit, and The unit delay time is determined. In this type of differential ring oscillator circuit, when a control voltage is applied to minimize the delay time to obtain a high oscillation frequency, not only the number of segments of the delay differential inversion amplifier circuit is required to the minimum, this paper scale is applicable to China Standard (CNS) A4 specification (210X297 mm) " -8-522549 A7 B7 V. Description of the invention (6) and 'required to make the floating capacitance of the output wiring of the delay differential inversion amplifier circuit smaller and the unit delay The time T DELAY becomes smaller. (Please read the precautions on the back before filling out this page.) However, to achieve high-speed serial communication, multiphase clock signals with equally spaced phase differences are required. The number of phases of a multi-phase clock signal is determined by the number of serial data corresponding to one parallel data. Generally, a multi-phase clock signal with 4 to 10 phases is required. Therefore, from among the clock signals φ 1 to Φ 16 shown in Fig. 3, a method of selecting a multi-phase clock signal having an equally spaced phase difference required for high-speed serial communication is described below. Generally, to make the clock of phase M, a differential ring oscillator circuit (n is a natural number) with a delay differential inversion amplifier circuit with n = η X Μ can be used. However, as described above, in the differential ring The minimum value of T cueK during the period of the oscillation circuit is determined by the number of segments of the delay differential inversion amplifier circuit and the unit delay time T DELAY of each segment. Therefore, when the high oscillation frequency required for series communication is obtained, the segment The number is preferably the minimum required. Therefore, the condition of η = 1 is generally selected, but the present invention can also be applied to the case where η > is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In this embodiment, η = 1, that is, N = M. In order to make an 8-phase clock signal, a delay differential inversion amplifier circuit with 8 segments is required. From the clock signals output by these delayed differential inversion amplifier circuits, in order to obtain an 8-phase multi-phase clock signal with an equally spaced phase difference, only the phase during which the time period divided by u0ck divided by 8 is selected is different. Clock signal. As shown in Fig. 3, as such clock signals, Φ 1, Φ 3, Φ 5 ..... Φ 1 5 odd clock signals, or Φ 2, Φ 4, Φ 6 ... ..Φ 1 6 Any of the even-numbered clock signals. In the actual paper size, the Chinese National Standard (CNS) A4 specification (210X297 mm) is applied. -9- 522549 A7 B7 Printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economy Clock signal, but you can get the same effect when you select an even clock signal. Fig. 4 is a circuit diagram showing a voltage controlled differential ring oscillator circuit and a buffer circuit including a semiconducting volume circuit according to the first embodiment of the present invention. Here, in the voltage differential ring oscillation circuit 100 shown in FIG. 1, in order to output the odd-numbered clock signals Φ 1, Φ 3, Φ 5 ..... Φ 1 5 as a multi-phase clock signal output 8 buffer circuits 30a ~ 301lh are required. To reduce the floating capacitance of the output wiring of the delay differential inversion amplifier circuit, when the circuit shown in Figure 4 is formed on a semiconductor substrate, it is necessary to configure and wire the self-delay differential inversion amplifier circuit 1 0 1 a The pull-out lines of polyphase clock signals from 3 to 1 hr to buffer circuit 3 0 1 a to 3 0 1 h 3 0 2 a to 3 0 2 d should be as short as possible. For this reason, the arrangement and wiring shown in FIG. 5 are conceivable. As shown in Fig. 5, two columns of delayed differential inversion amplifier circuits 1 0 1 a to 1 0 1 h are arranged. In each example, the delay inversion amplifier circuits that are continuous except for both ends are arranged adjacent to each other. In addition, the buffer circuit 3 0 1 a to 3 0 1 h is to make the pull-out wires 3 0 2 a to 3 0 2 d as short as possible, and the wiring is connected to the delay differential inversion amplifier circuit 1 0 1 a to 1 0 1 h. nearby. Because of the arrangement and wiring, the length of the wiring connecting the segments becomes the shortest, and the wiring parasitics caused by the wiring connecting the segments can be equalized and minimized. However, according to this wiring, the clock signals Φ 1, Φ 3, Φ 5, • ·, Φ 1 5 are supplied from the buffer circuits 3 0 1 a to 3 0 1 h to the parallel-series converter circuit 4 0 2. The wiring is divided into voltage-controlled differential ring oscillators (please read the precautions on the back before filling this page).
、1T 1· 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -10- 522549 A7 B7 五、發明説明（9) ，可將多相時脈訊號配線之浮遊電容差値成爲均等。 (請先閲讀背面之注意事項再填寫本頁) 第7 A圖係用來說明第6圖所示8段延遲差動反轉放 大電路之配置所用之圖。第7 B圖係作爲比較例，用來說 明第5圖所示8段延遲差動反轉放大電路之配置所用之圖 。於第7 A、7 B圖標示於延遲差動反轉放大電路之號碼 # 1〜# 8係表示電路性地連接之順序。於第7 B圖所示 比較例，電路性地連接之順序與所配置之順序爲相符，與 此相對，第7 A圖所示本實施形態，係電路性地連接之順 序與所配置之順序爲相異。 從第7 A、7 B圖就可淸楚，於本實施形態，連接8 段之延遲差動反轉放大電路之配線長度，爲與於比較例之 配線長度相較變長。然而，於本實施形態之配線長度，係 與於比較例之延遲差動反轉放大電路之列兩端之配線長度 約略相同，所以，於本實施形態之電壓控制差動環形振盪 電路之高周波特性，爲不會遜於比較例之電壓控制差動環 形振盪電路。 經濟部智慧財產局員工消費合作社印製 茲就本發明之第2實施形態說明如下。第8圖係關於 本發明第2實施形態之半導體積體電路，用來說明包含於 電壓控制差動環形振盪電路之延遲差動反轉放大電路之配 置所用之圖。於本實施形態，將延遲差動反轉放大電路之 段數N定爲1 〇。於第8圖，標示於延遲差動反轉放大電 路之號碼# 1〜# 1 0係表示電路性地連接之順序。 如第8圖所示，即使增加環狀連接之延遲差動反轉放 大電路之段數，因將這些延遲差動反轉放大電路交互地配 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) ~ 一 ' -12- 522549 Μ 五、發明説明（1〇) (請先閱讀背面之注意事項再填寫本頁) 置成第1列與第2列，就可只從配置於第1列與第2列中 一方之延遲差動反轉放大電路拉出多相時脈訊號。因此， 就可使多相時脈訊號配線之浮遊電容成爲均等。 一般來說，使用於Ν段之延遲差動反轉放大電路時， 關於η = 1、2.....Ν，當m爲Ν / 2以下之奇數 時將第m段之放大電路在半導體基板配置在第1列之第m 個，m爲較N / 2爲大之奇數時將第m段之放大電路在半 導體基板配置在第1列之第（N+1 - m)個，m爲N/ 2以下之偶數時將第m段之放大電路在半導體基板配置在 第2列之第m個，m爲較N / 2爲大之偶數時將第m段之 放大電路在半導體基板配置在第2列之第（N + 1 - m ) 個即可。 以上，將本發明依據實施形態做了說明，但是，本發 明係並非限定於上述實施形態，可在申請專利範圍內所記 載之範圍內自由地變形、變更。 【產業上之利用可能性】 經濟部智慧財產局員工消費合作社印製 關於本發明之半導體積體電路，係可利用於使用具有 等間隔相位差產生多相時脈訊號所用之環形振盪電路之圖 像機器或電腦等。 圖式之簡單說明 本發明之優點及特徵，關聯以下詳細說明與圖式考察 就可淸楚。於這些圖式，相同參照號碼係指相同構成元件 i紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ~ -13- 522549 A 7 B7__ 五、發明説明（11) ο (請先閱讀背面之注意事項再填寫本頁) 第1圖係表示包含關於本發明之第1實施形態之半導 體積體電路之電壓控制差動環形振盪電路之電路圖。 第2 Α圖及第2 Β圖係表示包含於第1圖所示電壓控 制差動環形振盪電路延遲差動反轉放大電路之圖。 第3圖係表示從包含於第1圖所示電壓控制差動環形 振盪電路之延遲差動反轉放大電路所輸出之多相時脈訊號 之電壓波形之圖。 第4圖係表示包含關於本發明之第1實施形態之半導 體積體電路之電壓控制差動環形振盪電路及緩衝電路之電 路圖。 第5圖係表示從電壓控制差動環形振盪電路拉出多相 時脈訊號所需之配置及配線一例之圖。 第6圖係關於本發明之第1實施形態之半導體電路， 表示從電壓控制差動環形振盪電路拉出多相時脈訊號所需 之配置及配線之圖。 經濟部智慧財產局員工消費合作社印製 第7 A圖係用來說明第6圖所示延遲差動反轉放大電 路之配置之圖，第7 B圖係用來說明第5圖所示延遲差動 反轉放大電路之配置圖。 第8圖係在關於本發明之第2實施形態之半導體積體 電路，用來說明延遲差動反轉放大電路之配置圖。 元件對照表 10 0 電壓控制差動環形振盪電路 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ~ ' -14 - 522549 A7 B7 五、發明説明（12) 經濟部智慧財產局員工消費合作社印製 1 〇 1 a 1 0 1 h 延 遲 差 動 反轉放大電路 1 〇 2 控 制 端 子 2 〇 6 非 反 轉 輸 入 端 子 2 〇 7 反 轉 輸 入 端 子 2 〇 8 非 反 轉 輸 出 端 子 2 0 9 反 轉 輸 出 丄山 觸 子 2 1 〇 控 制 電 壓 輸 入 端 子 V C 控 制 電 壓 2 〇 1 5 2 〇 2 電 阻 器 2 〇 3 5 2 〇 4 Μ 〇 S 電 晶 體 2 0 5 恒 電 流 源 1 〇 4 差 動 輸 入 丄山 m 子 對 1 〇 5 差 動 輸 出 七山 m 子 對 Φ 1 Φ 1 5 時 脈 訊 號 3 〇 1 a 3 〇 1 h 緩 衝 電 路 3 〇 2 a 3 〇 2 d 拉 出 線 4 〇 1 a 4 〇 1 b 配 線 4 〇 2 並 聯 — 串 聯 變 換 電 路 (請先閱讀背面之注意事項再填寫本頁) 衣. 、11 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -15-、 1T 1 · This paper size applies the Chinese National Standard (CNS) A4 specification (210X297mm) -10- 522549 A7 B7 V. Description of the invention (9), the floating capacitance difference of multiphase clock signal wiring can be made equal . (Please read the precautions on the back before filling this page.) Figure 7A is a diagram used to explain the configuration of the 8-segment differential inversion amplifier circuit shown in Figure 6. Figure 7B is used as a comparative example to illustrate the configuration of the 8-stage delay differential inversion amplifier circuit shown in Figure 5. The numbers 7A and 7B are shown in the numbers of the delayed differential inversion amplifier circuits. # 1 to # 8 indicate the order of circuit connection. In the comparative example shown in FIG. 7B, the order of the circuit connection is in accordance with the arranged order. In contrast, the embodiment shown in FIG. 7A is the order of the circuit connection and the arranged order. Are different. As can be seen from Figures 7A and 7B, in this embodiment, the wiring length of the 8-segment delay differential inversion amplifier circuit is longer than the wiring length of the comparative example. However, the wiring length in this embodiment is approximately the same as the wiring length at both ends of the delay differential inversion amplifier circuit of the comparative example. Therefore, the high-frequency characteristics of the voltage-controlled differential ring oscillator circuit in this embodiment are high. Is a voltage-controlled differential ring oscillator circuit that is not inferior to the comparative example. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs The second embodiment of the present invention is described below. Fig. 8 is a diagram for explaining the configuration of the delay differential inversion amplifier circuit included in the voltage-controlled differential ring oscillator circuit in the semiconductor integrated circuit according to the second embodiment of the present invention. In this embodiment, the number of stages N of the delay differential inversion amplifier circuit is set to 10. In FIG. 8, the numbers # 1 to # 1 0 marked on the delay differential inversion amplifier circuit indicate the order of circuit connection. As shown in Figure 8, even if the number of segments of the delay differential inversion amplifier circuit connected in a loop is increased, these delay differential inversion amplifier circuits are interactively configured with this paper. The Chinese standard (CNS) A4 specification (210X297) is applicable. Mm) ~ 1 '-12- 522549 Μ 5. Description of the invention (1〇) (Please read the precautions on the back before filling out this page) Set the first column and the second column, you can only configure from the first column One of the delayed differential inversion amplifier circuits in the second row and the second row pulls out a multi-phase clock signal. Therefore, the floating capacitance of the multi-phase clock signal wiring can be made equal. In general, when using a delay differential inversion amplifier circuit in the N stage, regarding η = 1, 2 ..... N, when m is an odd number below N / 2, the amplifier circuit in the m stage is placed in the semiconductor The substrate is arranged at the mth column in the first column. When m is an odd number larger than N / 2, the amplifying circuit of the mth stage is arranged at the (N + 1-m) th column of the semiconductor substrate in the first column, where m is When the number is even below N / 2, the amplifier circuit in the m-th stage is arranged on the semiconductor substrate at the m-th column. When m is an even number larger than N / 2, the amplifier circuit in the m-th stage is arranged on the semiconductor substrate. (N + 1-m) in the second column is sufficient. As mentioned above, the present invention has been described based on the embodiments. However, the present invention is not limited to the above-mentioned embodiments, and can be freely deformed and changed within the scope described in the scope of the patent application. [Industrial use possibilities] The printed circuit of the semiconductor integrated circuit of the present invention printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics is a diagram of a ring oscillator circuit that can be used to generate multi-phase clock signals with equally spaced phase differences. Like machines or computers. Brief Description of the Drawings The advantages and features of the present invention can be clearly understood in connection with the following detailed description and examination of the drawings. In these drawings, the same reference numbers refer to the same constituent elements. The paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) ~ -13- 522549 A 7 B7__ 5. Description of the invention (11) ο (Please read first (Notes on the reverse side, please fill in this page) Figure 1 is a circuit diagram showing a voltage-controlled differential ring oscillator circuit of a semiconductor integrated circuit according to the first embodiment of the present invention. Figures 2A and 2B are diagrams showing delay differential inversion amplifier circuits included in the voltage-controlled differential ring oscillator circuit shown in Figure 1. Fig. 3 is a diagram showing a voltage waveform of a multi-phase clock signal output from a delayed differential inversion amplifier circuit included in the voltage controlled differential ring oscillator circuit shown in Fig. 1. Fig. 4 is a circuit diagram showing a voltage controlled differential ring oscillator circuit and a buffer circuit including a semiconducting volume circuit according to the first embodiment of the present invention. Fig. 5 is a diagram showing an example of a configuration and wiring required for pulling out a multi-phase clock signal from a voltage-controlled differential ring oscillator circuit. Fig. 6 is a diagram showing a configuration and wiring required for pulling out a multi-phase clock signal from a voltage-controlled differential ring oscillator circuit in the semiconductor circuit according to the first embodiment of the present invention. Figure 7A printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs is used to illustrate the configuration of the delay differential inversion amplifier circuit shown in Figure 6, and Figure 7B is used to illustrate the delay difference shown in Figure 5. Configuration diagram of dynamic inversion amplifier circuit. Fig. 8 is a diagram illustrating a configuration of a delay differential inversion amplifier circuit in a semiconductor integrated circuit according to a second embodiment of the present invention. Component comparison table 10 0 Voltage-controlled differential ring oscillator circuit This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) ~ '-14-522549 A7 B7 V. Description of the invention (12) Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by a consumer cooperative 1 〇1 a 1 0 1 h Delay differential inversion amplifier circuit 1 〇2 Control terminal 2 〇6 Non-inverting input terminal 2 〇7 Inverting input terminal 2 〇8 Non-inverting output terminal 2 0 9 Inverted output Sheshan contact 2 1 〇 Control voltage input terminal VC Control voltage 2 〇 1 5 2 〇 2 Resistor 2 〇 3 5 2 〇 4 Μ 〇 Transistor 2 0 5 Constant current source 1 〇 4 Differential input Sheshan m sub-pair 1 〇5 Differential output Qishan m sub-pair Φ 1 Φ 1 5 Clock signal 3 〇1 a 3 〇1 h Snubber circuit 3 〇2 a 3 〇2 d Pull out line 4 〇1 a 4 〇1 b Wiring 4 〇2 Parallel-series conversion circuit (Please read the precautions on the back before Write this page) clothing., 11 scales paper applies China National Standard (CNS) A4 size (210X297 mm) -15-