JP3566174B2 - Synthesizer and signal analyzer system - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a digitally controlled clock signal synthesizer and a serial binary signal analyzer.
[0002]
[Prior art]
Digitally controlled clock signal synthesizers are known. A system known as an arbitrary waveform generator includes a source for a series of digital control signals representing the value of the output clock signal at each point in time. The rate at which the digital control signal is provided is controlled by the system clock, but its frequency is generally much higher than the frequency of the synchronized clock signal. These digital control signals are supplied to a digital-to-analog converter (DAC). The analog output signal from the DAC is filtered by a low-pass filter and compared with a threshold by a threshold detector to detect the level. The output signal of the threshold detector is a composite clock signal.
[0003]
During the system clock period, when the composite clock signal is high, the amplitude value of the digital signal is maximum. Also, during the system clock period, when the composite clock signal is low, the amplitude value of the digital signal is at a minimum. During the system clock period when the leading edge (leading edge) and the trailing edge (trailing edge) occur, the amplitude value of the digital signal is intermediate. The DAC generates an analog signal at a level corresponding to the value of the digital signal. For example, at the leading edge, the clock signal transitions from the minimum value of the previous system clock cycle to the maximum value of the next system clock cycle. During the leading edge of the system clock period, the low pass filtered analog signal rises relatively slowly due to the digital control signal having an intermediate value close to the minimum value. Intersect with the level. Conversely, a digital signal at an intermediate value near the maximum causes the low-pass filtered analog signal to rise relatively quickly, so that the signal crosses the threshold level relatively easily. In this case, in the system clock period, this leading edge occurs relatively easily. The same applies to trailing edges. In this manner, the digital clock signal may be synthesized with leading and trailing edges that occupy less than one portion within the system clock period.
[0004]
Such a system can generate a synthesized clock signal with relatively high resolution and precisely located edges. However, such systems require a system clock with a much higher frequency than the frequency of the composite clock signal. If a relatively high frequency synthesized clock is required, such a system would include a very high frequency system clock signal, and thus a high speed source of digital control signals, a DAC, a low pass filter, and threshold detection. Need a vessel. Such high frequency components are either very expensive or technically impossible.
[0005]
Other techniques have been developed to generate a synthesized clock signal with relatively high resolution and precisely positioned edges without the need for fast components. For example, U.S. Pat. No. 5,394,106 to Black et al., Feb. 28, 1995, entitled "Apparatus and Method for Combining Multiple Signals with Programmable Periods" discloses such a system. The system described in this patent includes a source for a series of digital control signals, a counter clocked by a system clock, a magnitude comparator, and a variable delay circuit. The digital control signal represents the time from the last occurring edge to the next desired edge. The first part of each digital control signal represents an integer part of how many system clock cycles the time from the previous edge of this composite clock signal to the desired time of the next edge. The second part of each digital control signal represents a fraction of the number of system clock cycles from the previous edge to the desired time of the next edge. The digital control signal is coupled via the accumulator to one input of the magnitude comparator and supplies the value from the counter to a second input of the magnitude comparator. The counter counts system clock cycles. When the required number of clock cycles has been counted (ie, the desired count has been reached), the magnitude comparator generates a logical "1" signal to indicate a match. Thus, the fractional portion of the digital control signal adjusts the variable delay circuit to delay the logic "1" output signal from the magnitude comparator by the required portion of the system clock cycle. The edge of the delayed output signal from the variable delay circuit is within the composite clock signal.
[0006]
The system of the aforementioned US Pat. No. 5,394,106 does not require the frequency of the system clock signal to be significantly higher than the frequency of the synthesized clock signal, and places edges within the synthesized clock signal at fractional resolution of the system clock cycle. can do. Instead, the frequency of the system clock signal is on the same order as the highest frequency desired for the composite clock signal. However, in systems such as described in U.S. Pat. No. 5,394,106, a new digital control signal from a digital control signal source is required in response to a "match" signal from the magnitude comparator. This is when an edge corresponding to the final digital control signal occurs. Such a system can and can be used to generate a phase-modulated composite clock signal (for jitter response measurement), thus requiring a new digital control value with time period variations. That is, the input digital control value is received asynchronously with respect to the system clock.
[0007]
However, first, those skilled in the art will appreciate that synchronous digital systems are easy to design, implement, and integrate with other digital systems. The asynchronous nature of U.S. Pat. No. 5,394,106 described above makes it difficult to integrate such systems into digital systems. Second, asynchronous systems are difficult to design and implement for accurate filtering. Thus, a desirable clock signal synthesizer does not require a much higher frequency system clock than the synthesized clock signal, allows for accurate and high resolution edge placement, and has a synchronized state (ie, synchronized to the system clock). In a state of receiving a digital control signal).
[0008]
Clock signal analyzers (analyzers) are known. Such an analyzer generates data representing the phase of the input clock signal. In a method corresponding to the above clock signal generator, one clock signal analyzer includes a counter, which starts counting on one edge of the input clock signal and stops on the next edge. This counter is clocked by the system clock (counts the system clock) and at the end of the counting period, the count indicates the time between two edges.
[0009]
The resolution of the above method is the system clock period. The finer resolution (higher resolution) method involves two gradient generators to achieve a finer resolution than the system clock. A plurality of pulses are used to indicate the location of the edge in the clock signal to be analyzed. A start pulse triggers a ramp generator configured to change from a minimum voltage to a maximum voltage during a system clock period. The ramp generator continues the ramp until the beginning of the next system clock cycle. At the beginning of the next system clock cycle, the value of the ramp signal is converted to a digital signal, indicating the fractional part of the clock cycle from the start pulse to the start of the next system clock cycle. Here, a low value indicates that a start pulse has occurred near the end of the system clock cycle, and a high value indicates that a start pulse has occurred shortly after the start of the system clock cycle. The start pulse enables the counter to start counting system clock cycles. The stop pulse disables the counter and triggers the second ramp generator. The second ramp generator operates in a manner similar to the first ramp generator to generate a digital value indicative of a fractional part of the system clock cycle from the stop pulse to the start of the next system clock cycle. I do. The value of the second ramp generator is also converted to a digital value. Thus, the period between the start and stop pulses is [number of system clock cycles of the counter] plus [the first complete system clock cycle represented by the digital value of the first ramp generator, and the start pulse. The fractional part of the clock cycle between the stop pulse and the fractional part of the clock cycle between the next complete system clock cycle represented by the digital value of the second ramp generator and the stop pulse.
[0010]
[Problems to be solved by the invention]
It is not always necessary to identify each edge of the synthesized clock signal and analyze the time of each edge of the input clock signal. In some cases, it is sufficient to provide edge data and receive edge timing data at a lower rate than the edge rate in the synthesized or analyzed data signal.
[0011]
[Means for Solving the Problems]
In accordance with the principles of the present invention, a digital phase synthesizer includes a source of a continuous phase data signal (a signal of continuous phase data). The interpolator generates a continuous edge arrangement data signal (a signal of continuous edge arrangement data) in response to each of the continuous phase data signals. The phase modulator generates an output clock signal having an edge located at a time determined by the continuous edge located data signal. Similarly, a digital phase analyzer comprises a source of a serial binary input signal having edges. The phase demodulator generates a continuous data signal representing the location of each edge of the serial binary input signal. The decimator generates a phase data signal at a rate slower than the edge of the serial binary input signal.
[0012]
According to the clock signal synthesizer according to the present invention, accurate and high-resolution edge arrangement can be performed without the need for a system clock having a frequency much higher than the frequency of the synthesized clock signal. Operate.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
1 and 2 are block diagrams of a phase measurement / generator system 10 for digital signals. The systems shown in FIGS. 1 and 2 can be modified. FIG. 1 is a block diagram of a system 10 configured to generate a clock output signal in response to a phase data signal, and FIG. 2 is a system configured to measure the phase of a serial binary input signal. It is a block diagram of 10. 1 and 2 are designated by the same reference numerals.
[0014]
1 and 2, input terminal IN is coupled to a system controller (not shown). The system controller generates a signal specifying a desired phase characteristic of the generated clock output signal. The input terminal IN is also connected to an input terminal of the preprocessor 5. An output of the preprocessor 5 is coupled to an input of the phase synthesizer 20. A data output of the phase synthesizer 20 is coupled to a clock output terminal, and a strobe signal output of the phase synthesizer 20 is coupled to a corresponding input of the pre-processor 5.
[0015]
The control input is coupled to a system controller (not shown) and receives data that controls the configuration and operation of the system 10. This control input terminal is also coupled to an input of the control interface circuit 12. From the status output terminal of the control interface circuit 12, a status signal indicating the operating status of the system 10 is generated and supplied to the system controller.
[0016]
The reference clock signal is supplied to a reference input of a phase locked loop (PLL) 14. Loop filter 15 is also coupled to PLL 14. PLL 14 provides clock signals to various elements of system 10. These elements are synchronized to the reference clock in a known manner. For simplicity of illustration, these clock signals are not shown in FIGS.
[0017]
In FIG. 2, input terminal IN is coupled to a source of a serial binary input signal. Input terminal IN is coupled to the input of phase analyzer 30. A phase data output of phase analyzer 30 is coupled to a data input of post processor 25. The output of post processor 25 is an output terminal for generating data representing the detected phase characteristics of the serial binary input signal. The strobe output of the analyzer 30 is coupled to a corresponding input of the post processor 25. Further, an output terminal for the recovered clock from the analyzer 30 is coupled to a received clock output terminal. The rest of the system shown in FIG. 2 is the same as the part shown in FIG. 1 and 2, the system 10 of FIG. 1 is the same as the system 10 of FIG. 2 and will be described in detail later.
[0018]
In operation, a system controller (not shown) provides control data to system 10 via control input terminals. Control interface 12 receives and saves information in any one of a variety of known ways. For example, the control input can be coupled to a multi-bit parallel digital bus. This digital bus is coupled to a microprocessor. Alternatively, in the illustrated embodiment, the control input terminals include a serial data signal line, a clock signal line, and a serial line including a control line for controlling the flow of data between the control interface 12. Digital input terminal. The control interface 12 includes a register that is coupled to the control input and stores various values received from the control input. The plurality of output terminals of the register are coupled to various circuits in system 10 and control these circuits in all known ways.
[0019]
Similarly, the control interface includes registers, or latches, or transmission gates (as needed), whose inputs are coupled to points in the system 10 to monitor their values. . The outputs of these circuits are coupled to status output terminals. Further, the above-described register holding the control value also has an output terminal coupled to the status output terminal. It is also possible for some of these registers to share a control value and another to supply a state value, sharing such a register. Depending on the control input, the status output can be a multi-bit parallel digital bus or, as in the illustrated embodiment, include data signal lines, clock signal lines and optional control lines. It can also be a serial signal line. A system controller (not shown) reads data from these circuits to determine the current state of system 10 in all known ways.
[0020]
In FIG. 1, a system controller (not shown) provides control data to control interface 12 to configure system 10 to operate as a clock output signal generator in a manner described in more detail below. In this operation mode, when new phase data is requested, the synthesizer 20 transmits a strobe signal to the preprocessor 5. In response to the strobe signal, the pre-processor 5 supplies data (phase data) indicating a desired phase characteristic of the clock output signal to the synthesizer 20. As will be described in detail later, the pre-processor 5 may execute the substantial signal processing together with the phase synthesizer 20, or the input phase characteristic signal directly received from the input terminal IN without performing the substantial processing. Through the phase synthesizer 20. However, in the illustrated embodiment, a relatively low-speed signal processing is executed by a method described later together with a relatively high-speed circuit in the phase synthesizer 20.
[0021]
Synthesizer 20 generates a clock output signal having edges arranged according to the phase data received from preprocessor 5. The edges of this clock output signal occur at a predetermined rate (baud). Note that phase modulation of these edges is also performed. However, as will be described in detail below, phase data from the pre-processor 5 is requested at a constant rate (via a strobe signal). This rate may be lower than a predetermined (baud) of an edge in the output serial binary signal. That is, the edge generated in the clock output signal is asynchronous with respect to the phase data from the preprocessor 5.
[0022]
In FIG. 2, a system controller (not shown) provides control data to control interface 12 to configure system 10 to operate as a serial binary input signal measurement system in a manner described in more detail below. In this mode of operation, the analyzer 30 receives a serial binary input signal. The edges of this serial binary input signal occur at approximately a predetermined rate (baud) but are not phase modulated. The analyzer 30 calculates data indicating the elapsed time from each edge in the serial binary input signal to the next continuous edge, and a series of phase expression data signals indicating the phase characteristics of the serial binary input signal received by the analyzer 30. Generate "phase data". These phase representation data signals "phase data" are available to the post processor 25 together with the strobe signal. The strobe signal indicates that new phase expression data “phase data” is available. In response to the strobe signal, post processor 25 receives the phase representation data "phase data" and generates an output signal indicative of the phase characteristics of the serial binary input signal. In a manner similar to the pre-processor 5 described above, the post processor 25 may perform substantial signal processing, or perform any substantial processing on the phase data output signal "phase data" received directly from the analyzer 30. The signal may be passed to the phase characteristic output terminal without performing the general signal processing. However, in the illustrated embodiment, post processor 25 performs the relatively slow signal processing as well as the relatively fast signal processing performed by analyzer 30, in a manner described in more detail below.
[0023]
As in the digital clock generation system described above in connection with FIGS. 1 and 2, and phase modulated, the edges in the serial binary input signal are at a predetermined rate (baud), as will be described in greater detail below. , While the phase data is provided to the post processor 25 at a constant rate (via a strobe signal). Therefore, the phase data is generated asynchronously with the edge of the serial binary input signal. Further, in the illustrated embodiment, analyzer 30 generates a recovered clock signal having substantially the same phase as the received serial binary input signal.
[0024]
FIG. 3 is a block diagram of the clock signal synthesizer 20 used in the system 10 shown in FIGS. In FIG. 3, phase data from the pre-processor 5 (FIGS. 1 and 2) is coupled to an input of an interpolation filter 22. The strobe signal output of the interpolation filter 22 is coupled to a corresponding input of the pre-processor 5. The data output of the interpolation filter 22 is coupled to the input of the phase modulator. The output of the phase modulator 26 is coupled to a clock signal output terminal.
[0025]
In operation, the interpolation filter 22 requests phase data from the pre-processor 5 by activating the strobe signal. In response to the strobe signal, pre-processor 5 provides data indicative of the desired phase characteristics of the clock output signal in a known manner, as described above. Next, the interpolation filter 22 generates a plurality of continuous edge placement data signals, each of which identifies the position of one edge in the clock output signal. In this method, the interpolation filter 22 generates a plurality of edge arrangement signals. With these signals, the phase modulator 26 generates a clock output signal. The phase characteristic of the clock output signal smoothly changes from the characteristic indicated by the previous phase data signal from the preprocessor 5 to the characteristic indicated by the last received phase data signal, as will be described in detail later. Phase modulator 26 generates a clock output signal having a placed edge in response to each of the edge placement signals from interpolation filter 22.
[0026]
FIG. 4 is a more detailed block diagram of the serial binary signal synthesizer 20 shown in FIGS. In FIG. 4, the phase data from the pre-processor 5 (of FIGS. 1 and 2) is coupled to a data input of an interpolator 220. An output of the interpolator 220 is coupled to an input of the bit decompressor 230. As will be described in greater detail below, the system clock signal from PLL 14 is coupled to the input of divider 232 (shown in dashed lines for reasons to be described later). The output of divider 232 is coupled to the data input of clock selector 234. The output of clock selector 234 is coupled to the clock input of interpolator 220. The strobe output of interpolator 220 is coupled to the strobe output of interpolation filter 20. The combination of the interpolator 220, the bit decompressor 230, the frequency divider 232, and the clock selector 234 forms the interpolation filter 22.
[0027]
PLL 14 generates a multi-phase clock signal at the system clock frequency. In the illustrated embodiment, the multi-phase clock signals include clock signals having phases φ0-φ7. The first phase φ0 of the multiphase clock signal is selected as a system clock signal and supplied to the input terminal of the counter 262.
[0028]
The output of bit expander 230 is coupled to a first input of adder 268. Each of the first and second outputs of adder 268 is coupled to a corresponding first and second control input of decode 272. An output of the decode 272 is coupled to a data input of an analog multiplexer (MUX) 274. The output of MUX 274 is coupled to the input of low pass filter (LPF) 276. The output of the low-pass filter 276 is supplied to the data input of the comparator 278. The output of comparator 278 is coupled to the output of synthesizer 20 to generate a clock output signal.
[0029]
A third output of adder 268 is coupled to respective inputs of a first digital to analog converter (DAC) 264 and a second DAC 266. Each output of the first and second DACs 264 and 266 generates signals A1 and A2 and is coupled to a corresponding input of the decoder 272. All phases of the polyphase system clock signals φ0-φ7 are coupled to a control input of analog MUX 274. The combination of the counter 262, the first DAC 264, the second DAC 266, the adder 268, the decoder 272, the MUX 274, the LPF 276, and the comparator 278 forms the phase modulator 26.
[0030]
The polyphase system clock signal from PLL 14 (FIGS. 1 and 2) is shown in FIG. In the illustrated embodiment, the multi-phase system clock includes eight clock signals of the same frequency but of eight phases at equal intervals to simplify the description of the invention. The polyphase system clock signal can be generated in a known manner by a ring oscillator. For a polyphase system clock signal, it is possible to include more or less than eight phases. One phase of the polyphase system clock signal is selected to provide the system clock signal. In the illustrated embodiment, φ0 is used like a system clock.
[0031]
The frequency divider 232 in the interpolation filter 22OrThese system clock signals are received and a plurality of clock signals are generated at each divisor of the system clock signal frequency (ie, １ ／, ４, ８ of the system clock frequency). In the preferred embodiment, divider 232 generates the nine such clock signals. The nine divided clock signals and the system clock signal are supplied to the clock selector 234. The clock selector 234 selects one of these clock signals as a clock signal for the interpolator 220.
[0032]
The interpolation filter 22 is a low-pass filter that interpolates between relatively sparse received phase data signals, and nominally generates an edge-arranged data signal at a specific baud rate. This arrangement allows the phase data input rate to range from a relatively slow rate of 1.5 MHz to higher frequencies, such as 700-1400 MHz. In the embodiment shown, an interpolation filter 22 is arranged in a known manner to interpolate the output edge arranged data signal between the received phase data signals.
[0033]
6, 7, andFigureFIG. 8 is a detailed block diagram of the interpolator 220 used in the clock signal synthesizer 20 of FIG. FIGS. 6, 7 and 8 show three block diagrams of the interpolator 220. FIG. In FIG. 6, phase data from the pre-processor 5 is supplied to an input terminal of a latch 222.. LaThe output of switch 222 is coupled to the input of first boxcar filter 226. An output of the first boxcar filter 226 is coupled to an input of a second boxcar filter 228. The output of box car 228 is coupled to the input of funnel shifter 229. The output of funnel shifter 229 is coupled to the output of interpolator 220, which is coupled to phase modulator 26 (FIG. 4). Baud rate to F_BAUDClock selector shown as2The clock signal from 34 (FIG. 4) is supplied to the clock input of the second boxcar filter 228 and to the input of the fixed frequency divider 223. The output of fixed frequency divider 223 is coupled to the clock input of first boxcar filter 226 and to the input of second fixed frequency divider 221. An output terminal of the second fixed frequency divider 221 is coupled to a clock input terminal of the latch 222 and a strobe output terminal of the interpolator 220.
[0034]
Boxcar filters are well known and exhibit a flat impulse response over a period of time. Those skilled in the art will appreciate that such a filter performs both linear interpolation and amplification on the input signal. The two boxcar filters operate in series and at the same time, performing a quadratic interpolation function and amplification. Those skilled in the art will also recognize that other interpolation techniques can be used successfully.
[0035]
In operation, the latch 222 receives the phase data from the pre-processor 5 and latches the phase data in response to a strobe signal from the second fixed frequency divider 221. The strobe signal is derived directly from the system clock signal by the divider 232 and the clock selector 234 (FIG. 4), and the first and second fixed dividers 223 and 221. Therefore, the phase data is received in synchronization with the system clock but without responding to the timing of an arbitrarily generated edge. The latched phase data is provided to a series connection of first and second boxcar filters 226 and 228. The first and second boxcar filters perform quadratic interpolation and amplification on the phase data signal to generate a series of continuous edge-located signals at a predetermined baud rate. The continuous edge arrangement signal is supplied to the phase modulator 26 (FIG. 4).
[0036]
The output of the second boxcar filter 228 is a multi-bit digital number of a predetermined number of bits. The funnel shifter 229 selects the subset of bits in a known manner and generates a clock coefficient M₃And M₄Operates to attenuate the amplitude of the sample from the second boxcar filter by an amount determined by The output from the funnel shifter 229 is supplied to a decompressor 230 (FIG. 4).
[0037]
One skilled in the art will appreciate that the boxcar filter can be decomposed into a series connection of an accumulator and a differentiator. Those skilled in the art will also understand that the operation of the accumulator and differentiator is linear, and that they can be arranged in any order. Further, it can be understood that the cumulative operation is a relatively high-speed operation, and the differential operation is a relatively low-speed operation.
[0038]
FIG. 7 shows the interpolator 220 of FIG. 6, where the first boxcar filter 226 can be decomposed into a series connected accumulator 252 and a differentiator 254, and the second boxcar filter 228 is connected in series. It can be decomposed into an accumulator 256 and a differentiator 258. At block 258, differentiator 258 is shown operating on samples separated by M samples, and differentiator 254 is shown operating on samples separated by M4 sampling. However, M = M₃・ M₄And the supplied clock signal is converted into a coefficient M by a first fixed frequency divider 223.₃, The period during which the differentiator operates is the same as the period during which the differentiator 258 operates.
[0039]
FIG. 8 shows another arrangement of the interpolator 220. Here, two differentiators 254 and 258 are directly coupled after latches 222, following two accumulators 252 and 256. In this case, the differentiator operates on adjacent samples (separated by one sample). However, since these differentiators are clocked by the strobe signal divided by M by the series connection of the first and second fixed frequency dividers 223 and 221, they operate over the same period. However, the circuit arrangement of FIG. 8 performs a relatively low-speed differentiation operation different from the relatively high-speed accumulation operation. Thus, the latch 222 and the two differentiators 254 and 258 can be located outside the integrated circuit chip on which the system 10 is assembled. As described above, these elements are arranged in the pre-processor 5. A high-speed accumulator is provided on the integrated circuit chip containing the system 10. By moving the low speed elements out of the integrated circuit chip containing the system 10, these circuit elements and the surface area required within the integrated circuit chip can be reduced.
[0040]
FIG. 4 is referred to again. Bit decompressor 230 receives an output signal from funnel shifter 229 (FIGS. 6-8). The bit expander 230 expands (extends) the number of bits in the output signal from the funnel shifter 229, and performs a low-pass filtering operation. For example, in the illustrated embodiment, bit decompressor 230 generates a 15-bit signal. In the preferred embodiment, more bits are required, depending on the configuration of the circuit described in detail below. In the illustrated embodiment, the filtering operation is performed by a first-order low-pass filter. In the illustrated embodiment, the filtering operation is configured by an infinite impulse response (IIR) filter. Bit decompressor 230 supplies the output signal to phase modulator 26.
[0041]
The signal from bit decompressor 230 can be viewed as a fixed point real number representing the desired time difference from the next edge of the unmodulated clock signal at the predetermined baud rate to the next edge of the composite clock output signal. That is, the signal from the bit decompressor 230 includes an integer portion having a fixed bit width and a fractional portion having a fixed bit width. This real number may be positive or negative. This integer part represents the number of complete periods of the system clock between the desired time of the next edge of the synthesized clock signal and the time of the next edge of the unmodulated clock signal, and the fractional part is It represents a portion of the system clock period between the desired time of the next edge of the signal and the time of the unmodulated clock signal.
[0042]
In the illustrated embodiment, the system clock frequency is related to the square of the baud rate. That is, if the baud rate is F_BAUDThen the system clock frequency is 2^m・ F_BAUDis there. In this case, each cycle of the clock signal at the given baud rate is 2^mSystem clock cycles. The value of m can be selected by the system controller via the control interface 12. In response to a control signal from the system controller via the control interface 12, the counter 262 is configured to match the selected value of m by configuring the counter into an m-bit counter. The m-bit counter 262 is responsive to one of a plurality of phases in the polyphase system clock, in the embodiment shown φ0. Thus, the output from m-bit counter 262 is an m-bit digital signal. This counter counts at the system clock rate and cycles at a predetermined baud rate, but the count starts at 0 at the beginning of the cycle and the count in the middle of the cycle is 2^m-1And the count at the end of the cycle is 2^m -1It is. The end of this cycle is just before restarting from zero.
[0043]
The countable size of the counter and the value of m are configured to provide a clock signal to the interpolator 220 at the desired baud rate from the system clock frequency. At the same time, the clock selector 234^mSelect the frequency division ratio according to the output. In this configuration, the clock signal from clock selector 234 has a predetermined baud rate. This is usually the desired configuration, but other configurations may be selected.
[0044]
For example, if the system clock frequency supplied by the PLL 14 is 1228.8 MHz and the desired baud rate is 2.4 MHz, m is selected as 9. Counter 262 is configured as a 9-bit counter, counts the system clock rate, and cycles at a predetermined baud rate. In this circulation (cycle), the count is 0 at the beginning of the cycle, the count is 256 in the middle of the cycle, and the count before restarting at 0 at the end of the cycle is 511.
[0045]
The operation of the phase modulator 26 can be easily understood by referring to the waveform diagrams shown in FIGS. The uppermost waveform in FIG. 9 shows the rising edge of the system clock. These edges are φ0 of the polyphase system clock signal, as described above. This system clock signal causes the counter 262 to count and cycle from 0 to 511 and back to 0. This is shown in the second waveform in FIG. 9 (counter 262) where the value at the multi-bit output of counter 262 corresponds to the leading edge (leading edge) of the system clock signal.
[0046]
The signal from bit expander 230 of interpolation filter 22 is, as described above, between the time of the next desired edge in the clock output signal and the time of the next edge in the nominal clock signal at the predetermined baud rate. Represents a time difference and is shown as a fixed point real number having an integer part and a fractional part. This signal is combined with the output of counter 262 in adder 268. As described above, the integer part of the fixed-point real number represents an integer number of system clock cycles, and the output signal of counter 262 also represents an integer number of system clock cycles. Therefore, the signal from the counter 262 can be regarded as a fixed point having only an integer part and a decimal part which is a zero value. In the preferred embodiment, the output of counter 262 is subtracted from the time difference signal from bit decompressor 230. Thus, the output of adder 268 is counted from 0 to 511, then through 256, and back to 1 through 1. However, the direction of counting does not affect the occurrence of edges. This is because 0 and 256 correspond to the same point in time, although the counts are separated in the forward or reverse direction.
[0047]
The difference signal from adder 268 can be considered a fixed point real number having an integer part and a fractional part. This signal controls the position of the next edge of the clock output signal in the following manner. The integer part of this signal is termed the coarse resolution signal and is provided to a first control input C of the decoder 272. The most significant part of the fractional part is an intermediate resolution signal, which is supplied to a second control input M of the decoder 272. In the illustrated embodiment, the intermediate resolution signal is a 3-bit signal. However, in the preferred embodiment, the intermediate resolution signal may be larger than three bits. The next most significant bit in the fractional part is the fine resolution signal and is provided to each input of the first and second digital-to-analog converters (DACs) 264 and 266. In the illustrated embodiment, the fine resolution signal F is also a 3-bit signal. However, in the preferred embodiment, the fine resolution signal may be larger than three bits.
[0048]
If the time difference signal from bit decompressor 230 is positive, the value of the output of adder 268 is greater than the value of the output of counter 262. If the time difference signal is negative, the value of the output of the adder 268 is smaller than the value of the output of the counter 262. The third waveform in FIG. 9 shows the integer (coarse resolution C) output of the adder 268 when the integer part of the time difference signal is +1. When the output value of counter 262 is subtracted from +1, the result is greater than the value of counter 262. The fourth waveform in FIG. 9 shows the integer (coarse resolution C) output of the adder 264 when the integer part of the time difference signal is -1. When the output value of the counter is subtracted from -1, the result is less than the value of counter 262.
[0049]
As described in detail below, the leading edge of the clock output signal occurs during the period when the integer output of adder 268 is zero. Also, the trailing edge of the clock output signal occurs during 256 integer outputs of adder 268. Adder 268 along with counter 262 allows for edge position and the phase of the generated clock output signal shifted by an integer number of system clock cycles. However, in the following description, it is assumed that the integer part of the time difference signal is equal to 0 and the integer value (coarse resolution C) from the adder 268 is equal to the value from the counter 262.
[0050]
The next eight waveforms in FIG. 9 show the phases φ0 to φ7 of the polyphase system clock signal. The left portion of these waveforms represents the signal of the system clock cycle when the integer output value C of adder 268 is equal to zero during the occurrence of the leading edge of the clock output signal. The right part shows the signal when C is 256 (the trailing edge of the clock output signal). As shown in FIG. 9, eight sub-intervals, which are determined by the relative phases of the respective signals in the multi-phase clock signal and are denoted by symbols W0 to W7, exist in a single clock cycle. Circuits that generate respective binary signals representing each of the sections W0-W7 or generate digital count signals having values indicative of each of the sections W0-W7 are designed and implemented in a manner known to those skilled in the art. it can.
[0051]
In a manner described in detail below, decoder 272 operates to generate eight signals D0-D7. The table shown in FIG. 11 is useful for understanding the operation of the decoder 272. In the table of FIG. 11, the leftmost column (column) indicates the coarse resolution value C (an integer value from the adder 268), and the second row (horizontal row) indicates the intermediate resolution value M (the value from the adder 268). (The three most significant bits of the fractional part of The rightmost column represents signals D0 to D7 generated by decoder 272. These signals D0 to D7 are multilevel analog signals. In the embodiment shown, these signals have nine possible levels. However, in the preferred embodiment, there are more than nine levels. The levels of these signals are determined by values ranging from 0 representing the minimum level to 8 representing the maximum level.
[0052]
The analog multiplexer (MUX) 274 cycles in the order of the signals D0-D7 once in each system clock cycle in response to the polyphase system clock signal. During the phase section W0, the MUX 274 supplies the D0 signal to the output terminal. Further, during the phase section W1, the MUX 274 supplies the D1 signal to the output terminal. Hereinafter, the same applies.
[0053]
The configuration of signals D0 to D7 generated by decoder 272 is determined by values C and M from adder 268. The specific values of the signals D0 to D7 generated by the decoder 272 are shown in columns D0 to D7 in the table of FIG. As shown in the middle row of the table of FIG. 11, during a period in which the C value is larger than 0 but smaller than 256, the intermediate resolution signal M (in column M, "X" meaning don't care (optional) ), The value of all of these multi-level analog signals D0 to D7 is 8. During this time, the decoder 272 couples the source of the level 8 analog signal to all of the output terminals D0-D7. Therefore, during this period, the signal generated by the MUX 274 has a constant value of 8. As shown in the bottom row of the table in FIG. 11, during the period when the output of adder 268 is greater than 256 but not rounded to zero, all of these multi-level analog signals D0-D7 have an intermediate resolution. The value is 0 regardless of the value of the signal M. During this period, the decoder 272 couples the source of the level 0 analog signal to all of the output terminals D0-D7. Therefore, during this period, the signal generated by the MUX 274 has a constant value of 0.
[0054]
The periods when the C signal is 0 are shown in the eight rows in the upper half of the table in FIG. 11 and the waveform on the left side in FIG. During this period, the signals D0 to D7 are formed by the following method. If the intermediate resolution signal M is zero, it can be assumed that the signal D0 is any one of the analog levels 1-8 (shown in FIG. 9 by multiple horizontal lines for the signal D0). The specific analog level is derived from signal A1 from first DAC 264. Note that this signal A1 is indicated by an entry “A1” in a column of the table of FIG. 11 representing a signal D0 in a row representing a C signal of 0 and a M signal of 0. In the illustrated embodiment, during this period, decode 272 provides the output of DAC 264 to the D0 output terminal. Assume that signals D1-D7 are at analog level 8 while C is equal to 0 and M is equal to 0. Decoder 272 couples the level 8 analog signal source to D1-D7 output terminals. As described above, when the MUX 274 scans the signals D0 to D7, the left end portion of the signal denoted by “0” in FIG. 9 occurs during the phase section W0 in a manner described later in detail, and a leading edge is generated. Occurs.
[0055]
If the intermediate resolution signal is equal to 1, the D0 signal is set to the analog value 0. As shown in FIG. 11, signal D1 can be assumed to have analog levels 1-8 (signal A1 from first DAC 264), and the remaining signals D2-D7 are assumed to have analog value 8. As described above, when the MUX 274 scans the signals D0 to D7, the left end portion of the signal denoted by “1” in FIG. 9 occurs, and a leading edge occurs during the phase section W1. Similarly, when the level of the M signal is 2 to 7, each of the signals D2 to D7 has a variable analog value from the signal A1 from the first DAC 264. The value of the previous Dx signal is the analog value 0, and the analog value of the subsequent Dx signal is 8. As described above, when the MUX 274 scans the signals D0 to D7, the left portion of the signal shown in FIG. 9 and labeled 2 to 7 occurs, and a leading edge occurs during each of the phase sections W2 to W7.
[0056]
The section where the C signal is equal to 256 is shown in the lower eight rows in the table of FIG. 11 and the left waveform of FIG. During this period, the signals D0 to D7 are formed by the following method. Assuming that the intermediate resolution signal M is 0, it is assumed that the signal D0 is any one of the analog levels 0-7 (indicated by the multiple horizontal lines for the signal D0 in FIG. 9). The particular analog level is derived from the signal A2 from the second DAC 266 indicated by entry “A2” in the table column of FIG. This “A2” indicates a signal D0 in a row representing 256 C signals and 0 M signals. In a particular embodiment, decoder 272 provides the output from second DAC 266 to the D0 output terminal during this period. For C equal to 256 and M equal to 0, signals D1-D7 are assumed to be at analog level 0. Decoder 272 couples a level 0 analog signal source to D1-D7 output terminals. As described above, when the MUX 274 scans the signals D0 to D7, the right portion of the signal labeled “0” in FIG. 9 occurs, and the trailing signal is generated during the phase section W0 in a manner described later in detail. Edges occur.
[0057]
If the intermediate resolution signal is equal to one, the D0 signal is set to the analog value eight. As shown in FIG. 11, signal D1 can be assumed to have analog levels 0-7 (signal A2 from second DAC 266), and the remaining signals D2-D7 are assumed to have analog value 0. As described above, when the MUX 274 scans the signals D0 to D7, the right portion of the signal labeled "1" in FIG. 9 occurs, and a trailing edge occurs in the phase section W1. Similarly, when the value of the M signal is 2 to 7, the signals D2 to D7 have variable analog values 0 to 7 from the signal A2 of the second DAC 266, respectively. The value of the previous Dx signal is the analog value 8, and the analog value of the subsequent Dx signal is 0. As described above, when the MUX 274 scans the signals D0 to D7, the right portions of the signals labeled 2 to 7 occur as shown in FIG. 9, and the trailing edge is shifted during the phase section W2 to W7. Each occurs.
[0058]
As described above, for each system clock cycle in response to the polyphase system clock signal, analog MUX 274 provides signals D0-D7 from decoder 272 to output terminal D in that order. Therefore, the generated signal D is subjected to low-pass filtering and compared with a threshold value to generate a clock output signal by a method described later.
[0059]
In the method described later, the fine resolution signal F from the adder 268 arranges an edge at a specific point in time within specific phase sections W0 to W7. The fine resolution signal F is supplied to the first and second DACs (DAC1 and DAC2) 264 and 266 as described above. The table of FIG. 12 shows the output levels of the analog signals A1 and A2 generated by the first and second DACs 264 and 266, corresponding to the respective values of the fine resolution signal F. That is, the first DAC (DAC1) 264 generates a level 1 analog signal A1 and the second DAC (DAC2) 266 simultaneously generates a level 7 analog signal A2 for the fine resolution signal F having a value of 0. . For a fine resolution signal F with a value of 1, the disk 1 DAC generates a level 2 analog signal A1, the second DAC generates a level 6 analog signal A2, and so on.
[0060]
FIG. 10 shows two possible waveforms for a selected signal D from MUX 274. The waveform D at the top in FIG. 10 shows a waveform in which the value of the fine resolution signal F from the adder 268 is 6. As shown in the table of FIG. 12, the value of the A1 signal is 2, and the value of the A2 signal is 6. In the illustrated waveform D, the time points of the A1 signal and the A2 signal are represented by a series of thin horizontal lines as shown in FIG. The actually selected A1 and A2 signals at D are indicated by bold lines. Since this signal D is low-pass filtered by the LPF 268, the resulting waveform is shown by the second waveform in FIG.
[0061]
The A1 level (2) is relatively low compared to the maximum level (8) at which the filtered signal rises, so the filtered waveform rises relatively slowly. Therefore, the filtered waveform rises relatively slowly through the threshold value Th (set in the middle of the maximum value and the minimum value in the illustrated example) in the period A1. Similarly, the A2 level (6) is relatively high compared to the minimum level (0) at which the filtered waveform drops, so the filtered waveform drops at a relatively slow rate. Therefore, the filtered waveform falls through the threshold value Th relatively late in the period A2.
[0062]
The filtered waveform is compared in comparator 278 with threshold value Th. When the value of the filtered waveform is below threshold Th, the output of comparator 278 is low. Also, when the value of the filtered waveform is higher than the threshold, the output of comparator 278 is high. The output of comparator 278 is as shown in the third waveform of FIG. 10, which is the clock output signal.
[0063]
A fourth waveform D in FIG. 10 shows a selected waveform when the value of the fine resolution signal from the interpolation filter 22 is 2. Therefore, as shown in the table of FIG. 12, the value of the A1 signal is 6, and the value of the A2 signal is 2. The selected signal D is indicated by a thick line. If this signal D is low-pass filtered by LPF 268, the resulting waveform is the fifth waveform in FIG.
[0064]
The filtered waveform rises relatively quickly because the A1 level (6) is relatively high compared to the maximum level (8) at which the filtered signal rises. Therefore, the filtered waveform rises through the threshold Th relatively early in the period A1. Similarly, the filtered waveform falls relatively quickly because the A2 level (2) is relatively low compared to the minimum level (0) at which the filtered waveform falls. Therefore, the filtered waveform falls through the threshold value Th relatively early in the period A2.
[0065]
The filtered waveform is compared in comparator 278 with threshold value Th. The output of comparator 278 is shown by the sixth waveform in FIG. 10, which is the clock output signal. As can be seen from FIGS. 9 and 10, the position of each edge can be located with a resolution of 1/64 of the system clock period in response to fine and coarse resolution signals from the interpolation filter 22. The phase data signal from the pre-processor 5 is received at a rate lower than the predetermined baud rate and is received synchronously at a fixed frequency instead of the edge-dependent rate generated on the clock output signal.
[0066]
Those skilled in the art will appreciate that the least significant bit signal at the output of counter 262 represents a clock signal divided by two from the system clock signal at the input of counter 262. Each of the other bit outputs represents the clock signal divided by two from the next lower bit. Thus, the counter 262 is considered to be a multi-bit frequency divider as represented by the frequency divider 232 of the interpolation filter 22. Thus, a single counter 262, in the embodiment shown, has its output terminals coupled to both an adder 268 in phase modulator 26 and a clock selector 234 in interpolation filter 22. (The clock selector 234 also receives the undivided system clock signal from the PLL 14.) Since the interpolation filter 22 shares the clock divider 232 with the counter 262 in the phase modulator 26, the interpolation filter 22 22 is indicated by a dotted line.
[0067]
Next, reference is made to the digital phase analyzer shown in FIG. FIG. 13 is a block diagram of a clock signal analyzer used in the system 10 shown in FIGS. In FIG. 13, input terminal IN is coupled to a source of a serial binary input signal. This input terminal IN is coupled to the input end of the phase modulator 32. Also, the phaseDemodulatorThe output of 32 is coupled to the input of anti-aliasing filter 36. An output of the anti-aliasing filter 36 is coupled to an input of a decimator 39. The data output of the decimator 39 generates data indicative of the phase characteristics of the serial binary input signal at the input terminal IN and is coupled to the output terminal "phase data". A strobe output end of the decimator 39 is coupled to a strobe output terminal.
[0068]
The serial binary input signal at the input terminal IN has an edge that occurs nominally at a time corresponding to a predetermined baud rate. This serial binary input signal is a phase modulation signal in which the position of the edge varies with the phase. Alternatively, this signal is a data carrying signal with or without an edge and represents the value of the data carried by this data carrying signal. In the case of a data-carrying signal, edges occur at approximately a given baud rate.
[0069]
phaseDemodulator32 generates edge position data identifying the position of each edge in the serial binary input signal. When each edge is detected, edge position data is generated. The edge position data corresponds to the edge arrangement data described above with reference to the clock synthesizer 20. The decimator 39 generates one sample indicating the phase characteristic of the serial binary input signal for each predetermined number of edge position samples in synchronization with the system clock and asynchronously with the generation of the edge. Anti-aliasing filter 36 prevents aliasing in the decimation process in a known manner.
[0070]
Referring again to FIG. The phase modulator 26, configured as shown in FIG. 4 and operating as described above, optionally has an input coupled to the output of a demodulator 32, as indicated by the dashed line in FIG. The output of the phase modulator 26 is connected by a dotted line to an output terminal for generating a received clock output signal. As described above, as shown in FIG. 4, the phase modulator receives the edge arrangement data and generates a clock output signal in response to the edge arrangement data. The phase demodulator 32 generates edge position data associated with the received serial binary input signal from the input terminal IN. This edge position data corresponds to the edge arrangement data received from the interpolation filter 22 in FIG. In response to this data, phase modulator 26 can generate a recovered clock output signal having a phase corresponding to the received edge placement data and having a phase corresponding to the received serial binary input signal at input terminal IN. .
[0071]
FIG. 14 shows a detailed block diagram of the phase analyzer 30 shown in FIG. 1, FIG. 2 and FIG. In FIG. 14, an input terminal IN is coupled to a source of a serial binary input signal. This input terminal IN is also coupled to the input terminal of the delay circuit 322. The output of delay circuit 322 is coupled to the data input of latch array 324. The output of latch array 324 is coupled to the input of binary encoder 326. The data output of binary encoder 326 is coupled to a first input of register 328. The output of register 328 is coupled to anti-aliasing filter 36 and phase modulator 26.
[0072]
The system clock signal which is φ0 of the polyphase system clock signal is supplied to the input terminal of the counter 330. An output of the counter 330 is coupled to a second input of the register 328. The combination of delay circuit 322, latch array 324, binary encoder 326, counter 330, and register 328 form phase demodulator 32.
[0073]
The output of register 328 is coupled to the input of bit decompressor 362. The output of this bit decompressor is coupled to the data input of the first boxcar filter 364. The output of the first boxcar filter 364 is coupled to the data input of the second boxcar filter 366. The output of the second boxcar filter is coupled to the data input of the third boxcar filter 368. Third Boxcar Filter 368Is coupled to the input of barrel shifter 370. The output of barrel shifter 370 is coupled to the input of latch 392. Latch 392 generates phase representation data (data representing the phase) representing the phase characteristics of the serial binary input signal and is coupled to output terminal "phase data".
[0074]
The system clock signal from the PLL 14 is also supplied to the input terminal of the frequency divider 372. The output of divider 372 is coupled to the input of clock selector 374. An output of the clock selector 374 is coupled to an input of the first fixed frequency divider 376 and to respective clock inputs of the first and second boxcar filters 364 and 366. The output of the first fixed frequency divider 376 is coupled to the input of the second fixed frequency divider 394 and the clock input of the third boxcar filter 368. The output of the second fixed frequency divider 394 is coupled to the clock input of the latch 392. Bit decompressor 362, first, second and third boxcar filters 364, 366 and 368, barrel shifter 370, clock divider 372, clock selector 374, first fixed divider The combination with the device 376 forms the anti-aliasing filter 36. The combination of the latch 392 and the second fixed frequency divider 394 forms the decimator 39.
[0075]
In operation, the combination of the delay circuit 322, the latch array 324, and the binary encoder 326 operate to detect edges in the serial binary input signal at the input terminal IN in a manner described in detail below. When an edge is detected, the binary encoder generates a signal at its clock output. With this signal, the register 328 latches data at each data output terminal of the counter 330 and the binary encoder 326. Counter 330 counts the number of system clock cycles. Thus, the value of the count latched in register 328 represents an integer number of system clock cycles from the previously detected edge. This gives a rough instruction of the edge position.
[0076]
FIG. 15 is a detailed block diagram of the delay circuit 322 and the latch array circuit 324 as shown in FIG. In FIG. 15, the latch array 324 comprises an array of eight rows of latches, each row including eight latches. Each latch is a D flip-flop, and each D flip-flop has a D input, a clock input (shown as a small triangle), a Q output (sign Q only for the upper left latch L0 of latch array 324). Shown). A total of 64 flip-flops form an 8-by-8 array.
[0077]
The φ1 clock signal is commonly supplied to the clock input terminals of the eight D flip-flops in the first (leftmost) column. These latches are labeled L0 to L7 from the top row to the bottom row. The outputs of these latches are coupled to output terminals Q0-Q7 of latch array 324, respectively. The φ2 clock signal is commonly supplied to the clock input terminals of the eight D flip-flops in the second column. These latches are labeled L8 to L15 from the top row to the bottom row. The output terminals of these latches are respectively coupled to output terminals Q8-Q15 (omitted for simplicity of the figure). The φ3 clock signal is commonly supplied to the clock input terminals of the eight D flip-flops in the third column. These latches are labeled L16 to L23 from the top row to the bottom row. The outputs of these latches are respectively coupled to output terminals Q16-Q23 (omitted for simplicity of illustration). The φ4 clock signal is commonly supplied to the clock input terminals of the eight D flip-flops in the fourth column. These latches are labeled L24 to L31 from the top row to the bottom row. The output terminals of these latches are respectively coupled to output terminals Q24-Q31 (omitted for simplicity of illustration).
[0078]
The φ5 clock signal is commonly supplied to the clock input terminals of the eight D flip-flops in the fifth column. These latches are labeled L32 to L39 from the top row to the bottom row. The outputs of these latches are respectively coupled to output terminals Q32-Q39 (omitted for simplicity of the figure). The φ6 clock signal is commonly supplied to clock input terminals of eight D flip-flops in the sixth column. These latches are labeled L40 to L47 from the top row to the bottom row. The outputs of these latches are respectively coupled to output terminals Q40-Q47 (omitted for simplicity of the figure). The φ7 clock signal is commonly supplied to clock input terminals of eight D flip-flops in the seventh column. These latches are labeled L48 to L55 from the top row to the bottom row. The outputs of these latches are respectively coupled to output terminals Q48-Q55 (omitted for simplicity of the figure). The φ8 clock signal is commonly supplied to the clock input terminals of the eight D flip-flops in the eighth column (the rightmost column). These latches are labeled L56 to L63 from the top row to the bottom row. The outputs of these latches are coupled to output terminals Q56-Q63, respectively (only Q62 and Q63 are shown for simplicity).
[0079]
The input terminal IN is connected to the first delay circuit 322 (1), the second delay circuit 322 (2), the third delay circuit 322 (3), the fourth delay circuit 322 (4), the fifth delay circuit 322 (5), The sixth delay circuit 322 (6) and the seventh delay circuit 322 (7) are coupled to the serially connected input terminals. First delay circuit 322 (1), second delay circuit 322 (2), third delay circuit 322 (3), fourth delay circuit 322 (4), fifth delay circuit 322 (5), sixth delay circuit 322 The combination of (6) and the seventh delay circuit 322 (7) forms the delay circuit 322.
[0080]
At the output of the seventh delay circuit 322 (7), the C0 input signal to the latch array 324 occurs, and the first (top) row of latches (L0, L8, L16, L24, L32, L40, L48 and L56). Are commonly supplied to the input terminal D of the At the output of the sixth delay circuit 322 (6), the C1 input signal to the latch array 324 occurs, and the inputs of the second row of latches (L1, L9, L17, L25, L33, L41, L49 and L57). D is supplied in common. At the output of the fifth delay circuit 322 (5), the C2 input signal to the latch array 324 occurs, and the inputs of the third row of latches (L2, L10, L18, L26, L34, L42, L50 and L58). D is supplied in common. At the output of the fourth delay circuit 322 (4), a C3 input signal to the latch array 324 is generated, and the input of the fourth row of latches (L3, L11, L19, L27, L35, L43, L51 and L59). D is supplied in common. At the output of the third delay circuit 322 (3), the C4 input signal to the latch array 324 occurs, and the inputs of the fifth row of latches (L4, L12, L20, L28, L36, L44, L52 and L60). D is supplied in common. At the output of the second delay circuit 322 (2), a C5 input signal to the latch array 324 is generated, and the inputs of the sixth row (L5, L13, L21, L29, L37, L45, L53 and L61) of the latch. D is supplied in common. At the output of the first delay circuit 322 (1), a C6 input signal to the latch array 324 occurs, and the inputs of the seventh row of latches (L6, L14, L22, L30, L38, L46, L54 and L62). D is supplied in common. The input terminal IN produces a C7 input signal to the latch array 324, which is commonly supplied to the input D of the eighth row of latches (L7, L15, L23, L31, L39, L47, L55 and L63).
[0081]
The operation of the demodulator 32 of FIG. 14 and, in particular, the delay circuit 322 and latch array 324 of FIG. 15 can be better understood with reference to the waveform diagram of FIG. In FIG. 16, the uppermost waveform is a part of the serial binary input signal (IN) which is the rising edge. The second waveform is the system clocksignalAnd, as mentioned above, this leading edge is the polyphase system clock.signalIs the phase φ0. Counter 330 (FIG. 14) increments the count on each rising edge of the system clock signal. In the illustrated waveform, the rising edge of the serial binary input signal occurs after the counter 330 has reached the value 83 and before incrementing to 84. As described above, the combination of delay circuit 322, latch array 324, and binary encoder 326 detects an edge and causes register 328 to latch the value of counter 330 in response to the detection of the edge. In the illustrated waveform, register 328 latches the value 83.
[0082]
The next eight waveforms are the polyphase system clocksignalIs shown. These signals define eight phase sections W0 to W7, as described in detail below. The next waveform is the higher resolution serial binary input signal (IN), which is also the signal C7 provided to the latch array 324. The rising edge occurs at approximately three quarters of the phase interval W5.
[0083]
In operation, each of the delay circuits 322 (X) provides a fixed delay of 1/64 of the system clock signal. The serial binary input signal passes through a series connection of delay circuits 322 (1) -322 (7) to form delay signals C0-C7. Latches L0-L7 receive signals C0-C7, respectively, and are clocked by the phase φ1 signal. Therefore, the latches L0 to L7 latch the eight delayed signals C0 to C7 at the rising edge of the phase φ1 signal, and generate the signals latched at the output terminals Q0 to Q7, respectively. In the illustrated waveform, these signals are all logic 0 signals. Latches L8 to L15 are clocked by the phase φ2 signal, latch eight delayed signals C0 to C7 at the rising edge of the φ2 signal, and output the signals latched at output terminals Q8 to Q15 (not shown). Each occurs. Hereinafter, the same applies. In particular, the latches L40 to L47 latch eight delayed signals C0 to C7 generated at the rising edge of the phase φ6 signal, and generate the signals latched at the output terminals Q40 to Q47, respectively. The values of these samples will be described later. Latches L56 to L63 latch eight delayed signals C0 to C7 at the rising edge of the phase φ0 signal, and generate signals latched at output terminals Q56 to Q63, respectively. These signals are all logic ones.
[0084]
In FIG. 16, the C7 signal is indicated by a thick line. Each of the C6-C0 signals is delayed by 1/64 of the system clock period with respect to the previous signal, and is shown by a thin line in FIG. At the rising edge of the phase φ6 signal, the rising edge of the serial binary input signal that is the C7 signal has already occurred. Therefore, the C7 signal is a logical 1 signal. The latch L47 that receives the C7 signal latches the logic 1 signal and generates a Q47 output signal that is a logic 1 signal. Similarly, at the rising edge of the phase φ6 signal, the rising edges of the C6 and C5 signals also occur. Therefore, the latches L46 and L45 receiving the C6 and C5 delay signals latch the logic 1 signal and generate the logic 46 Q46 and Q45 output signals, respectively.
[0085]
Conversely, the C4 delayed signal at the rising edge of the phase φ6, that is, the rising edge of the C4 delayed signal has not yet occurred. Therefore, the latch L44 that receives the C4 delay signal latches the logic 0 signal and generates a Q44 output signal that is a logic 0 signal. Similarly, at the rising edge of the phase φ6 signal, the rising edges of the C3 and C0 signals have not yet occurred. Therefore, the latches L43 to L40 that receive the C3 to C0 delay signals latch the logic 0 signal and generate the Q43 to Q40 output signals, which are logic 0 signals, respectively.
[0086]
The binary encoder 326 processes the Q0 to Q63 signals to detect an edge. All logical values of the Q0 to Q63 signals are the same (that is, all are logical 1 signals or all logical 0 signals). This is the case when the system clock interval is before or after the system clock interval in which the count of the counter 33 is 83. In FIG. 16, the upper three waveforms are referred to. For the preceding system clock interval, the Q0-Q63 signals are all logic zero signals. Further, for the subsequent system clock section, the Q0 to Q63 signals are all logic 1 signals. In this case, no clock signal is generated at the clock output terminal of the binary encoder 326.
[0087]
However, if two adjacent Q signals have different logical values, the binary encoder 326 detects an edge. In the waveform shown in FIG. 16, during the system clock interval in which the counter has a value of 83, signal Q44 is a logic 0 value and signal Q45 is a logic 1 value. This indicates a leading edge. In a similar manner, the signal Q_nIs a logical 1 value and the signal Q_{n + 1}If is a logical zero value, a trailing edge is detected. In each case, a multi-bit binary signal, which is the value of the number of Q signals immediately before the change of the logical value, is supplied to the register 328 by the binary encoder 326, and the clock signal is supplied to the register 328.
[0088]
In the illustrated embodiment, a 6-bit binary signal having a value of 44 is provided to register 328. Register 328 responds to the clock signal from binary encoder 326 with the value of counter 330 (representing the number of complete clock cycles since the last detected edge) and the value from encoder 326 (current system). Latch (representing the fractional position of the edge in the clock cycle). In the illustrated embodiment, the output from register 328 is a 15-bit digital signal. In a preferred embodiment, register 328 operates in a synchronous manner to receive the system clock at the clock input terminal and the clock output signal from binary encoder 326 at the latch enable input terminal.
[0089]
The edge detection function in the binary encoder 326 is represented by Q_nAnd Q_{n + 1}Exclusive OR (Q_n  EOR Q_{n + 1}) Can be obtained by calculating for all n. For all n, (Q_n  EOR Q_{n + 1}If) = 0 (ie, if all signals have the same logical value), no edge is detected and no clock signal is generated in register 328. For any n, (Q_n  EOR Q_{n + 1}) = 1 (that is, Q_nIs Q_{n + 1}Binary encoder 326 generates a value of n at the data output terminal and generates a clock signal for register 328.
[0090]
In the illustrated embodiment, eight delayed signals are provided to each of the eight rows of the latch, and eight columns of the latch receive each of the eight phase signals from the polyphase system clock to provide a system clock. A detection resolution of 1/64 of the cycle is given. One skilled in the art will appreciate that other configurations are possible. For example, sixteen delay circuits providing a delay of 1/128 of the system clock period can be coupled to each of the sixteen rows of the latch, and eight columns of the latch provide eight individual positions from the polyphase system clock. Upon receiving the phase signal, a detection resolution of 1/128 of the system clock period can be achieved. Alternatively, eight delay circuits providing a delay of 1/128 of the system clock period can be coupled to each of the eight rows of the latch, and sixteen columns of the latch are used to provide sixteen phase signals of the polyphase system clock. As a result, a detection resolution of 1/128 of the system clock period can be achieved. Alternatively, sixteen delay circuits, which provide a delay of 1/256 of the system clock, are coupled to each of the sixteen rows of the latch, and the sixteen columns of the latch provide the sixteen phase signals from the polyphase system clock. And a detection resolution of 1/256 of the system clock period can be achieved.
[0091]
Edge position data from register 328 that occurs during each detected edge is also available to other circuit elements. For example, in the illustrated embodiment, edge position data is provided to a phase modulator 26, which generates a reproduced serial binary signal based on the data. Similarly, other functions can be performed in response to this data.
[0092]
The edge position data from the register 328 is also supplied to the anti-aliasing filter 36. As described above, for the interpolation filter 22 (FIG. 4), the combination of the divider 372 and the clock selector 374 provides anti-aliasing at either the system clock frequency or a divisor of this system clock frequency. Operate to select the clock frequency for the filter 36. As described above, the counter 330 that receives the system clock provides the clock dividing function of the frequency divider 372.
[0093]
The clock signal selected from the clock selector 374 becomes a clock signal for the first and second boxcar filters. This signal is counted by a first fixed frequency divider 376 to count M₃, And the second fixed frequency divider 394 counts M₄Divided by The output clock signal from the first fixed frequency divider 376 becomes a clock signal for the third boxcar filter 368, and the output clock signal from the second fixed frequency divider 394 becomes a clock signal for the latch 392.
[0094]
The anti-aliasing filter 36 includes a series connection of a first-order low-pass filter and bit expander 362 and three boxcar filters 364, 366, and 368, each of which has a predetermined time window. Average the input samples over The bit decompressor 362 is implemented as a primary LPF. In the embodiment shown, this is implemented in a known manner as an IIR filter. Further, the bit expander 362 expands the number of bits of the output signal from 15 bits that can be used by the register 328 to 23 bits. The series connection of the first and second boxcar filters 364 and 366 operates to average M samples on the selected filter clock from the clock selector 374. The third boxcar filter 368 has a fixed coefficient M₃Operates to average M samples at the selected filter clock frequency divided by. The output signal from the third boxcar filter 368 is a low pass filtered version of a series of edge position data signals from register 328. This filtering action prevents aliasing artifacts that occurred during the decimation process in a known manner. As described above, barrel shifter 370 shifts the filtered phase data signal to account for gain changes induced by the low pass filtered boxcar filter. Latch 392 latches one output phase data signal from all of the M edge position data from register 328. Note that M = M₃・ M₄It is. These output phase data samples are provided to post processor 25 (FIGS. 1 and 2), and the clock signal to latch 392 operates as a strobe signal for post processor 25.
[0095]
As described above, for some of the above signal processing, the clock output signal synthesizer can be shared with the processor 5 and the serial binary signal analyzer can be shared with the post processor 25. is there. FIGS. 17 to 20 are detailed block diagrams of the anti-aliasing filter 36 shown in FIG. 14, and the technique shown in FIGS. 17 to 20 can be applied to the interpolation filter shown in FIG.
[0096]
17 to 20 are four block diagrams of the configuration of the anti-aliasing filter 36 in FIG. FIG. 17 is a simplified block diagram of the anti-aliasing filter 36 shown in FIG. In FIG. 17, a series connection of first, second and third boxcar filters 364, 366 and 368 is coupled between a source of the edge position data signal and a latch 392. The first and second boxcar filters 364 and 366 provide a baud rate F_BAUDIs clocked by the clock signal. The third boxcar filter 368 is_BAUD/ M₃Is clocked by the clock signal. Latch 392 is_BAUD/ M clocked by the clock signal. Note that M = M₃・ M₄And this clock signal is a strobe signal.
[0097]
As is well known, the averaging function is considered to be a combination of a relatively high-speed operation accumulation function and a relatively low-speed operation differentiation function. FIG. 18 shows each of the first, second and third boxcar filters 364, 366 and 368 which can be decomposed in a known manner into a series circuit of accumulators and differentiators. The first boxcar filter 364 includes a series connection with the accumulator 42 and the differentiator 44, and the second boxcar filter 366 includes a series connection with the accumulator 62 and the differentiator 64. Boxcar filter 368 includes a series connection with accumulator 82 and differentiator 84. Since the accumulation and differentiation processes are linear processes, the accumulators 42, 62, 82 and the differentiators 44, 64, 84 can be connected in series in any order.
[0098]
FIG. 19 shows a different configuration in which three accumulators 42, 62 and 82 are connected before three differentiators 44 ', 64' and 84 '. In FIG. 19, first and second accumulators 42 and 62 have a baud rate F_BAUD, And the third accumulator 82 outputs F_BAUD/ M₃Clock at a rate of These three differentiators 44 ', 64', 84 'are all F_BAUD/ M₃Clocked by a clock signal at a rate of
[0099]
FIG. 20 shows another configuration in which a latch 392 is arranged with a series connection of three accumulators 42, 62 and 82 and a series connection of three differentiators 44 ", 64" and 84 ". , The latch 392 and the three differentiators 44 ″, 64 ″, and 84 ″_BAUDAll are clocked by the clock signal at a rate of / M. This arrangement groups the differentiating circuits 44 ", 64" and 84 "at the end of the signal processing chain. In the illustrated embodiment, the three accumulators 42, 62 and 82 and the latch 392 are , On the other hand, the differentiators 44 ", 64" and 84 "are formed outside of this chip in the post processor 25 of FIG.
[0100]
The boxcar filters 224 and 226 in the interpolation filter 22 shown in FIG. 4 can likewise be decomposed into accumulators and differentiators, arranged such that the differentiators are configured outside the integrated circuit chip of the preprocessor 5. it can. The rearrangement of the process disclosed herein does not change the functionality described above, but shifts to a relatively slow process outside of the chip and reduces the circuits that need to be created on the integrated circuit chip. This reduces the cost of such a chip and any equipment using such a chip.
[0101]
A comparison of the interpolation filter 22 of FIG. 4 with the anti-aliasing filter 36 of FIG. 14 shows that the same elements are shared by both of these filters. For example, a series circuit of a PLL 14, a clock divider (232 and 372), a clock selector (234 and 374), a first fixed divider (236 and 376), and a second fixed divider (238 and 394) is provided. , Interpolation filter 22 and anti-aliasing filter 36. Using any technique known to those skilled in the art, the remaining elements, the first boxcar filter (224 and 364), the second boxcar filter (226 and 366), and the third boxcar filter (230 and 362), barrel filters (228 and 370), and latches (222 and 393) can be electrically reconfigured by switching the clock input and data to the appropriate output of the corresponding other element. . Similarly, the input terminal of the phase modulator 26 is electrically switched to the output of the interpolator 22 when the system operates as a clock signal synthesizer, and the phase demodulator 32 when the system operates as a clock signal analyzer. May be electrically switched to the output terminal. FIG. 1 andFigureIn 2, the operation mode can be controlled by a control signal supplied from the system controller (not shown) to the system 10 via the control interface 12. Control interface 12 provides appropriate control signals to the switching elements to couple the illustrated elements in a desired manner.
[0102]
The serial binary signal synthesizer described above receives the phase representation data synchronous with the fixed frequency system clock, and the serial binary signal analyzer generates the phase representation data in synchronization with the fixed frequency system clock. Such a system that operates synchronously is easy to use as part of a measuring instrument. Further, the digital filtering required in such a system, ie, the interpolation and anti-aliasing filters, is easy to design and implement. Further, it will be appreciated that the serial binary signal analyzer can operate on data signals with or without the presence of edges and without the need for a separate clock recovery circuit.
[0103]
【The invention's effect】
As described above, according to the present invention, accurate and high-resolution edge arrangement can be performed without requiring a system clock having a frequency much higher than the frequency of the synthesized clock signal, and operation can be performed in a synchronized state.
[Brief description of the drawings]
FIG. 1 is a block diagram of a phase measurement / generator system for a serial binary signal.
FIG. 2 is a block diagram of a phase measurement / generator system for a serial binary signal.
FIG. 3 is a block diagram of a clock signal synthesizer used in the systems shown in FIGS. 1 and 2;
FIG. 4 is a more detailed block diagram of the clock signal synthesizer shown in FIG.
FIG. 5 is a waveform diagram useful for understanding the operation of the phase measurement / generator system according to the present invention.
6 is a more detailed block diagram of an interpolator used in the clock signal synthesizer of FIG.
FIG. 7 is a more detailed block diagram of an interpolator used in the clock signal synthesizer of FIG.
8 is a more detailed block diagram of an interpolator used in the clock signal synthesizer of FIG.
FIG. 9 is a waveform diagram useful for understanding the operation of the phase modulator in the clock signal synthesizer shown in FIGS. 3 and 4.
FIG. 10 is a waveform diagram useful for understanding the operation of the phase modulator in the clock signal synthesizer shown in FIGS. 3 and 4.
FIG. 11 is a diagram useful in understanding the operation of the phase modulator in the clock signal synthesizer shown in FIGS. 3 and 4.
FIG. 12 is a diagram useful in understanding the operation of the phase modulator in the clock signal synthesizer shown in FIGS. 3 and 4;
FIG. 13 is a block diagram of a serial binary input signal analyzer used in the system shown in FIGS. 1 and 2;
FIG. 14 is a more detailed block diagram of the serial binary input signal analyzer shown in FIG.
FIG. 15 is a more detailed block diagram of the delay and latch array circuit shown in FIG.
FIG. 16 is a waveform diagram useful for understanding the operation of the serial binary input signal analyzer shown in FIGS. 14 and 15;
FIG. 17 is a more detailed block diagram of a filter used in the serial binary input signal analyzer shown in FIG.
FIG. 18 is a more detailed block diagram of a filter used in the serial binary input signal analyzer shown in FIG.
19 is a more detailed block diagram of a filter used in the serial binary input signal analyzer shown in FIG.
FIG. 20 is a more detailed block diagram of a filter used in the serial binary input signal analyzer shown in FIG.
[Explanation of symbols]
5 Pre-processor
10 Phase measurement / generator system
12 Control interface
14 PLL
15 Loop filter
20 Synthesizer
22 Interpolation filter
25 Post Processor
26, 220 modulator
222 latch
226, 228 Boxcar filter
229 Shifter
230 bit expander
234 Clock selector
262 counter
272 decoder
278 Comparator

Claims (1)

The source of the system clock signal;
A control interface;
A phase modulator;
A phase demodulator;
A system comprising: a system configurable filter coupled to the phase modulator and the phase demodulator, receiving the system clock signal from the signal source, and receiving control from the control interface,
The system is configured to operate in first and second modes of operation in response to control from the control interface,
In the first mode,
The reconfigurable filter is configured to operate as an interpolator, identifies a predetermined phase characteristic of a clock output signal, receives phase data synchronized with the system clock signal, and responds to the phase data with an edge. Generate a placement data signal,
The phase demodulator is coupled to the configurable filter, receives the edge-located data signal, and has an edge located at a time determined by each of the edge-located data signals in response to the system clock signal. Generates a clock output signal,
In the second operation mode,
The phase demodulator receives a serial binary input signal and continuously generates an edge position data signal representing a state transition of the serial binary input signal in response to the system clock signal;
The configurable filter is configured to operate as an anti-aliasing filter and decimation, is coupled to the phase demodulator, receives the edge position data signal, and synchronizes with the system clock signal. A synthesizer and signal analyzer system for generating phase data from an edge position data signal.

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