JP2006109521A - Signal analyzer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate phase data representing an edge position of a serial binary input signal. <P>SOLUTION: The signal analyzer comprises a phase demodulator 32 which receives a serial binary input signal and continuously generates edge position data signals representing shift positions of this serial binary input signal, and a decimeter 39, coupled through an anti-aliasing filter 36 to the phase demodulator, for generating phase data from the edge position data signals synchronously with a system clock signal and asynchronously with the generation of edges. The anti-aliasing filter prevents aliasing in decimeter processing. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a serial binary signal analyzer.

  Digitally controlled clock signal synthesizers are known. A system known as an arbitrary waveform generator includes a signal source for a series of digital control signals that represent the value of the output clock signal at each point in time. The rate at which the digital control signal is supplied is controlled by the system clock, but its frequency is generally much higher than the frequency of the synchronized clock signal. These digital control signals are supplied to a digital-to-analog converter (DAC). The analog output signal from the DAC is filtered by a low pass filter and compared with a threshold value by a threshold detector to detect its level. The output signal of the threshold detector is a synthesized clock signal.

  During the system clock, the amplitude value of the digital signal is maximum when the synthesized clock signal is high. Also, during the system clock period, the amplitude value of the digital signal is minimum when the synthesized clock signal is low. During the system clock where the leading edge (leading edge) and trailing edge (trailing edge) occur, the amplitude value of the digital signal is intermediate. The DAC generates an analog signal having a level corresponding to the value of the digital signal. For example, at the leading edge, the clock signal transitions from the minimum value of the previous system clock cycle to the maximum value of the next system clock cycle. In the leading edge system clock period, the low-pass filtered analog signal rises relatively slowly due to an intermediate digital control signal close to the minimum value. Cross the level. On the contrary, the digital signal at an intermediate value close to the maximum value causes the low-pass filtered analog signal to rise relatively quickly, so that the signal crosses the threshold level relatively easily. In this case, this leading edge occurs relatively easily in the system clock period. The same applies to the trailing edge. In this way, the digital clock signal may be combined with a leading edge and a trailing edge that occupy less than one portion of the system clock period.

  Such a system can generate a composite clock signal having edges that are accurately positioned with relatively high resolution. However, such a system requires a system clock with a frequency much higher than the frequency of the synthesized clock signal. When a relatively high frequency synthesis clock is required, such a system can provide a very high frequency system clock signal with a high speed signal source of digital control signals, a DAC, a low pass filter, and threshold detection. Need a vessel. Such high frequency components are either very expensive or technically impossible.

  Other techniques have also been developed that generate a composite clock signal with relatively high resolution and precisely positioned edges without the need for high speed components. For example, Black et al., US Pat. No. 5,394,106, issued February 28, 1995, “Apparatus and Method for Combining Multiple Signals with Programmable Periods” discloses such a system. The system described in this US patent includes a signal source for a series of digital control signals, a counter clocked by a system clock, a magnitude comparator, and a variable delay circuit. The digital control signal represents the time from the last generated edge to the next desired edge. The first part of each digital control signal represents the integer part of how many times the system clock cycle is from the previous edge of the composite clock signal to the desired time of the next edge. The second part of each digital control signal represents the fractional part of how many times the system clock cycle is from the previous edge to the desired time of the next edge. The digital control signal is coupled via an accumulator to one input of the magnitude comparator and supplies the value from the counter to the second input of the magnitude comparator. The counter counts system clock cycles. When the required number of clock cycles have been counted (ie, the desired count has been reached), the magnitude comparator generates a logic “1” signal to indicate a match. Thus, the fractional portion of the digital control signal adjusts the variable delay circuit to delay the logic “1” output signal from the magnitude comparator by the required portion of the system clock cycle. The delayed output signal from the variable delay circuit has an edge in the synthesized clock signal.

  The above-mentioned US Pat. No. 5,394,106 system does not require the frequency of the system clock signal to be significantly higher than the frequency of the synthesized clock signal, and places an edge in the synthesized clock signal at a fractional resolution of the system clock cycle. can do. Instead, the frequency of the system clock signal is on the same order as the highest frequency desired for the synthesized clock signal. However, a system such as that described in US Pat. No. 5,394,106 requires a new digital control signal from a digital control signal source in response to a “match” signal from the magnitude comparator. This is when an edge corresponding to the final digital control signal occurs. Since such a system can and will be used to generate a phase modulation composite clock signal (for jitter response measurement), it requires a new digital control value with variations in time period. That is, the input digital control value is received asynchronously with respect to the system clock.

  First, however, those skilled in the art will appreciate that synchronous digital systems are easy to design, implement, and integrate with other digital systems. The asynchronous nature of the aforementioned US Pat. No. 5,394,106 makes it difficult to integrate such a system into a digital system. Second, asynchronous systems are difficult to design and implement for accurate filtering. Thus, the desired clock signal synthesizer does not require a much higher frequency system clock than the synthesized clock signal, enables accurate and high resolution edge placement and is synchronized (ie synchronized to the system clock). In a state of receiving a digital control signal).

  Clock signal analyzers are known. Such an analyzer generates data representing the phase of the input clock signal. In a method corresponding to the clock signal generator described above, one clock signal analyzer includes a counter that starts counting at one edge of the input clock signal and stops at the next edge. This counter is clocked by the system clock (counts the system clock), and at the end of the counting period, the count value indicates the time between the two edges.

  The resolution of the above method is the system clock period. The finer resolution (higher resolution) method includes two ramp generators to achieve finer resolution than the system clock. Multiple pulses are used to indicate the position of the edge within the clock signal to be analyzed. A start pulse triggers a ramp generator that is configured to change from a minimum voltage to a maximum voltage during the system clock period. This ramp generator maintains the ramp until the beginning of the next system clock cycle. At the beginning of the next system clock cycle, the value of the ramp signal is converted to a digital signal, indicating the fractional portion of the clock cycle from the start pulse to the start of the next system clock cycle. Here, a low value indicates that a start pulse has occurred near the end of the system clock cycle, and a high value indicates that a start pulse has occurred immediately after the start of the system clock cycle. The start pulse enables (activates) the counter and starts counting system clock cycles. The stop pulse disables the counter and triggers the second ramp generator. This second slope generator operates in the same manner as the first slope generator to generate a digital value indicating the fractional part of the system clock cycle from the stop pulse to the start of the next system clock cycle. To do. The value of the second slope generator is also converted to a digital value. Thus, the period between the start and stop pulses is [number of system clock cycles of the counter] plus [first complete system clock cycle represented by the digital value of the first ramp generator] and the start pulse. The fractional portion of the clock cycle between] and minus [the fractional portion of the clock cycle between the next complete system clock cycle represented by the digital value of the second ramp generator and the stop pulse].

United States Patent No. 5,394,106

  It is not always necessary to identify each edge of the synthesized clock signal and analyze the time of each edge of the input clock signal. In some cases, it is sufficient to provide edge data and receive edge timing data at a rate lower than the edge rate in the synthesized or analyzed data signal.

  In accordance with the principles of the present invention, a digital phase synthesizer comprises a signal source for continuous phase data signals (continuous phase data signals). The interpolator generates a continuous edge arrangement data signal (continuous edge arrangement data signal) in response to each of the continuous phase data signals. The phase modulator generates an output clock signal having edges located at times determined by the continuous edge placement data signal. Similarly, the digital phase analyzer comprises a signal source for a serial binary input signal having edges. The phase demodulator generates a continuous data signal that represents the location of each edge of the serial binary input signal. The decimator (decimation circuit) generates a phase data signal at a slower rate than the edge of the serial binary input signal.

  The clock signal synthesizer according to the present invention enables accurate and high-resolution edge placement without requiring a system clock with a frequency much higher than the frequency of the synthesized clock signal. Operate.

  As described above, according to the present invention, an accurate and high-resolution edge arrangement is possible and a synchronous operation is possible without requiring a system clock having a frequency much higher than the frequency of the synthesized clock signal.

  1 and 2 are block diagrams of a phase measurement / generator system 10 for digital signals. The system shown in FIGS. 1 and 2 can be modified. FIG. 1 is a block diagram of a system 10 configured to generate a clock output signal in response to a phase data signal, and FIG. 2 is a system configured to measure the phase of a serial binary input signal. 10 is a block diagram of FIG. Those elements that are the same in FIGS. 1 and 2 are indicated with the same reference numerals.

  1 and 2, input terminal IN is coupled to a system controller (not shown). The system controller generates a signal that specifies the desired phase characteristics of the generated clock output signal. The input terminal IN is also coupled to the input end of the pre-processor 5. The output of pre-processor 5 is coupled to the input of phase synthesizer 20. The data output terminal of the phase synthesizer 20 is coupled to the clock output terminal, and the strobe signal output terminal of the phase synthesizer 20 is coupled to the corresponding input terminal of the pre-processor 5.

  The control input terminal is coupled to a system controller (not shown) and receives data that controls the configuration and operation of the system 10. This control input terminal is also coupled to the input end of the control interface circuit 12. A status signal indicating the operating state of the system 10 is generated from the status output terminal of the control interface circuit 12 and supplied to the system controller.

  The reference clock signal is supplied to a reference input terminal of a phase locked loop (PLL) 14. A loop filter 15 is also coupled to the PLL 14. The PLL 14 provides a clock signal to various elements of the system 10. These elements are synchronized to the reference clock in a known manner. These clock signals are not shown in FIGS. 1 and 2 for the sake of simplicity.

  In FIG. 2, the input terminal IN is coupled to a signal source of a serial binary input signal. Input terminal IN is coupled to the input end of phase analyzer 30. The phase data output of the phase analyzer 30 is coupled to the data input of the post processor 25. The output end of the post processor 25 is an output terminal that generates data representing the detected phase characteristics of the serial binary input signal. The strobe output of analyzer 30 is coupled to the corresponding input of post processor 25. Further, the recovered clock output terminal from the analyzer 30 is coupled to the receive clock output terminal. The rest of the system shown in FIG. 2 is the same as that shown in FIG. 1 and 2, the system 10 in FIG. 1 is the same as the system 10 in FIG. 2, and details will be described later.

  In operation, a system controller (not shown) provides control data to the system 10 via a control input terminal. The control interface 12 receives and saves information in any one of a variety of known ways. For example, the control input terminal can be coupled to a multi-bit parallel digital bus. This digital bus is coupled to a microprocessor. Instead, in the illustrated embodiment, the control input terminal includes a serial data signal line, a clock signal line, and a control line for controlling the flow of data between the control interface 12. Digital input terminal. The control interface 12 includes a register, which is coupled to the control input terminal and stores various values received from the control input terminal. The plurality of output terminals of the register are coupled to various circuits in the system 10 and all control these circuits in a known manner.

  Similarly, the control interface includes registers, latches, or transmission gates (as required), and these inputs are coupled to points in the system 10 to monitor their values. . The output terminals of these circuits are coupled to the status output terminal. In addition, the above-described register holding the control value also has an output terminal coupled to the status output terminal. It is also possible to share such a register so that one part holds the control value and the other part supplies the status value. Depending on the control input terminal, the status output terminal can be a multi-bit parallel digital bus or, as in the illustrated embodiment, includes a data signal line, a clock signal line and optional control lines. Can also be a serial signal line. A system controller (not shown) reads data from these circuits in all known ways to determine the current state of the system 10.

  In FIG. 1, a system controller (not shown) supplies control data to the control interface 12 to configure the system 10 to operate as a clock output signal generator in a manner that will be described in detail below. In this operation mode, the synthesizer 20 transmits a strobe signal to the pre-processor 5 when new phase data is requested. In response to this strobe signal, the pre-processor 5 supplies data (phase data) indicating the desired phase characteristics of the clock output signal to the synthesizer 20. As will be described in detail later, the pre-processor 5 performs the substantial signal processing together with the phase synthesizer 20, or the input phase characteristic signal received directly from the input terminal IN without performing the substantial processing. Is passed through the phase synthesizer 20. However, in the illustrated embodiment, relatively low-speed signal processing is executed by a method described later together with a relatively high-speed circuit in the phase synthesizer 20.

  The synthesizer 20 generates a clock output signal having edges arranged according to the phase data received from the pre-processor 5. The edge of this clock output signal occurs at a predetermined rate (baud). Note that phase modulation of these edges is also performed. However, as will be described in detail later, phase data from the pre-processor 5 is required at a constant rate (via a strobe signal). This rate may be lower than a predetermined edge (baud) in the output serial binary signal. That is, the edge generated by the clock output signal becomes asynchronous with respect to the phase data from the pre-processor 5.

  In FIG. 2, a system controller (not shown) provides control data to the control interface 12 to configure the system 10 to operate as a serial binary input signal measurement system in a manner that will be described in detail below. In this mode of operation, the analyzer 30 receives a serial binary input signal. The edges of this serial binary input signal occur at approximately a predetermined rate (baud) but are not phase modulated. The analyzer 30 calculates data indicating elapsed time from each edge to the next consecutive edge in the serial binary input signal, and a series of phase expression data signals indicating the phase characteristics of the serial binary input signal received by the analyzer 30. Generate "phase data". These phase representation data signals “phase data” are available to the post processor 25 along with the strobe signal. The strobe signal indicates that new phase expression data “phase data” is available. In response to the strobe signal, the post processor 25 receives the phase representation data “phase data” and generates an output signal indicative of the phase characteristics of the serial binary input signal. In a manner similar to the pre-processor 5 described above, the post-processor 25 may perform substantial signal processing, or do not perform any substantial processing on the phase data output signal “phase data” received directly from the analyzer 30. Instead of performing typical signal processing, the signal may be passed through the phase characteristic output terminal. However, in the illustrated embodiment, the post processor 25 performs relatively slow signal processing in addition to the relatively fast signal processing performed by the analyzer 30 in a manner that will be described in detail below.

  Similar to the digital clock generation system described above with reference to FIGS. 1 and 2, and also being phase modulated, the edges in the serial binary input signal have a predetermined rate (baud) as will be described in detail below. Phase data is provided to the post processor 25 at a constant rate (via a strobe signal). Thus, phase data is generated asynchronously with the edges in the serial binary input signal. Further, in the illustrated embodiment, the analyzer 30 generates a recovered clock signal having approximately the same phase as the received serial binary input signal.

  FIG. 3 is a block diagram of the clock signal synthesizer 20 used in the system 10 shown in FIGS. In FIG. 3, phase data from pre-processor 5 (FIGS. 1 and 2) is coupled to the input of interpolation filter 22. The strobe signal output of the interpolation filter 22 is coupled to the corresponding input of the pre-processor 5. The data output end of the interpolation filter 22 is coupled to the input end of the phase modulator. The output of the phase modulator 26 is coupled to the clock signal output terminal.

  In operation, the interpolation filter 22 requests phase data from the pre-processor 5 by activating the strobe signal. In response to the strobe signal, the pre-processor 5 supplies data indicative of the desired phase characteristics of the clock output signal in a known manner as described above. Next, the interpolation filter 22 generates a plurality of continuous edge arrangement data signals, each of which identifies the position of one edge in the clock output signal. In this method, the interpolation filter 22 generates a plurality of edge arrangement signals. With these signals, the phase modulator 26 generates a clock output signal. As will be described later in detail, the phase characteristic of the clock output signal smoothly changes from the characteristic indicated by the previous phase data signal from the pre-processor 5 to the characteristic indicated by the last received phase data signal. The phase modulator 26 generates a clock output signal having edges arranged in response to each of the edge arrangement signals from the interpolation filter 22.

  FIG. 4 is a more detailed block diagram of the serial binary signal synthesizer 20 shown in FIGS. In FIG. 4, the phase data from pre-processor 5 (of FIGS. 1 and 2) is coupled to the data input of interpolator 220. The output end of the interpolator 220 is coupled to the input end of the bit expander 230. As will be described in detail below, the system clock signal from PLL 14 is coupled to the input of frequency divider 232 (shown in dotted lines for reasons described below). The output of frequency divider 232 is coupled to the data input of clock selector 234. The output of clock selector 234 is coupled to the clock input of interpolator 220. The strobe output end of the interpolator 220 is coupled to the strobe output end of the interpolation filter 22. A combination of the interpolator 220, the bit expander 230, the frequency divider 232, and the clock selector 234 forms the interpolation filter 22.

  The PLL 14 generates a multi-phase clock signal having a system clock frequency. In the illustrated embodiment, the multiphase clock signal includes a clock signal having a phase of φ0 to φ7. The first phase φ0 of the multiphase clock signal is selected as the system clock signal and supplied to the input terminal of the counter 262.

  The output of bit expander 230 is coupled to the first input of adder 268. Each of the first and second output ends of summer 268 is coupled to a corresponding first and second control input end of decode 272. The output of decode 272 is coupled to the data input of analog multiplexer (MUX) 274. The output of MUX 274 is coupled to the input of a low pass filter (LPF) 276. The output terminal of the low pass filter 276 is supplied to the data input terminal of the comparator 278. The output of comparator 278 is coupled to the output of synthesizer 20 to generate a clock output signal.

  A third output of adder 268 is coupled to the inputs of first digital-to-analog converter (DAC) 264 and second DAC 266. Each output of the first and second DACs 264 and 266 generates signals A 1 and A 2 and is coupled to a corresponding input of the decoder 272. All phases of the multiphase system clock signals φ0 to φ7 are coupled to the control input of the analog MUX 274. The combination of the counter 262, the first DAC 264, the second DAC 266, the adder 268, the decoder 272, the MUX 274, the LPF 276, and the comparator 278 form the phase modulator 26.

  The multiphase system clock signal from PLL 14 (FIGS. 1 and 2) is shown in FIG. In the illustrated embodiment, the multiphase system clock includes eight clock signals of the same frequency but eight phases that are equally spaced to simplify the invention. The polyphase system clock signal can be generated by a ring oscillator in a known manner. For multiphase system clock signals, it is possible to include more or less than eight phases. One phase of the multiphase system clock signal is selected to provide the system clock signal. In the illustrated embodiment, φ0 is used as a system clock.

  A frequency divider 232 in the interpolation filter 22 receives the system clock signal from the PLL 14, and each divisor of the system clock signal frequency (ie 1/2, 1/4, 1/8 of the system clock frequency). Etc.) to generate a plurality of clock signals. In the preferred embodiment, divider 232 generates nine such clock signals. The clock signal divided into nine parts and the system clock signal are supplied to the clock selector 234. The clock selector 234 selects one of these clock signals as a clock signal for the interpolator 220.

  The interpolation filter 22 is a low-pass filter that interpolates between relatively sparse received phase data signals, and generates an edge arrangement data signal nominally at a specific baud rate. With this arrangement, the phase data input rate can range from a relatively slow rate of 1.5 MHz to a high frequency such as 700 to 1400 MHz. In the illustrated embodiment, the interpolation filter 22 is arranged by a known method to interpolate the output edge arrangement data signal between the reception phase data signals.

  FIGS. 6, 7 and 8 are detailed block diagrams of the interpolator 220 used in the clock signal synthesizer 20 of FIG. 6, 7 and 8 show three block diagrams of the interpolator 220. FIG. In FIG. 6, the phase data from the pre-processor 5 is supplied to the input terminal of the latch 222. The output end of the latch 222 is coupled to the input end of the first boxcar filter 226. The output of the first boxcar filter 226 is coupled to the input of the second boxcar filter 228. The output of boxcar 228 is coupled to the input of funnel shifter 229. The output of funnel shifter 229 is coupled to the output of interpolator 220, which is coupled to phase modulator 26 (FIG. 4). The clock signal from the clock selector 234 (FIG. 4) indicating the baud rate as FBAUD is supplied to the clock input terminal of the second boxcar filter 228 and the input terminal of the fixed frequency divider 223. The output of fixed divider 223 is coupled to the clock input of first boxcar filter 226 and the input of second fixed divider 221. The output terminal of the second fixed frequency divider 221 is coupled to the clock input terminal of the latch 222 and the strobe output terminal of the interpolator 220.

  Boxcar filters are well known and exhibit flat impulse response characteristics over a period of time. One skilled in the art will appreciate that such a filter performs linear interpolation and amplification on the input signal. Two such boxcar filters operate in series and in the same period to perform a quadratic interpolation function and amplification. One skilled in the art will also appreciate that other interpolation techniques can be used successfully.

  In operation, the latch 222 receives phase data from the pre-processor 5 and latches the phase data in response to the strobe signal from the second fixed divider 221. The strobe signal is derived directly from the system clock signal by the divider 232 and the clock selector 234 (FIG. 4) and the first and second fixed dividers 223 and 221. Thus, the phase data is received in synchronization with the system clock, but without responding to the timing of an arbitrarily generated edge. The latched phase data is supplied to a series connection of first and second boxcar filters 226 and 228. The first and second boxcar filters perform quadratic interpolation and amplification on the phase data signal to generate a series of continuous edge placement signals at a predetermined baud rate. The continuous edge placement signal is supplied to the phase modulator 26 (FIG. 4).

The output of the second boxcar filter 228 is a multi-bit digital number with a predetermined number of bits. Funnel shifter 229 selects the multi-bit subset in a known manner and shifts the subset by an amount determined by clock coefficients M ₃ and M ₄ to attenuate the amplitude of the sample from the second boxcar filter. To work. The output from the funnel shifter 229 is supplied to the decompressor 230 (FIG. 4).

  One skilled in the art will appreciate that a boxcar filter can be decomposed into a series connection of an accumulator and a differentiator. One skilled in the art will also appreciate that the accumulator and differentiator operations are linear operations and can therefore be arranged in any order. Further, it can be understood that the cumulative operation is a relatively high-speed operation, and the differential operation is a relatively low-speed operation.

FIG. 7 shows the interpolator 220 of FIG. 6, wherein the first boxcar filter 226 can be decomposed into a series connected accumulator 252 and differentiator 254, and the second boxcar filter 228 is connected in series. It can be decomposed into an accumulator 256 and a differentiator 258. In block 228, differentiator 258 is shown operating on samples separated by M samples, and differentiator 254 is shown operating on samples separated by M ₄ sampling. However, since M = M ₃ · M ₄ and the supplied clock signal is divided by the coefficient M ₃ by the first fixed frequency divider 223, the period during which the differentiator operates is the period during which the differentiator 258 operates. The same.

  FIG. 8 shows another arrangement of interpolator 220. Here, the two differentiators 254 and 258 are directly coupled after the latch 222 to follow the two accumulators 252 and 256. In this case, the differentiator operates on adjacent samples (separated by one sample). However, since these differentiators are clocked by the strobe signal divided by M by the series connection of the first and second fixed frequency dividers 223 and 221, the differentiators operate over the same period. However, the circuit arrangement of FIG. 8 performs a relatively low speed differential operation different from the relatively high speed accumulation operation. Thus, the latch 222 and the two differentiators 254 and 258 can be placed outside the integrated circuit chip on which the system 10 is assembled. As described above, these elements are arranged in the pre-processor 5. A high speed accumulator is provided on the integrated circuit chip containing the system 10. By moving low speed elements out of the integrated circuit chip containing the system 10, these circuit elements and the surface area required within the integrated circuit chip can be reduced.

  Refer to FIG. 4 again. Bit expander 230 receives the output signal from funnel shifter 229 (FIGS. 6-8R> 8). The bit expander 230 expands (expands) the number of bits in the output signal from the funnel shifter 229 and executes a low-pass filtering operation. For example, in the illustrated embodiment, the bit expander 230 generates a 15 bit signal. In the preferred embodiment, more bits are required depending on the circuit configuration described in detail below. In the illustrated embodiment, the filtering operation is performed by a first order low pass filter, but in the illustrated embodiment, it comprises an infinite impulse response (IIR) filter. The bit expander 230 supplies the output signal to the phase modulator 26.

  The signal from the bit expander 230 can be viewed as a fixed point real number representing the desired time difference from the next edge of the unmodulated clock signal at a predetermined baud rate to the next edge of the synthesized clock output signal. That is, the signal from the bit expander 230 includes an integer part having a fixed bit width and a fractional part having a fixed bit width. This real number may be positive or negative. This integer part represents the number of complete periods of the system clock between the desired time of the next edge of the synthesized clock signal and the time of the next edge of the unmodulated clock signal, and the fractional part is the synthesized part Represents the portion of the system clock period between the desired time of the next edge of the clock signal and the time of the unmodulated clock signal.

In the illustrated embodiment, the system clock frequency is related to the square of the baud rate. That is, if the baud rate is F _BAUD , the system clock frequency is 2 ^m · F _BAUD . In this case, each cycle of the clock signal at a predetermined baud rate includes 2 ^m system clock cycles. The value of m can be selected by the system controller via the control interface 12. In response to a control signal from the system controller via the control interface 12, a counter 262 is formed to fit the selected value of m by configuring an m-bit counter. The m-bit counter 262 is responsive to one of a plurality of phases in the multiphase system clock, in the illustrated embodiment φ0. Thus, the output from m-bit counter 262 is an m-bit digital signal. This counter counts at the system clock rate and circulates at a given baud rate, but at the beginning of the cycle the count starts at 0, the middle count of the cycle is 2 ^m-1 , The end count is 2 ^m −1. The end of this cycle is just before resuming from zero.

  The countable size of the counter and the value of m are configured to provide a clock signal to the interpolator 220 at a desired baud rate from the system clock frequency. At the same time, the clock selector 234 selects the frequency division ratio based on the 2m output from the clock frequency divider 232. In this configuration, the clock signal from the clock selector 234 has a predetermined baud rate. This is usually the desired configuration, but other configurations may be selected.

  For example, if the system clock frequency supplied by the PLL 14 is 1228.8 MHz and the desired baud rate is 2.4 MHz, m is selected as 9. Counter 262 is configured as a 9-bit counter, counts the system clock rate, and circulates at a predetermined baud rate. In this cycle (cycle), the count is 0 at the beginning of the cycle, the count is 256 in the middle of the cycle, and the count before restarting at 0 at the end of the cycle is 511.

  The operation of the phase modulator 26 can be easily understood by referring to the waveform diagrams shown in FIGS. The top waveform in FIG. 9 shows the rising edge of the system clock. These edges are φ0 of the multiphase system clock signal, as described above. With this system clock signal, the counter 262 counts and cycles from 0 to 511 and back to 0. This is shown in the second waveform in FIG. 9 (counter 262) as the value of the multi-bit output end of the counter 262 corresponding to the leading edge (leading edge) of the system clock signal.

  The signal from the bit stretcher 230 of the interpolation filter 22 is between the next desired edge time in the clock output signal and the next edge time in the nominal clock signal at a predetermined baud rate, as described above. Represents the time difference and is shown as a fixed point real number with an integer part and a fractional part. This signal is combined with the output of counter 262 at adder 268. As described above, the integer portion of the fixed point real number represents an integer number of system clock cycles, and the output signal of counter 262 also represents an integer number of system clock cycles. Therefore, the signal from the counter 262 can be regarded as a fixed point having only an integer part and a decimal part having a zero value. In the preferred embodiment, the output of counter 262 is subtracted from the time difference signal from bit expander 230. Thus, the output of adder 268 is counted from 0 to 511, then counted through 256, and then back to 0 through 1. However, the counting direction does not affect the generation of edges. This is because 0 and 256 correspond to the same point in time, although the counts are different depending on whether they are forward or backward.

  The difference signal from the adder 268 can be regarded as a fixed-point real number having an integer part and a decimal part. This signal controls the position of the next edge of the clock output signal in the following manner. The integer part of this signal is named the coarse resolution signal and is supplied to the first control input C of the decoder 272. The most significant digit portion of the fractional portion is an intermediate resolution signal and is supplied to the second control input terminal M of the decoder 272. In the illustrated embodiment, the intermediate resolution signal is a 3-bit signal. However, in the preferred embodiment, the intermediate resolution signal may be greater than 3 bits. The next bit from the most significant bit in the fractional part is a fine resolution signal, which is supplied to the inputs of first and second digital-to-analog converters (DACs) 264 and 266. In the illustrated embodiment, the fine resolution signal F is also a 3-bit signal. However, in a preferred embodiment, the fine resolution signal may be greater than 3 bits.

  If the time difference signal from the bit expander 230 is positive, the output value of the adder 268 is larger than the output value of the counter 262. If the time difference signal is negative, the output value of the adder 268 is smaller than the output value of the counter 262. The third waveform in FIG. 9 shows the integer (coarse resolution C) output of the adder 268 when the integer part of the time difference signal is +1. When the output value of the counter 262 is subtracted from +1, the result is greater than the value of the counter 262. The fourth waveform in FIG. 9 shows the integer (coarse resolution C) output of the adder 264 when the integer part of the time difference signal is -1. When the output value of the counter is subtracted from −1, the result is smaller than the value of the counter 262.

  As will be described in detail later, the leading edge of the clock output signal occurs while the integer output of the adder 268 is zero. Also, the trailing edge of the clock output signal occurs during the period when the integer output of the adder 268 is 256. Along with the counter 262, an adder 268 enables the edge position and the phase of the clock output signal generated as shifted by an integer number of system clock cycles. However, in the following description, it is assumed that the integer part of the time difference signal is equal to 0 and the integer value from the adder 268 (coarse resolution C) is equal to the value from the counter 262.

  The next eight waveforms in FIG. 9 show the phases φ0 to φ7 of the multiphase system clock signal. The left part of these waveforms represents the signal of the system clock cycle when the integer output value C of adder 268 is equal to 0 while the leading edge of the clock output signal occurs. Further, the right part shows a signal when C is 256 (trailing edge of the clock output signal). As shown in FIG. 9, there are eight partial sections that are determined by the relative phase of each signal in the multiphase clock signal and are labeled W0 to W7 in a single clock cycle. A circuit that generates each binary signal representing each of the sections W0 to W7 or generates a digital count signal having a value indicating each of the sections W0 to W7 is designed and realized by a person skilled in the art in a known manner. it can.

  The decoder 272 operates to generate eight signals D0-D7 in a manner described in detail below. The table shown in FIG. 11 is useful for understanding the operation of the decoder 272. In the table of FIG. 11, the leftmost column (column) indicates the coarse resolution value C (integer value from the adder 268), and the second row (horizontal row) indicates the intermediate resolution value M (value from the adder 268). The most significant 3 bits of the decimal part). The rightmost column represents the signals D0 to D7 generated by the decoder 272. These signals D0 to D7 are multilevel analog signals. In the illustrated embodiment, these signals have nine possible levels. However, in the preferred embodiment, there are more than nine levels. The levels of these signals are determined by values ranging from 0 representing the minimum level to 8 representing the maximum level.

  The analog multiplexer (MUX) 274 cycles in the order of signals D0-D7 once in each system clock cycle in response to the multiphase system clock signal. During the phase interval W0, the MUX 274 supplies the D0 signal to the output terminal. During the phase interval W1, the MUX 274 supplies the D1 signal to the output terminal. The same applies hereinafter.

  The configuration of the signals D0 to D7 generated by the decoder 272 is determined by the values C and M from the adder 268. Specific values of the signals D0 to D7 generated by the decoder 272 are indicated by columns D0 to D7 in the table of FIG. As shown in the middle row of the table of FIG. 11, during the period in which the C value is greater than 0 but smaller than 256, the intermediate resolution signal M (in column M, “Don't care (may be optional)” All the values of these multilevel analog signals D0 to D7 are 8. During this period, the decoder 272 couples a level 8 analog signal source to all of the output terminals D0-D7. Therefore, the signal generated by MUX 274 during this period is a constant value of 8. As shown in the bottom row of the table of FIG. 11, during the period when the output of the adder 268 is greater than 256 but not rounded to zero, all of these multi-level analog signals D0-D7 have an intermediate resolution. The value is 0 regardless of the value of the signal M. During this period, the decoder 272 couples the level 0 analog signal source to all of the output terminals D0-D7. Therefore, during this period, the signal generated by the MUX 274 has a constant value of 0.

  The period when the C signal is 0 is shown in the upper half of the table of FIG. 11 and the left waveform of FIG. During this period, signals D0 to D7 are formed by the following method. If the intermediate resolution signal M is 0, the signal D0 can be assumed to be any 1 of analog levels 1-8 (shown in FIG. 9 by a number of horizontal lines for the signal D0). The specific analog level is derived from the signal A1 from the first DAC 264. The signal A1 is indicated by an entry “A1” in the column of the table of FIG. 11 representing the signal D0 in the row representing the 0 C signal and the 0 M signal. In the illustrated embodiment, during this period, decode 272 provides the output of DAC 264 to the D0 output terminal. Assume that signals D1-D7 are at analog level 8 while C is equal to 0 and M is equal to 0. Decoder 272 couples a level 8 analog signal source to the D1-D7 output terminals. As described above, when the MUX 274 scans the signals D0 to D7, the left end portion of the signal indicated by “0” in FIG. 9 is generated during the phase interval W0 in the method described in detail later, and the leading edge is generated. Arise.

  When the intermediate resolution signal is equal to 1, the D0 signal is set to an analog value of 0. As shown in FIG. 11, the signal D1 can be assumed to be analog levels 1-8 (signal A1 from the first DAC 264), and the remaining signals D2-D7 are assumed to be analog value 8. As described above, when the MUX 274 scans the signals D0 to D7, the left end portion of the signal labeled “1” in FIG. 9 is generated, and a leading edge is generated during the phase interval W1. Similarly, when the level of the M signal is 2-7, each of the signals D2-D7 has a variable analog value from the signal A1 from the first DAC 264. The value of the previous Dx signal is the analog value 0, and the analog value of the subsequent Dx signal is 8. As described above, when the MUX 274 scans the signals D0 to D7, the left portion of the signal shown in FIG. 9 and labeled 2 to 7 is generated, and a leading edge is generated during each of the phase intervals W2 to W7.

  The interval where the C signal is equal to 256 is shown in the lower half of the eight rows in the table of FIG. 11 and the waveform on the left side of FIG. During this period, signals D0 to D7 are formed by the following method. If the intermediate resolution signal M is 0, the signal D0 is assumed to be any one of analog levels 0-7 (indicated by a number of horizontal lines for the signal D0 in FIG. 9). The specific analog level is derived from the signal A2 from the second DAC 266 indicated by the entry “A2” in the column of the table of FIG. This “A2” indicates a signal D0 in a row representing 256 C signals and 0 M signals. In a specific embodiment, the decoder 272 provides the output from the second DAC 266 to the D0 output terminal during this period. For C equal to 256 and M equal to 0, signals D1-D7 are assumed to be at analog level 0. Decoder 272 couples a level 0 analog signal source to the D1-D7 output terminals. As described above, when the MUX 274 scans the signals D0 to D7, the right portion of the signal labeled “0” in FIG. 9 is generated, and the trailing period during the phase interval W0 is generated in a manner described in detail later. Edges are generated.

  When the intermediate resolution signal is equal to 1, the D0 signal is set to an analog value of 8. As shown in FIG. 11, signal D1 can be assumed to be at analog levels 0-7 (signal A2 from second DAC 266), and the remaining signals D2-D7 are assumed to have an analog value of zero. As described above, when the MUX 274 scans the signals D0 to D7, the right portion of the signal labeled “1” in FIG. 9 is generated, and a trailing edge is generated in the phase interval W1. Similarly, when the value of the M signal is 2 to 7, the signals D2 to D7 respectively have variable analog values 0 to 7 from the signal A2 of the second DAC 266. The value of the previous Dx signal is the analog value 8, and the analog value of the subsequent Dx signal is 0. As described above, when the MUX 274 scans the signals D0 to D7, as shown in FIG. 9, the right part of the signal labeled 2 to 7 is generated, and the trailing edge is generated during the phase interval W2 to W7. Each occurs.

  As described above, for each system clock cycle in response to the multiphase system clock signal, analog MUX 274 supplies signals D0-D7 from decoder 272 to output terminal D in that order. Therefore, the generated signal D is subjected to low-pass filtering by a method described later, and is compared with a threshold value to generate a clock output signal.

  The fine resolution signal F from the adder 268 arranges an edge at a specific time point in a specific phase section W0 to W7 by a method described later. The fine resolution signal F is supplied to the first and second DACs (DAC1 and DAC2) 264 and 266 as described above. The table of FIG. 12 represents each output level of the analog signals A1 and A2 generated by the first and second DACs 264 and 266 corresponding to each value of the fine resolution signal F. That is, for the fine resolution signal F having the value 0, the first DAC (DAC1) 264 generates the level 8 analog signal A1, and the second DAC (DAC2) 266 simultaneously generates the level 0 analog signal A2. . For a fine resolution signal F with a value of 1, the first DAC generates a level 7 analog signal A1, the second DAC generates a level 1 analog signal A2, and so on.

  FIG. 10 shows two possible waveforms for the selected signal D from MUX 274. The uppermost waveform D in FIG. 10 shows a selected waveform in which the value of the fine resolution signal F from the adder 268 is 6. As shown in the table of FIG. 12, the value of the A1 signal is 2 and the value of the A2 signal is 6. In the illustrated waveform D, the time points of the A1 signal and the A2 signal are represented by a series of thin horizontal lines as shown in FIG. The actually selected A1 and A2 signals in D are indicated by thick lines. Since this signal D is low-pass filtered by the LPF 276, the resulting waveform is shown by the second waveform in FIG. 1010.

  Compared to the maximum level (8) at which the filtered signal rises, the A1 level (2) is relatively low, so the filtered waveform rises at a relatively slow rate. Therefore, the filtered waveform passes through and rises a threshold value Th (in the illustrated embodiment, set between the maximum value and the minimum value) relatively late in the A1 period. Similarly, since the A2 level (6) is relatively high compared to the minimum level (0) at which the filtered waveform falls, the filtered waveform falls at a relatively slow rate. Therefore, the filtered waveform passes through the threshold value Th relatively slowly in the A2 period.

  The filtered waveform is compared with a threshold value Th by a comparator 278. When the value of the filtered waveform is below the threshold Th, the output of the comparator 278 is low. Also, when the value of the filtered waveform is higher than the threshold value, the output of the comparator 278 is high. The output of the comparator 278 is as shown in the third waveform of FIG. 10, which is a clock output signal.

  A fourth waveform D in FIG. 10 shows a selected waveform when the value of the fine resolution signal from the interpolation filter 22 is 2. Therefore, as shown in the table of FIG. 12, the value of the A1 signal is 6, and the value of the A2 signal is 2. The selected signal D is indicated by a thick line. When this signal D is low-pass filtered by the LPF 268, the resulting waveform is the fifth waveform in FIG.

  Since the A1 level (6) is relatively high compared to the maximum level (8) at which the filtered signal rises, the filtered waveform rises relatively quickly. Therefore, the filtered waveform passes through the threshold Th relatively quickly in the A1 period and rises. Similarly, since the A2 level (2) is relatively low compared to the minimum level (0) at which the filtered waveform falls, the filtered waveform falls relatively quickly. Therefore, the filtered waveform passes through the threshold Th relatively quickly in the A2 period and falls.

  The filtered waveform is compared with a threshold value Th by a comparator 278. The output of the comparator 278 is shown by the sixth waveform in FIG. 10, which is a clock output signal. As can be seen from FIGS. 9 and 10R> 0, the position of each edge can be arranged with a resolution of 1/64 of the system clock period in response to the fine resolution and coarse resolution signals from the interpolation filter 22. The phase data signal from the pre-processor 5 is received at a rate slower than a predetermined baud rate and is received synchronously at a fixed frequency instead of a rate that depends on the edge generated by the clock output signal.

  Those skilled in the art will appreciate that the least significant bit signal at the output of counter 262 represents the clock signal divided by two from the system clock signal at the input of counter 262. Each of the other bit outputs represents a clock signal divided by 2 from the next lower bit. Thus, the counter 262 can be considered as a multi-bit divider as represented by the divider 232 of the interpolation filter 22. For this reason, the single counter 262 is coupled to both the adder 268 in the phase modulator 26 and the clock selector 234 in the interpolation filter 22 at the output terminals in the illustrated embodiment. (The clock selector 234 also receives the undivided system clock signal from the PLL 14.) Since the interpolation filter 22 shares the counter 262 and the clock divider 232 in the phase modulator 26, the interpolation filter In FIG. 22, it is indicated by a dotted line.

  Next, reference is made to the digital phase analyzer shown in FIG. FIG. 13 is a block diagram of a clock signal analyzer used in the system 10 shown in FIGS. In FIG. 13, the input terminal IN is coupled to a signal source of a serial binary input signal. This input terminal IN is coupled to the input end of the phase demodulator 32. The output end of the phase demodulator 32 is coupled to the input end of the anti-aliasing filter 36. The output of anti-aliasing filter 36 is coupled to the input of decimator 39. The data output terminal of the decimator 39 generates data indicating the phase characteristics of the serial binary input signal at the input terminal IN and is coupled to the output terminal “phase data”. The strobe output end of decimator 39 is coupled to the strobe output terminal.

  The serial binary input signal at input terminal IN has an edge that occurs at a time corresponding to a nominal baud rate. This serial binary input signal is a phase modulation signal in which the edge position varies with the phase. Alternatively, this signal is a data carrier signal with or without an edge and represents the value of the data carried by this data carrier signal. In the case of a data carrier signal, the edge occurs at approximately a predetermined baud rate.

  The phase demodulator 32 generates edge position data that specifies the position of each edge in the serial binary input signal. Edge position data is generated when each edge is detected. This edge position data corresponds to the edge arrangement data described above with reference to the clock synthesizer 20. The decimator 39 generates one sample indicating the phase characteristic of the serial binary input signal for every predetermined number of edge position samples in synchronization with the system clock and asynchronously with the generation of the edge. The anti-aliasing filter 36 prevents aliasing in the decimation process in a known manner.

  Still referring to FIG. The phase modulator 26, configured as shown in FIG. 4 and operating as described above, optionally has an input coupled to the output of the demodulator 32. The output of phase modulator 26 is coupled to an output terminal that generates a received clock output signal. As described above, as shown in FIG. 4, the phase modulator receives the edge arrangement data and generates a clock output signal in response to the edge arrangement data. The phase demodulator 32 generates edge position data related to the received serial binary input signal from the input terminal IN. This edge position data corresponds to the edge arrangement data received from the interpolation filter 22 of FIG. In response to this data, the phase modulator 26 can generate a recovered clock output signal having a phase corresponding to the received edge arrangement data and having a phase corresponding to the received serial binary input signal at the input terminal IN. .

  FIG. 14 shows a detailed block diagram of the phase analyzer 30 shown in FIG. 1, FIG. 2 and FIG. In FIG. 14, the input terminal IN is coupled to a signal source of a serial binary input signal. This input terminal IN is also coupled to the input terminal of delay circuit 322. The output terminal of delay circuit 322 is coupled to the data input terminal of latch array (array) 324. The output end of latch array 324 is coupled to the input end of binary encoder 326. The data output of binary encoder 326 is coupled to the first input of register 328. The output of register 328 is coupled to anti-aliasing filter 36 and phase modulator 26.

  A system clock signal that is φ0 of the multiphase system clock signal is supplied to the input terminal of the counter 330. The output of counter 330 is coupled to the second input of register 328. The combination of delay circuit 322, latch array 324, binary encoder 326, counter 330 and register 328 form phase demodulator 32.

  The output of register 328 is coupled to the input of bit expander 362. The output of this bit expander is coupled to the data input of the first boxcar filter 364. The output of the first boxcar filter 364 is coupled to the data input of the second boxcar filter 366. The output of the second boxcar filter is coupled to the data input of the third boxcar filter 368. The output of third boxcar filter 368 is coupled to the input of barrel shifter 370. The output end of barrel shifter 370 is coupled to the input end of latch 392. The latch 392 generates phase expression data (phase data) indicating the phase characteristics of the serial binary input signal, and is coupled to the output terminal “phase data”.

  The system clock signal from the PLL 14 is also supplied to the input terminal of the frequency divider 372. The output terminal of frequency divider 372 is coupled to the input terminal of clock selector 374. The output of the clock selector 374 is coupled to the input of the first fixed divider 376 and the clock inputs of the first and second boxcar filters 364 and 366. The output of the first fixed divider 376 is coupled to the input of the second fixed divider 394 and the clock input of the third boxcar filter 368. The output terminal of the second fixed frequency divider 394 is coupled to the clock input terminal of the latch 392. Bit expander 362, first, second and third boxcar filters 364, 366 and 368, barrel shifter 370, clock divider 372, clock selector 374, first fixed divider The combination with the device 376 constitutes the anti-aliasing filter 36. The combination of the latch 392 and the second fixed frequency divider 394 constitutes the decimator 39.

  In operation, the combination of delay circuit 322, latch array 324, and binary encoder 326 operates to detect an edge in the serial binary input signal at input terminal IN in a manner that will be described in detail below. When an edge is detected, the binary encoder generates a signal at its clock output. In response to this signal, the register 328 latches data at the data output terminals of the counter 330 and the binary encoder 326. The counter 330 counts system clock cycles. Thus, the count value latched in register 328 represents an integer number of system clock cycles from the previously detected edge. This gives a rough indication of the edge position.

  FIG. 15 is a detailed block diagram of the delay circuit 322 and latch array circuit 324 as shown in FIG. In FIG. 15, the latch array 324 is composed of an array of 8 rows of latches, each row containing 8 latches. Each latch is a D flip-flop, and each D flip-flop has a D input terminal, a clock input terminal, and a Q output terminal (symbol Q is shown only for the latch L0 at the upper left of the latch array 324). A total of 64 flip-flops form an 8 × 8 array.

  The φ1 clock signal is supplied in common to the clock input terminals of the eight D flip-flops in the first (leftmost) column. These latches are labeled L0 to L7 from the top row to the bottom row. The output ends of these latches are coupled to output terminals Q0-Q7 of latch array 324, respectively. The φ2 clock signal is supplied in common to the clock input terminals of the eight D flip-flops in the second column. These latches are labeled L8 to L15 from the top row to the bottom row. The output terminals of these latches are respectively coupled to output terminals Q8 to Q15 (omitted for simplicity of illustration). The φ3 clock signal is supplied in common to the clock input terminals of the eight D flip-flops in the third column. These latches are labeled L16 to L23 from the top row to the bottom row. The output terminals of these latches are respectively coupled to the output terminals Q16 to Q23 (omitted for simplicity of illustration). The φ4 clock signal is supplied in common to the clock input terminals of the eight D flip-flops in the fourth column. These latches are labeled L24 to L31 from the top row to the bottom row. The output terminals of these latches are respectively coupled to the output terminals Q24 to Q31 (omitted for simplicity of illustration).

  The φ5 clock signal is supplied in common to the clock input terminals of the eight D flip-flops in the fifth column. These latches are labeled L32 to L39 from the top row to the bottom row. The output terminals of these latches are respectively coupled to output terminals Q32 to Q39 (omitted for simplicity of illustration). The φ6 clock signal is supplied in common to the clock input terminals of the eight D flip-flops in the sixth column. These latches are labeled L40 to L47 from the top row to the bottom row. The output ends of these latches are respectively coupled to output terminals Q40 to Q47 (omitted for simplicity of illustration). The φ7 clock signal is supplied in common to the clock input terminals of the eight D flip-flops in the seventh column. These latches are labeled L48 to L55 from the top row to the bottom row. The output terminals of these latches are respectively coupled to output terminals Q48 to Q55 (omitted for simplicity of illustration). The φ8 clock signal is commonly supplied to the clock input terminals of the eight D flip-flops in the eighth column (right end column). These latches are labeled L56 to L63 from the top row to the bottom row. The output ends of these latches are coupled to output terminals Q56 to Q63, respectively (only Q62 and Q63 are shown for simplicity of illustration).

  The input terminal IN includes a first delay circuit 322 (1), a second delay circuit 322 (2), a third delay circuit 322 (3), a fourth delay circuit 322 (4), a fifth delay circuit 322 (5), The sixth delay circuit 322 (6) and the seventh delay circuit 322 (7) are coupled to the serially connected input terminals. First delay circuit 322 (1), second delay circuit 322 (2), third delay circuit 322 (3), fourth delay circuit 322 (4), fifth delay circuit 322 (5), sixth delay circuit 322 The combination of (6) and the seventh delay circuit 322 (7) constitutes the delay circuit 322.

  The C0 input signal to the latch array 324 is produced at the output of the seventh delay circuit 322 (7), and the first (top) row of latches (L0, L8, L16, L24, L32, L40, L48 and L56). Are commonly supplied to the input terminal D. The C1 input signal to the latch array 324 is generated at the output end of the sixth delay circuit 322 (6), and the input ends of the second rows (L1, L9, L17, L25, L33, L41, L49 and L57) of the latches. D is commonly supplied. The C2 input signal to the latch array 324 is produced at the output of the fifth delay circuit 322 (5), and the input of the third row of latches (L2, L10, L18, L26, L34, L42, L50 and L58). D is commonly supplied. The C3 input signal to the latch array 324 is generated at the output terminal of the fourth delay circuit 322 (4), and the input terminals of the fourth row (L3, L11, L19, L27, L35, L43, L51 and L59) of the latch are generated. D is commonly supplied. The C4 input signal to the latch array 324 is generated at the output terminal of the third delay circuit 322 (3), and the input terminals of the fifth row (L4, L12, L20, L28, L36, L44, L52 and L60) of the latch are generated. D is commonly supplied. The C5 input signal to the latch array 324 is generated at the output terminal of the second delay circuit 322 (2), and the input terminals of the sixth row (L5, L13, L21, L29, L37, L45, L53, and L61) of the latch are generated. D is commonly supplied. The C6 input signal to the latch array 324 is generated at the output terminal of the first delay circuit 322 (1), and the input terminals of the seventh row (L6, L14, L22, L30, L38, L46, L54 and L62) of the latch are generated. D is commonly supplied. A C7 input signal to the latch array 324 is generated at the input terminal IN and is supplied in common to the input terminals D of the eighth row (L7, L15, L23, L31, L39, L47, L55, and L63) of the latch.

  The operation of the demodulator 32 of FIG. 14 and in particular the delay circuit 322 and latch array 324 of FIG. 15 can be better understood with reference to the waveform diagram of FIG. In FIG. 16, the uppermost waveform is a part of the serial binary input signal (IN) which is a rising edge. The second waveform shows the leading edge of the system clock signal, and as described above, this leading edge is the phase φ0 of the multiphase system clock signal. Counter 330 (FIG. 14) increments the count at each rising edge of the system clock signal. In the waveform shown, the rising edge of the serial binary input signal occurs after the counter 330 reaches the value 83 and before incrementing to 84. As described above, the combination of delay circuit 322, latch array 324, and binary encoder 326 detects an edge and causes register 328 to latch the value of counter 330 in response to the detection of the edge. In the waveform shown, register 328 latches the value 83.

  The next eight waveforms show the polyphase system clock signal. These signals define eight phase intervals W0 to W7, as will be described later in detail. The next waveform is the higher resolution serial binary input signal (IN) and also the signal C7 supplied to the latch array 324. The rising edge occurs at approximately three quarters of the phase interval W5.

  In operation, each of the delay circuits 322 (X) provides a fixed delay of 1/64 of the system clock signal. The serial binary input signal passes through a series connection of delay circuits 322 (1) -322 (7) to form delayed signals C0-C7. Latches L0-L7 receive signals C0-C7, respectively, and are clocked by the phase φ1 signal. Therefore, the latches L0 to L7 latch the eight delayed signals C0 to C7 at the rising edge of the phase φ1 signal, and generate the signals latched at the output terminals Q0 to Q7, respectively. In the waveform shown, these signals are all logic zero signals. The latches L8 to L15 are clocked by the phase φ2 signal, latch the eight delay signals C0 to C7 at the rising edge of the φ2 signal, and receive the signals latched at the output terminals Q8 to Q15 (not shown). Each occurs. The same applies hereinafter. In particular, the latches L40 to L47 latch eight delay signals C0 to C7 generated at the rising edge of the phase φ6 signal, and generate the signals latched at the output terminals Q40 to Q47, respectively. The values of these samples will be described later. Latches L56 to L63 latch the eight delay signals C0 to C7 at the rising edge of the phase φ0 signal, and generate the signals latched at the output terminals Q56 to Q63, respectively. These signals are all logic one.

  In FIG. 16, the C7 signal is indicated by a thick line. Each of the C6-C0 signals is delayed by 1/64 of the system clock period with respect to the previous signal, and is indicated by a thin line in FIG. At the rising edge of the phase φ6 signal, the rising edge of the serial binary input signal, which is the C7 signal, has already occurred. Thus, the C7 signal is a logic 1 signal. The latch L47 that receives the C7 signal latches the logic 1 signal and generates a Q47 output signal that is a logic 1 signal. Similarly, rising edges of the C6 and C5 signals also occur at the rising edge of the phase φ6 signal. Therefore, the latches L46 and L45 that receive the C6 and C5 delay signals latch the logic 1 signal and generate Q46 and Q45 output signals, which are logic 1 signals, respectively.

  Conversely, the C4 delay signal at the rising edge of phase φ6, that is, the rising edge of the C4 delay signal does not yet occur. Thus, the latch L44 that receives the C4 delay signal latches the logic 0 signal and generates a Q44 output signal that is a logic 0 signal. Similarly, the rising edges of the C3 and C0 signals have not yet occurred at the rising edge of the phase φ6 signal. Therefore, the latches L43 to L40 that receive the C3 to C0 delay signals latch the logic 0 signal and generate Q43 to Q40 output signals that are logic 0 signals, respectively.

  A binary encoder 326 processes the Q0-Q63 signals to detect edges. All the logical values of the Q0 to Q63 signals are the same (that is, all are logic 1 signals or all are logic 0 signals). This is the case when the system clock period is before or after the system clock period where the count of the counter 33 is 83. In FIG. 16, the upper three waveforms are referred to. For the preceding system clock interval, the Q0-Q63 signals are all logic 0 signals. Further, for the subsequent system clock period, the Q0 to Q63 signals are all logic 1 signals. In this case, no clock signal is generated at the clock output terminal of the binary encoder 326.

  However, if two adjacent Q signals have different logic values, the binary encoder 326 detects an edge. In the waveform shown in FIG. 16, during the system clock period in which the counter has the value 83, the signal Q44 is a logic 0 value and the signal Q45 is a logic 1 value. This indicates the leading edge. In a similar manner, if signal Qn is a logic 1 value and signal Qn + 1 is a logic 0 value, a trailing edge is detected. In either case, a multi-bit binary signal that is the value of the number of Q signals immediately before the change of the logical value is supplied to the register 328 by the binary encoder 326, and the clock signal is supplied to the register 328.

  In the illustrated embodiment, a 6-bit binary signal with a value of 44 is provided to register 328. Register 328 is responsive to the clock signal from binary encoder 326 to indicate the value of counter 330 (representing the number of complete clock cycles since the last detected edge) and the value from encoder 326 (current system Represents the decimal position of the edge in the clock cycle). In the illustrated embodiment, the output from register 328 is a 15-bit digital signal. In the preferred embodiment, register 328 operates in a synchronous fashion to receive the system clock at the clock input terminal and the clock output signal from binary encoder 326 at the latch enable input terminal.

It will be appreciated by those skilled in the art that the edge detection function in binary encoder 326 is obtained by calculating the exclusive OR of Q _n and Q _{n + 1} (Q _n EOR Q _{n + 1} ) for all n. Can understand. If (Q _n EOR Q _{n + 1} ) = 0 for all n (ie if all signals have the same logic value), no edge is detected and a clock signal is generated in register 328 do not do. For any n, if (Q _n EOR Q _{n + 1} ) = 1 (ie Q _n is different from Q _{n + 1} ), binary encoder 326 generates a value of n at the data output terminal. Generate a clock signal for register 328.

  In the illustrated embodiment, eight delay signals are provided to each of the eight rows of latches, and the eight columns of latches receive each of the eight phase signals from the multiphase system clock to provide a system clock. Provides a detection resolution of 1 / 64th of the period. Those skilled in the art will appreciate that other configurations are possible. For example, sixteen delay circuits with a delay of 1/128 of the system clock period can be coupled to each of the sixteen rows of latches, and the eight columns of latches have eight positions from the multiphase system clock. Upon receiving the phase signal, a detection resolution of 1/128 of the system clock period can be achieved. Alternatively, eight delay circuits with a delay of 1/128 of the system clock period can be coupled to each of the eight rows of latches, and the sixteen columns of latches are each of the sixteen phase signals of the multiphase system clock. In response, a detection resolution of 1/128 of the system clock period can be achieved. Alternatively, 16 delay circuits that delay 1/256 of the system clock are coupled to each of the 16 rows of latches, and the 16 columns of latches are each of the 16 phase signals from the multiphase system clock. And a detection resolution of 1/256 of the system clock period can be achieved.

  The edge position data from register 328 that occurs during each detected edge is also available to other circuit elements. For example, in the illustrated embodiment, edge position data is supplied to a phase modulator 26, which generates a regenerated serial binary signal based on that data. Similarly, other functions can be performed in response to this data.

  Edge position data from register 328 is also supplied to anti-aliasing filter 36. As described above, for interpolation filter 22 (FIG. 4), the combination of divider 372 and clock selector 374 is anti-aliasing at either the system clock frequency or a divisor of this system clock frequency. Operates to select the clock frequency for the filter 36. Further, as described above, the counter 330 that receives the system clock provides the clock frequency dividing function of the frequency divider 372.

The selected clock signal from the clock selector 374 becomes the clock signal for the first and second boxcar filters. This signal is divided by the count M ₃ in the first fixed divider 376 and further divided by the count M ₄ in the second fixed divider 394. The output clock signal from the first fixed divider 376 becomes the clock signal for the third boxcar filter 368, and the output clock signal from the second fixed divider 394 becomes the clock signal for the latch 392.

The anti-aliasing filter 36 comprises a series connection of a first order low pass filter and bit stretcher 362 and three boxcar filters 364, 366 and 368, each of which has a predetermined time window. Average the input samples over. Bit expander 362 is implemented as a primary LPF. In the illustrated embodiment, this is implemented as an IIR filter in a known manner. Further, the bit expander 362 expands the number of bits of the output signal from 15 bits usable by the register 328 to 23 bits. The series connection of the first and second boxcar filters 364 and 366 operates to average the M samples at the selected filter clock from the clock selector 374. Third boxcar filter 368, at a fixed factor M ₃ divided down selected filter clock frequency operates to average the M samples. The output signal from the third boxcar filter 368 is a low pass filtered version of the series of edge position data signals from register 328. This filtering operation prevents aliasing artifacts that occur during the decimation process in a known manner. As described above, the barrel shifter 370 shifts the filtered phase data signal to account for gain changes induced by the low pass filtered boxcar filter. The latch 392 latches one output phase data signal from all the M edge position data from the register 328. Note that M = M ₃ · M ₄ . These output phase data samples are supplied to the post processor 25 (FIGS. 1 and 2), and the clock signal to the latch 392 operates as a strobe signal for the post processor 25.

  As described above, for some of the signal processing described above, the clock output signal synthesizer can be shared with the processor 5, and the serial binary signal analyzer can be shared with the post processor 25. is there. 17 to 20 are detailed block diagrams of the anti-aliasing filter 36 shown in FIG. 14, and the technique shown in FIGS. 17 to 20 can be similarly applied to the interpolation filter shown in FIG.

17 to 20 are four block diagrams of the configuration of the anti-aliasing filter 36 of FIG. FIG. 17 is a simplified block diagram of the anti-aliasing filter 36 shown in FIG. In FIG. 17, a series connection of first, second and third boxcar filters 364, 366 and 368 is coupled between a signal source for edge position data signals and a latch 392. The first and second boxcar filters 364 and 366 are clocked by a clock signal at a baud rate F _BAUD . The third boxcar filter 368 is clocked by the clock signal at F _BAUD / M ₃ . The latch 392 is clocked by the clock signal at F _BAUD / M. Note that M = M ₃ · M ₄ , and this clock signal is a strobe signal.

  As is well known, the averaging function can be considered as a combination of a relatively high speed accumulating function and a relatively low speed differential function. FIG. 18 shows each of the first, second and third boxcar filters 364, 366 and 368 that can be decomposed into a series circuit of accumulators and differentiators in a known manner. The first boxcar filter 364 includes a series connection with the accumulator 42 and the differentiator 44, and the second boxcar filter 366 includes a series connection with the accumulator 62 and the differentiator 64, and the third Boxcar filter 368 includes a series connection with accumulator 82 and differentiator 84. Since the accumulation and differentiation processes are linear processes, the accumulators 42, 62, and 82 and the differentiators 44, 64, and 84 can be connected in series in an arbitrary order.

FIG. 19 shows a different configuration in which three accumulators 42, 62, and 82 are connected in front of three differentiators 44 ′, 64 ′, and 84 ′. In FIG. 19, the first and second accumulators 42 and 62 are clocked by a clock signal at a baud rate F _BAUD , and the third accumulator 82 is clocked by a clock signal at a rate of F _BAUD / M _3. . These three differentiators 44 ', 64', 84 'are all clocked by the clock signal at a rate of F _BAUD / M ₃ .

20 shows another configuration in which a latch 392 is arranged with a series connection of three accumulators 42, 62 and 82 and a series connection of three differentiators 44 ″, 64 ″ and 84 ″. The latch 392 and the three differentiators 44 ", 64" and 84 "are all clocked by the clock signal at a rate of F _BAUD / M. This configuration groups the differentiating circuits 44 ", 64" and 84 "at the end of the signal processing chain. In this illustrated embodiment, the three accumulators 42, 62 and 82 and the latch 392 are The differentiators 44 ", 64" and 84 "are formed on the post processor 25 of FIG. 14 outside this chip.

  Similarly, the boxcar filters 224 and 226 in the interpolation filter 22 shown in FIG. 4 can be decomposed into an accumulator and a differentiator, and the differentiators are arranged outside the integrated circuit chip of the pre-processor 5. it can. The process rearrangement disclosed herein does not change the functions described above, but moves to a relatively slow process outside the chip, reducing the circuitry that needs to be created on the integrated circuit chip. This reduces the cost of such a chip and any device that uses such a chip.

  Comparing the interpolation filter 22 of FIG. 4 with the anti-aliasing filter 36 of FIG. 14, it can be seen that the same elements are shared by both of these filters. For example, a series circuit of a PLL 14, a clock divider (232 and 372), a clock selector (234 and 374), a first fixed divider (236 and 376), and a second fixed divider (238 and 394) is provided. Used for both the interpolation filter 22 and the anti-aliasing filter 36. The remaining elements, the first boxcar filter (224 and 364), the second boxcar filter (226 and 366) and the third boxcar filter (230 and 362), barrel filters (228 and 370), and latches (222 and 393) can be electrically reconfigured by switching the clock input and data to the appropriate output terminals of the corresponding other elements. . Similarly, the input terminal of phase modulator 26 is electrically switched to the output of interpolator 22 when the system operates as a clock signal synthesizer, and phase demodulator 32 when the system operates as a clock signal analyzer. It may be electrically switched to the output terminal. 1 and 2, the operation mode can be controlled by a control signal supplied from the system controller (not shown) to the system 10 via the control interface 12. The control interface 12 provides appropriate control signals to the switching elements to combine the illustrated elements in a desired manner.

  The serial binary signal synthesizer described above receives phase representation data synchronized with the fixed frequency system clock, and the serial binary signal analyzer generates phase representation data in synchronization with the fixed frequency system clock. Such a system that operates synchronously is easy to use as part of a measuring instrument. Furthermore, the digital filtering required in such systems, i.e., interpolation and anti-aliasing filters, is easy to design and implement. Furthermore, it will be appreciated that a serial binary signal analyzer can operate on a data signal, regardless of the presence or absence of an edge, without the need for a separate clock recovery circuit.

FIG. 2 is a block diagram of a phase measurement / generator system for serial binary signals. FIG. 2 is a block diagram of a phase measurement / generator system for serial binary signals. FIG. 3 is a block diagram of a clock signal synthesizer used in the system shown in FIGS. 1 and 2. FIG. 4 is a more detailed block diagram of the clock signal synthesizer shown in FIG. 3. FIG. 5 is a waveform diagram useful for understanding the operation of the phase measurement / generator system according to the present invention. FIG. 5 is a more detailed block diagram of an interpolator used in the clock signal synthesizer of FIG. 4. FIG. 5 is a more detailed block diagram of an interpolator used in the clock signal synthesizer of FIG. 4. FIG. 5 is a more detailed block diagram of an interpolator used in the clock signal synthesizer of FIG. 4. FIG. 5 is a waveform diagram useful for understanding the operation of the phase modulator in the clock signal synthesizer shown in FIGS. 3 and 4. FIG. 5 is a waveform diagram useful for understanding the operation of the phase modulator in the clock signal synthesizer shown in FIGS. 3 and 4. FIG. 5 is a diagram useful for understanding the operation of the phase modulator in the clock signal synthesizer shown in FIGS. 3 and 4. FIG. 5 is a diagram useful for understanding the operation of the phase modulator in the clock signal synthesizer shown in FIGS. 3 and 4. FIG. 3 is a block diagram of a serial binary input signal analyzer used in the system shown in FIGS. 1 and 2. FIG. 14 is a more detailed block diagram of the serial binary input signal analyzer shown in FIG. 13. FIG. 15 is a more detailed block diagram of the delay and latch array circuit shown in FIG. FIG. 16 is a waveform diagram useful for understanding the operation of the serial binary input signal analyzer shown in FIGS. 14 and 15. FIG. 15 is a more detailed block diagram of a filter used in the serial binary input signal analyzer shown in FIG. 14. FIG. 15 is a more detailed block diagram of a filter used in the serial binary input signal analyzer shown in FIG. 14. FIG. 15 is a more detailed block diagram of a filter used in the serial binary input signal analyzer shown in FIG. 14. FIG. 15 is a more detailed block diagram of a filter used in the serial binary input signal analyzer shown in FIG. 14.

Explanation of symbols

5 Pre-processor 10 Phase measurement / generator system 12 Control interface 14 PLL
15 Loop Filter 20 Synthesizer 22 Interpolation Filter 25 Post Processor 26 Modulator 222 Latch 226, 228 Boxcar Filter 229 Shifter 230 Bit Expander 234 Clock Selector 262 Counter 272 Decoder 278 Comparator

Claims (1)

A phase demodulator that receives a serial binary input signal and continuously generates an edge position data signal representing a transition position of the serial binary input signal;
A decimator coupled to the phase demodulator via an anti-aliasing filter and generating phase data from the edge position data signal in synchronization with a system clock signal and asynchronously with the generation of the edge;
A serial binary input signal analyzer wherein the anti-aliasing filter prevents aliasing in the decimator process.

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