CN1297071C

CN1297071C - Digital phase analyzer and synthesizer

Info

Publication number: CN1297071C
Application number: CN 200410030425
Authority: CN
Inventors: D·H·沃拉维尔; D·G·克尼里姆
Original assignee: Tektronix Inc
Current assignee: Tektronix Inc
Priority date: 2000-03-25
Filing date: 2000-03-25
Publication date: 2007-01-24
Anticipated expiration: 2020-03-25
Also published as: CN1533033A

Abstract

The present invention relates to a digital phase position synthesizer which comprises a continuous phase position data signal source, an interpolator for responding each continuous phase position data signal and generating continuous edge configuration data signals, and a phase modulator for generating output clock signals put at the edge of time determined by the continuous edge configuration data signals. Similarly, a digital phase analyzer comprises an edged serial binary input signal source, a phase demodulator for generating continuous data signals to represent each edge position of serial binary input signals, and an extractor for generating phase position data signals at a ratio lower than the edge of the serial binary input signal.

Description

Digital phase analyzer and synthesizer

The application is that application number is 00117954.3, the applying date is on March 25th, 2000, denomination of invention is divided an application for the patent application of " digital phase analyzer and synthesizer ".

Technical field

The present invention relates to a kind of digital control clock signal synthesizer and serial binary signal analyzer.

Background technology

Digital control clock signal synthesizer is well-known.The system that is called as AWG (Arbitrary Waveform Generator) comprises one group of digital controlled signal source that is illustrated in the clock signal value of current time.System clock control provides the ratio of digital controlled signal, and system clock has the frequency higher than synthetic clock signal usually.These digital controlled signals are provided for digital to analog converter (DAC).The analog signal of DAC output is low pass filtering and carries out threshold test.The signal of threshold dector output is exactly the clock signal of synthesizing.

For system clock cycle, when synthetic clock signal was high, digital signal had maximum, and for system clock cycle, when synthetic clock signal was low, digital signal had minimum value.For the system clock cycle that rising edge and trailing edge take place, digital signal has median.DAC produces an analog signal with the corresponding level of digital signal value.For example, at rising edge, clock signal from the minimum value of previous system clock cycle excessively to the maximum of next system clock cycle.At the system clock cycle of rising edge, the digital controlled signal of the median of close minimum value rises the low-pass filtering analog signal lentamente relatively, thereby it is later relatively to make signal pass through threshold level.Then, the generation of rising edge is later relatively in this system clock cycle.On the contrary, the digital controlled signal of close peaked median rises the low-pass filtering analog signal apace relatively, thereby makes signal pass through threshold level relatively early.In this case, the generation of rising edge is relatively early in this system clock cycle.The situation of trailing edge is similar.By this way, use the rising and falling edges composite number wordclock signal of the part position that is positioned at system clock cycle.

Such system can produce one to be had by relative synthetic clock signal than the accurate edge of locating of high de-agglomeration.Yet such system need be higher than the system clock frequency of synthetic clock signal substantially.Because synthetic clock needs a higher relatively frequency, then such system needs the clock signal of system of a high frequency and the high-speed figure control signal source of a correspondence, DAC, low pass filter, and threshold dector.Such high fdrequency component cost is higher, in addition technical be impossible.

Developed to provide and had by relatively, but do not needed the other technologies of higher components than the accurate synthetic clock signal at the edge of location of high de-agglomeration.For example, license to people such as Black February 28 nineteen ninety-five, title is the synthetic apparatus and method that are used to have the signal in cycle able to programme, United States Patent (USP) 5,394, and 106 disclose a such system.The system of this patent disclosure comprises set of number control signal source, by the counter of system clock timing, and magnitude comparator and a variable delay circuit.Digital controlled signal was represented from the edge of last generation to the time at the edge that the next one requires.The part of each digital controlled signal is represented from the integer system clock cycle to the time location at the next edge of desired synthetic clock signal on the edge, front.The second portion of each digital controlled signal is represented from the fractional part to the system clock cycle of the time location at desired next edge on the edge, front.Digital controlled signal is connected to an input of magnitude comparator by an accumulator and will offers second input of magnitude comparator from the value of counter.The rolling counters forward system clock cycle, and when counting desired clock cycle during number (, reached desired counting), magnitude comparator produces logic ' a 1 ' signal to indicate a coupling.Then, the fractional part of digital controlled signal is that condition is to postpone to be used for logic ' 1 ' output signal from magnitude comparator partly that required of system clock cycle with the variable delay circuit.Delay output signal from variable delay circuit produces an edge in synthetic clock signal.

Substantially be higher than in the frequency that does not need clock signal of system under the situation of the frequency of synthesizing clock signal, 5,394,106 system is placed into synthetic clock signal in the decimal decomposition part of system clock cycle with the edge.As an alternative, the frequency of clock signal of system only need be with synthetic clock signal in the identical magnitude of desired highest frequency.Yet 5,394,106 such systems need a new digital controlled signal from the digital controlled signal source with response ' coupling ' signal from magnitude comparator, that is, and and when the edge that produces corresponding to digital controlled signal at last.Because can use such system, and use it for the synthetic clock signal of phase modulated of generation (with regard to the shake response measurement), when changing the time cycle, need new digital control value.In other words, receive the input digit controlling value asynchronously with system clock.

Yet, one skilled in the art would recognize that synchronous digital hierarchy is easier to design, realize, and the digital system that is integrated into other.5,394,106 systems asynchronous feasible with such system integration to a digital system comparatively the difficulty.The second, asynchronous system makes accurate filtering be difficult for design and realizes.Like this, under the situation of the system clock that does not need to have the frequency that is higher than the frequency of synthesizing clock signal substantially, need a kind of clock signal synthesizer, this synthesizer allows accurately and the configuration of the edge of high de-agglomeration, and this synthesizer is with method of synchronization operation (that is, the digital controlled signal of reception and system clock are synchronous).

The clock signal analyzer also is well-known.Such analyzer produces the data of expression input clock signal phase place.In the mode corresponding with above-described clock-signal generator, a clock signal analyzer comprises that an edge at input clock signal starts the counter that stops at next edge.This counter is by the system clock timing, and the counting when the count cycle finishes provides two time representations between the edge.

Top method has the decomposition of system clock cycle.A kind ofly be used to realize that the method for better decomposing comprises two ramp generators, compare these two ramp generators with system clock and can realize decomposing preferably.Position, edge in the clock signal that pulse is used to represent to be analyzed.A starting impulse triggers a ramp generator, and this ramp generator is crossed over maximum voltage from minimum voltage during a system clock cycle.This ramp generator continues till the next clock cycle begins.Ramp signal value when the next clock cycle begins is converted to digital signal, and is the expression of the fractional part of clock cycle of beginning from the beginning pulse to the next clock cycle: smaller value represent the starting impulse that occurs near the end of this clock cycle higher value represent that the starting impulse that occurs only follows after system clock cycle.Starting impulse also starts the counter of a beginning number system clock cycle.Stop pulse stops counter and triggers second ramp generator.Second ramp generator is to operate and to produce the digital value of the fractional part of the clock cycle that an indication begins from stop pulse to the next clock cycle with the similar mode of first ramp generator.The value of second ramp generator also is converted to a digital value.Like this, duration between starting impulse and the stop pulse can be defined as, system clock cycle number in the counter, the fractional part of first clock cycle of holonomic system between the clock cycle that adds starting impulse and represented by the digital value of first ramp generator deducts stop pulse and the fractional part of the clock cycle of next holonomic system between the clock cycle of being represented by the digital value of second wave producer.

Each edge of the synthetic clock signal of regulation is always not necessary, and the time at each edge of analysis input clock signal is always not necessary yet.In some cases, the low ratio of the edge ratio in the data-signal that is lower than synthetic or analysis provide the edge data, and it is just enough to receive the edge timing data.

Summary of the invention

According to principle of the present invention, a digital phase synthesizer comprises a continuous phase data signal source.In interpolater response continuous phase data-signal each produces continuous edge configuration data signals.Phase-modulator produces a clock signal, and this signal has the edge of usually being determined configuration by continuous edge configuration data signals.Similarly, a digital phase analyzer comprises one group of serial binary input signal source with edge.A phase demodulator produces the continuous data signal of each position, edge of expression serial binary input signal.A withdrawal device produces phase data signal at the low ratio that is lower than the edge that produces the serial binary input signal.

Under the situation of the frequency of the frequency that does not need system clock to have to be higher than substantially synthetic clock signal, allow accurate and higher decomposition edge to dispose according to clock signal synthesizer according to the present invention, and this synthesizer is operated with the method for synchronization.

Description of drawings

In the accompanying drawing:

Fig. 1 is a block diagram that is used for the phase measurement/generator system of serial binary signal;

Fig. 2 is the block diagram that can be used for the clock signal synthesizer of system shown in Figure 1;

Fig. 3 is the more detailed block diagram of clock signal synthesizer shown in Figure 2;

Fig. 4 is the oscillogram that is used to understand according to the operation of phase measurement/generator system of the present invention;

Fig. 5 is the more detailed block diagram of interpolater that can be used for the clock signal synthesizer of Fig. 3;

Fig. 6 and 7 oscillograms, Fig. 9 and 8 is tables, all is used to understand the operation of the phase-modulator of the clock signal synthesizer shown in Fig. 2 and 3;

Figure 10 is the block diagram that can be used for the serial binary input signal analyzer of system shown in Figure 1;

Figure 11 is the more detailed block diagram of serial binary input signal analyzer shown in Figure 10;

Figure 12 is the delay shown in Figure 11 and the more detailed block diagram of register array circuit;

Figure 13 is the oscillogram that is used to understand the operation of the serial binary input signal analyzer shown in Figure 11 and 12;

Figure 14 is the more detailed block diagram that can be used for the filter of serial binary input signal analyzer shown in Figure 11.

Embodiment

Fig. 1 is a block diagram that is used for the phase measurement/generator system 10 of digital signal.Fig. 1 a is configured to be used for the response phase data-signal to produce the block diagram of system 10 of clock output signal and Fig. 1 b is the block diagram that is configured to be used to measure the system 10 of serial binary phase of input signals.Identical parts are marked by identical reference numerals among Fig. 1 a and the b.

At Fig. 1 a, input is connected to the system controller (not shown) of signal of the phase property of a hope that produces the clock output signal that regulation produced.

Input is connected to the input of preprocessor 5.The output of preprocessor 5 is connected to the input of synthesizer 20.The data output end of synthesizer 20 is connected to output terminal of clock, and the gating signal output of synthesizer 20 is connected to the respective input of preprocessor 5.

The control input end is connected to the system controller (not shown) and receives the data of the configuration and the operation that are used for control system 10.The control input end is connected to the input of control interface circuit 12.The status signal of the operating condition of the state output end generation expression system 10 of control interface circuit 12 also is connected to system controller.

Reference clock signal is connected to the reference input of phase-locked loop (PLL) 14.Loop filter 15 also is connected to PLL14.PLL14 offers each parts of system 10 with clock signal, and each parts is synchronized to reference clock with known manner.For simplifying accompanying drawing, not shown these clock signals of Fig. 1.

At Fig. 1 b, input is connected to the serial binary input signal source.Input is connected to the input of analyzer 30.The phase data output of analyzer 30 is connected to the data input pin of preprocessor 25.The output of preprocessor 25 is connected to the output of the data of the detected phase characteristic that produces expression serial binary input signal.The gating output of analyzer 30 is connected to the respective input of preprocessor 25.In addition, the recovered clock output from analyzer 30 is connected to the recovered clock output.The remainder of system shown in Fig. 1 b is identical with the part shown in Fig. 1 a.In the mode of describing in detail below, the system 10 of Fig. 1 a is identical with the system of Fig. 1 b, shown in the dotted line between connection layout 1a and Fig. 1 b.

In operation, the system controller (not shown) offers control data through the control input end system 10.Control interface 12 is with any reception in the various known manner and store these information.For example, the control input end can be connected to the multi-bit parallel number bus, and the multi-bit parallel number bus is connected to a microprocessor.As a kind of replacement, the embodiment that is illustrating, the control input end is a kind of serial digital input terminal, and it comprises a serial data signal line, a clock cable, but also may comprise be used for control flows to or from the control line of the data flow of control interface 12.Control interface 12 comprises the register that is connected to the control input terminal, is used to store the value from the control input terminal.The outlet terminal of register all in known manner with system 10 in control a plurality of circuit be connected.

Similarly, control interface can comprise register, perhaps latch, and perhaps transmission gate (as required), thus its input terminal is connected the value of monitoring node with the node of system 10.The outlet terminal of these circuit is connected with the state outlet terminal.In addition, above-described register comprises controlling value, also can make their outlet terminal be connected to the state outlet terminal.Also may share these control registers, and some controlling values that comprise and other state value that provides.For the control input terminal, the state outlet terminal can be the multi-bit parallel data/address bus, perhaps resembles in the embodiment that provides, and is the serial signal line that comprises data signal line, clock cable and possible control line.The system controller (not shown) can come judgement system 10 with a kind of known mode reading of data from these circuit current state.

In Fig. 1 a, the system controller (not shown) provides control data to control interface 12, comes configuration-system 10 to make it as the clock output signal generator, and its mode will describe in detail below.Under this operator scheme, synthesizer 20 sends gating signal to preprocessor 5 when the phase data that will look for novelty.As the response to this gating signal, preprocessor 5 will represent accordingly that the data of the phase characteristic of clock output signal offer synthesizer 20.As to be described in detail below, preprocessor 5 both can carry out physical signal with synthesizer 20 to be handled, and also can not have to make under the situation of entity handles the input phase characteristic signal directly from the input to the synthesizer 20.Yet at described embodiment, pre-preprocessor 5 and the relative high speed circuit in the synthesizer 20 are carried out the signal processing of relative low speed together in following described mode.

Synthesizer 20 produces the clock output signal with edge of placing according to the phase data that receives from pre-preprocessor 5.Clock output signal has basically the edge that occurs at estimated rate (baud), comprises the phase modulated at these edges.Yet, needing (through gating signal) phase data at constant ratio from pre-preprocessor 5, this constant ratio is less than predetermined (baud) ratio at the edge in the output serial binary signal, and all these carry out in the following mode of more describing in detail.That is, the edge in the clock output signal that is produced produces asynchronously with phase data from pre-preprocessor 5.

At Fig. 1 b, the system controller (not shown) has offered control data control interface 12 with configuration-system, makes it in the following mode of more describing in detail, is operating as a serial binary input signal measuring system.In this operator scheme, analyzer 30 receives has the serial binary input signal at the edge of estimated rate (baud) appearance basically, but carries out phase modulated.Analyzer 30 calculates the data of the time that expression experienced to the continuous edge of the next one from each edge of serial binary input signal IN, and produces the phase meter registration number of the it is believed that phase data sequence of the serial binary phase of input signals characteristic that an expression analyzer 30 receives.Whether available gating signal one is used from preprocessor 25 to the new phase meter registration of these phase meter registration numbers of it is believed that PHASE DATA and expression according to phase data.Response gating signal, preprocessor 25 receiving phases are represented the data signal phase data and are produced the output signal of an expression serial binary phase of input signals characteristic.In the mode similar to above-described pre-preprocessor 5, preprocessor 25 can be carried out physical signal and handle, or also can under situation, make without any entity handles phase data phase of output signal data directly from analyzer 30 to the phase characteristic output.Yet at described embodiment, preprocessor 25 is handled the signal processing of carrying out relative low speed together in following described mode with the relative high speed signal in the analyzer 30.

Produce system class seemingly with top with reference to the described digital dock of Fig. 1 a, phase data is offered preprocessor 25 (through gating signal) at constant ratio, edge in the serial binary input signal appears at predetermined ratio (baud) substantially simultaneously, although carry out phase modulated, all these carry out in mode described below.Like this, with the serial binary input signal in the edge produce phase data asynchronously.In addition, in illustrated embodiment, analyzer 30 also produces a recovered clock signal with identical with the serial binary input signal that receives basically phase place.

Fig. 2 is the block diagram that can be used for the clock signal synthesizer 20 of system shown in Figure 1 10.At Fig. 2, will be connected to an input of interpolation filter 22 from the phase data of pre-preprocessor 5 (Fig. 1).The gating signal output of interpolation filter 22 is connected to the respective input of pre-preprocessor 5.The data output end of interpolation filter 22 is connected to an input of phase-modulator 26.An output of phase-modulator 26 is connected to clock signal output terminal.

In operation, interpolation filter 22 is by starting the phase data of gating signal requirement from pre-preprocessor 5.Response gating signal, pre-preprocessor 5 provide the data of the phase characteristic of the desired clock output signal CLK OUT of expression with above-described known manner.Interpolation filter 22 then produces continuous edge configuration data signals, the position at an edge in each such signal regulation clock output signal.By this way, interpolation filter 22 produces the edge configuration signal, in the following mode of more describing in detail, this signal is that condition produces a clock output signal with phase-modulator 26, and this clock output signal has the phase characteristic of the characteristic smooth change that a phase data signal that receives to the end from the characteristic of representing at preceding phase data signal from pre-preprocessor 5 represents.Phase-modulator 26 produces has each and the clock output signal at the edge placed of response from the edge configuration signal of interpolation filter 22.

Fig. 3 is the more detailed block diagram of a serial binary signal synthesizer 20 shown in Fig. 1 and 2.At Fig. 3, be connected to the data input pin of interpolater 220 from the phase data of pre-preprocessor 5 (Fig. 1).An output of interpolater 220 connects an input of the expander 230 that puts in place.More describe in detail as following, be connected to an input of frequency divider 232 from the clock signal of system of PLL14.An output of frequency divider 232 is connected to a data input of clock selector 234.A data output of clock selector 234 is connected to the input end of clock of interpolater 220.The gating output of interpolater 220 is connected to the output of interpolation filter 20.Interpolater 220, position expander 230, frequency divider 232 and clock selector 234 be combined to form interpolation filter 22.

PLL14 also produces a multi-phase clock signal at system clock frequency.In illustrated embodiment, multi-phase clock signal comprises the clock signal with phase 0 to φ 7.Select first phase place of multi-phase clock signal, φ 0, as clock signal of system, and is connected to an input of counter 262.

An output of position expander 230 is connected to the first input end of adder 268.Corresponding first and second outputs of adder 268 are connected to corresponding first and second control input ends of decoder 272.The output of decoder 272 is connected to a data input of analog multiplexer (MUX) 274.The output of MUX 274 is connected to the input of low pass filter 276.The output of low pass filter (LPF) 276 is connected to the data input of comparator 278.The output of comparator 278 is connected to the output of synthesizer 20 and produces clock output signal.

The 3rd output of adder 268 is connected to the respective input of first digital-to-analog converter (DAC) 264 and the 2nd DAC266.First and second DAC264 and 266 corresponding output end produce signal A1 and A2 and are connected to the respective input of decoder 272.All phase places of leggy clock signal of system, φ is connected to the control input end of simulation MUX 274 to φ 7.Counter 252, MUX274, LPF276 and comparator 278 be combined to form phase-modulator 26.

Fig. 4 illustrates the leggy clock signal of system from PLL14 (Fig. 1).At the embodiment that illustrates, the leggy system clock comprises 8 clock signals with same frequency, but is respectively the phase place of 8 equipartitions, so that simplify description of the invention.The leggy clock signal of system can be produced with known manner by ring oscillator.The leggy clock signal of system also may comprise the phase place greater or less than 8.A phase place in the selection leggy clock signal of system is to provide a clock signal of system.At the embodiment that illustrates, use φ 0 as system clock.

Frequency divider 232 in the interpolation filter 22 is from PLL14 receiving system clock signal, and produces a plurality of clock signals at the corresponding subharmonic (that is, 1/2,1/4,1/8 etc. of system clock frequency) of clock signal of system frequency.At preferred embodiment, frequency divider 232 produces 9 such clock signals.These 9 sub-frequency clock signals, and clock signal of system offer clock selector 234, the clock signal as interpolater 220 that clock selector 234 is selected in these signals.

Interpolation filter 22 is one and carries out interpolation between rare relatively receiving phase data-signal, nominally to produce the low pass filter in the edge of baud configuration data signals.This design allows phase data input ratio from relatively low ratio 1.5MHz, is increased to resemble 700 to 1400MHz such frequencies in a big way.At the embodiment that illustrates, with known manner configuration interpolater 22, so that the interpolation of the output edge configuration data signals between the receiving phase data-signal is provided.

Fig. 5 is the more detailed block diagram of the interpolater 220 of a clock signal synthesizer 20 that can be used for Fig. 3.Fig. 5 illustrates three block diagrams of interpolater 220.At Fig. 5 a, will be connected to an input of latch 222 from the phase data of pre-preprocessor 5.An output of latch 222 is connected to an input of the first boxcar filter 226.An output of the first boxcar filter 226 is connected to an input of the second boxcar filter 228.An output of the second boxcar filter 228 is connected to an input of a funnel phase shifter 229.An output of funnel phase shifter 229 is connected to an output of interpolater 220, and an output of interpolater 220 is connected to phase-modulator 26 (Fig. 3).At baud F _BAUDA clock signal from clock selector 234 (Fig. 3) that illustrates is connected to an input of the frequency divider 223 of the input end of clock of the second boxcar filter 228 and fixed frequency.An output of fixed frequency branch frequency 223 is connected to the input end of clock of the first boxcar filter 226 and an input of the second fixed frequency branch frequency 221.An output of the second fixed frequency branch frequency 221 is connected to the input end of clock of latch 222 and the gating output of interpolater 220.

The boxcar filter is well-known, and has the flat pulse response characteristic in the preset time cycle.Those skilled in the art recognizes that such filter will provide the linear interpolation and the amplification of input signal.Series connection, and be operated in two such boxcar filters of identical time cycle a secondary interpolation functions and amplification will be provided.Those skilled in the art also recognizes the interpolation scheme that also can adopt other.

In operation, latch 222 receives from the phase data and the response of pre-preprocessor 5 and deposits this signal from the gating signal of the second fixed frequency frequency divider 221.Gating signal directly obtains from the frequency division of clock signal of system by frequency divider 232 and clock selector 234 (Fig. 3) and first and second fixed frquency dividers 223 and 221.Therefore, with system clock receiving phase data synchronously, and phase data does not respond the timing at the edge of any generation.Deposit phase data and offer the series connection of the first and second boxcar filters 226 and 228.The first and second boxcar filters provide the secondary interpolation of phase data signal and amplification and produce one group of continuous edge configuration signal at baud.Continuous edge configuration signal is offered phase-modulator 26 (Fig. 3).

The output of the second boxcar filter 228 is the long number numbers of words with predetermined figure.Funnel phase shifter 229 carries out work so that pass through to select the amplitude of the subclass decay of position from the sample of the second boxcar filter, and according to clock factor M ₃And M ₄With known manner it is carried out phase shift.The output of funnel phase shifter 229 connects the expander 230 (Fig. 3) that puts in place.

It will be appreciated by those skilled in the art that the boxcar filter can be decomposed into the series connection of accumulator and difference engine.Those skilled in the art also understands because accumulator and difference engine be operating as linear operation, it can be with any arranged in order.Further, also understanding the operation that adds up is an operation relatively at a high speed, and difference operation is the operation of a relative low speed.

Fig. 5 b illustrates the interpolater 220 of Fig. 5 a, and wherein the first boxcar filter 226 is decomposed into the series connection of accumulator 252 and difference engine 254, and the second boxcar filter 228 is decomposed into the series connection of accumulator 256 and difference engine 258.Square frame 258 illustrates the sample that 258 pairs of M samples of difference engine separate and operates, and 254 couples of M of difference engine ₄The sample that sample separates is operated.Yet, because M=M ₃M ₄, and the clock signal that is provided is passed through the first boxcar frequency divider 223 by factor M ₃Carry out frequency division, the time cycle of difference engine operation is identical with the time cycle of difference engine 258 operations.

Fig. 5 c illustrates another configuration of interpolater 220, and wherein two

difference engines

254 and 258 are directly connected to the back of latch 222, and latch 222 is followed by two accumulators 252 and 256.Difference engine is operated adjacent sample (by a sample separately) in this case, but because it is by the gating signal timing, this gating signal is carried out frequency division by the series connection of the first and second fixed

frequency frequency dividers

223 and 221 by M, and difference engine still operates in the identical time cycle.Yet the configuration of Fig. 5 c separates the difference operation of relative low speed with the relative operation that adds up at a high speed.Therefore, latch 222, and can the be placed on it outside of integrated circuit (IC) chip of construction system 10 of two difference engines 254 and 258.These parts are placed in the pre-preprocessor 5, as mentioned above.The high speed accumulator is retained in the integrated chip that comprises system 10.By the low speed parts are shifted out the integrated circuit (IC) chip that comprises system 10, reduced circuitry needed parts in the integrated circuit (IC) chip, and the interface area.

Referring again to Fig. 3, the output signal that position expander 230 receives from funnel phase shifter 229 (Fig. 5).Position expander 230 expands from the figure place in the output signal of funnel phase shifter 229, and carries out the low speed filtering operation.For example, at the embodiment that illustrates, position expander 230 produces the signal with 15.At preferred embodiment,, can require more position according to the circuit arrangement of describing in detail below.At the embodiment that illustrates, carry out filtering by first order low pass filter, constitute by a HIR filter in the embodiment first order low-pass filtering that illustrates.Position expander 230 offers phase-modulator 26 with output signal.

Come the signal of self-alignment expander 230 to be considered to represent the fixing point real number of desired next unmodulated clock edges of carrying out with baud to the time difference amount at the edge of next synthetic clock output signal, promptly, come the signal of self-alignment expander 230 to comprise the integer part that fixed bit is wide, and the fixing fractional part of bit wide.This real number can be plus or minus.Integer part is represented the number of the total system clock cycle between the time location at next edge of the time location at next edge of desired synthetic clock signal and unmodulated clock signal, and fractional part is represented the fractional part of the system clock cycle between the time location at next edge of the time location at next edge of synthetic clock signal and unmodulated clock signal.

At the embodiment that illustrates, system clock frequency is relevant to baud with 2 power.That is, if baud is F _BAUD, then system clock frequency is 2 ^mF _BAUDIn this case, each clock signal period of representing with baud comprises 2 ^mSystem clock cycle.The value of M can be selected through control interface 12 by system controller.Response is from the control signal of system's control through control interface 12, and configuration counter 262 is so that come consistent with selected m value by being configured as the m digit counter.In the M digit counter 262 response leggy clock signal of system one: at the embodiment that illustrates, phase place Φ 0.Therefore, be output as m position digital signal with baud number system clock ratio and cycle from m digit counter 262, that is, beginning counting in the cycle is 0, is 2 in the cycle intermediate total ^M+1, and be 2 finishing counting ^m-1, be 0 only beginning.

The size of configuration counter, and the value of m is so that provide clock signal from system clock frequency to interpolater 220 with the baud that requires.Simultaneously, configurable clock generator selector 234 is to select output from Clock dividers 232 divided by 2 ^mIn this configuration, be baud from the clock signal unit of clock selector 234.This is normally desired, although also can select other configurations.

For example, if the system clock frequency that PLL14 provides is 1228.8MHz, and desired baud is 2.4MHz, and then m is chosen as 9.Counter 262 is configured to 9 digit counters, and with baud number system clock ratio, and the cycle, that is, beginning counting in the cycle is 0, is 256 in the cycle intermediate total, and is 511 at 0 end cycle counting before restarting.

Can understand the operation of phase-modulator 26 preferably by the oscillogram shown in reference Fig. 6 and 7.The highest waveform among Fig. 6 is represented the rising edge of clock signal of system, and as mentioned above, this rising edge is the Φ 0 of leggy clock signal of system.Clock signal of system is that condition is counted and cycle from 0 to 511 and get back to 0 with counter 262.This is represented corresponding to second waveform among Fig. 6 of the value of the multidigit output of the counter 262 of the response rising edge of clock signal of system by expression.

From interpolation filter 22 the position expander 230 signal, represent that with baud the next one of clock output signal requires the time difference between the time location at next edge of the time location at edge and nominal clock signal, and being expressed as a fixing point real number with integer and fractional part, all these are as mentioned above.This signal is in the output combination of adder 268 with counter 262.As mentioned above, the integer part of fixing point real number is represented the integer part of system clock cycle, and also represents the integer part of system clock cycle from the output signal of counter 262.Like this, be considered to only have the fixing point real number of integer part and null value fractional part from the signal of counter 262.At preferred embodiment, from deduct the output of counter 262 from the time difference signal of expander 230 not.Therefore, adder 268 is output as from 0 to 511 countdown, then successively decreases by 256, then by 1 successively decrease back 0 number.Yet counting direction does not influence the generation at edge, because 0 and 256 be identical in the time cycle, with count increments with successively decrease irrelevant.

Difference signal from adder 268 also is considered to a fixing point real number with integer part and fractional part.This signal is controlled the configuration at the next edge of clock output signal in the following manner.The integer part of this signal is called as rough segmentation and separates signal, and is connected to the first control input end C of decoder 272.The highest significant position of fractional part is a middle decomposed signal, and is connected to the second control input end M of decoder 272.At the embodiment that illustrates, middle decomposed signal is a tribute signal.Yet at preferred embodiment, middle decomposed signal can be more than three.The next most significant part of fractional part is meticulous decomposed signal and the respective input that is connected to first and second digital to analog converters (DAC) 264 and 266.At the embodiment that illustrates, meticulous decomposed signal F also is a tribute signal.Yet at preferred embodiment, this meticulous decomposed signal can be more than three.

If the time difference signal that comes self-alignment expander 230 is being for just, then the output valve of adder 268 is greater than the output valve of counter 262, and if the time difference signal for negative, then the output valve of adder 268 is less than the output valve of counter 262.The integer part of difference signal was integer (C is separated in the rough segmentation) output of+1 o'clock adder 268 between the 3rd waveform of Fig. 6 was represented at that time.When+1 deducts the output valve of counter 262, the result is the value greater than the value of counter 262.The integer part of difference signal was integer (C is separated in the rough segmentation) output of-1 o'clock adder 268 between the 4th waveform of Fig. 6 was represented at that time.When-1 deducts the output valve of counter 262, the result is the value less than the value of counter 262.

As described in detail later, be output as the rising edge that produces clock output signal during time interval of 0 at the integer of adder 268 and produce trailing edge be output as time interval of 256 at the integer of adder 268 during.Adder 268 and counter 262 combinations allow the position, edge, and the phase place of such clock output signal that produces is by a phase shift integer system clock cycle.Yet in the following description, the integer part of supposing the time difference signal equals 0 and equal value from counter 262 from the integer (C is separated in rough segmentation) of adder 268 thus.

Following 8 oscillograms of Fig. 6 are represented the leggy clock signal of system of phase place Φ 0 to Φ 7.The left part of these oscillograms was illustrated in during the time interval of the rising edge that produces clock output signal, integer output valve when adder 268, C equals these signals of 0 o'clock, and expression these signals when C equals 256 (trailing edges of clock output signal) are divided in the right side.As shown in Figure 6, in a single clock cycle, exist by the dependent phase definition of the corresponding signal in the multi-phase clock signal, be marked by W0 to W7,8 sub-time intervals.Those skilled in the art can with known manner design and Implement be used for producing express time at interval W0 or have the express time circuit of W0 digital count signal of corresponding one value in the W7 at interval to each corresponding binary signal of W7.

Decoder 272 is operated to produce 8 signal D0 to D7 in the mode of describing in detail below.Table shown in Fig. 8 helps to understand the operation of decoder 272.In the table of Fig. 8, left column represents that rough segmentation separates C (from the integer value of adder), and decomposition value M in second line display (from the highest effective three of the fractional part of adder 268).Right column represents that the signal D0 of decoder 272 generations is to D7.Signal D0 is many level analog signal to D7.At the embodiment that illustrates, these signals have 9 possible values, although can be more than 9 level at preferred embodiment.These signal levels can be represented minimum levels by from 0, to 8, and the value defined that the expression maximum level changes.

Analog multiplexer (MUX) 274 response leggy clock signal of system pass through signal D0 to D7 with the sequential loop of every next system clock cycle.During phase intervals W0, MUX274 offers its output with the D0 signal; During phase intervals W1, MUX274 offers its output with the D1 signal, and the like.

The signal D0 that decoder 272 produces to the configuration of D7 based on C and M value from adder 268.The signal D0 that decoder 272 produces is represented to D7 by the row D0 in Fig. 8 table to the particular value of D7.In the C value greater than 0 less than 256 the time interval during, in Fig. 8 table in the middle of row illustrate, all these many level analog signals D0 have value 8 to D7, with the value of middle decomposed signal M irrelevant (by the M row interior " X " represent that implication is ' haveing nothing to do ').In this interim, the simulation signal generator that decoder 272 will have level 8 is connected to all output D0 to D7.Like this, the signal that is produced by MUX274 at this interval has steady state value 8.Greater than 256 but during not covering time interval of 0, the nethermost row in Fig. 8 table illustrates, all these many level analog signals D0 have value 0 to D7, and are irrelevant with the value of middle decomposed signal M in the output of adder 268.In this interim, the simulation signal generator that decoder 272 will have level 0 is connected to all output D0 to D7.Like this, the signal that is produced by MUX274 at this interval has steady state value 0.

Eighth row in Fig. 8 table middle and upper part, and the oscillogram in Fig. 6 left side illustrates the time interval that the C signal equals 0.D0 forms in following mode to D7 in this blank signal.If middle decomposed signal M is 0, then signal D0 will present any one (a plurality of horizontal lines by the signal D0 among Fig. 6 are represented) in the analog level 1 to 8.Specific analog level obtains from the signal A1 from a DAC 264, and this signal is by item " A1 " expression in the row in Fig. 8 table, and signal D0 is shown in this tabulation, and signal D0 is positioned at the row of expression C signal 0 and M signal 0.At the embodiment that illustrates, in this time interval, decoder 272 is connected to the D0 output with the output of a DAC264.For equaling 0 C and equal 0 M, signal D0 will present analog level 8 to D7.The simulation signal generator that decoder 272 will have level 8 is connected to D0 to the D7 output.As the inswept signal D0 of MUX274 during, as mentioned above, produce the left part that is marked with the signal of " 0 " among Fig. 6, and during phase intervals W0, produce rising edge in the mode of describing in detail below to D7.

If middle decomposed signal equals 1, with the D0 signal sets to the analogue value 0.Signal D1 can present analog level 1 to 8 (from the signal A1 of a DAC264); And residual signal signal D2 presents the analogue value 8 to D7, as shown in Figure 8.When the inswept signal D0 of MUX274 to D7, as mentioned above, produce among Fig. 6 and be marked with the left part of the signal of " 1 ", and during phase intervals W1, produce rising edge.Similarly, when the M signal has value 2 to 7, signal D2 has the variable analogue value 1 to 8 from the signal A1 of a DAC264 respectively to D7.The Dx signal value of front has the analogue value 0 and the Dx signal value of following has simulation value 8.When the inswept signal D0 of MUX274 to D7, as mentioned above, produce the left part that is marked with 2 to 7 signal among Fig. 6, and during W7, produce rising edge at phase intervals W2 respectively.

Eighth row in Fig. 8 table middle and lower part, and the oscillogram on Fig. 6 right side illustrates the time interval that the C signal equals 256.D0 forms in following mode to D7 in this blank signal.If middle decomposed signal M is 0, then signal D0 will present any one (a plurality of horizontal lines by the signal D0 among Fig. 6 are represented) in the analog level 1 to 8.Specific analog level obtains from the signal A2 from the 2nd DAC 266, and this signal is by item " A2 " expression in the row in Fig. 8 table, and signal D0 is shown in this tabulation, and signal D0 is positioned at the row of expression C signal 256 and M signal 0.At the embodiment that illustrates, in this time interval, decoder 272 is connected to the D0 output with the output of the 2nd DAC264.For equaling 256 C and equal 0 M, signal D1 will present analog level 0 to D7.The simulation signal generator that decoder 272 will have level 0 is connected to D1 to the D7 output.As the inswept signal D0 of MUX274 during, as mentioned above, produce the right side part that is marked with the signal of " 0 " among Fig. 6, and during phase intervals W0, produce trailing edge in the mode of describing in detail below to D7.

If middle decomposed signal equals 0, with the D0 signal sets to the analogue value 8.Signal D1 can present analog level 0 to 7 (from the signal A2 of the 2nd DAC266); And residual signal signal D2 presents the analogue value 0 to D7, as shown in Figure 8.When the inswept signal D0 of MUX274 to D7, as mentioned above, produce among Fig. 6 and be marked with the right side part of the signal of " 1 ", and during phase intervals W1, produce trailing edge.Similarly, when the M signal has value 2 to 7, signal D2 has the variable analogue value 0 to 7 from the signal A2 of the 2nd DAC266 respectively to D7.The Dx signal value of front has the analogue value 8 and the Dx signal value of following has the analogue value 0.When the inswept signal D0 of MUX274 to D7, as mentioned above, produce the right side part that is marked with 2 to 7 signal among Fig. 6, and during W7, produce trailing edge at phase intervals W2 respectively.

As mentioned above, the signal D0 of simulation MUX274 response multi-phase clock signal self-demarking code in the future device 272 is sequentially connected to its output D to D7 with every next system clock cycle.Signal D and the detection threshold that is produced with the mode low-pass filtering that describes below like this is to produce clock output signal.

From the meticulous decomposed signal F of adder 268 edge is placed on the prescribed phases stipulated time of W0 in the W7 at interval in the following manner.Meticulous as mentioned above decomposed signal F is connected to first and second DACs (DAC1 264 and DAC2 266).Fig. 9 illustrates and indicates first and second DAC, and 264 and 266 provide, corresponding to each value of meticulous decomposed signal F, the corresponding output level of analog signal A1 and A2.That is, for the meticulous decomposed signal F with value 0, a DAC (DAC1) 264 produces an analog signal A1 and the 2nd DAC (DAC2) 266 with level 1 and produces an analog signal A2 with level 7 simultaneously.For the meticulous decomposed signal F with value 1, a DAC produces an analog signal A1 and the 2nd DAC with level 2 and produces an analog signal A2 with level 6 simultaneously, and the like.

Fig. 7 illustrates two possible oscillograms that are used for the signal D of selected MUX274.Uppermost oscillogram d represents the waveform of a selection among Fig. 7, and wherein the value from the meticulous decomposed signal F of adder 268 is 6.As shown in Fig. 9 table, like this, the value of A1 signal be 2 and the value of A2 signal be 6.At the oscillogram D that illustrates, the time location of A1 signal and A2 signal is represented by one group of thin horizontal line, with the same among Fig. 6.With A1 in the D of actual selection and A2 signal indication is thick line.When this signal during by the LPF268 low-pass filtering, second waveform in Fig. 7 is represented the waveform that produced.

Compare with the maximum level (8) of filtering electrical level rising, because A1 level (2) is relatively low, the filtering waveform rises relatively slow.Therefore, the filtering level is at the passing threshold of the rising later Th in the A1 time interval (in that the centre that embodiment is set in minimum and maximum value is shown).Similarly, compare with the minimum levels (0) that the filtering level descends, because A2 level (6) is higher relatively, the filtering waveform descends relatively slow.Therefore, the filtering level is at the passing threshold of the decline later Th in the A2 time interval.

Filtering waveform and threshold value Th are compared in comparator 278.When the value of filtering waveform during less than threshold value Th, the output of comparator 278 is less, and when the value of filtering waveform during greater than threshold value Th, the output of comparator 278 is bigger.At the 3rd waveform of Fig. 7 the output of comparator 278 is shown, and it is a clock output signal.

The 4th waveform D of Fig. 7 illustrates the waveform of a selection, and wherein the meticulous decomposed signal value from interpolation filter 22 is 2.Like this, the A1 signal value be 6 and the A2 signal value be 2, as shown in Fig. 9 table.The signal D that selects is expressed as thick line.As this signal D during by the LPF268 low-pass filtering, the waveform table that is produced is shown in the 5th waveform of Fig. 7.

Compare with the maximum level (8) of filtering electrical level rising, because A1 level (6) is higher relatively, the filtering waveform rises very fast relatively.Therefore, the filtering level is at the passing threshold of the rising in early time Th in the A1 time interval.Similarly, compare with the minimum levels (0) that the filtering level descends, because A2 level (2) is relatively low, the filtering waveform descends very fast relatively.Therefore, the filtering level is at the passing threshold of the decline in early time Th in the A2 time interval.

Filtering waveform and threshold value Th are compared in comparator 278.The output of comparator 278 is expressed as the 6th waveform of Fig. 7, and is clock output signal CLK OUT.Shown in Fig. 6 and 7, response is from the centre of

interpolation filter

22 and 1/64 position of decomposing each edge of placement of meticulous decomposed signal using system clock cycle.In addition, to receive phase data signal than the low ratio of baud from pre-preprocessor 5., and receive with fixing Frequency Synchronization, rather than based on the ratio at the edge that is produced in the clock output signal.

The signal indication of least significant bit that person of skill in the art will appreciate that counter 262 outputs is from the clock signal of 2 frequency divisions of the clock signal of system of the input of counter 262.And each other output signal is represented a clock signal from 2 frequency divisions of next least significant bit.Then, counter 262 can also be considered to represent a multidigit frequency divider, is for example represented by the frequency divider 232 of interpolation filter 22.For this purpose, use single one by one counter at the embodiment that illustrates, its output not only is connected to the adder 268 of phase-modulator 26 but also is connected to clock selector 234 in the interpolation filter 22.Because interpolation filter 22 is shared Clock dividers 232 with the counter 262 in the phase-modulator 26, it illustrates in interpolation filter 22 (clock selector 234 also receives the clock signal of system from the not frequency division of PLL14).

Referring now to the digital phase analyzer shown in Fig. 1 b, Figure 10 is the block diagram that can be used for the clock signal analyzer of system shown in Figure 1 10.At Figure 10, input IN is connected to one group of binary input signal source.Input is connected to the input of phase demodulator 32.And the output of phase demodulator 32 is connected to the input of anti-glitch filter 36.The output of anti-glitch filter 36 is connected to the input of withdrawal device 39.The data output end of withdrawal device 39 produces the data of the serial binary phase of input signals characteristic of expression input, and is connected to the phase data output.Gating output from withdrawal device 39 is connected to the gating output.

The serial binary input signal has general edge corresponding to the baud time location at input.This serial binary input signal can be a phase modulated signal, and wherein the position at edge changes in phase place, and perhaps signal can be a data transfer signals, wherein represents such edge or appearance by the data of signal transmission, or does not occur.Under the data cases that transmits signal, the edge of appearance will take place on baud in fact.

Phase demodulator 32 produces the edge position data at each edge in the expression serial binary input signal.Generation edge position data and reference clock synthesizer 20 are consistent with the edge position data as mentioned above when detecting each edge.Withdrawal device 39 produces a sample, represents serial binary phase of input signals characteristic, each default edge positional number and the modulation of system clock synchronism earth pulse, and asynchronous with the generation at edge.Anti-glitch filter 36 prevents obscuring in the extraction process in known manner.

In addition, refer again to Figure 10, the phase-modulator 26 that has structure shown in Figure 3 and work as mentioned above can have the input that links to each other with the output of demodulator 32, shown in the dashed line view of Figure 10.The output of phase-modulator 26 links to each other with the output that produces the recovered clock output signal in dashed line view.As mentioned above, with reference to Fig. 3, phase-modulator is accepted the edge position data and responds this edge position data to produce clock output signal.Phase demodulator 32 produces and the relevant edge position data of accepting from input of serial binary input signal, and this edge position data is corresponding to the edge position data from interpolation filter 22 receptions of Fig. 3.As the response to these data, phase-modulator 26 can produce a clock recovered output signal, and it has and the corresponding phase place of edge position data that receives, and consistent with the serial binary input signal that receives at input terminal.

Figure 11 is the more detailed block diagram of the analyzer 30 that provides in Fig. 1 and 10.In Figure 11, input terminal links to each other with the source of serial binary input signal.This input terminal links to each other with the input of a delay circuit 322.The output of delay circuit 322 links to each other with the data input pin of register array 324.The output of latch arrays 324 links to each other with the input of serial binary decoder 326.The data output end of binary decoder 326 links to each other with the first input end of register 328.The output of register 328 links to each other with phase-modulator 26 with anti-glitch filter 36.

Clock signal of system, it is multi-phase clock signal φ 0, links to each other with the input of counter 330.The output of counter 330 links to each other with second input of register 328.Delay circuit 322, latch arrays 324, binary coder 326, counter 330 and register 328 constitute phase demodulator 32 together.

The output of register 328 links to each other with the input of position expander 362.The output of position expander links to each other with the data input pin of the first boxcar filter 364.The output of the first boxcar filter 364 links to each other with the data input pin of the second boxcar filter 366.The output of the second boxcar filter 366 links to each other with the data input pin of the 3rd boxcar filter 368.The output of the 3rd boxcar filter 368 links to each other with the input of cylinder shifter 370.The output of cylinder shifter 370 links to each other with the input of latch 392.The phase place that latch 392 produces representative data is come description string row binary phase of input signals characteristic, and links to each other with the phase data output.

Clock signal of system from PLL 14 also links to each other with the input of frequency divider 372.The output of frequency divider 372 links to each other with the input of clock selector 374.The corresponding input end of clock of the output of clock selector 374 and first fixed frquency divider, 376 inputs and the first and second boxcar filters 364,366 links to each other.The output of first fixed frquency divider 376 links to each other with the input of second fixed frquency divider 394 and the input end of clock of the 3rd boxcar filter 368.The output of second fixed frquency divider 394 links to each other with the input end of clock of latch 392.Position expander 362, the corresponding the first, the second and the 3rd boxcar filter 364,366,368, cylinder shifter 370, frequency divider 372, clock selector 374, and first fixed frquency divider 376 constitutes anti-glitch filter 36 together.The latch 392 and second fixed frquency divider 394 constitute withdrawal device 39 together.

In operation, delay circuit 322, latch arrays 324 and binary coder 326 are worked together, and at the edge of input detection serial binary input signal, its mode will be described in greater detail below.When detecting an edge, binary coder produces a signal at its output terminal of clock, and it is condition with register 328 with the corresponding data output that these data are closed to counter 330 and binary coder 326.The cycle count of 330 pairs of system clocks of counter.Then, the count value that is stored in register 328 represent one-time detection in the past to the integer system clock cycle that begins of edge.So just provided the position on edge roughly.

Figure 12 is the delay circuit 322 shown in Figure 11 and the more detailed block diagram of latch arrays circuit 324.At Figure 12, latch arrays 324 is made up of 8 row latch arrays, every row comprises 8 latchs, each latch is a D flip-flop, and each D flip-flop has a D input, an input end of clock (being represented by little triangle) and Q output (only the latch L0 by the upper left quarter of latch arrays 324 represents).The summation of 64 triggers constitutes an array with 8 row and 8 row.

Φ 1 clock signal jointly offers the input end of clock of 8 D flip-flops of first (leftmost side) row.These latchs are from being up to most the most descending L0 of being marked by to L7.The output of these latchs is connected respectively to the output Q0 of latch arrays 324 to Q7.Φ 2 clock signals jointly offer the input end of clock of 8 D flip-flops of secondary series.These latchs are from being up to most the most descending L8 of being marked by to L15.The output of these latchs is connected respectively to the output Q8 of latch arrays 324 to Q15 (not shown for simplicity).Φ 3 clock signals jointly offer the input end of clock of tertial 8 D flip-flops.These latchs are from being up to most the most descending L16 of being marked by to L23.The output of these latchs is connected respectively to the output Q16 of latch arrays 324 to Q23 (not shown for simplicity).Φ 4 clock signals jointly offer the input end of clock of 8 D flip-flops of the 4th row.These latchs are from being up to most the most descending L24 of being marked by to L31.The output of these latchs is connected respectively to the output Q24 of latch arrays 324 to Q31 (not shown for simplicity).Φ 5 clock signals jointly offer the input end of clock of 8 D flip-flops of the 5th row.These latchs are from being up to most the most descending L32 of being marked by to L39.The output of these latchs is connected respectively to the output Q32 of latch arrays 324 to Q39 (not shown for simplicity).Φ 6 clock signals jointly offer the input end of clock of 8 D flip-flops of the 6th row.These latchs are from being up to most the most descending L40 of being marked by to L47.The output of these latchs is connected respectively to the output Q40 of latch arrays 324 to Q47 (not shown for simplicity).Φ 7 clock signals jointly offer the input end of clock of 8 D flip-flops of the 7th row.These latchs are from being up to most the most descending L48 of being marked by to L55.The output of these latchs is connected respectively to the output Q48 of latch arrays 324 to Q55 (not shown for simplicity).Φ 8 clock signals jointly offer the input end of clock of 8 D flip-flops of the 8th row.These latchs are from being up to most the most descending L56 of being marked by to L63.The output of these latchs is connected respectively to the output Q56 of latch arrays 324 to Q63 (not shown for simplicity).

Input IN is connected to first delay circuit, 322 (1), second delay circuit the 322 (2), the 3rd delay circuit 322 (3), the 4th delay circuit 322 (4), the 5th delay circuit the 322 (5), the 6th delay circuit 322 (6), and the input of the series connection of the 7th delay circuit 322 (7).First delay circuit, 322 (1), second delay circuit the 322 (2), the 3rd delay circuit 322 (3), the 4th delay circuit 322 (4), the 5th delay circuit the 322 (5), the 6th delay circuit 322 (6), and the 7th delay circuit 322 (7) constitute delay circuit 322.

The output of the 7th delay circuit 322 (7) produces the C0 signal of latch arrays 324 and jointly is connected to the input D of first row (L0, L8, L16, L24, L32, L40, L48 and L56) of latch.The output of the 7th delay circuit 322 (7) produces the C0 signal of latch arrays 324 and jointly is connected to the input D of first row (L0, L8, L16, L24, L32, L40, L48 and L56) of latch.The output of the 6th delay circuit 322 (6) produces the C1 signal of latch arrays 324 and jointly is connected to the input D of second row (L1, L9, L17, L25, L33, L41, L49 and L57) of latch.The output of the 5th delay circuit 322 (5) produces the C2 signal of latch arrays 324 and jointly is connected to the input D of the third line (L2, L10, L18, L26, L34, L42, L50 and L58) of latch.The output of the 4th delay circuit 322 (4) produces the C3 signal of latch arrays 324 and jointly is connected to the input D of the fourth line (L3, L11, L19, L27, L35, L43, L51 and L59) of latch.The output of the 3rd delay circuit 322 (3) produces the C4 signal of latch arrays 324 and jointly is connected to the input D of the fifth line (L4, L12, L20, L28, L36, L44, L52 and L60) of latch.The output of second delay circuit 322 (2) produces the C5 input signal of latch arrays 324 and jointly is connected to the input D of the 6th row (L5, L13, L21, L29, L37, L45, L53 and L61) of latch.The output of first delay circuit 322 (1) produces the C6 input signal of latch arrays 324 and jointly is connected to the input D of the 7th row (L6, L14, L22, L30, L38, L46, L54 and L62) of latch.Input IN produces the C7 input signal of latch arrays 324 and jointly is connected to the input D of the 8th row (L7, L15, L23, L31, L39, L48, L56 and L64) of latch.

Can understand the delay circuit 322 of demodulator, particularly Figure 12 of Figure 11 and the operation of latch arrays 324 better with reference to oscillogram shown in Figure 13.At Figure 13, uppermost waveform is a serial binary input signal IN part, and a rising edge is shown.Second waveform is represented the rising edge of clock signal of system, and as mentioned above, this signal is the phase place Φ 0 of leggy clock signal of system.Counter 330 (Figure 11) increases its counting at each rising edge of clock signal of system.Embodiment shown in the word after counter 330 values of obtaining 83, and occurs at its rising edge that is increased to serial binary input signal IN before 84.As previously mentioned, delay circuit 322, the combine detection edge of latch circuit 324 and binary decoder 326, and the value that makes latch 328 latch counter 330 when detecting the edge is a condition.

8 following waveforms are represented the multi-phase clock system signal.8 phase intervals of these signal definitions, W0 describes in detail as the front to W7.The serial binary input signal IN that next waveform is bigger decomposition (also provides the signal (C7) to latch circuit 324.Rising edge appears in about 3/4 o'clock by phase intervals W5.

In operation, each in the delay circuit 322 (x) is designed to provide the fixed delay of one 1/64 clock signal of system.The combination of serial binary input signal IN by delay circuit 322 (1) to 322 (7) is to form one group of inhibit signal C0 to C7.Latch L0 distinguishes received signal C0 to C7 to L7, and by phase place Φ 1 signal timing.Like this, latch L0 to L7 at the rising edge latch signal C0 of phase place Φ 1 signal to C7, and produce latch signal at output Q0 to Q7 respectively.At the waveform that illustrates, these signals all are logic ' 0 ' signals.Latch L8 by phase place Φ 2 signal timing, and latchs 8 inhibit signal C0 to C7 at the rising edge of phase place Φ 2 signals to L15, and produces the latch signal (not shown) at output Q8 to Q15 respectively, and the like.Specifically be expressed as, latch L40 is latched in 8 inhibit signal C0 that the rising edge of phase place Φ 6 signals receives to C7 to L47, and respectively at output Q40 to Q47 generation latch signal.Below these sample values will be discussed.Latch 56 to L63 is latched in 8 inhibit signal C0 that the rising edge of phase place Φ 0 signal receives to C7, and respectively at output Q40 to Q47 generation latch signal.These signals all are logics ' 1 '.

At Figure 13 the C7 signal is represented by a thick line.Represent C6 to the C0 signal by the fine rule of Figure 13, be delayed 1/64 system clock cycle with respect to each signal of signal of front.At the rising edge of phase place Φ 6 signals, the rising edge of serial binary input signal IN has appearred, and this serial binary input signal IN is the C7 signal.Like this, the C7 signal is logic ' a 1 ' signal.Like this, receive latch L47 latching logic ' 1 ' signal of C7 signal, and be produced as the Q47 output signal of logic ' 1 ' signal.Similarly, at the rising edge of phase place Φ 6 signals, the rising edge of C2 and C6 signal has appearred.Like this, receive the latch L46 and L45 latching logic ' 1 ' signal of C6 and C5 inhibit signal, and be produced as the Q46 and the Q45 output signal of logic ' 1 ' signal respectively.

On the contrary, also do not produce phase place Φ 6 signal rising edges, the C4 inhibit signal of C4 inhibit signal rising edge.Like this, receive the latch L44 of C4 inhibit signal, latch logic ' a 0 ' signal, and be produced as the Q44 output signal of logic ' 0 ' signal.Similarly, at phase place Φ 6 signal rising edges, still also do not produce the rising edge of C0 and C3 signal.Like this, receive latch L43 and the L40 of C3, latch logic ' a 0 ' signal, and be produced as the Q43 and the Q40 output signal of logic ' 0 ' signal respectively to the C0 inhibit signal.

Binary coder 326 handle Q0 to the Q63 signal with the detection edge.If all Q0 to the logical value of Q63 signal identical (that is, perhaps be full logic ' 1 ' signal or entirely for logic ' 0 ' signal), then detect boundless edge.Here it is, and the counting of the system clock time interval in counter 330 is 83 o'clock the situation of system clock before or after the time interval.With reference to uppermost three oscillograms in Figure 13, in the preceding system clock time interval, Q0 is logic ' a 0 ' signal and in the back system clock time interval, Q0 is logic ' a 1 ' signal to the Q63 signal entirely to the Q63 signal entirely.In this case, at the output terminal of clock of binary coder 326 clocking not.

Yet,, detect an edge by binary coder 326 if two adjacent Q signals have different logical values.In the oscillogram shown in Figure 13, have at counter during the system clock time interval of value 83, signal Q44 has logic ' 0 ' value and signal Q45 has logic ' 1 ' value.This represents a rising edge.In a similar fashion, signal Qn+1 has logic ' 0 ' value if signal Qn has logic ' 1 ' value, then detects a trailing edge.In either case, the multidigit binary signal that will just be in the value with Q signal number before the variation of logical value by binary coder 326 offers register 328 and clock signal is offered register 328.

Embodiment is being shown, and the 6-position binary signal that will have value 44 offers register 328.Response is from the clock signal of binary coder 326, the value of register 328 storage counters 330 (expression detect backmost along after the complete clock periodicity) and from the value (fractional part of the position, edge in the expression present clock period cycle) of encoder 326.At the embodiment that illustrates, be output as 15 position digital signals from register 328.At a preferred embodiment, register 328 is operated with the method for synchronization, in input end of clock receiving system clock signal, and the clock output signal that enables input from depositing of binary coder 326.

Person of skill in the art will appreciate that can be by the different edge measuring ability (Qn  Qn+1) that provides in the binary coder 326 of Qn and Qn+1 be provided for all n.If for all n (Qn  Qn+1)=0 (that is), then detect boundless edge and do not produce the clock signal that is used for register 328 if all signals have identical logical value.If for all n (Qn  Qn+1)=1 (that is, Qn is different with Qn+1), then binary coder 326 produces a n value and produces the clock signal that is used for register 328 at data output end.

At the embodiment that illustrates, 8 inhibit signals are offered the register of 8 corresponding lines, and 8 row of register receive from 8 respective phase signal of leggy system clock and detect and decompose to produce 1/64 of a system clock cycle.The configuration that person of skill in the art will appreciate that other is possible.For example, 16 delay circuits that 1/128 of the display system clock cycle is postponed offer the register of corresponding line, and 8 row of register receive from 8 respective phase signal of leggy system clock and detect and decompose to produce 1/128 of a system clock cycle.Perhaps, 8 delay circuits that 1/128 of the display system clock cycle is postponed offer the register of 8 corresponding lines, and 16 row of register receive from 16 respective phase signal of leggy system clock and detect and decompose to produce 1/128 of a system clock cycle.Perhaps, 16 delay circuits that 1/256 of the display system clock cycle is postponed offer the register of 16 corresponding lines, and 16 row of register receive from 16 respective phase signal of leggy system clock and detect and decompose to produce 1/256 of a system clock cycle.

Detect at each that edge occurs, can be used for other circuit blocks from the edge position data of register 328.For example, at the embodiment that illustrates, the edge position data can offer phase-modulator 26, and this phase-modulator produces one according to these data and recovers the serial binary signal.Also can respond these data and carry out other functions.

Edge position data from register 328 also offers anti-glitch filter 36.As mentioned above, with respect to interpolation filter 22 (Fig. 3), frequency divider 372 and the clock frequency of clock selector 374 co-operations to select one to be used for anti-glitch filter 36 perhaps are the subharmonic of system clock frequency or system clock frequency.As mentioned above, the counter 330 that is connected to system clock provides the clock division function of frequency divider 372.

Selected clock signal from clock selector 374 provides a clock signal that is used for the first and second boxcar filters.At first fixed frquency divider 376, this signal is followed at second fixed frquency divider 394 once more by factor M also by factor M frequency division ₄Frequency division.Clock signal from the first fixed clock frequency divider 376 provides a clock signal that is used for the 3rd boxcar filter, and provides a clock signal that is used for latch 392 from the clock signal of the second fixed clock frequency divider 394.

Anti-glitch filter 36 is by a first order low pass filter and a position expander 362, and the series connection of three boxcar filters 364,366 and 368 constitutes the sample on the average predetermined time window of wherein each.Position expander 362 is embodied as first order LPF.At the embodiment that illustrates, it is embodied as an iir filter with known manner.In addition, expander 362 15 that the figure place in its output signal is obtained from register 328 in position extend to 23.The series connection of operating the first and second boxcar filters 364 and 366 is with on average from M sample of the selected filter clock frequency of clock selector 374.Operate the 3rd boxcar filter 368 with on average by M sample of the selected filter clock frequency of fixed factors M frequency division.From the output signal of the 3rd boxcar filter 368 is low-pass filtered version from one group of edge location data signal of register 328.This filtering prevents that with known manner anti-false factor from occurring during extracting processing.As mentioned above, bucket (barrel) phase shifter 370 phase-shift filtering phase data signals are with the change in gain of explanation by the introducing of low-pass filtering boxcar filter.Latch 392 latchs from output phase signal, wherein a M=M in every M the edge position data sample of register 328 ₃M ₄These output phase data samples offer preprocessor 25 (Fig. 1), and are used as the gating signal of preprocessor 25 to the clock signal of latch 392.

As mentioned above, under the situation of clock output signal synthesizer, might share with pre-preprocessor 5, perhaps under the situation of serial binary input signal analyzer, use preprocessor 25 for some signal processing discussed above.Figure 14 is the more detailed block diagram of the anti-false filter 36 shown in Figure 11, although the technology shown in Figure 14 can be used for the interpolation filter shown in Fig. 3 equally.

Figure 14 is made up of four block diagrams of the corresponding configuration of the anti-glitch filter 36 of Figure 11.Figure 14 a is the simplified block diagram of the anti-glitch filter 36 shown in Figure 11.At Figure 14 a, the first, the second and the 3rd boxcar filter 364,366 and 368 be connected in series between location data signal source, edge and the latch 392.The first and second boxcar filters, 364 and 366 by baud F _BAUDThe clock signal timing at place.The 3rd boxcar filter 368 is by baud F _BAUDThe clock signal timing at/M place.Latch 392 is by baud F _BAUThe clock signal timing at/M place, wherein M=M _AM ₄, this clock signal also is a gating signal.

Just as is known, average function can be considered to accumulate the combination of function, and the accumulation function is a relative high speed operation, and the difference function is considered to relative low-speed handing.Figure 14 b illustrates the first, the second and the 3rd boxcar filter that is decomposed into the series connection of accumulator and difference engine with known manner, each in 364,366 and 368.First boxcar 364 comprises the series connection of accumulator 42 and difference engine 44; Second boxcar 366 comprises the series connection of accumulator 62 and difference engine 64; The 3rd boxcar 368 comprises the series connection of accumulator 82 and difference engine 84.Because add up and difference processing be linear process, accumulator 42,62 and 82 and difference engine 44,64 and 84 can be with the series connection of any order.

Figure 14 c is a different configuration, and wherein three accumulators 42,62 and 82 are connected to three difference engines 44 ', 64 ' and 84 '.At Figure 14 c, first and second accumulators 42 and 62 are by baud F _BAUDThe clock signal timing, the 3rd accumulator 82 is by F _BAUD/ M ₃The clock signal timing of ratio.Three difference engines 44 ', 64 ' and 84 ' are all by F _BAUD/ M ₃The clock signal timing of ratio.

Figure 14 d is another configuration, and wherein register 392 is positioned at three accumulators 42,62 and 82 and three difference engines 44 ", 64 " and 84 " between.At Figure 14 d, register 392 and three difference engines 44 ", 64 " and 84 " all by F _BAUDThe clock signal timing of/M ratio.This is configured in signal processing end of chain (EOC) time-division group difference engine circuit 44 ", 64 " and 84 ", signal processing chain is at the F of relative low speed _BAUD/ M operation.At the embodiment that illustrates, in the semiconductor chip that comprises system 10, constitute three accumulators 42,62 and 82, and register 392, and difference engine 44 ", 64 " and 84 " be formed in chip exterior, and be in the preprocessor 25 of Figure 11.

Boxcar filter

234 and 226 in the interpolation filter 22 shown in Fig. 3 can be decomposed into accumulator and difference engine similarly and reconfigure, so difference engine can be in the integrated circuit (IC) chip outside constituting in the preprocessor 5 in advance.The disclosed this processing of the application reconfigures and does not change above-mentioned functions, but relative low-speed processing is shifted out chip.Reduced the circuit that must in integrated circuit (IC) chip, constitute.This has just reduced such chip, and the cost that uses any product of such chip.

The interpolation filter 22 of Fig. 3 and the anti-glitch filter 36 of Figure 11 are compared, share a lot of identical parts at these two filters as can be seen.For example, PLL14, Clock dividers (232 and 372), clock selector (234 and 374), first fixed frquency divider (236 and 376) and second fixed frquency divider (238 and 394) appear at interpolation filter 22 and anti-glitch filter 36.Remainder: the first boxcar filter (224 and 364), second boxcar filter (226 and 366) and the 3rd boxcar filter 368; Position expander (230 and 362); Bucket phase shifter (228 and 370); And latch (222 and 392); Can use and well known to a person skilled in the art that any way is electrically connected by the suitable output that data and input end of clock is switched to corresponding miscellaneous part.Similarly, the input of phase-modulator 26 can be when system operation is a clock signal synthesizer be outputted to the output of the phase demodulator 32 when system operation is a clock signal analyzer from interpolater 22.With reference to Fig. 1, carry out the control operation pattern through control interface 12 by the control signal that is provided to system 10 from the system controller (not shown).Control interface 12 can be provided to switching part with appropriate control signals so that connect the parts that illustrate in the mode that requires.

Aforesaid serial binary signal synthesizer and fixed frequency system clock synchronization ground receiving phase is represented data, and serial binary signal analyzer and fixed frequency system clock synchronization real estate looks bit representation data.Synchronously such system operatively is easy to the part as measuring instrument.In addition, be easy to design and be embodied as necessary digital filtering in interpolation filter and the such system of anti-glitch filter.Further, be appreciated that under the situation that does not need clock recovery circuitry separately, the serial binary signal analyzer can be handled the digital signal that the edge wherein occurs or do not occur.

Claims

1. clock output signal synthesizer comprises:

A preprocessor (5) is used to provide the phase data of the predetermined phase characteristic that shows a clock output signal,

An interpolater that links to each other with described preprocessor is used to receive the phase data of the predetermined phase characteristic that shows a clock output signal, and described phase data and clock signal of system are synchronous, and responds described phase data and produce the edge configuration data signals; With

A phase-modulator is connected to described interpolater, is used for producing the clock output signal with the edge that is placed on the time of being determined by each described edge configuration data signals according to described clock signal of system.

2. serial binary input signal analyzer comprises:

A phase demodulator is used to receive a serial binary input signal, produces the marginal position data-signal that changes between the state of the described serial binary input signal of expression continuously; With

A withdrawal device is connected to described phase demodulator by an anti-glitch filter, is used for synchronously producing phase data signal from described marginal position data-signal with clock signal of system.

3. analyzer as claimed in claim 2, further comprise a phase-modulator, be connected to phase demodulator, to produce one from edge configuration data signals clock recovered output signal, described clock recovered output signal has the phase place identical with the serial binary input signal.

4. clock system comprises:

A clock signal of system source;

A control unit interface;

A phase-modulator; With

A phase demodulator;

A configurable filter receives described clock signal of system from described signal source, and receives instruction from described control unit interface, and described configurable filter also links to each other with described phase demodulator with described phase-modulator; Wherein

This system is configured to respond the instruction from described control unit interface, with first operation mode, wherein:

With described configurable filter configuration is as an interpolater, be used to receive the phase data of the predetermined phase characteristic that shows a clock output signal, described phase data and clock signal of system are synchronous, and respond described phase data generation edge configuration data signals; With

Described phase-modulator links to each other with described configurable filter, be used to receive described edge configuration data signals, produce clock output signal according to described clock signal of system with the edge that is placed on the time of determining by each described edge configuration data signals;

This system is configured to respond the instruction from described control unit interface, with second operation mode, wherein:

Described phase demodulator is used to receive a serial binary input signal, according to described clock signal of system, produces the marginal position data-signal of the state-transition of the described serial binary input signal of expression continuously; With

Described configurable filter is configured to an anti-glitch filter/withdrawal device, link to each other with described phase demodulator, be used to receive described marginal position data-signal, synchronously produce phase data signal from described marginal position data-signal with described clock signal of system.

5. system as claimed in claim 4, wherein at second configuration mode, phase-modulator is connected to phase demodulator, and to produce one from edge configuration data signals clock recovered output signal, described clock recovered output signal has the phase place identical with the serial binary input signal.