CN1603853A - Method for constructing two-stage sweep test structure with low test power dissipation - Google Patents
Method for constructing two-stage sweep test structure with low test power dissipation Download PDFInfo
- Publication number
- CN1603853A CN1603853A CN 200410088881 CN200410088881A CN1603853A CN 1603853 A CN1603853 A CN 1603853A CN 200410088881 CN200410088881 CN 200410088881 CN 200410088881 A CN200410088881 A CN 200410088881A CN 1603853 A CN1603853 A CN 1603853A
- Authority
- CN
- China
- Prior art keywords
- unit
- timing unit
- conv
- scanning sequence
- clk
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000012360 testing method Methods 0.000 title claims description 64
- 238000000151 deposition Methods 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract 1
- 238000000691 measurement method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 239000002131 composite material Substances 0.000 description 5
- 238000013461 design Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 101100113692 Caenorhabditis elegans clk-2 gene Proteins 0.000 description 1
- 101100003180 Colletotrichum lindemuthianum ATG1 gene Proteins 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000013144 data compression Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
It is a method to form a two-step scanner structure with low power consumption and belongs to integration circuit measurement technique field. The method is characterized by the following: first to get a form judging whether there is common composition relay between any two time sequences from circuit net single file; to classify the units into groups according to the form; to alter all the time sequence units into scanning time sequence unit; to select one scanning sequence unit from each group to form a scanning chain connected to the time signal clk#-[1] and the rest scanning time sequence units is classified into small groups connected to the time signal clk#-[2].
Description
Technical field
The invention belongs to integrated circuit Testability Design technical field
Background technology
At first, introduce background knowledge and related definition:
Composite door: value and the clock signal of the output signal line of door is irrelevant, and such door is called composite door, the type of composite door comprise not gate, with or door, Sheffer stroke gate, rejection gate, XOR gate, biconditional gate etc.
The sequential door: the value of the output signal line of door is relevant with clock signal, and such door is called the sequential door, is also referred to as timing unit.The input of sequential door has logic input and clock input, is output as logic output.Usually when the rising edge of clock input signal or negative edge arrive, read in the value of logic input signal, thereby produce the value of respective logic output signal.
Make up follow-up: in circuit structure, the output signal line of composite door is that the combination of input signal cable of this composite door is follow-up.Making up follow-up relation can iteration.For example among Fig. 1, d is that the combination of a is follow-up, and e is that the combination of d is follow-up, and that e also is the combination of a is follow-up.
Directly combination is follow-up: adjacent combination is follow-up, and to be called direct combination follow-up.For example among Fig. 1, d is that the direct combination of a is follow-up, but that e is not the direct combination of a is follow-up.
Common combination is follow-up: for example among Fig. 1, e is that the combination of a is follow-up, and e also is that the combination of c is follow-up, and then a and c have the follow-up e of common combination.
Test: the method that after Chip Packaging, chip quality is detected.Owing to can't directly visit the internal circuit of chip after the Chip Packaging, therefore the method that the test of chip is adopted is the input end built-in test vector at chip, and collects test response at chip output.Real income test response and the deserved test response of non-fault circuit are compared, thereby judge that chip circuit has non-fault.
Test generation problem: for the fault that may exist in the circuit, searching can detect the test vector of this fault, and this problem is called test generation problem.
Sweep test: sweep test is to generate the complex nature of the problem for reducing sequential circuit testing, circuit is carried out a kind of method of Testability Design.This method is divided into timing unit and two parts of combinational logic with sequential circuit, as shown in Figure 2, add MUX then and transform timing unit as the scanning sequence unit, a plurality of scanning sequences unit is connected to become scan chain from beginning to end, drive by a scanning input scan-in, be connected to a scanning output scan-out at last, as shown in Figure 3.When signal test was 0, MUX gating combinational logic was normal operating conditions; When signal test is 1, MUX gated sweep chain, circuit enters the sweep test state.
The scanning sequence unit: the timing unit that utilizes the method house of correction of sweep test to get, such as MUX among Fig. 3 and the common structure of forming of timing unit.
Scan chain (scan chain): the sweep test structure (Fig. 4) that is formed by connecting from beginning to end by a plurality of scanning sequences unit.The length of scan chain is the number that comprises the scanning sequence unit in the scan chain.
Testing power consumption: the testing power consumption that produces when circuit is tested mainly result from circuit internal signal wire occurrence logic value upset (logical one-＞logical zero, logical zero-＞logical one).In the sweep test structure, testing power consumption mainly results from inserting of test vector and shifting out in the process of test response, the upset of the timing unit of circuit and its follow-up assembled unit occurrence logic value.
The way that in the past reduced the sweep test power consumption mainly contains: sort to test vector (1); (2) timing unit is sorted; (3) add steering logic in the back of timing unit, make test vector insert in the process, the upset of logical value only occurs in timing unit, can not propagate in the follow-up combinational logic; (4) test vector is carried out encoding and decoding; (5) introduce the additional logic structure, make that the logic upset only occurred in the part timing unit when test vector was inserted.
Method (1) (2) (5) has just reduced testing power consumption, test duration does not reduce, the additional logic that method (3) (5) is introduced is brought certain area overhead, and circuit performance is descended to some extent, what method (4) then was primarily aimed at is the problem of data volume, can be so that power consumption decreases in data compression.
Summary of the invention
The present invention adopts two-stage sweep test structure, and the scanning sequence dividing elements is arrived different clock zones.The scanning sequence unit of the first order constitutes traditional scan chain architecture, and its clock input signal is clk
1Partial scanning sequence unit is divided into a plurality of groups, and its clock input signal is clk
2, the logic input of each scanning sequence unit group is connected to the logic output of a scanning sequence unit in the first order.
If the scanning sequence unit G of group in the second level
iComprise scanning sequence unit g
1' g
2' ... g
n', G
iIn the logic input of each scanning sequence unit be connected to scanning sequence unit f in the first order
i' logic output, scanning sequence unit g then
1' g
2' ... g
n' f
i' pairing timing unit g
1g
2G
nf
iShould meet the following conditions: wherein any two timing units all do not have identical combination follow-up in circuit structure.
In built-in test when vector, at first corresponding test vector is presented in the scan chain by scan input end, establishing scan chain length is l, then a test vector being presented in the scan chain of the first order needs l clk
1Clock period, because the first order is controlled by different clock input signals with partial scanning sequence unit, the partial scanning sequence of this process unit does not overturn.Next, the logic output valve with each scanning sequence unit in the first order is presented in the corresponding partial scanning sequence unit group clk of needs
2Clock period, the scanning sequence unit of the first order does not overturn in this process.
According to the information of circuit structure, after timing unit divided into groups, most of timing unit can be divided into the second level.Insert in the process of scan chain at test vector, have only the scanning sequence unit in the first order scan chain to overturn, the upset number of times is largely reduced; And the scanning sequence unit that test vector is inserted in the second level only needs a clock period, and the upset number of times is also largely reduced, thereby has reduced the sweep test power consumption.
The invention is characterized in: it contains following steps successively:
The 1st step: initialization,, adopt N*N form conv[N to computing machine input circuit netlist file] [N] write down the mutual relationship of timing unit on circuit structure, and wherein N is the sum of timing unit; If for i ≠ j, i ∈ [1, N], timing unit i and the timing unit j of j ∈ [1, N], i and j have common combination follow-up on circuit structure, then conv[i] [j]=conv[j] [i]=1, otherwise conv[i] [j]=conv[j] [i]=0;
The 1.1st step: set up conv[N] [N] form;
The 1.1.1 step: for all timing units in the circuit, output signal line corresponding identification in circuit of establishing timing unit i is iOut, with the follow-up array successor_of_iOut[that deposits in successively of the combination of timing unit i] in,
Method is as follows: at first with the follow-up i of direct combination of timing unit i
1i
2I
NDeposit in the array, then successively with i
1i
2I
nFollow-up also the depositing in the array of direct combination, till the unit that deposits array in has been a timing unit or original output;
1.1.2 step: for any two timing unit i and j, if successor_of_iOut[] and successor_of_jOut[] in same unit is arranged, conv[i then] [j]=conv[j] [i]=1; Otherwise conv[i] [j]=conv[j] [i]=0;
The 2nd step: according to N*N form conv[N] [N] divide into groups to timing unit;
The 2.1st step: the set of establishing timing unit is F, and each group is respectively G
1G
2G
n
The 2.2nd step:, otherwise carried out for the 2.4th step if the F non-NULL then carried out for the 2.3rd step;
The 2.3rd step: set up new group G
m, m ∈ [1, n] appoints a timing unit g who gets among the F to put into G
m, among the traversal F
Remaining timing unit is if certain sequential unit f satisfies g ∈ G
m, conv[f] and [g]=0, then f is put into G
m, upgrade F and G
m, continue remaining timing unit among the traversal F; Traversal finishes the back and changeed for the 2.2nd step;
The 2.4th step: grouping finishes
The 3rd step:, the 2nd step gained group result is adjusted for making grouping evenly;
The 3.1st step: from G
1G
2G
nIn select maximum group G
MaxWith smallest group G
Min, G
MaxBe the maximum group of contained timing unit quantity, G
MinIt is the group of contained timing unit minimum number;
The 3.2nd step: from G
MaxIn select the g ∈ G that satisfies condition
Min, conv[f] and the timing unit f of [g]=0, put into G with f
Min, upgrade G
MaxAnd G
Min
The 3.3rd step: carry out the 3.1st step and the 3.2nd step repeatedly, up to G
MaxWith G
MinSize to differ be 1 or G
MaxIn can not find the g ∈ G that satisfies condition
Min, conv[f] and till the timing unit f of [g]=0;
The 4th step: according to adjusting later group result G
1G
2G
nConstruct the two-stage sweep test structure of low testing power consumption
The 4.1st step: before each timing unit, add MUX MUX respectively, transform the scanning sequence unit as;
The 4.2nd step: from G
1G
2G
nIn respectively select a scanning sequence unit g
1' g
2' ... g
n', constitute a scan chain, scanning sequence unit g
1' g
2' ... g
n' clock input be connected to clock signal clk
1
The 4.3rd step: G
1G
2G
nIn the clock input of remaining scanning sequence unit be connected to clock signal clk
2
The 4.4th step: with G
1In the logic input of remaining scanning sequence unit be connected to scanning sequence unit g
1' logic output, with G
2In the logic input of remaining scanning sequence unit be connected to scanning sequence unit g
2' logic output, by that analogy, with G
nIn the logic input of remaining scanning sequence unit be connected to scanning sequence unit g
n' logic output;
The 4.5th step: clock signal clk is connected respectively to two inputs and door AND
1And AND
2Input end, control signal C
1And C
2Be connected respectively to AND
1And AND
2Another input end, clk
1And clk
2Be respectively AND
1And AND
2Output; Work as C
1=1 and C
2=0 o'clock, clk
1Effectively and clk
2Invalid; Work as C
1=0 and C
2=1 o'clock, clk
1Invalid and clk
2Effectively.(as Fig. 5)
Use proof:
Experiment porch is a SUN BLADE2000 workstation, and the test patterns generator that adopts in the experiment is ATALANTA, and fault simulator is HOPE.Provided the experimental result that the present invention is applied to a part of ISCAS89 and ITC99 circuit in the table 1, Full Scan is the experimental result that strand scans fully in the table, Two Stage Scan is an experimental result of the present invention, FC (Fault Coverage) represents fault coverage, the difficult number of faults of surveying of #HF (Hard Fault) expression, the test average power consumption that #VEC (Vector) expression test vector number, TP (Test Power) and PTP (Peak Test Power) are represented test average power consumption of the present invention respectively and tested peak power and the complete sweep test structure of strand with test peak power and compare shared number percent.
As can be seen from Table 1, adopt two-stage sweep test structure of the present invention, can be when guaranteeing that this constant and difficult survey number of faults of original fault coverage and test vector base does not increase, make test average power consumption and test peak power and all reduced significantly.
Table 1: the experimental result that the present invention is applied to ISCAS89 and ITC99 circuit
| Circuit name | Strand scans fully | The present invention | |||||||
| FC | #HF | #VEC | ?FC | #HF | #VEC | ?TP(％) | PTP(％) | ||
| ISCAS89 | ?S9234 | ?93.48 | ?452 | ?371 | ?93.61 | ?452 | ?365 | ?1.22 | ?1.40 |
| ?S9234.1 | ?93.48 | ?452 | ?376 | ?93.66 | ?452 | ?376 | ?1.13 | ?1.24 | |
| ?S13207 | ?98.46 | ?151 | ?466 | ?98.51 | ?151 | ?466 | ?0.51 | ?0.46 | |
| ?S13207.1 | ?98.46 | ?151 | ?486 | ?98.51 | ?151 | ?468 | ?0.32 | ?0.35 | |
| ?S15850 | ?96.68 | ?389 | ?436 | ?96.74 | ?389 | ?428 | ?0.56 | ?0.52 | |
| ?S15850.1 | ?96.68 | ?389 | ?434 | ?96.75 | ?389 | ?420 | ?0.38 | ?0.36 | |
| ?S38417 | ?99.47 | ?165 | ?899 | ?99.47 | ?165 | ?854 | ?0.08 | ?0.10 | |
| ?S38584 | ?95.85 | ?1506 | ?651 | ?95.84 | ?1506 | ?648 | ?0.14 | ?0.13 | |
| ?S38584.1 | ?95.85 | ?1506 | ?655 | ?95.89 | ?1506 | ?651 | ?0.11 | ?0.11 | |
| ?ITC99 | ?B17 | ?97.01 | ?2293 | ?2301 | ?97.15 | ?2207 | ?2321 | ?0.20 | ?0.21 |
| ?B18 | ?96.11 | ?7334 | ?2944 | ?96.19 | ?7220 | ?2879 | ?0.12 | ?0.11 | |
Description of drawings
Fig. 1: make up follow-up synoptic diagram.
Fig. 2: sequential circuit synoptic diagram.
Fig. 3: sequential circuit is carried out the sweep test synoptic diagram.
Fig. 4: scan chain synoptic diagram.
Fig. 5: clock signal clk1 and clk2 synoptic diagram
Fig. 6: circuit diagram.
Fig. 7: form conv[12] [12].
Fig. 8: two-stage sweep test structural representation.
Fig. 9: structure has the program flow chart of the two-stage sweep test structure of low testing power consumption.
Embodiment
The embodiment of said method is described by object lesson respectively below.
Example 1: circuit as shown in Figure 6, timing unit wherein adds up to 3, the output signal line of timing unit 1 is designated 1Out=5 in circuit, the output signal line of timing unit 2 is designated 2Out=6 in circuit, the output signal line of timing unit 3 is designated 3Out=7 in circuit, adopt array successor_of_5[], successor_of_6[] and successor_of_7[] store timing unit 1,2 and 3 respectively combination follow-up.
Set up form conv[3] process of [3] is as follows:
1) for the timing unit in the circuit 1,1Out=5,5 have only one, and directly combination is follow-up 15, deposits array successor_of_5[in 15].
17 is the input of timing unit 1, therefore needn't down search for again; 16 have arrived original output, therefore needn't down search for again.Finish.
Like this, array successor_of_5[] in the storage content be: 15,17,16; In like manner, array successor_of_6[] in the storage content be: 10,13,12,14,15,17,16; Array successor_of_7[] in the storage content be: 9,11,12,14,15,17,16.
2) timing unit 1 and 2 has common combination follow-up 15, so conv[1] [2]=conv[2] [1]=1;
Example 2: in certain circuit timing unit add up to 12, gather and be F, provided the form conv[12 that represents the mutual relationship of these timing units on circuit structure among Fig. 7] [12].
According to form conv[12] [12] as follows to the situation that timing unit divides into groups:
Set up new group G
1, timing unit 1 is put into G
1, G
1={ 1}; Remaining timing unit among the traversal F is found timing unit 2 conv[2 that satisfies condition] [1]=0, g ∈ G also promptly satisfies condition
1, conv[2] and [g]=0, therefore timing unit 2 is put into G
1, G
1=1,2}; Remaining timing unit among the traversal F is found timing unit 4 conv[4 that satisfies condition] [1]=0 and conv[4] [2]=0, g ∈ G also promptly satisfies condition
1, conv[4] and [g]=0, therefore timing unit 4 is put into G
1, G
1=1,2,4}; Remaining timing unit among the traversal F is found timing unit 7 conv[7 that satisfies condition] [1]=0 and conv[7] [2]=0 and conv[7] [4]=0, g ∈ G also promptly satisfies condition
1, conv[7] and [g]=0, therefore timing unit 7 is put into G
1, G
1=1,2,4,7}; Remaining timing unit among the traversal F is found timing unit 10 conv[10 that satisfies condition] [1]=0 and conv[10] [2]=0 and conv[10] [4]=0 and conv[10] [7]=0, g ∈ G also promptly satisfies condition
1, conv[10] and [g]=0, therefore timing unit 10 is put into G
1, G
1=1,2,4,7,10}.By that analogy, obtain G
2=3,11,12}, G
3=5,6,8,9}.Grouping finishes.
According to form conv[12] [12] situation that above group result is adjusted is as follows:
Select maximum group G
Max=G1, smallest group G
Min=G2 is from G
MaxIn select timing unit 2 conv[2 that satisfies condition] [3]=0 and conv[2] [11]=0 and conv[2] [12]=0, g ∈ G also promptly satisfies condition
Min, conv[2] and [g]=0, therefore timing unit 2 is put into G
2So, G
1=1,4,7,10}, G
2=2,3,11,12}, G
3=5,6,8,9}.Satisfied the uniform condition of grouping this moment, adjusts and finish.
The situation of constructing the two-stage Scan Architecture with low testing power consumption according to adjusted group result is as follows:
Before each timing unit, add MUX MUX respectively, transform the scanning sequence unit as; According to adjusted group result, from each group G
1, G
2, G
3In select a scanning sequence unit 1 ', 2 ', 5 ' respectively and constitute a scan chain, scanning sequence unit 1 ', 2 ', 5 ' clock input are connected to clock signal clk
1The clock input of each group residue timing unit is connected to clock signal clk
2: G
1The logic input of middle residue timing unit is connected to the logic output of scanning sequence unit 1 ', G
2The logic input of middle residue timing unit is connected to the logic output of scanning sequence unit 2 ', G
3The logic input of middle residue timing unit is connected to the logic output of scanning sequence unit 5 '; Clock signal clk
1And clk
2Add that by same clock signal clk two control signals produce with door by two, as shown in Figure 5; Finish.
Claims (1)
1. structure has the method for the two-stage sweep test structure of low testing power consumption, it is characterized in that: it contains following steps successively: the 1st step: initialization, to computing machine input circuit netlist file, adopt N*N form conv[N] [N] write down the mutual relationship of timing unit on circuit structure, and wherein N is the sum of timing unit; If for i ≠ j, i ∈ [1, N], timing unit i and the timing unit j of j ∈ [1, N], i and j have common combination follow-up on circuit structure, then conv[i] [j]=conv[j] [i]=1, otherwise conv[i] [j]=conv[j] [i]=0;
The 1.1st step: set up conv[N] [N] form;
The 1.1.1 step: for all timing units in the circuit, if the output signal line of timing unit i corresponding identification in circuit is iOut, with the follow-up array successor_of_iOut[that deposits in successively of the combination of timing unit i] in, method is as follows: at first with the follow-up i of direct combination of timing unit i
1i
2I
nDeposit in the array, then successively with i
1i
2I
nFollow-up also the depositing in the array of direct combination, till the unit that deposits array in has been a timing unit or original output;
1.1.2 step: for any two timing unit i and j, if successor_of_iOut[] and successor_of_jOut[] in same unit is arranged, conv[i then] [j]=conv[j] [i]=1; Otherwise conv[i] [j]=conv[j] [i]=0;
The 2nd step: according to N*N form conv[N] [N] divide into groups to timing unit;
The 2.1st step: the set of establishing timing unit is F, and each group is respectively G
1G
2G
n
The 2.2nd step:, otherwise carried out for the 2.4th step if the F non-NULL then carried out for the 2.3rd step;
The 2.3rd step: set up new group G
m, m ∈ [1, n] appoints a timing unit g who gets among the F to put into G
m, remaining timing unit among the traversal F is if certain sequential unit f satisfies g ∈ G
m, conv[f] and [g]=0, then f is put into G
m, upgrade F and G
m, continue remaining timing unit among the traversal F; Traversal finishes the back and changeed for the 2.2nd step;
The 2.4th step: grouping finishes
The 3rd step:, the 2nd step gained group result is adjusted for making grouping evenly;
The 3.1st step: from G
1G
2G
nIn select maximum group G
MaxWith smallest group G
Min, G
MaxBe the maximum group of contained timing unit quantity, G
MinIt is the group of contained timing unit minimum number;
The 3.2nd step: from G
MaxIn select the g ∈ G that satisfies condition
Min, conv[f] and the timing unit f of [g]=0, put into G with f
Min, upgrade G
MaxAnd G
Min
The 3.3rd step: carry out the 3.1st step and the 3.2nd step repeatedly, up to G
MaxWith G
MinSize to differ be 1 or G
MaxIn can not find the g ∈ G that satisfies condition
Min, conv[f] and till the timing unit f of [g]=0;
The 4th step: according to adjusting later group result G
1G
2G
nConstruct the two-stage sweep test structure of low testing power consumption
The 4.1st step: before each timing unit, add MUX MUX respectively, transform the scanning sequence unit as;
The 4.2nd step: from G
1G
2G
nIn respectively select a scanning sequence unit g
1' g
2' ... g
n', constitute a scan chain, scanning sequence unit g
1' g
2' ... g
n' clock input be connected to clock signal clk
1
The 4.3rd step: G
1G
2G
nIn the clock input of remaining scanning sequence unit be connected to clock signal clk
2
The 4.4th step: with G
1In the logic input of remaining scanning sequence unit be connected to scanning sequence unit g
1' logic output, with G
2In the logic input of remaining scanning sequence unit be connected to scanning sequence unit g
2' logic output, by that analogy, with G
nIn the logic input of remaining scanning sequence unit be connected to scanning sequence unit g
n' logic output;
The 4.5th step: clock signal clk is connected respectively to two inputs and door AND
1And AND
2Input end, control signal C
1And C
2Be connected respectively to AND
1And AND
2Another input end, clk
1And clk
2Be respectively AND
1And AND
2Output; Work as C
1=1 and C
2=0 o'clock, clk
1Effectively and clk
2Invalid; Work as C
1=0 and C
2=1 o'clock, clk
1Invalid and clk
2Effectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100888813A CN100417950C (en) | 2004-11-08 | 2004-11-08 | Method for constructing two-stage sweep test structure with low test power dissipation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100888813A CN100417950C (en) | 2004-11-08 | 2004-11-08 | Method for constructing two-stage sweep test structure with low test power dissipation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1603853A true CN1603853A (en) | 2005-04-06 |
| CN100417950C CN100417950C (en) | 2008-09-10 |
Family
ID=34667180
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100888813A Expired - Fee Related CN100417950C (en) | 2004-11-08 | 2004-11-08 | Method for constructing two-stage sweep test structure with low test power dissipation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100417950C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102323539A (en) * | 2011-07-29 | 2012-01-18 | 清华大学 | Method for generating delay fault test vector set |
| CN104569790A (en) * | 2015-01-28 | 2015-04-29 | 清华大学 | Thermal-driving testability design structure and method capable of reducing small delay defect over-testing |
| CN105807206A (en) * | 2016-03-11 | 2016-07-27 | 福州瑞芯微电子股份有限公司 | Chip test clock circuit and test method thereof |
| CN107966645A (en) * | 2017-11-15 | 2018-04-27 | 北京物芯科技有限责任公司 | A kind of temporal constraint method and device of the sweep test of integrated circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3981281B2 (en) * | 2002-02-14 | 2007-09-26 | 松下電器産業株式会社 | Semiconductor integrated circuit design method and test method |
| CN1267739C (en) * | 2002-12-30 | 2006-08-02 | 清华大学 | Scanning design with nano-scanning design test cost and test vector input method |
-
2004
- 2004-11-08 CN CNB2004100888813A patent/CN100417950C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102323539A (en) * | 2011-07-29 | 2012-01-18 | 清华大学 | Method for generating delay fault test vector set |
| CN102323539B (en) * | 2011-07-29 | 2013-06-19 | 清华大学 | Method for generating delay fault test vector set |
| CN104569790A (en) * | 2015-01-28 | 2015-04-29 | 清华大学 | Thermal-driving testability design structure and method capable of reducing small delay defect over-testing |
| CN104569790B (en) * | 2015-01-28 | 2017-05-31 | 清华大学 | Reduce thermal drivers Testability Design structure and method that small delay defects cross test |
| CN105807206A (en) * | 2016-03-11 | 2016-07-27 | 福州瑞芯微电子股份有限公司 | Chip test clock circuit and test method thereof |
| CN107966645A (en) * | 2017-11-15 | 2018-04-27 | 北京物芯科技有限责任公司 | A kind of temporal constraint method and device of the sweep test of integrated circuit |
| CN107966645B (en) * | 2017-11-15 | 2019-11-22 | 北京物芯科技有限责任公司 | A kind of temporal constraint method and device of the sweep test of integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100417950C (en) | 2008-09-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Karnagel et al. | Adaptive work placement for query processing on heterogeneous computing resources | |
| CN111967468A (en) | FPGA-based lightweight target detection neural network implementation method | |
| CN1267739C (en) | Scanning design with nano-scanning design test cost and test vector input method | |
| CN1955945A (en) | Method and device for automatic generating test executive routine sequence of software test process | |
| WO2007109322A2 (en) | Speeding up defect diagnosis techniques | |
| CN1441481A (en) | Design method and detection method for semiconductor integrated circuit | |
| Chang et al. | A memory-optimized and energy-efficient CNN acceleration architecture based on FPGA | |
| CN111767689A (en) | Three-dimensional integrated circuit layout method based on graphic processing | |
| Lin et al. | A high-speed low-cost CNN inference accelerator for depthwise separable convolution | |
| US11175338B2 (en) | System and method for compacting test data in many-core processors | |
| CN1560646A (en) | Quick integrated circuit testing process optimization method | |
| Jiang et al. | A novel stochastic gradient descent algorithm based on grouping over heterogeneous cluster systems for distributed deep learning | |
| Sun et al. | Sense: Model-hardware codesign for accelerating sparse CNNs on systolic arrays | |
| CN1603853A (en) | Method for constructing two-stage sweep test structure with low test power dissipation | |
| CN1452316A (en) | Scanning path circuit and semiconductor IC contg. said scanning path circuit | |
| CN1577284A (en) | Method and apparatus for realizing boundary Scanning test | |
| CN113762480A (en) | Time sequence processing accelerator based on one-dimensional convolutional neural network | |
| CN112001492A (en) | Mixed flow type acceleration framework and acceleration method for binary weight Densenet model | |
| CN107562948A (en) | A kind of printenv multidimensional data clustering method based on distance | |
| CN109583006B (en) | Dynamic optimization method of field programmable gate array convolution layer based on cyclic cutting and rearrangement | |
| CN107742051B (en) | Method for quickly optimizing size of FPGA circuit transistor | |
| CN1641371A (en) | Test method for a semiconductor integrated circuit and a semiconductor integrated circuit | |
| Choi et al. | VLSI processor of parallel genetic algorithm | |
| CN1928578A (en) | Test circuit and test method thereof | |
| CN1560769A (en) | Cmbined circuit equipment checking method based on satisfiability |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080910 Termination date: 20151108 |
|
| EXPY | Termination of patent right or utility model |