CN104569790B - Reduce thermal drivers Testability Design structure and method that small delay defects cross test - Google Patents
Reduce thermal drivers Testability Design structure and method that small delay defects cross test Download PDFInfo
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Abstract
The present invention proposes that a kind of small delay defects of reduction cross the thermal drivers Testability Design structure of test, including：N scanning chain group, wherein, each scanning chain group includes k sub- scan chain, and k sub- scan chain is divided by every original scan chains in circuit and obtained；N demultiplexer DMUX, n DMUX is arranged between n scan input end and the n input of scanning chain group correspondingly；The first multiplexers of n MUX, n MUX are arranged between n scanning output end and the n output end for scanning chain group correspondingly；Control unit, for controlling k sub- scan chain in n scanning chain group to be tested successively.The thermal drivers Testability Design structure that the small delay defects of reduction according to embodiments of the present invention cross test can effectively reduce small delay defects and cross test.
Description
Technical field
It is more particularly to a kind of to reduce the heat drive that small delay defects cross test the present invention relates to ic test technique field
Dynamic Testability Design structure.
Background technology
As semiconductor technology is more and more accurate, the door inside circuit is more and more intensive, jump of the circuit in normal work
Parameter can be more and more, and many times more taller than the number of transitions of normal work of circuit number of transitions in test process, therefore greatly
The unit interval circuit number of transitions of amount can be that the region of many overheats is produced on circuit, referred to as focus (hotspot) region, together
When, the Temperature Distribution for also resulting in circuit is very uneven.Because the number of transitions of circuit is more and more, the power consumption of circuit is also increasingly
Height, and too high circuit power consumption, the testing cost that circuit needs can be caused higher, while the life-span of circuit can be reduced.It is existing above
As can also cause the delay of part path in circuit increases.Therefore, some original trouble-free circuits will be surveyed to there is event by mistake
The circuit of barrier, can so reduce the yield of circuit while can be that cost increases.Problem based on the above, it is necessary to go analysis circuit
In test process, the circuit occurrence cause for failure is surveyed by mistake.
During circuit is test for, due to resistance drop (IR-drop) or overheat, the delay of circuit can increase.
In three-dimensional circuit, the problem of overheat is particularly acute due to the high density of three-dimensional circuit.Temperature buzzer (thermal
Emergency) paths its extra its time that has been delayed over due to overheat relaxes in indication circuit
(slack).Therefore, it is faulted circuit that some original trouble-free circuits will be missed survey, causes to survey phenomenon generation by mistake.
If as soon as paths in circuit relax because the failure in path causes it to be delayed over the given time,
The delay fault of a paths can be produced.Small delay fault (SDD) is due to circuit crosstalk (crosstalk), process deviation
Caused by (process variation) and power supply noise (power supply noise).They can potentially result in circuit
Time of origin failure.The delay of small delay fault can cause that path more long turns into failure path.The saltus step for being sensitized short path is surveyed
Examination vector will not detect small delay fault.Although conventional academia has many circuit temperatures that reduce with analysis power supply noise
Research, for example some scholars reduce circuit temperature by using new test structure, and some scholars are by using an overall situation
Average voltage information estimates resistance drop.But temperature buzzer is not all reduced well, so as to reduce the number of test.
And in order to reduce the consumption of the power/energy in circuit testing procedures, many sweep test structures are also proposed by scholars, then so far
Still neither one is effective untill the present reduces the thermal drivers testability structure that small delay defects cross test.
The content of the invention
It is contemplated that at least solving one of above-mentioned technical problem.
Therefore, it is an object of the invention to propose a kind of can effectively reduce the small delay of reduction that small delay defects cross test
Defect crosses the thermal drivers Testability Design structure of test.
To achieve these goals, embodiment of the invention discloses that a kind of reduce the thermal drivers that small delay defects cross test
Testability Design structure, including：N scanning chain group, wherein, each scanning chain group includes k sub- scan chain, the k son
Scan chain is divided by every original scan chains in circuit and obtained；N demultiplexer DMUX, the n DMUX is one by one
It is arranged in correspondence between the input of n scan input end and the n scanning chain group；N the first multiplexer MUX,
The n MUX is arranged between the output end of n scanning output end and the n scanning chain group correspondingly；And control
Unit, described control unit is connected with described n scanning chain group, the n DMUX and n MUX respectively, for controlling n
K sub- scan chain in individual scanning chain group is tested successively, meanwhile, control the n DMUX to be connect by n scan input end
The test data of receipts is transferred to corresponding sub- scan chain, and controls the n MUX by the test result of corresponding sub- scan chain
Exported by the n scanning output end.
The small delay defects of reduction according to embodiments of the present invention cross the thermal drivers Testability Design structure of test, Ke Yiyou
Effect reduces the thermal drivers Testability Design structure that small delay defects cross test that reduces that small delay defects cross test, while reducing
Power consumption in circuit testing procedures.
In addition, according to the above embodiment of the present invention reduce the thermal drivers Testability Design knot that small delay defects cross test
Structure can also have following additional technical characteristic：
In some instances, described control unit includes：Working condition port switching x, test port test, clock signal
Input port clk, length for k register and n sub-control unit, wherein, the n sub-control unit respectively with the work
Make state port switching x, test port test, clock signal input terminal a mouthful clk to be connected with the register, with according to work shape
The value of state switching signal, test signal, clock signal and the register control individual sub- scan chains of k in n scanning chain group according to
It is secondary to be tested, meanwhile, control the n DMUX that the test data received by n scan input end is transferred into corresponding son
Scan chain, and control the n MUX that the test result of corresponding sub- scan chain is exported by the n scanning output end.
In some instances, the sub-control unit includes：First and door, the described first first input end and institute with door
Working condition port switching x is stated to be connected, wherein, a pair of the second input difference one of the n n of sub-control unit individual first and door
Ground is answered to be connected with 1 to the kth position of the register；Keep bolt, the first input end of the holding bolt and described first
It is connected with the output end of door, the second input connection for keeping bolt keeps signal hold；Second and door, described second with
First input end and the clock signal input terminal a mouthful clk for door is connected, described second and door the second input and the guarantor
The output end for holding bolt is connected；Second multiplexer mux, the mux respectively with the clock signal input terminal mouthful clk, institute
State second to be connected with the output end and the test port test of door, the output end of the second multiplexer mux and institute
N scanning chain group is stated to be connected.
In some instances, wherein, when in circuit test state, the working condition port switching x puts 1, works as place
When circuit working state, the working condition port switching x sets to 0；When in circuit working state, test initiation state and survey
During examination trapped state, 0 is all entered as, the test port test sets to 0, when in shift test data state, the test
Port test puts 1；When in test initiation state and test trapped state, the clock signal input terminal mouthful clk is to described
Reduce the thermal drivers Testability Design structure input clock signal that small delay defects cross test.
In some instances, the original state of the register is the 1st position 1, remaining position 0.
In some instances, each demultiplexer DMUX includes k output end, a pair of the k output end 1
Ground is answered to be connected with the k input of sub- scan chain of corresponding scanning chain group.
In some instances, each output end of each demultiplexer DMUX respectively with corresponding scanning chain group
The many inputs of sub- scan chain in k sub- scan chain are connected.
In some instances, also include：N XOR network, the n XOR network settings are answered in the n the first multichannel
Between output end with device MUX and the n scanning chain group.
Additional aspect of the invention and advantage will be set forth in part in the description, and will partly become from the following description
Obtain substantially, or recognized by practice of the invention.
Brief description of the drawings
Of the invention above-mentioned and/or additional aspect and advantage will become from description of the accompanying drawings below to embodiment is combined
Substantially and be readily appreciated that, wherein：
Fig. 1 is the thermal drivers Testability Design knot that the small delay defects of reduction according to an embodiment of the invention cross test
The structured flowchart of structure；
Fig. 2 is the circuit test that the small delay defects of reduction based on scan chain according to an embodiment of the invention cross test
The schematic diagram of system (i.e. thermal drivers testability (DFT) design structure)；
Fig. 3 is the circuit test that the small delay defects of reduction based on scanning tree according to an embodiment of the invention cross test
The schematic diagram of system (i.e. thermal drivers testability (DFT) design structure)；And
Fig. 4 is the schematic diagram of the Test Strategy based on the test system shown in Fig. 2 and Fig. 3.
Specific embodiment
Embodiments of the invention are described below in detail, the example of the embodiment is shown in the drawings, wherein from start to finish
Same or similar label represents same or similar element or the element with same or like function.Below with reference to attached
It is exemplary to scheme the embodiment of description, is only used for explaining the present invention, and is not considered as limiting the invention.
In the description of the invention, it is to be understood that term " " center ", " longitudinal direction ", " transverse direction ", " on ", D score,
The orientation or position relationship of the instruction such as "front", "rear", "left", "right", " vertical ", " level ", " top ", " bottom ", " interior ", " outward " are
Based on orientation shown in the drawings or position relationship, it is for only for ease of and describes the present invention and simplify to describe, rather than instruction or dark
Showing the device or element of meaning must have specific orientation, with specific azimuth configuration and operation therefore it is not intended that right
Limitation of the invention.Additionally, term " first ", " second " are only used for describing purpose, and it is not intended that indicating or implying relative
Importance.
In the description of the invention, it is necessary to illustrate, unless otherwise clearly defined and limited, term " installation ", " phase
Company ", " connection " should be interpreted broadly, for example, it may be being fixedly connected, or being detachably connected, or be integrally connected；Can
Being to mechanically connect, or electrically connect；Can be joined directly together, it is also possible to be indirectly connected to by intermediary, Ke Yishi
Two connections of element internal.For the ordinary skill in the art, with concrete condition above-mentioned term can be understood at this
Concrete meaning in invention.
The thermal drivers for crossing test below in conjunction with the Description of Drawings small delay defects of reduction according to embodiments of the present invention can be tested
Property design structure.
Fig. 1 is the thermal drivers Testability Design knot that the small delay defects of reduction according to an embodiment of the invention cross test
The structured flowchart of structure.As shown in figure 1, the thermal drivers that the small delay defects of reduction according to an embodiment of the invention cross test can be surveyed
Examination property design structure 100, including：N scanning chain group 110, n demultiplexer DMUX, n the first multiplexer
MUX and control unit 120.
Wherein, each scanning chain group includes k sub- scan chain, and k sub- scan chain is by every original scan chains in circuit
Division is obtained.N DMUX is arranged between n scan input end and the n input of scanning chain group 110 correspondingly.N
MUX is arranged between n scanning output end and the n output end of scanning chain group 110 correspondingly.Control unit 120 is distinguished
Be connected with n scanning chain group 110, n DMUX and n MUX, for control the n individual sub- scan chain of the k scanned in chain group 110 according to
It is secondary to be tested, meanwhile, the test data received by n scan input end is transferred to corresponding son scanning by n DMUX of control
Chain, and n MUX of control exports the test result of corresponding sub- scan chain by the n scanning output end.
As a specific example, as shown in Fig. 2 being the circuit that the small delay defects of reduction based on scan chain cross test
The schematic diagram of test system (i.e. thermal drivers testability (DFT) design structure).Specifically, with reference to shown in Fig. 1 and Fig. 2, control
Unit processed 120 includes：Working condition port switching x, test port test, clock signal input terminal mouthful clk, length are posted for k's
Storage and n sub-control unit.
Wherein, n sub-control unit respectively with working condition port switching x, test port test, clock signal input terminal
Mouth clk is connected with register, with the value control according to working condition switching signal, test signal, clock signal and the register
K sub- scan chain in n scanning chain group processed is tested successively, meanwhile, control the n DMUX to be input into by n scanning
Hold the test data for receiving to be transferred to corresponding sub- scan chain, and control the n MUX by the test of corresponding sub- scan chain
Result is exported by the n scanning output end.
With reference to shown in Fig. 2, sub-control unit includes：First with door (NAND gate in left side), keep bolt, second and door
(NAND gate on right side) and the second multiplexer mux.Wherein, first with the first input end of door and working condition port switching
X is connected, wherein, n n of sub-control unit first is distinguished correspondingly with the 1st of register the with the second input of door
It is connected to kth position.Keep the first input end of bolt to be connected with first with the output end of door, keep the second input of bolt to connect
Meet holding signal hold；Second and door, second is connected with the first input end of door with clock signal input terminal mouthful clk, second and
Second input of door is connected with the output end of bolt is kept.Second multiplexer mux respectively with clock signal input terminal mouthful
Clk, second are connected with the output end and test port test of door, output end and the n scan chain of the second multiplexer mux
Group is connected.
Operation principle is as follows：
With reference to shown in Fig. 2, in the sweep test structure of this thermal drivers Testability Design based on scan chain architecture, often
Individual demultiplexer DMUX include k output end, the k output end correspondingly with it is corresponding scan chain group k
The input of individual sub- scan chain is connected.The information of any structure and Butut wiring, this structure is not needed to be used only for reducing electricity
The saltus step number of unit interval during drive test examination.In this structure, there are n scan input end mouthful and n scanning output end
Mouthful.Each scan input end mouthful drives k scan chain, and this k scan chain is referred to as one and scans chain group, and scan chain group and
, it is necessary to place a demultiplexer (DMUX) between scan input end mouthful, and in scanning chain group and scanning output end
After mouthful, in addition it is also necessary to place a multiplexer (MUX).DMUX and MUX is driven by same control signal.For example,
When each scan input end mouthful drives 16 scan chains, in addition it is also necessary to place 4 extra ports.It should be noted that
Scan input end mouthful and scanning output end mouth are connected to same scanning chain group.
In this structure, every time scanning input and scanning the output stage whenever, when and only one scan chain
Scan chain in group can be enabled, and other all scan chains can all be in non-enabled state.Therefore, in test process, need
The scanning to be repeated input (or the scanning output) stage loads test data (or output test response data).In circuit work
State, the test response data of all scan chains can be captured in test acquisition phase.
As shown in Fig. 2 the circuit logic in left side is the extra hardware expense that the present invention needs addition, it is used as whole
The control unit of DFT structures.First, DFT structures of the invention need to add an extra port x, and this port is in circuit
Test mode, can be assigned 1, in circuit working state, can be assigned 0.Secondly, it is necessary to add a test port
Test, this port is all entered as 0 when circuit normal work, test are initiated and test trapped state, is set to not make
Energy；And circuit be shift test data state when, be entered as 1, be set to enabled state, this displaced condition when
Wait, test ports are directed to each MUX and are set to same value, it is ensured that the normal work of DFT structures of the present invention.Testing
Cheng Zhong, test vector moves into the stage of circuit, and this extra hardware is used in the corresponding scan chain of selection, the clk shown in Fig. 2
Signal, is the clock signal of circuit, and state and test capture shape are initiated in the test that this clock signal can simultaneously act on circuit
State.
There is the register that a length is k in Fig. 2 lower left corners, and k is the scanning that corresponding each scan input end mouthful drives
The bar number of chain.The original state of the register is that the leftmost side is 1, and remaining whole is set to 0, first surveys each in expression test process
Individual scanning leftmost that scan chain of chain group, it is assumed that the depth capacity of the scan chain in circuit is d, often by d clock week
Phase, the register will will carry out shifting function, the second for moving on to left side by the 1 of leftmost side position, and then left-most position is
0, indication circuit starts to be tested for the left side Article 2 scan chain of each scanning chain group, and this process is held to circulate and held
Continue down.Signal x1Exactly it is used for the signal element for controlling the register shift to operate, being in test scanning in circuit-under-test moves
In the position stage, the signal is set to 0, does not enable；When each group of correspondence position scan chain has been tested, i.e., this is posted
When storage needs to carry out shifting function, the signal can be set to 1, be that register performs shifting function, then, test vector
Corresponding next scan chain of each scanning chain group can be moved into.
There is k MUX in control unit on the left of Fig. 2, also comprising two and door and a holding bolt before each MUX
(hold latch).Wherein first respectively connected a deposit of extra input port x and the lower left corner with the input of door
Device, and a holding bolt should be connected to the output of door, this unit also carries out holding letter with a hold signal to circuit
Number operation.The value for keeping the output port of bolt is determined by the value of corresponding register, the input hold letters of the unit
Number when the circuit test vector shift stage, 1 can be set to, be set to enabled state；Initiate and survey in circuit test vector
The vectorial acquisition phase of examination, can be set to 0, be set to not enabled state.It should be noted that circuit test vector is initiated and capture rank
Section, test signals are equally set to 0, are set to not enabled state.
The MUX and DMUX of each scanning chain group that Fig. 2 right sides circuit is added can in the same time be set to identical in phase
Value.Below this process is illustrated with an example.Assuming that k=16, each scans chain group and includes 16 scan chains.When every
When DMUX before one scanning chain group is set to 0000 by corresponding selection input signal, test scan vector can be moved into each
In first scan chain of individual scanning chain group；Same mode, when DMUX is set to 1111, test scan vector can be moved into
16th article of scan chain of each scanning chain group, i.e., in the last item scan chain.The selection input signal of DMUX is connected to one
Extra k1The counter of position, k=2k1, k is the scanning chain number that each scanning chain group is included.
Assuming that circuit-under-test has n bar scan chains originally, every scan chain of script is first further partitioned into k parts by the present invention, i.e.,
Structure of the invention can include nk bar scan chains.And script is divided into k parts of scan chain, still can be placed on same
Scanning chain group, will every scan chain of script be divided into one scanning chain group of k part recomposition, therefore, the present invention is altogether comprising n
Individual scanning chain group, each scanning chain group includes k bar scan chains.When circuit is in proceeds by test, first survey
Examination vector v can be moved into the circuit.Specific as follows, first, first scan chain of each scanning chain group can receive to be moved into
Test vector, while other scan chains can be set to not enabled state.After by d clock cycle, each scan chain
The Article 2 scan chain of group can be strobed, and the test vector that reception is moved into, other scan chains are set to not enabled state.This
Individual process lasts till that all of test vector has been loaded into circuit.In ensuing test vector mounting phase, initially
Input (PI) can be set to the corresponding values of test vector v, and then all of scan chain can enter test acquisition phase, for capturing
Test response data.After all of test vector is loaded and is captured, said process just terminates.
The small delay defects of reduction according to embodiments of the present invention cross the thermal drivers Testability Design structure of test, Ke Yiyou
Effect reduces the thermal drivers Testability Design structure that small delay defects cross test that reduces that small delay defects cross test, while reducing
Power consumption in circuit testing procedures.
In order to further reduce the power consumption in circuit testing procedures, and reduce the number of transitions in test process and test
Time, the embodiment of the present invention the small delay defects of reduction cross test thermal drivers Testability Design structure in, such as Fig. 3 institutes
Show, each output end of each demultiplexer DMUX respectively with it is many in k sub- scan chain of corresponding scanning chain group
The input of individual sub- scan chain is connected.I.e. embodiments of the invention propose a kind of small delay defects mistake of reduction based on scanning tree
The small delay defects of reduction of test cross the thermal drivers Testability Design structure (i.e. thermal drivers Testability Design structure) of test.
In this structure, also include：N XOR network, n XOR network settings are in the n the first multiplexer MUX and described
Between the n output end of scanning chain group.
Specifically, it is shown in Figure 3, only Fig. 1 is made into structure based on scanning tree based on scan chain architecture, its
Remaining logic is constant.This structure can further lower test number of transitions and the testing time compared with the structure based on scan chain.Fig. 3
In, the output port of each DMUX drives the individual scan chains of k ', when all one trees driven by DMUX are all by identical
Clock drives.All same one-level scan chains in same scanning tree can all be endowed identical value.In two frame circuits, if
Two trigger f1And f2There is no identical follow-up, they can just divide in a group.
K ' bar scan chains (v will be set1,1,v1,2,…,v1,d),(v2,1,v2,2,…,v2,d),…,(vk’,1,vk’,2,…,vk’,d)
Driven by same one tree, then v1,1,v2,1,…,vk’,1There is no identical follow-up in two frame circuits.With Fig. 1 based on scanning
The DFT structures of chain compare, and each scan input end of the DFT structures based on scanning tree mouthful is passed to test data is parallel
Multi-scanning chain, therefore, the number of transitions in testing time and test can decline to a great extent.
In this configuration, placement one is also needed between scan chain and the test output terminal mouth for being driven by identical clock signal
Individual XOR networks.If the input port number of sweep test is fixed, then the depth of scan chain is compared with based on scan chain
DFT structures can decline to a great extent.Assuming that the l bar scan chains (v of scanning output end mouthful1,1,v1,2,…,v1,d),(v2,1,v2,2,…,
v2,d),…,(v l,1,v l,2,…,v l,d) connected by same XOR tree, shown as the following formula, scanning output end mouthful m is equal to
The k maximum of XOR networks, OiIt is i-th value of XOR networks.
M=max { O1,O2,…,Ok}。
It should be noted that at least one MUX will have k input port, because all of k XOR networks are at least needed
Want an output port.Under any circumstance, the most inputs of each scanning output end mouthful selection.Such as IWLS2005
In vga circuits, k=8, n=10, k1=ln8=3.The circuit includes 17079 triggers, and the value of each group of scanning tree is
14, that is to say, that the output end of each DMUX drives 14 scan chains, therefore, each scan input end mouthful drives 112
Scan chain.The maximum depth of DFT structure of the present invention based on scanning tree is 16.Therefore, DFT structure of the present invention based on scanning tree
Temperature buzzer not only can be further effectively reduced, number of transitions and testing time, compression verification excitation can also be greatly reduced
And response data.
As shown in figure 3, this structure is in test mode, x signal ports are set to 1, and are set in circuit working state
It is 0.Test signals as the DFT structures of Fig. 1, scanning displacement stage be set to 1, circuit work, test initiate and
Test vector acquisition phase is set to 0.All of sweep trigger is all driven by same clk clock signals.Shift register
Each d clock cycle just does a shifting function, and d represents the depth capacity of scan chain.X1Rank is swept in circuit test vector
Section is set to 0, and 1 is set to when shift register needs shifting function.Then, test vector will enter next group scan chain
In.
It is the number of scan input end mouthful in Fig. 3 to make n.The heat for crossing test with the small delay defects of reduction based on scan chain is driven
Unlike dynamic Testability Design structure, sweep trigger is divided into bar scan chain by this structure based on scanning tree.This
A little scan chains can be divided into n group, and every group includes bar scan chain, and wherein k represents the scanning tree number of driving, and k ' represents every
The scanning chain number that scanning tree is included.When circuit loads first test vector v, step is as follows：Test vector is moved first
Enter in every group of first scanning tree, remaining scanning tree is set to not enable.Likewise, when first scanning tree loaded it
Afterwards, in starting second scanning tree for move into test vector every group.This process persistently carry out until all of scanning tree all
Test vector is loaded.
The small delay defects of reduction according to embodiments of the present invention cross the thermal drivers Testability Design structure of test, Ke Yijin
Power consumption in one step reduction circuit testing procedures, and reduce the number of transitions in test process and testing time.
Fig. 4 is illustrated based on the small delayed test strategy of thermal drivers on DFT structures proposed by the present invention, and this strategy can
To be used on scan chain architecture proposed by the present invention and scanning tree construction simultaneously.The strategy can effectively reduce temperature buzzer
Number, so as to reduce the number of test.Before test, all small delayed test failures (SDD) of test selection it is all most
Length can survey path.Test process can be divided into g part, all be each time to choose to relax (slack) comprising the minimum time |
T |/g test vector.Circulated subsequently into first, untilEnd loop.T is selected firstiTest vector collection, should
Test vector collection possesses lax sensitized path of minimum time, T=T-Ti.When having selected TiAfter test vector collection, enter back into
Second circulation, the mark that the circulation terminates is Ti.In this circulation, first group of survey is selected from orderly test set first
Examination vector v, the register of control unit in DFT structures of the invention is set to 10 ... 0, T ← T- { v }, P ← P- { v }.Then select
Lead to first scan chain of each scanning chain group, while not enabling remaining scan chain.Test vector v is squeezed into first to sweep
Chain is retouched, keeps bolt to move into the stage for hold mode in test vector with season.When first scan chain has loaded test vector
Afterwards, by the extra register shift of control unit to next state.Similar, the Article 2 for gating each scanning chain group is swept
Chain is retouched, while not enabling remaining scan chain.Continue above procedure until all of scan chain have received test vector.Most
All sweep triggers are set to test mounting phase afterwards, test vector capture is then carried out.Work as TiCirculation inside end.Connect
The temperature information of more novel circuit, the delay information in all selected paths in more novel circuit calculates the new temperature for generating
Alarm number.Above procedure persistently carry out untilSystemic circulation outside end.Finally return to final temperature buzzer number
Mesh and test set.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means to combine specific features, structure, material or spy that the embodiment or example are described
Point is contained at least one embodiment of the invention or example.In this manual, to the schematic representation of above-mentioned term not
Necessarily refer to identical embodiment or example.And, the specific features of description, structure, material or feature can be any
One or more embodiments or example in combine in an appropriate manner.
Although an embodiment of the present invention has been shown and described, it will be understood by those skilled in the art that：Not
Can these embodiments be carried out with various changes, modification, replacement and modification in the case of departing from principle of the invention and objective, this
The scope of invention is by claim and its equivalent limits.
Claims (7)
1. it is a kind of to reduce the thermal drivers Testability Design structure that small delay defects cross test, it is characterised in that including：
N scanning chain group, wherein, each scanning chain group includes k sub- scan chain, and the k sub- scan chain is by every in circuit
Bar original scan chains are divided and obtained；
N demultiplexer DMUX, it is defeated that the n demultiplexer DMUX is arranged on n scanning correspondingly
Enter between end and the n input for scanning chain group；
N the first multiplexer MUX, the n the first multiplexer MUX is arranged on n scanning output correspondingly
Between the output end of end and the n scanning chain group；And
Control unit, described control unit scans chain group, the n demultiplexer DMUX and institute with described n respectively
State n the first multiplexer MUX to be connected, for controlling k sub- scan chain in n scanning chain group to be tested successively, together
When, control the n demultiplexer DMUX that the test data received by n scan input end is transferred into corresponding son
Scan chain, and control the n first multiplexer MUX by the test result of corresponding sub- scan chain by the n
Scanning output end is exported, and described control unit includes：Working condition port switching x, test port test, clock signal are defeated
Inbound port clk, length for k register and n sub-control unit, wherein, the n sub-control unit respectively with the work
State port switching x, test port test, clock signal input terminal a mouthful clk are connected with the register, with according to working condition
The value of switching signal, test signal, clock signal and the register controls the n k scanned in chain group sub- scan chain successively
Tested, meanwhile, the test data for controlling the n demultiplexer DMUX to be received by n scan input end is passed
It is defeated to corresponding sub- scan chain, and control the n first multiplexer MUX by the test result of corresponding sub- scan chain
Exported by the n scanning output end.
2. it is according to claim 1 to reduce the thermal drivers Testability Design structure that small delay defects cross test, its feature
It is that the sub-control unit includes：
First and door, described first is connected with the first input end of door with the working condition port switching x, wherein, n son control
N first of unit processed is connected with 1 to the kth position of the register correspondingly respectively with the second input of door；
Bolt, the first input end of the holding bolt is kept to be connected with described first with the output end of door, the holding bolt
The connection of the second input keep signal hold；
Second and door, described second is connected with the first input end of door with the clock signal input terminal mouthful clk, described second and
Second input of door is connected with the output end of the holding bolt；
Second multiplexer mux, the second multiplexer mux respectively with the clock signal input terminal mouthful clk, described
Second is connected with the output end and the test port test of door, the output end and the n of the second multiplexer mux
Individual scanning chain group is connected.
3. it is according to claim 2 to reduce the thermal drivers Testability Design structure that small delay defects cross test, its feature
It is, wherein,
When in circuit test state, the working condition port switching x puts 1, when in circuit working state, the work
Make state port switching x to set to 0；
When in circuit working state, test initiation state and test trapped state, the test port test is entered as
0, the test port test sets to 0, and when in shift test data state, the test port test puts 1；
When in test initiation state and test trapped state, the clock signal input terminal mouthful clk reduces small prolonging to described
Slow defect crosses the thermal drivers Testability Design structure input clock signal of test.
4. it is according to claim 2 to reduce the thermal drivers Testability Design structure that small delay defects cross test, its feature
It is that the original state of the register is the 1st position 1, remaining position 0.
5. the small delay defects of reduction according to claim any one of 1-4 cross the thermal drivers Testability Design knot of test
Structure, it is characterised in that each demultiplexer DMUX include k output end, the k output end correspondingly with phase
The k input of sub- scan chain of the scanning chain group answered is connected.
6. the small delay defects of reduction according to claim any one of 1-4 cross the thermal drivers Testability Design knot of test
Structure, it is characterised in that k son of each output end of each demultiplexer DMUX respectively with corresponding scanning chain group is swept
The many inputs of sub- scan chain retouched in chain are connected.
7. it is according to claim 6 to reduce the thermal drivers Testability Design structure that small delay defects cross test, its feature
It is also to include：
N XOR network, the n XOR network settings are in the n the first multiplexer MUX and the n scanning chain group
Output end between.
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