JP3558923B2 - Wire bonding method and heater plate used in the method - Google Patents

Wire bonding method and heater plate used in the method Download PDF

Info

Publication number
JP3558923B2
JP3558923B2 JP15188599A JP15188599A JP3558923B2 JP 3558923 B2 JP3558923 B2 JP 3558923B2 JP 15188599 A JP15188599 A JP 15188599A JP 15188599 A JP15188599 A JP 15188599A JP 3558923 B2 JP3558923 B2 JP 3558923B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
heater plate
wire bonding
concave portion
vacuum hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP15188599A
Other languages
Japanese (ja)
Other versions
JP2000340602A (en
Inventor
啓二 今戸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Science and Technology Agency
Original Assignee
Japan Science and Technology Agency
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Science and Technology Agency filed Critical Japan Science and Technology Agency
Priority to JP15188599A priority Critical patent/JP3558923B2/en
Publication of JP2000340602A publication Critical patent/JP2000340602A/en
Application granted granted Critical
Publication of JP3558923B2 publication Critical patent/JP3558923B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/78251—Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/787—Means for aligning
    • H01L2224/78743—Suction holding means
    • H01L2224/78744—Suction holding means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【産業上の利用分野】
本発明は、半導体チップに金線（外部リード線）を接合するワイヤボンディング法に関するものであり、特に半導体チップに外部リード線を接合するワイヤボンディング作業時において半導体チップをヒータープレート上にしっかりと保持することができるワイヤボンディング法およびその方法に使用するヒータープレートに関するものである。
【０００２】
【従来の技術】
ワイヤボンディングは、ＩＣ製造工程の中で欠くことのできない工程であるが、半導体の製造不良の６０％は、ワイヤボンディングに係わるということであり、半導体の製造不良率を減少させるために効果的なワイヤボンディング法の研究が進められている。
超音波ワイヤボンディングは、アイランドと呼ばれる薄い金属板上に半導体チップを接着したものをヒータープレート上に載置固定し、ヒータープレートによって半導体チップを加熱した状態で超音波溶接により外部リード線を半導体チップに接合している。この時ヒータープレート上で半導体チップが移動せぬように保持するには、図５に示すようにヒータープレート１に小さなバキューム孔７をあけ、半導体チップ３を接着したアイランド３ａをこのバキューム孔７からの負圧により吸引吸着している。
【０００３】
【発明が解決しようとする課題】
しかし、半導体チップが小さくなると、超音波接着時に半導体チップが振動しチップの固定が難しくなり、不十分な固定状態で外部リード線の溶接を行うと、接合不良等の問題が起こる。
本発明者はこのような事態の改善を図るために、超音波印加時の半導体チップの振動を解析し接合不良の原因を明かにし、その対策としてヒータープレートに形成したバキューム孔の周囲に四角や円形等の形状をした浅い凹部を形成することで、接合不良が改善されることを見いだした。
【０００４】
本発明は上記知見にもとづいてなされたもので、半導体チップを載置するヒータープレートのバキューム孔の周囲に、半導体チップの載置面積よりも少ない凹部を形成し、バキューム孔からの負圧を凹部全体に作用させ広い面積で半導体チップをヒータープレート上にしっかり保持できるワイヤボンディング法を提供することにより、上記問題点を解決することを目的とする。
【０００５】
【課題を解決するための手段】
このため、本発明が採用した技術解決手段は、半導体チップに外部リード線を接合する超音波ワイヤボンディングにおいて、半導体チップを載置するヒータープレートに半導体チップの載置面積よりも小さく、かつバキューム孔よりも大きな面積の凹部を一つ形成し、前記凹部に載置した半導体チップを前記凹部に作用する前記バキューム孔からの負圧によって保持することを特徴とするワイヤボンディング法である。また、半導体チップに外部リード線を接合する超音波ワイヤボンディングに使用するヒータープレートであって、ヒータープレートの半導体チップ載置部に、半導体チップの載置面積よりも小さく、かつバキューム孔よりも大きな面積の凹部を一つ形成し、該凹部を前記バキューム孔と連通して構成したことを特徴とするワイヤボンディング法に使用するヒータープレートである。また、前記凹部の面積は半導体チップ載置面積の３０〜７０％、好ましくは５０〜６０％であり、また凹部の深さは０．０５〜０．５ｍｍ、好ましくは０．１ｍｍ〜０．２ｍｍであることを特徴とするワイヤボンディング法に使用するヒータープレートである。
【０００６】
【実施形態】
以下図面を参照して本発明に係る実施形態を説明すると、図１は、超音波ワイヤボンダーの概略図、図２は半導体チップ（アイランドに接着したもの）をヒータープレート上に載置した状態の断面図である。
なお、以下の用いる半導体チップとは、半導体チップ単体あるいは半導体チップをアイランドに接着したものの総称として用いることにする。
図において、１はヒータープレート、２はリードフレーム、３はＩＣチップ（半導体チップ）、４は押さえ、５は外部リード線、６は超音波ホーンである。
ヒータープレート１には図２に示すようにバキューム孔７に連通する凹部（リセス）８が形成されており、ヒータープレート１上に載置された半導体チップ３は前記凹部８に作用する負圧によりヒータープレート１に吸引吸着されている。凹部８の形状は四角形、その他の多角形、あるいは円形などであり、凹部８の面積は半導体チップ載置面積（半導体チップ自体あるいはアイランドを介してヒータプレート上に置かれた半導体チップの載置面積）の３０〜７０％、好ましくは５０〜６０％であり、また凹部の深さは０．０５〜０．５ｍｍ、好ましくは０．１ｍｍ〜０．２ｍｍとする。
【０００７】
前記半導体チップ３の周囲には図１に示すようにリードフレーム２が配置され、押さえ４によってヒータープレート１上に保持されており、リードフレーム２と半導体チップ３とは外部リード線５により電気的に接合される。前記外部リード線５は従来と同様に超音波ホーン６により超音波接合される。
本発明では、超音波ホーン６によって外部リード線５を半導体チップ３に接合する際に、ヒータープレート１上に載置した半導体チップ３を、バキューム孔７に連通した凹部８に発生する負圧を利用してヒータープレート上に保持できるため、ワイヤボンディングによる接合不良を改善することができる。
【０００８】
図３、図４に本発明に係る凹部（リセス）による振動抑制効果を、最も接合不良を起こし易い箇所について実験した結果を示す。図３より超音波パワー（ＵＳ＝８０）が大きいと、アイランド（半導体チップ）面積とリセス面積との比κが５０％のものと従来のヒータープレートとの有意差は認められないが、超音波パワーが小さくなると（ＵＳ＝６０）、アイランド面積とリセス面積との比κが５０％のものの方が従来のものよりも振動抑制効果が大きくなる。また図４の７０％リセスの場合は振動振幅が非常に小さくなっており、振動抑制効果のさらに大きいことがわかる。
【０００９】
本発明のワイヤボンディング法は、ヒータープレート側にバキューム孔と連通する凹部を形成するという簡単な方法で半導体チップをヒータープレート上にしっかりと保持することができ、ワイヤボンディングの接続不良を解消することができる。なお凹部の形状は上記実施形態に示した形状に限らず、種々の形状を採用することができる。
また本発明はその精神または主要な特徴から逸脱することなく、他のいかなる形でも実施できる。そのため、前述の実施形態はあらゆる点で単なる例示にすぎず限定的に解釈してはならない。
【００１０】
【発明の効果】
以上詳細に述べたように本発明はヒータープレートに形成したバキューム孔に連通して凹部を形成することで、バキューム孔から作用する負圧により半導体チップを広い面積で吸引しヒータープレート上に保持できるため、ワイヤボンディングによる接合不良を確実に改善できるという優れた効果を奏することができる。
【図面の簡単な説明】
【図１】本発明の一実施形態であるワイヤボンディングの斜視図である。
【図２】本発明の実施形態に係るヒータープレートとアイランドを有する半導体チップとの断面図である。
【図３】本発明に係る凹部（リセス）による振動抑制効果の第１実験データである。
【図４】本発明に係る凹部（リセス）による振動抑制効果の第２実験データである。
【図５】従来のヒータープレートとアイランドに接着した半導体チップの断面図である。[0001]
[Industrial applications]
The present invention relates to a wire bonding method for bonding a gold wire (external lead wire) to a semiconductor chip, and particularly to a semiconductor chip firmly held on a heater plate during a wire bonding operation for bonding an external lead wire to a semiconductor chip. The present invention relates to a wire bonding method that can be performed and a heater plate used in the method.
[0002]
[Prior art]
Wire bonding is an indispensable step in an IC manufacturing process, but 60% of semiconductor manufacturing defects are related to wire bonding, and are effective in reducing the semiconductor manufacturing defect rate. Research on the wire bonding method is ongoing.
In ultrasonic wire bonding, a semiconductor chip bonded to a thin metal plate called an island is mounted and fixed on a heater plate, and the semiconductor chip is heated by the heater plate. Is joined to. At this time, in order to keep the semiconductor chip from moving on the heater plate, a small vacuum hole 7 is formed in the heater plate 1 as shown in FIG. 5, and the island 3a to which the semiconductor chip 3 is bonded is removed from the vacuum hole 7. Is sucked and adsorbed by the negative pressure.
[0003]
[Problems to be solved by the invention]
However, when the size of the semiconductor chip is reduced, the semiconductor chip vibrates at the time of ultrasonic bonding, and it becomes difficult to fix the chip. If welding of the external lead wire is performed in an insufficiently fixed state, a problem such as poor joining occurs.
In order to improve such a situation, the present inventor analyzed the vibration of the semiconductor chip at the time of applying ultrasonic waves, clarified the cause of the bonding failure, and took a square or a square around the vacuum hole formed in the heater plate as a countermeasure. By forming a shallow concave portion having a circular shape or the like, it has been found that poor bonding is improved.
[0004]
The present invention has been made based on the above findings, and has a recess formed around a vacuum hole of a heater plate on which a semiconductor chip is mounted, the recess being smaller than the mounting area of the semiconductor chip, thereby reducing the negative pressure from the vacuum hole. It is an object of the present invention to solve the above-mentioned problems by providing a wire bonding method that can act as a whole and securely hold a semiconductor chip on a heater plate in a wide area.
[0005]
[Means for Solving the Problems]
For this reason, the technical solution adopted by the present invention is that, in ultrasonic wire bonding in which an external lead wire is bonded to a semiconductor chip, a heater plate on which the semiconductor chip is mounted is smaller than a mounting area of the semiconductor chip and a vacuum hole is provided. A wire bonding method is characterized in that one concave portion having a larger area is formed, and a semiconductor chip placed in the concave portion is held by negative pressure from the vacuum hole acting on the concave portion . Also, a heater plate used for ultrasonic wire bonding for joining an external lead wire to a semiconductor chip, wherein the heater chip has a semiconductor chip mounting portion, which is smaller than the mounting area of the semiconductor chip and larger than the vacuum hole. A heater plate for use in a wire bonding method, wherein one concave portion having an area is formed and the concave portion is connected to the vacuum hole . The area of the recess is 30 to 70%, preferably 50 to 60% of the mounting area of the semiconductor chip, and the depth of the recess is 0.05 to 0.5 mm, preferably 0.1 to 0.2 mm. A heater plate for use in a wire bonding method, characterized in that:
[0006]
Embodiment
FIG. 1 is a schematic view of an ultrasonic wire bonder, and FIG. 2 is a diagram showing a state in which a semiconductor chip (adhered to an island) is mounted on a heater plate. It is sectional drawing.
The semiconductor chip used hereinafter is used as a generic term for a single semiconductor chip or a semiconductor chip bonded to an island.
In the figure, 1 is a heater plate, 2 is a lead frame, 3 is an IC chip (semiconductor chip), 4 is a holder, 5 is an external lead wire, and 6 is an ultrasonic horn.
As shown in FIG. 2, a recess (recess) 8 communicating with the vacuum hole 7 is formed in the heater plate 1, and the semiconductor chip 3 placed on the heater plate 1 is moved by a negative pressure acting on the recess 8. The heater plate 1 is suction-adsorbed. The shape of the concave portion 8 is a quadrangle, another polygon, or a circle, and the area of the concave portion 8 is the semiconductor chip mounting area (the mounting area of the semiconductor chip itself or the semiconductor chip mounted on the heater plate via the island. ) Is 30 to 70%, preferably 50 to 60%, and the depth of the concave portion is 0.05 to 0.5 mm, preferably 0.1 to 0.2 mm.
[0007]
A lead frame 2 is arranged around the semiconductor chip 3 as shown in FIG. 1 and is held on a heater plate 1 by a retainer 4. The lead frame 2 and the semiconductor chip 3 are electrically connected by external lead wires 5. Joined to. The external lead wire 5 is ultrasonically bonded by an ultrasonic horn 6 as in the conventional case.
According to the present invention, when the external lead wire 5 is joined to the semiconductor chip 3 by the ultrasonic horn 6, the semiconductor chip 3 placed on the heater plate 1 is subjected to a negative pressure generated in the concave portion 8 communicating with the vacuum hole 7. Since it can be held on the heater plate by utilizing, bonding failure due to wire bonding can be improved.
[0008]
FIG. 3 and FIG. 4 show the results of experiments on the effect of suppressing vibrations by the recesses (recesses) according to the present invention at locations where joint failure is most likely to occur. As shown in FIG. 3, when the ultrasonic power (US = 80) is large, the difference between the island (semiconductor chip) area and the recess area having a ratio κ of 50% is not significantly different from that of the conventional heater plate. When the power is reduced (US = 60), the vibration suppression effect is larger when the ratio κ between the island area and the recess area is 50% than when the conventional one is used. Also, in the case of the 70% recess shown in FIG. 4, the vibration amplitude is very small, and it can be seen that the vibration suppression effect is even greater.
[0009]
According to the wire bonding method of the present invention, a semiconductor chip can be firmly held on a heater plate by a simple method of forming a concave portion communicating with a vacuum hole on a heater plate side, and connection failure of wire bonding is eliminated. Can be. The shape of the concave portion is not limited to the shape shown in the above embodiment, and various shapes can be adopted.
The present invention may be embodied in any other form without departing from its spirit or essential characteristics. Therefore, the above-described embodiment is merely an example in all aspects and should not be interpreted in a limited manner.
[0010]
【The invention's effect】
As described above in detail, according to the present invention, by forming a recess in communication with the vacuum hole formed in the heater plate, the semiconductor chip can be sucked over a large area by the negative pressure acting from the vacuum hole and held on the heater plate. Therefore, an excellent effect that the bonding failure due to wire bonding can be reliably improved can be achieved.
[Brief description of the drawings]
FIG. 1 is a perspective view of wire bonding according to an embodiment of the present invention.
FIG. 2 is a sectional view of a heater plate and a semiconductor chip having islands according to an embodiment of the present invention.
FIG. 3 is first experimental data of a vibration suppression effect by a recess according to the present invention.
FIG. 4 is second experimental data of the vibration suppression effect by the concave portion (recess) according to the present invention.
FIG. 5 is a sectional view of a conventional heater plate and a semiconductor chip bonded to an island.

Claims (3)

半導体チップに外部リード線を接合する超音波ワイヤボンディングにおいて、半導体チップを載置するヒータープレートに半導体チップの載置面積よりも小さく、かつバキューム孔よりも大きな面積の凹部を一つ形成し、前記凹部に載置した半導体チップを前記凹部に作用する前記バキューム孔からの負圧によって保持することを特徴とするワイヤボンディング法。In ultrasonic wire bonding in which an external lead wire is bonded to a semiconductor chip, a heater plate on which the semiconductor chip is mounted is formed with one recess having an area smaller than the mounting area of the semiconductor chip and larger than a vacuum hole, A wire bonding method , wherein a semiconductor chip placed in a concave portion is held by negative pressure from the vacuum hole acting on the concave portion . 半導体チップに外部リード線を接合する超音波ワイヤボンディングに使用するヒータープレートであって、ヒータープレートの半導体チップ載置部に、半導体チップの載置面積よりも小さく、かつバキューム孔よりも大きな面積の凹部を一つ形成し、該凹部を前記バキューム孔と連通して構成したことを特徴とするワイヤボンディング法に使用するヒータープレート。A heater plate used for ultrasonic wire bonding for joining an external lead wire to a semiconductor chip. The heater plate has a semiconductor chip mounting portion having an area smaller than a mounting area of the semiconductor chip and larger than a vacuum hole. A heater plate for use in a wire bonding method, wherein one concave portion is formed and the concave portion communicates with the vacuum hole . 前記凹部の面積は半導体チップ載置面積の３０〜７０％、好ましくは５０〜６０％であり、また凹部の深さは０．０５〜０．５ｍｍ、好ましくは０．１ｍｍ〜０．２ｍｍであることを特徴とする請求項２に記載のワイヤボンディング法に使用するヒータープレート。The area of the recess is 30 to 70%, preferably 50 to 60% of the semiconductor chip mounting area, and the depth of the recess is 0.05 to 0.5 mm, preferably 0.1 mm to 0.2 mm. A heater plate for use in the wire bonding method according to claim 2, characterized in that:
JP15188599A 1999-05-31 1999-05-31 Wire bonding method and heater plate used in the method Expired - Fee Related JP3558923B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15188599A JP3558923B2 (en) 1999-05-31 1999-05-31 Wire bonding method and heater plate used in the method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15188599A JP3558923B2 (en) 1999-05-31 1999-05-31 Wire bonding method and heater plate used in the method

Publications (2)

Publication Number Publication Date
JP2000340602A JP2000340602A (en) 2000-12-08
JP3558923B2 true JP3558923B2 (en) 2004-08-25

Family

ID=15528343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15188599A Expired - Fee Related JP3558923B2 (en) 1999-05-31 1999-05-31 Wire bonding method and heater plate used in the method

Country Status (1)

Country Link
JP (1) JP3558923B2 (en)

Also Published As

Publication number Publication date
JP2000340602A (en) 2000-12-08

Similar Documents

Publication Publication Date Title
US6158645A (en) Method of bonding radiation plate
JP3558923B2 (en) Wire bonding method and heater plate used in the method
JP3522906B2 (en) Ultrasonic bonding method and apparatus
JP2003068962A (en) Frame and method for manufacturing semiconductor device
JPH08148512A (en) Production of semiconductor device
JP2000124767A (en) Substrate mounting method for saw filter chip and saw filter chip
JP4491321B2 (en) Ultrasonic mounting method and ultrasonic mounting apparatus used therefor
JP2001257236A (en) Manufacturing method of electronic device
JP2001127244A (en) Multichip semiconductor device and method of manufacturing the same
JPH0529404A (en) Tool for bonding of al wiring lead
JPH08162598A (en) Semiconductor device
JPH11288960A (en) Wire-bonding connection and tool for bonding surface removal removal
JPH01231334A (en) Wire bonding method
JP2972681B2 (en) Semiconductor device and manufacturing method thereof
JP3146634B2 (en) Semiconductor device wire bonding apparatus and semiconductor device manufacturing method
JPH1012655A (en) Heater plate for wire bonder
JP3404735B2 (en) Semiconductor device manufacturing lead frame and semiconductor device manufacturing lead frame assembly manufacturing method
JPH0290540A (en) Semiconductor device
JP2001291734A (en) Method and apparatus of wire bonding
JP4601159B2 (en) Wire bonding method and wire bonding apparatus for semiconductor device
JPH04369235A (en) Fabrication of semiconductor device
JPS5878434A (en) Bonding method for semiconductor element
JPS60194546A (en) Semiconductor device
JPH11243112A (en) Device and method for wire bonding
JPH05326812A (en) Lead frame for semiconductor device, wire bonding device and wire bonding method for semiconductor chip using thereof

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20040122

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040217

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040413

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20040518

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20040519

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090528

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090528

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100528

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110528

Year of fee payment: 7

LAPS Cancellation because of no payment of annual fees