JP3557158B2 - Manufacturing method of high voltage semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a high-breakdown-voltage semiconductor device having a planar structure, and more particularly to a method for manufacturing a high-breakdown-voltage semiconductor device having a planar structure which is simplified with a small number of mask steps.
[0002]
[Prior art]
A bipolar transistor having a high withstand voltage planar structure has a structure in which a plurality of guard rings are provided around the transistor to expand a depletion layer and provide a withstand voltage. In addition, the manufacturing method uses a mask process and a heat treatment process frequently, such as formation of a field nitride film and phosphorus treatment.
[0003]
7 to 13 show a method of manufacturing a conventional bipolar transistor having a high breakdown voltage planar structure.
[0004]
FIG. 7 shows a step of forming a collector region. N ⁺ diffusion is performed on both surfaces of the N ⁻ type silicon substrate 32, and after forming the N ⁺ type layer 31, one is removed. After polishing, an N ⁺ / N ⁻ layer is formed to form a collector region. An oxide film 33 is provided, a mask is formed with the resist film PR except for the planned base region and the planned guard ring portion, and the oxide film 33 in the planned base region and the planned guard ring portion is removed by etching.
[0005]
FIG. 8 shows a step of forming the base region 38. After boron ions are implanted into the entire surface, an oxide film 33 is formed to remove dirt on the surface and prevent out-diffusion. The base region 38 and the guard ring 40 having a depth of about 30 μm are formed by diffusing boron ions by annealing.
[0006]
FIG. 9 shows a step of forming a high concentration region on the surface of the base region. Since the base region 38 has a low impurity concentration, the contact resistance with Al-Si increases when an electrode is formed. To prevent this, a high concentration region is provided on the surface of the base region 38. The oxide film 33 on the base region 38 is removed by etching using a photoresist mask except for the base region 38 to expose the surface of the base region 38. After depositing boron on the surface of the base region 38 and removing the glass layer on the surface, a thick oxide film 33 is deposited on the entire surface, and boron is diffused on the surface of the base region 38 to form a high concentration region.
[0007]
FIG. 10 shows a step of forming the field nitride film 34. A nitride film is deposited on the entire surface by LP-CVD. The nitride film on the base region 38 is removed by plasma etching, contamination from the outside is prevented, and the surface is stabilized to form the field nitride film 34. Further, a non-doped oxide film 33 is formed by the CVD method, and the structurally unstable CVD film is reinforced by baking to prevent bleeding in the next step of photoetching.
[0008]
FIG. 11 shows a step of forming the emitter region 44. The oxide film 33 in the predetermined emitter region and the predetermined annular ring portion is removed using a photoresist mask, and phosphorus is deposited. Thereafter, the glass layer on the surface is removed by wet etching, and an oxide film 33 for preventing out-diffusion is formed. Thereafter, phosphorus is diffused by annealing to form an emitter region 44 and an annular ring 45. The hFE that determines the amplification of the transistor is controlled by the emitter diffusion time.
[0009]
Further, a phosphorus treatment is performed to getter heavy metals in the oxide film 33. Phosphorus is deposited on the entire surface, baked after hot water washing, and gettering of heavy metals in oxide film 33 is performed.
[0010]
12 and 13 show steps of forming an electrode.
[0011]
In FIG. 12, in order to form electrodes on the semiconductor substrate which has been subjected to the phosphorus treatment, contact holes in respective regions are formed in the oxide film 33 by using a photoresist. At this time, if particles are present on the wafer, pinholes may be formed in portions other than the contact holes. Therefore, in order to reduce the influence, a photoresist step is performed twice to form a pattern of the contact holes.
[0012]
Thereafter, aluminum is deposited on the entire surface, and aluminum serving as the base electrode 47, the emitter electrode 46, and the shield electrode 48 is left by photoetching. Alloy to obtain ohmic contact with silicon. Further, by performing a heat treatment at a temperature lower than that of the alloy for a long time, the characteristics are stabilized, and the base electrode 47, the emitter electrode 46, and the shield electrode 48 are formed.
[0013]
In FIG. 13, a nitride film is formed on the surface, and a passivation film 50 is provided. The passivation film 50 prevents external contamination and protects the aluminum base electrode 47, the emitter electrode 46, and the shield electrode 48. Further, in order to remove the nitride film which has wrapped around the back surface when the passivation film 50 is formed, a back surface treatment is performed to form a collector electrode 51 on the back surface.
[0014]
Further, as shown in FIG. 13, the structure of the bipolar transistor having the high breakdown voltage planar structure is as follows.
[0015]
A collector region including an N ⁺ type layer 31 and an N ⁻ type layer 32 of a silicon substrate is formed, and a P type base region 38 is provided on the surface of the N ⁻ type layer 32. An N ⁺ type emitter region 44 is formed on the surface of the base region 38. A plurality of P-type guard rings 40 are provided around the base region 38. An oxide film 33 is formed on the guard ring, and a field nitride film 34 is further formed thereon to protect the region where the depletion layer extends.
[0016]
At the chip end, an N ⁺ type annular ring 45 and a shield electrode 48 are provided to suppress the spread of the depletion layer. A base electrode 47 and an emitter electrode 46 are formed on the front surface, a passivation film 50 for protecting external contamination is formed, and a collector electrode 51 is formed on the back surface.
[0017]
[Problems to be solved by the invention]
In such a conventional bipolar transistor having a planar structure, a mask step or a heat treatment step is performed by forming a field nitride film, performing a phosphorus treatment for gettering for removing heavy metal in an oxide film, forming a contact hole, or forming a passivation film. Was heavily used. For this reason, the number of steps is increased, and there is a limit in reducing the manufacturing cost.
[0018]
[Means for Solving the Problems]
The present invention has been made in view of such problems, a step of forming a diffusion hole on a predetermined reverse conductivity type base region and a reverse conductivity type guard ring region on the surface of a semiconductor substrate of one conductivity type, and performing base diffusion, Forming a thick oxide film on the substrate, forming an emitter diffusion hole in the oxide film on the base region, and depositing impurities in the emitter region; forming a thick oxide film on the substrate; A step of performing emitter diffusion after thickly depositing a phosphorus glass layer. The high breakdown voltage semiconductor device realizes low cost operation by rationalizing the flow and reducing the number of mask steps and heat treatment steps. Can be provided.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described with reference to FIGS. 1 to 6 by taking an NPN-type bipolar transistor as an example.
[0020]
The bipolar transistor has a step of forming diffusion holes on a predetermined reverse conductivity type base region 8 and a reverse conductivity type guard ring 10 region on a surface of a semiconductor substrate of one conductivity type to perform base diffusion, and a thick oxide film formed on the substrate. Forming an emitter diffusion hole 11 in the oxide film 3 on the base region 8 and depositing (depositing) impurities in the emitter region 14; and forming a thick oxide film 3 on the substrate. After thickly depositing a phosphor glass (PSG) layer 13 thereon, performing emitter diffusion.
[0021]
FIGS. 1 to 3 show a process of forming a diffusion hole on a predetermined reverse conductivity type base region and a reverse conductivity type guard ring region on the surface of a semiconductor substrate of one conductivity type to perform base diffusion.
[0022]
In FIG. 1, a collector region is formed by epitaxially growing an N ⁻ type layer 2 on an N ⁺ type layer 1 of a silicon substrate. Alternatively, the collector region may be formed by performing N ⁺ diffusion on both surfaces of the N ⁻ type silicon substrate 2, removing one of the N ⁺ type layers 1 after forming the N ⁺ type layers 1, and polish the N ⁺ / N ⁻ layers. An oxide film 3 is formed on the surface, and a mask made of a photoresist is applied to a predetermined base region and a predetermined guard ring to remove the oxide film 3 by etching.
[0023]
In FIG. 2, boron is ion-implanted into the entire surface at a dose of 3 to 5 × 10 ¹⁴ cm ⁻² and an implantation energy of 100 Kev. Thereafter, in order to remove dirt on the surface and prevent out-diffusion, oxide film 3 is formed by thermal oxidation to a thickness of about 1 μm, and boron is diffused by annealing to diffuse base layer 8 having a depth of about 30 μm and guard ring 10. To form
[0024]
FIG. 3 shows that the oxide film 3 of about 1 μm formed before the base diffusion is first etched over the entire surface, and only the oxide film 3 on the base region 8 and the guard ring 10 is removed to expose the base region 8 and the guard ring 10 region. I do. As a result of this etching, the oxide film 3 on the remaining collector region is free of the boron impurity layer on the surface due to the formation of the base region 8 to form a clean oxide film 3.
[0025]
Further, a high concentration region is formed on the surface of the base region 8. Since the base region 8 has a low impurity concentration, the contact resistance with Al-Si increases when an electrode is formed. To prevent this, a high concentration region is provided on the surface of the base region 8. After depositing high concentration boron in the base region 8 and removing the glass layer on the surface, a thick oxide film 3 is formed on the entire surface.
[0026]
When the oxide film 3 is formed, boron is diffused on the surface of the base region 8 to provide a high concentration region. The surface of the guard ring region 10 also becomes a high-concentration region similarly, but has no effect.
[0027]
FIG. 4 shows a process of forming an emitter diffusion hole in a thick oxide film on a base region and depositing an impurity in the emitter region.
[0028]
An emitter diffusion hole 11 is formed in the thick oxide film 3 formed at the time of forming the high concentration region to form a predetermined emitter region, and an annular ring hole 12 is formed to form a predetermined annular ring. Unnecessary portions are removed by etching using a photoresist mask to provide an emitter diffusion hole 11 and an annular ring hole 12, and phosphorus is deposited on the entire surface. Thereafter, the glass layer on the surface is removed by wet etching.
[0029]
FIG. 5 shows a process of forming an oxide film thickly, depositing a PSG layer on the oxide film thickly, and then performing emitter diffusion.
[0030]
An oxide film 3 for preventing out-diffusion is formed to a thickness of about 0.7 μm, and PSG layer 13 is formed on the thick oxide film 3 by depositing PSG to a thickness of about 1.2 μm by CVD. By the heat treatment, N ⁺ -type ions attached to the emitter diffusion hole 11 and the annular ring hole 12 are diffused into the base region 8 and the substrate surface to form the emitter region 14 and the annular ring 15. The hFE that determines the amplification of the transistor is controlled by the emitter diffusion time.
[0031]
At this time, the heavy metals in the oxide film can be gettered by the phosphorus contained in the PSG layer 13. Since the heavy metal gettering can be performed at the same time as the emitter diffusion, the conventional phosphorus treatment step can be omitted.
[0032]
Further, since the PSG layer 13 serves as a passivation film, the conventional steps of forming a field nitride film and forming a passivation protection film are not required.
[0033]
FIG. 6 shows the formation of the electrodes. In order to form electrodes on the semiconductor substrate, contact holes in respective regions are formed in the oxide film 3 by photoetching. At this time, by using a thick resist, the photoresist step which has been conventionally performed twice can be completed only once.
[0034]
Thereafter, aluminum is deposited on the entire surface, and aluminum serving as the base electrode 17, the emitter electrode 16, and the shield electrode 18 is left by photoetching. Further, each electrode is formed by alloying to obtain ohmic contact with silicon. Further, a collector electrode 21 is formed on the back surface.
[0035]
As shown in FIG. 6, the structure of the bipolar transistor having a high breakdown voltage planar structure of the present invention is as follows.
[0036]
A collector region composed of an N ⁺ type layer 1 and an N ⁻ type layer 2 of a silicon substrate is formed, and a P type base region 8 is provided on the surface of the N ⁻ type layer 2. An N ⁺ type emitter region 14 is formed on the surface of the base region 8. A plurality of P-type guard rings 10 are provided around the base region 8. An oxide film 3 is formed on the guard ring 10, and a PSG layer 13 is further formed thereon.
[0037]
At the chip end, an N ⁺ type annular ring 15 and a shield electrode 18 are provided to suppress the spread of the depletion layer. A base electrode 17 and an emitter electrode 16 are formed on the front surface, and a collector electrode 21 is formed on the back surface.
[0038]
The feature of the present invention resides in that the PSG layer 13 is formed and then the emitter is diffused.
[0039]
First, since the PSG layer 13 can protect the region where the depletion layer extends by this manufacturing method, the conventional step of forming a field nitride film can be omitted.
[0040]
Second, since the oxide film 3 can be gettered by the phosphorus in the PSG layer 13 during the emitter diffusion, the phosphorus treatment step can be used also for the emitter diffusion and can be omitted.
[0041]
Third, since the PSG layer 13 can be used as a substitute for passivation to prevent contamination from the outside, steps of forming a passivation protective film such as the conventional generation of a nitride film and the accompanying back surface treatment can be omitted.
[0042]
【The invention's effect】
According to the manufacturing method of the present invention, the mask step and the heat treatment step can be largely omitted.
[0043]
First, the PSG 13 layer can protect the region where the depletion layer extends, so that the conventional step of forming the field nitride film 34 can be omitted.
[0044]
Second, by depositing impurities in the emitter region 14, forming the PSG layer 13 and then performing emitter diffusion, the heavy metal in the oxide film 3 can be gettered by the phosphorus in the PSG layer 13 simultaneously with the emitter diffusion. Therefore, the phosphorus treatment can be used for the emitter diffusion, and the phosphorus treatment step is not required.
[0045]
Third, since the PSG layer 13 also protects external contamination, the conventional process of forming the conventional passivation film 50, such as the formation of the nitride film and the accompanying back surface treatment, can be omitted.
[0046]
More specifically, since the flow can be streamlined, for example, the number of masking steps is four in spite of the high breakdown voltage planar structure, the manufacturing cost can be greatly reduced, and a bipolar transistor having a high breakdown voltage planar structure by low cost operation can be realized.
[Brief description of the drawings]
FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device having a planar structure according to the present invention.
FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device having a planar structure according to the present invention.
FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device having a planar structure according to the present invention.
FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device having a planar structure according to the present invention.
FIG. 5 is a cross-sectional view illustrating a method of manufacturing a semiconductor device having a planar structure according to the present invention.
FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device having a planar structure according to the present invention.
FIG. 7 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device having a planar structure.
FIG. 8 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device having a planar structure.
FIG. 9 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device having a planar structure.
FIG. 10 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device having a planar structure.
FIG. 11 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device having a planar structure.
FIG. 12 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device having a planar structure.
FIG. 13 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device having a planar structure.

Claims (3)

A diffusion hole is formed in a first oxide film on a predetermined reverse conductivity type base region and a reverse conductivity type guard ring region on a surface of the one conductivity type semiconductor substrate, and a reverse conductivity type impurity is exposed on the exposed substrate surface. The process of introducing
  Forming a thick second oxide film on the entire surface and diffusing the impurity of the opposite conductivity type to form a deep base region;
  A diffusion hole is formed in the oxide film on the base region and the guard ring region, a high concentration of a reverse conductivity type impurity is introduced into the surface, and a thick third oxide film is formed to form a reverse conductivity type impurity region. The process of
  Forming an emitter diffusion hole in the thick third oxide film on the surface of the base region and depositing one conductivity type impurity;
  Forming a thick fourth oxide film after removing the glass layer on the surface, and forming a thick PSG layer on the oxide film;
  Annealing the PSG layer and performing emitter diffusion of the one conductivity type impurity simultaneously by heat treatment to form an emitter region;
  Forming a contact hole in the PSG layer and the oxide film on the base region and the emitter region using the PSG layer as a protective film, and depositing a metal layer on the PSG layer. Manufacturing method of a high breakdown voltage semiconductor device. After forming the base region, etching the entire surface of the thick second oxide film to expose only the guard ring region and the surface of the base region, and introducing a reverse conductivity type impurity using the thick second oxide film as a mask. The method for manufacturing a high withstand voltage semiconductor device according to claim 1, wherein: 2. The method according to claim 1, wherein gettering of impurities by the PSG layer is performed simultaneously during the diffusion of the emitter.

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