JP2001007349A - Low voltage zener diode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a low voltage Zener diode from deteriorating in ESD strength due to reduction in impurity concentration of the outermost surface (with a depth of about 0 to 1 μm) of a guard ring, a leakage current from increasing due to the formation of an inversion layer, and the Zener diode from deteriorating in product characteristics, such as Zener breakdown voltage. SOLUTION: After a guard ring is oxidized and pushed into or a main junction is oxidized and pushed into, the same conductivity impurities with the guard ring are diffused into a solid phase or a vapor phase or implanted as ions for doping, by which a high concentration (1.0×1020 to 1.0×1022/cm3) impurity doped layer is formed on the outermost surface layer 5 (with a depth of about 0 to 1 μm) of the guard ring to make up for a reduction in the impurity concentration of an outermost surface layer 8 due to thermal history in processes which are carried out after the thermal treatment where a guard ring is oxidized and pushed in, and a low-voltage Zener diode of high ESD strength and low coupling capacitance can be stably manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a high ESD (electro-static d.
The present invention relates to a low-voltage zener diode having a low junction capacitance and a withstand capability.

[0002]

2. Description of the Related Art A conventional low-voltage Zener diode is:
After solid-phase diffusion, gas diffusion, or ion implantation of a P-type impurity having a conductivity type opposite to that of the substrate on the main surface of the Si substrate containing the N-type impurity, oxidization is performed to form a guard ring. Further, after solid-phase diffusion, gas diffusion, or ion implantation of an N-type impurity inside the guard ring, necessary oxidization is performed to form a main junction. Next, an impurity of the same type as that of the substrate is diffused on the opposite surface of the Si substrate, if necessary, and then immersion oxidation is performed to form an ohmic layer.

FIG. 3 is a diagram showing a conventional process flow for oxidizing the guard ring, diffusing the main junction, and oxidizing the guard ring, and a cross section of the process.

Referring to FIG. 3, in a conventional process, guard ring diffusion is performed on an N-type Si substrate 1 using a required oxide film 2 (SiO ₂ ) as a mask to form a P-type impurity boron (B).
A guard ring P ⁺⁺ layer 3 is formed. Next, a guard ring is oxidized and pressed at a high temperature (normally, 1150 ° C. or more), and the guard ring is pressed to a required depth (normally, 4 μm or more). At this time, the impurity concentration of the guard ring decreases, and the P layer 4 and the outermost P ⁻ layer 5 are formed. Further, the P ⁺⁺ layer 6 is formed inside the guard ring by diffusion of the main junction, and the main junction is oxidized and pressed to form a main junction P ⁺ 7 layer having a depth at which required product characteristics can be obtained.

In such a conventional manufacturing method, the impurity concentration at the outermost surface of the guard ring (depth of about 0 to 1 μm) decreases due to the thermal history after the guard ring is oxidized and pushed, and the ESD (elasticity)
When an electro-static discharge is applied, the conductivity of the P ^- layer 5 on the outermost surface lowers, so that the resistance becomes negative, a hot spot is formed, and a thermal runaway current flows.
N junction destruction occurs (Wunch-Bell model).

In general, as a method of manufacturing a Zener diode, in the thermal history after the oxidation indentation, the guard ring oxidation intrusion is the most severe, and the impurity concentration in this step is remarkably reduced (about 1 to 3 digits).

[0007]

The above-mentioned conventional low-voltage zener diode has the following problems.

The first problem is that the ESD resistance decreases due to a decrease in the impurity concentration at the outermost surface of the guard ring (depth of about 0 to 1 μm), and it becomes difficult to manufacture a Zener diode having a required ESD resistance. .

Due to the oxidation of the guard ring, the diffusion of the main junction, the oxidation of the main junction, and the heat history at the time of forming the ohmic layer, the impurities on the outermost surface of the guard ring diffuse into and out of the substrate. In particular, when phosphorus (P) is used as the N-type impurity of the substrate and boron (B) is used as the P-type dopant for the guard ring diffusion, the P-type impurity boron is absorbed into the oxide film at the interface with the oxide film on the guard ring. And the redistribution of impurities due to the accumulation of N-type impurity phosphorus, the P-type impurity concentration at the outermost surface of the guard ring is remarkably reduced.

Therefore, in response to avalanche breakdown at the time of application of ESD, a decrease in the conductivity at the outermost surface of the guard ring (region having a low impurity concentration) results in negative resistance, forming a hot spot and causing a thermal runaway current to flow. And PN junction breakdown.

A second problem is that in a low-voltage zener diode having a voltage of 7 V or less, when the impurity concentration of the Si substrate is high and the impurity concentration on the outermost surface of the guard ring is remarkably reduced, an inversion layer is formed when a voltage is applied to the PN junction. Are formed, and product characteristics are impaired, such as an increase in leak current and a decrease in Zener breakdown voltage.

An object of the present invention is to stably produce a low-voltage zener diode having a low junction capacitance and a high ESD resistance.

[0013]

SUMMARY OF THE INVENTION The present invention provides a method of manufacturing a semiconductor device, comprising the steps of:
An impurity of the same conductivity type as that of the guard ring is subjected to solid phase diffusion, gas diffusion, or ion implantation, and a high concentration (1.0 × 10 ²⁰ to
1.0 × 10 ²² / cm ³ ) An impurity doped layer is formed.

The outermost surface layer of the guard ring (depth about 0 to 1 μm)
m), the high concentration (1.0 × 10 ^{20 to} 1.0 × 10 ²² /
cm ³ ) By forming an impurity-doped layer, it is possible to compensate for a reduction in impurity concentration at the outermost surface of the guard ring at the time of indentation of the guard ring or formation of the main junction, and to conduct electricity at the outermost surface of the guard ring when ESD is applied. A decrease is prevented, the formation of a hot spot is prevented, and the ESD resistance is improved.

[0015]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of a low-voltage zener diode according to the present invention, in which a high-concentration impurity-doped layer is formed on the outermost surface of a guard ring after a guard ring is oxidized and pushed, and It is a figure showing the processing section.

Referring to FIG. 1, first, guard ring diffusion is performed on an N-type Si substrate 1 using a required oxide film 2 (SiO ₂ ) as a mask, and a guard ring P ⁺⁺ layer of P-type impurity boron (B) is formed. Form 3 Next, at high temperature (usually $ 11
The guard ring is oxidized and pushed in at a temperature of 50 ° C. or more, and the guard ring is pushed to a required depth (usually ≒ 4 μm or more). At this time, the impurity concentration of the guard ring decreases, and the P layer 4 and the outermost P ⁻ layer 5 are formed. The steps up to the guard ring oxidizing intrusion are the same as those in the above-described conventional process.

Next, guard ring oxidation with a remarkable decrease in concentration
After pressing, adjust the impurity concentration on the outermost surface of the guard ring
To perform solid phase diffusion, gas diffusion, or ion implantation.
The outermost surface P of the guard ring^-5 layers, about 0 depth
1 μm, high concentration (1.0 × 10 ²⁰~ 1.0 × 10^{twenty two}Pieces/
cm^Three) The outermost surface P of the impurity⁺⁺The layer 8 is formed. After this
After the main junction is diffused, it is the same as the above-described conventional process.

After the diffusion of the main junction, the process is the same as the above-mentioned conventional process. However, since the thermal history after the diffusion of the main junction is not so severe, the guard ring outermost surface P ⁺⁺ layer 8 remains.

FIG. 2 shows a second embodiment of the present invention, showing a process flow in the case where an impurity doped layer is formed on the outermost surface of a guard ring after oxidizing and pushing in a main junction, and a processing cross section thereof. is there.

Referring to FIG. 2, guard ring diffusion is first performed on an N-type Si substrate 1 using a required oxide film 2 (SiO ₂ ) as a mask, and a guard ring P ⁺⁺ layer made of P-type impurity boron (B) is formed. Form 3 Next, at high temperature (usually $ 11
A guard ring is oxidized and pushed into the guard ring to a required depth (usually ≒ 4 μm or more). At this time, the impurity concentration of the guard ring decreases, and the P layer 4 and the outermost P ⁻ layer 5 are formed.

Further, a P ⁺⁺ layer 6 is formed inside the guard ring by diffusion of the main junction, and the main junction is oxidized and pressed to form a P ⁺ 7 layer of the main junction. The steps up to the oxidization of the main junction are the same as those in the conventional process.

Next, after oxidation pushing the main junction, the impurity concentration adjusting process of the guard ring outermost surface is provided, ion implantation, the outermost surface P of the guard ring ^- the fifth layer, about depth 0
～1Myuemu, to form a high concentration ^{(1.0 × 10 20 ~1.0 × 10} 22 atoms / cm ³⁾ the outermost surface P ^{+ +} layer 8 of impurities.

As described above, by adjusting the impurity concentration after the formation of the main junction, the heat history is smaller than in the first embodiment, and the decrease in the impurity concentration at the outermost surface is further reduced.
This is advantageous for improving the ESD resistance.

If the gettering diffusion of phosphorus and the ohmic diffusion on the opposite surface of the Si substrate are required after the formation of the main junction,
The formation of the high-concentration impurity-doped layer on the outermost surface of the guard ring may be performed after these high-temperature heat treatments.

[0026]

As described above, according to the present invention, by providing an impurity concentration adjusting step, a decrease in the impurity concentration at the outermost surface is compensated for, and the conductivity of the outermost surface of the guard ring at the time of ESD application is reduced. By preventing the formation of hot spots and improving the ESD resistance, a Zener diode having a low junction capacitance and a high ESD resistance can be stably manufactured.

Also, the present invention provides an impurity concentration adjusting step, which can prevent the lowering of the impurity concentration at the outermost surface of the guard ring in the low-voltage zener diode and the formation of the inversion layer, thereby providing a high impurity concentration Si.
In a low-voltage zener diode of 7 V or less using the substrate 1, it is possible to manufacture a product having a high ESD resistance and a low junction capacitance without impairing product characteristics such as an increase in leakage current and a decrease in zener breakdown voltage.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention;
FIG. 7 is a diagram showing a process flow in the case where a high-concentration impurity-doped layer is formed on the outermost surface of the guard ring after the guard ring is oxidized and pressed, and a processing cross section thereof.

FIG. 2 is a diagram showing a second embodiment of the present invention;
FIG. 9 is a diagram showing a process flow in the case where an impurity-doped layer is formed on the outermost surface of the guard ring after the main junction is oxidized and pressed, and a processed cross section thereof.

FIG. 3 is a diagram showing a conventional process flow of oxidizing intrusion of a guard ring, diffusion of a main junction, and oxidizing intrusion, and a processed cross section thereof.

[Explanation of symbols]

Reference Signs List 1 N-type Si substrate N ⁺ 2 Oxide film (SiO ₂ ) 3 Guard ring diffusion P ⁺⁺ layer 4 Guard ring diffusion P layer (after oxidized press) 5 Guard ring outermost surface P ^- layer (after oxidized press) 6 Main junction diffusion P ⁺⁺ layer 7 Main junction diffusion P ⁺ layer (after oxidation indentation) 8 Guard ring outermost surface P ⁺⁺ layer (after adjustment of guard ring outermost surface concentration)

Claims (6)

[Claims] 1. A low-voltage zener diode having a structure in which a guard ring is formed on the outer periphery of a main junction, wherein an impurity-doped layer providing high ESD resistance is formed on a surface layer of the guard ring. Zener diode. 2. The impurity-doped layer has a concentration of 1.0 × 1.
2. The low-voltage Zener diode according to claim 1, wherein the high-concentration impurity-doped layer has a concentration of 0 ^{20 to} 1.0 × 10 ²² / cm ^3. 3. The low-voltage zener diode according to claim 1, wherein said surface layer is an outermost surface layer having a depth of about 0 to 1 μm. 4. The method for manufacturing a low-voltage zener diode according to claim 1, wherein said impurity-doped layer is formed after forming a guard ring. Method. 5. The method for manufacturing a low-voltage zener diode according to claim 1, wherein said impurity-doped layer is formed after forming a main junction. Production method. 6. A method for manufacturing a low-voltage zener diode according to claim 1, wherein said impurity-doped layer is formed after forming an ohmic layer on a surface opposite to a silicon substrate. Method of manufacturing Zener diode.