CN104810285A - Method and system for manufacturing planar VDMOS (vertical double diffused metal-oxide semiconductor field effect transistor) ring region - Google Patents
Method and system for manufacturing planar VDMOS (vertical double diffused metal-oxide semiconductor field effect transistor) ring region Download PDFInfo
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- CN104810285A CN104810285A CN201410032189.2A CN201410032189A CN104810285A CN 104810285 A CN104810285 A CN 104810285A CN 201410032189 A CN201410032189 A CN 201410032189A CN 104810285 A CN104810285 A CN 104810285A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims abstract description 33
- 230000005669 field effect Effects 0.000 title abstract description 5
- 239000004065 semiconductor Substances 0.000 title abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 4
- 150000004706 metal oxides Chemical class 0.000 title abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 32
- 238000001259 photo etching Methods 0.000 claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 8
- 238000002360 preparation method Methods 0.000 abstract description 8
- 238000005468 ion implantation Methods 0.000 abstract description 6
- 238000002513 implantation Methods 0.000 abstract description 3
- 238000002347 injection Methods 0.000 description 10
- 239000007924 injection Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 238000007630 basic procedure Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000003245 coal Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a method and a system for manufacturing a planar VDMOS (vertical double diffused metal-oxide semiconductor field effect transistor) ring region. The method is characterized by comprising the steps of completing photoetching, etching and first conduction type ion implantation for a terminal ring region; and completing photoetching, etching and second type of ion implantation for a cut-off ring region, wherein the second conduction type is the same as the conduction type of a VDMOS active region and is opposite to the first conduction type. According to the method and the system provided by the invention for manufacturing the VDMOS ring region, the manufacturing process of the ring region is optimized, etching and implantation for the terminal ring region is completed at first, and etching and implantation for the cut-off ring region is completed. The side wall morphology of the terminal ring region in effectively prevented from being affected by unclean photoresist removing in the preparation process of the cut-off ring region, thereby improving the side wall morphology of the terminal ring region, and solving technical problem of withstand voltage reduction and low reliability of devices.
Description
Technical field
The present invention relates to field of semiconductor fabrication processes, particularly relate to a kind of plane VDMOS ring district's manufacture method and system.
Background technology
Vertical double diffused metal-oxide semiconductor field effect transistor (VDMOS) has the advantage of bipolar transistor and common metal-oxide semiconductor field effect transistor (MOS) device concurrently.For modern plane VDMOS device; generally all adopt shallow buried coal structure; typical junction depth value is 4-7um; under so shallow junction depth; if device does not increase any terminal protection measure; puncture voltage is than ideally namely the withstand voltage of parallel plane knot is low by 50%, and therefore, terminal protection is a key technology of plane VDMOS device.At the fringe region of device, foreign atom has diffuseed to form cylinder knot or sphere knot in marginal zone, because these two kinds knots all exist curvature, depletion region also exists surface field curvature effect, causes this position electric field to be concentrated, punctures and will first appear at these regions.In order to improve device electric breakdown strength, usually using end ring technology, depletion region electric field is evened up laterally.And use the cut-off of N-type cut-off ring in outermost, as shown in Figure 1.
Therefore, end ring plays a very important role for device withstand voltage, and the change of any ring district pattern all can cause withstand voltage reduction.In plane VDMOS technique, after growth initial oxide layer (Fig. 2) and the etching completing field-effect transistor (JFET) district and injection (Fig. 3), first the photoetching of cut-off ring, etching and injection (Fig. 4, Fig. 5) can be carried out, then (Fig. 6) is removed photoresist by dry method+wet method+cleaning, finally carry out the photoetching of end ring, etching and injection (Fig. 7), to complete the whole manufacturing process in plane VDMOS ring district.
But in the above-mentioned steps of prior art, because the litho pattern Ke Kai district ending ring is less, and Implantation Energy and dosage are very large, easily cause the situation of removing photoresist unclean after injecting to occur.Follow-up make end ring time, when the initial oxide layer of ring-side wall is gone sordid glue to block, in the wet etch step of end ring, burr will be there is at the sidewall in end ring district, cause pattern irregular, as shown in Figure 8, Figure 9.This ring district burr phenomena all will play negative effect for the withstand voltage of device and reliability testing.
Summary of the invention
(1) technical problem that will solve
The invention provides a kind of plane VDMOS ring district's manufacture method and system, in manufacture ring district process, easily produce ring district burr phenomena to solve in prior art, cause the irregular technical problem of pattern.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of plane VDMOS ring district manufacture method, comprising:
Complete the photoetching in end ring district, etching and the first conductive type ion to inject;
Complete the photoetching in cut-off ring district, etching and the second conductive type ion to inject, described second conduction type is identical with plane VDMOS active area conduction type, contrary with the first conduction type.
Further,
Described first conduction type is N-type, and described second conduction type is P type.
Further,
Described first conduction type is P type, and described second conduction type is N-type.
Further,
Described end ring district comprises one or more end ring.
Further,
When described end ring district comprises multiple end ring, described end ring interval equal difference from inside to outside increases.
On the other hand, the present invention also provides a kind of plane VDMOS ring district manufacturing system, comprising:
End ring manufacturing cell, injects for completing the photoetching in end ring district, etching and the first conductive type ion;
Cut-off ring manufacturing cell, inject for completing the cut-off photoetching in ring district, etching and the second conductive type ion, described second conduction type is identical with plane VDMOS active area conduction type, contrary with the first conduction type.
Further,
Described first conduction type is N-type, and described second conduction type is P type.
Further,
Described first conduction type is P type, and described second conduction type is N-type.
Further,
Described end ring district comprises one or more end ring.
Further,
When described end ring district comprises multiple end ring, described end ring interval equal difference from inside to outside increases.
(3) beneficial effect
Visible, in plane VDMOS ring district's manufacture method provided by the invention and system, by optimizing ring district Making programme, first completing etching and the injection in end ring district, then completing etching and the injection in cut-off ring district again.Efficiently avoid end ring district sidewall profile and be subject to removing photoresist in cut-off ring district preparation process unclean impact, improve end ring district sidewall profile, solve the technical problem that device withstand voltage reduces and reliability is not high.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of end ring technology;
Fig. 2 is the schematic diagram growing initial oxide layer in plane VDMOS manufacturing process;
Fig. 3 is JFET district etching and injection schematic diagram in plane VDMOS manufacturing process;
Fig. 4 ends the photoetching of ring, etching and injects schematic diagram in plane VDMOS manufacturing process;
Fig. 5 ends the photoetching of ring, etching and injects vertical view in plane VDMOS manufacturing process;
Fig. 6 is the process schematic that removes photoresist in plane VDMOS manufacturing process;
Fig. 7 is photoetching, the etching of end ring in plane VDMOS manufacturing process and injects schematic diagram;
Fig. 8 is the ring district pattern vertical view of prior art in plane VDMOS manufacturing process;
Fig. 9 is the ring district pattern end view of prior art in plane VDMOS manufacturing process;
Figure 10 is the basic procedure schematic diagram of embodiment of the present invention plane VDMOS ring district manufacture method;
Figure 11 is the schematic flow sheet of a preferred embodiment of the invention plane VDMOS ring district manufacture method;
Figure 12 is the ring district pattern vertical view manufactured by a preferred embodiment of the invention plane VDMOS ring district manufacture method;
Figure 13 is the ring district pattern end view manufactured by a preferred embodiment of the invention plane VDMOS ring district manufacture method;
Figure 14 is the basic structure schematic diagram of embodiment of the present invention plane VDMOS ring district manufacturing system.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
First the embodiment of the present invention provides a kind of plane VDMOS ring district manufacture method, see Figure 10, comprising:
Step 1001: complete the photoetching in end ring district, etching and the first conductive type ion and inject.
Step 1002: complete the photoetching in cut-off ring district, etching and the second conductive type ion and inject, described second conduction type is identical with plane VDMOS active area conduction type, contrary with the first conduction type.
Visible, in the plane VDMOS ring district manufacture method that the embodiment of the present invention provides, by optimizing ring district Making programme, first completing etching and the injection in end ring district, then completing etching and the injection in cut-off ring district again.Efficiently avoid end ring district sidewall profile and be subject to removing photoresist in cut-off ring district preparation process unclean impact, improve end ring district sidewall profile, solve the technical problem that device withstand voltage reduces and reliability is not high.
In one embodiment of the invention, preferably, the first conduction type can be N-type, and correspondingly, the second conduction type can be P type.
In another embodiment of the present invention, preferably, the first conduction type can be P type, and correspondingly, the second conduction type can be N-type.
In one embodiment of the invention, the end ring structure in end ring district can be an end ring, or the mode that multiple end ring is arranged side by side.
In another embodiment of the present invention, in order to equipotential lines can be made progressively gently to end in plane VDMOS device surface, when end ring district comprises multiple end ring, preferably, the scheme that end ring gap can adopt equal difference to increase, namely interval equal difference from inside to outside increases.
Below specifically to prepare the ring district of a kind of plane VDMOS, describe the implementation procedure of the embodiment of the present invention in detail, see Figure 11:
Step 1101: complete the photoetching in end ring district, etching and P+ ion implantation.
Be in the plane VDMOS device of N-type an active area, the ion implantation type of end ring needs for P type.In this step, first carry out the photoetching in end ring district, etching and ion implantation process, wherein end ring is 5, and interval is from inside to outside followed successively by: 1um, 2um, 3um and 4um.
Step 1102: complete the photoetching in cut-off ring district, etching and N+ ion implantation.
In this step, after the preparation process completing end ring district, then carry out ending the preparation process in ring district, effectively can avoid ending in the preparation of ring district the problem of not net impacts end ring district pattern of removing photoresist like this.Prepare Hou Huan district pattern as shown in Figure 12 and Figure 13.
So far, then the preparation process in embodiment of the present invention plane VDMOS ring district is completed.
One embodiment of the invention also provides a kind of plane VDMOS ring district manufacturing system, as Figure 14, comprising:
End ring manufacturing cell 1401, injects for completing the photoetching in end ring district, etching and the first conductive type ion;
Cut-off ring manufacturing cell 1402, inject for completing the cut-off photoetching in ring district, etching and the second conductive type ion, described second conduction type is identical with plane VDMOS active area conduction type, contrary with the first conduction type.
In one embodiment of the invention, preferably, the first conduction type can be N-type, and correspondingly, the second conduction type can be P type.
In another embodiment of the present invention, preferably, the first conduction type can be P type, and correspondingly, the second conduction type can be N-type.
In one embodiment of the invention, the end ring structure in end ring district can be an end ring, or the mode that multiple end ring is arranged side by side.
In another embodiment of the present invention, in order to equipotential lines can be made progressively gently to end in plane VDMOS device surface, when end ring district comprises multiple end ring, preferably, the scheme that end ring gap can adopt equal difference to increase, namely interval equal difference from inside to outside increases.
Visible, the embodiment of the present invention has following beneficial effect:
In the plane VDMOS ring district's manufacture method provided in the embodiment of the present invention and system, by optimizing ring district Making programme, first completing etching and the injection in end ring district, then completing etching and the injection in cut-off ring district again.Efficiently avoid end ring district sidewall profile and be subject to removing photoresist in cut-off ring district preparation process unclean impact, improve end ring district sidewall profile, solve the technical problem that device withstand voltage reduces and reliability is not high.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (10)
1. a plane VDMOS ring district manufacture method, is characterized in that, comprising:
Complete the photoetching in end ring district, etching and the first conductive type ion to inject;
Complete the photoetching in cut-off ring district, etching and the second conductive type ion to inject, described second conduction type is identical with plane VDMOS active area conduction type, contrary with the first conduction type.
2. plane VDMOS ring district according to claim 1 manufacture method, is characterized in that:
Described first conduction type is N-type, and described second conduction type is P type.
3. plane VDMOS ring district according to claim 1 manufacture method, is characterized in that:
Described first conduction type is P type, and described second conduction type is N-type.
4. plane VDMOS ring district according to any one of claim 1 to 3 manufacture method, is characterized in that:
Described end ring district comprises one or more end ring.
5. plane VDMOS ring district according to claim 4 manufacture method, is characterized in that:
When described end ring district comprises multiple end ring, described end ring interval equal difference from inside to outside increases.
6. a plane VDMOS ring district manufacturing system, is characterized in that, comprising:
End ring manufacturing cell, injects for completing the photoetching in end ring district, etching and the first conductive type ion;
Cut-off ring manufacturing cell, inject for completing the cut-off photoetching in ring district, etching and the second conductive type ion, described second conduction type is identical with plane VDMOS active area conduction type, contrary with the first conduction type.
7. plane VDMOS ring district according to claim 6 manufacturing system, is characterized in that:
Described first conduction type is N-type, and described second conduction type is P type.
8. plane VDMOS ring district according to claim 6 manufacture method, is characterized in that:
Described first conduction type is P type, and described second conduction type is N-type.
9. the plane VDMOS ring district manufacture method according to any one of claim 6 to 8, is characterized in that:
Described end ring district comprises one or more end ring.
10. plane VDMOS ring district according to claim 9 manufacture method, is characterized in that:
When described end ring district comprises multiple end ring, described end ring interval equal difference from inside to outside increases.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410032189.2A CN104810285A (en) | 2014-01-23 | 2014-01-23 | Method and system for manufacturing planar VDMOS (vertical double diffused metal-oxide semiconductor field effect transistor) ring region |
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| CN201410032189.2A CN104810285A (en) | 2014-01-23 | 2014-01-23 | Method and system for manufacturing planar VDMOS (vertical double diffused metal-oxide semiconductor field effect transistor) ring region |
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Application publication date: 20150729 |