CN104810285A - Method and system for manufacturing planar VDMOS (vertical double diffused metal-oxide semiconductor field effect transistor) ring region - Google Patents
Method and system for manufacturing planar VDMOS (vertical double diffused metal-oxide semiconductor field effect transistor) ring region Download PDFInfo
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- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
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Abstract
本发明提供一种平面VDMOS环区制造方法和系统，包括：完成终端环区的光刻、刻蚀及第一导电类型离子注入；完成截止环区的光刻、刻蚀及第二导电类型离子注入，所述第二导电类型与平面VDMOS有源区导电类型相同，与第一导电类型相反。在本发明提供的平面VDMOS环区制造方法和系统中，通过优化环区制作流程，首先完成终端环区的刻蚀及注入，而后再完成截止环区的刻蚀及注入。有效地避免了终端环区侧壁形貌受到截止环区制备过程中去胶不净的影响，改善了终端环区侧壁形貌，解决了器件耐压降低和可靠性不高的技术问题。
The present invention provides a method and system for manufacturing a planar VDMOS ring region, including: completing the photolithography, etching and first conductivity type ion implantation of the terminal ring region; completing the photolithography, etching and second conductivity type ion implantation of the stop ring region implanted, the second conductivity type is the same as the conductivity type of the planar VDMOS active region, and opposite to the first conductivity type. In the planar VDMOS ring region manufacturing method and system provided by the present invention, by optimizing the ring region manufacturing process, the etching and implantation of the terminal ring region are completed first, and then the etching and implantation of the stop ring region are completed. It effectively avoids the sidewall morphology of the terminal ring region from being affected by the unclean glue removal during the preparation process of the stop ring region, improves the sidewall morphology of the terminal ring region, and solves the technical problems of reduced withstand voltage and low reliability of the device.
Description
技术领域technical field
本发明涉及半导体制造工艺领域，尤其涉及一种平面VDMOS环区制造方法和系统。The invention relates to the field of semiconductor manufacturing technology, in particular to a method and system for manufacturing a planar VDMOS ring area.
背景技术Background technique
垂直双扩散金属-氧化物半导体场效应晶体管（VDMOS）兼有双极晶体管和普通金属-氧化物半导体场效应晶体管（MOS）器件的优点。对于现代平面VDMOS器件来说，一般都采用浅平面结结构，典型的结深值为4-7um，在这么浅的结深下，器件如果没有增加任何终端保护措施，击穿电压要比理想情况下即平行平面结的耐压值低50%，因此，终端保护是平面VDMOS器件的一项关键技术。在器件的边缘区域，杂质原子在边缘区扩散形成了柱面结或球面结，由于这两种结均存在曲率，耗尽区也存在表面电场曲率效应，导致该位置电场集中，击穿将首先出现在这些区域。为了提高器件击穿电压，通常使用终端环技术，将耗尽区电场向外侧拉平。并在最外侧使用N型截止环截止，如图1所示。Vertical double-diffused metal-oxide semiconductor field-effect transistors (VDMOS) combine the advantages of bipolar transistors and ordinary metal-oxide semiconductor field-effect transistor (MOS) devices. For modern planar VDMOS devices, a shallow planar junction structure is generally used, and the typical junction depth is 4-7um. Under such a shallow junction depth, if no terminal protection measures are added to the device, the breakdown voltage will be lower than ideal. The next is that the withstand voltage value of the parallel planar junction is 50% lower. Therefore, terminal protection is a key technology for planar VDMOS devices. In the edge region of the device, impurity atoms diffuse in the edge region to form a cylindrical junction or a spherical junction. Since the two junctions have curvature, the depletion region also has the curvature effect of the surface electric field, which leads to the concentration of the electric field at this position, and the breakdown will first appear in these areas. In order to improve the breakdown voltage of the device, the terminal ring technology is usually used to flatten the electric field of the depletion region to the outside. And use the N-type cut-off ring on the outermost side, as shown in Figure 1.
因此，终端环对于器件耐压有很重要的作用，任何环区形貌的变化都会引起耐压降低。在平面VDMOS工艺中，在生长初始氧化层（图2）和完成场效应晶体管（JFET）区的刻蚀和注入（图3）之后，首先会进行截止环的光刻、刻蚀及注入（图4、图5），然后通过干法+湿法+清洗去胶（图6），最后进行终端环的光刻、刻蚀及注入（图7），以完成平面VDMOS环区的整个制作过程。Therefore, the terminal ring plays an important role in the withstand voltage of the device, and any change in the shape of the ring region will cause a decrease in the withstand voltage. In the planar VDMOS process, after growing the initial oxide layer (Figure 2) and completing the etching and implantation of the field-effect transistor (JFET) region (Figure 3), the photolithography, etching and implantation of the stop ring (Figure 3) are first performed. 4. Figure 5), then through dry method + wet method + cleaning and deglue (Figure 6), and finally perform photolithography, etching and implantation of the terminal ring (Figure 7) to complete the entire manufacturing process of the planar VDMOS ring area.
但是，在现有技术的上述步骤中，由于截止环的光刻图形刻开区较小，而注入能量和剂量很大，易导致注入后去胶不净的情况出现。在后续做终端环时，当环侧壁的初始氧化层被去不干净的胶遮挡，在终端环的湿法腐蚀步骤中，将会在终端环区的侧壁出现毛刺，导致形貌不规则，如图8、图9所示。这种环区毛刺现象对于器件的耐压及可靠性测试都将起到负面作用。However, in the above-mentioned steps of the prior art, since the photolithography pattern of the stop ring is small, the implantation energy and dose are large, which easily leads to the situation that the glue is not clean after implantation. When the terminal ring is made later, when the initial oxide layer on the side wall of the ring is blocked by the unclean glue, in the wet etching step of the terminal ring, burrs will appear on the side wall of the terminal ring area, resulting in irregular morphology , as shown in Figure 8 and Figure 9. This burr phenomenon in the ring area will have a negative effect on the withstand voltage and reliability test of the device.
发明内容Contents of the invention
（一）要解决的技术问题(1) Technical problems to be solved
本发明提供一种平面VDMOS环区制造方法和系统，以解决现有技术中在制造环区过程中易产生环区毛刺现象，导致形貌不规则的技术问题。The invention provides a planar VDMOS ring area manufacturing method and system to solve the technical problem in the prior art that ring area burrs are easily generated during the ring area manufacturing process, resulting in irregular appearance.
（二）技术方案(2) Technical solutions
为解决上述技术问题，本发明提供一种平面VDMOS环区制造方法，包括：In order to solve the above technical problems, the present invention provides a method for manufacturing a planar VDMOS ring region, including:
完成终端环区的光刻、刻蚀及第一导电类型离子注入；Complete the photolithography, etching and ion implantation of the first conductivity type in the terminal ring region;
完成截止环区的光刻、刻蚀及第二导电类型离子注入，所述第二导电类型与平面VDMOS有源区导电类型相同，与第一导电类型相反。The photolithography, etching and second conductivity type ion implantation of the stop ring region are completed, the second conductivity type is the same as the conductivity type of the planar VDMOS active region and opposite to the first conductivity type.
进一步地，further,
所述第一导电类型为N型，所述第二导电类型为P型。The first conductivity type is N type, and the second conductivity type is P type.
进一步地，further,
所述第一导电类型为P型，所述第二导电类型为N型。The first conductivity type is P-type, and the second conductivity type is N-type.
进一步地，further,
所述终端环区包括一个或多个终端环。The terminal ring region includes one or more terminal rings.
进一步地，further,
当所述终端环区包括多个终端环时，所述终端环由内而外的间隔等差增加。When the terminal ring area includes a plurality of terminal rings, the intervals of the terminal rings increase equally from inside to outside.
另一方面，本发明还提供一种平面VDMOS环区制造系统，包括：On the other hand, the present invention also provides a planar VDMOS ring area manufacturing system, including:
终端环制造单元，用于完成终端环区的光刻、刻蚀及第一导电类型离子注入；The terminal ring manufacturing unit is used to complete the photolithography, etching and ion implantation of the first conductivity type in the terminal ring region;
截止环制造单元，用于完成截止环区的光刻、刻蚀及第二导电类型离子注入，所述第二导电类型与平面VDMOS有源区导电类型相同，与第一导电类型相反。The stop ring manufacturing unit is used to complete photolithography, etching and second conductivity type ion implantation of the stop ring region. The second conductivity type is the same as the conductivity type of the planar VDMOS active region and opposite to the first conductivity type.
进一步地，further,
所述第一导电类型为N型，所述第二导电类型为P型。The first conductivity type is N type, and the second conductivity type is P type.
进一步地，further,
所述第一导电类型为P型，所述第二导电类型为N型。The first conductivity type is P-type, and the second conductivity type is N-type.
进一步地，further,
所述终端环区包括一个或多个终端环。The terminal ring region includes one or more terminal rings.
进一步地，further,
当所述终端环区包括多个终端环时，所述终端环由内而外的间隔等差增加。When the terminal ring area includes a plurality of terminal rings, the intervals of the terminal rings increase equally from inside to outside.
（三）有益效果(3) Beneficial effects
可见，在本发明提供的平面VDMOS环区制造方法和系统中，通过优化环区制作流程，首先完成终端环区的刻蚀及注入，而后再完成截止环区的刻蚀及注入。有效地避免了终端环区侧壁形貌受到截止环区制备过程中去胶不净的影响，改善了终端环区侧壁形貌，解决了器件耐压降低和可靠性不高的技术问题。It can be seen that in the planar VDMOS ring region manufacturing method and system provided by the present invention, by optimizing the ring region manufacturing process, the etching and implantation of the terminal ring region are completed first, and then the etching and implantation of the stop ring region are completed. It effectively avoids the sidewall morphology of the terminal ring region from being affected by the unclean glue removal during the preparation process of the stop ring region, improves the sidewall morphology of the terminal ring region, and solves the technical problems of reduced withstand voltage and low reliability of the device.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.
图1是终端环技术的结构示意图；FIG. 1 is a schematic structural diagram of a termination ring technology;
图2是平面VDMOS制造工艺中生长初始氧化层的示意图；2 is a schematic diagram of growing an initial oxide layer in a planar VDMOS manufacturing process;
图3是平面VDMOS制造工艺中JFET区刻蚀和注入示意图；3 is a schematic diagram of etching and implantation of the JFET region in the planar VDMOS manufacturing process;
图4是平面VDMOS制造工艺中截止环的光刻、刻蚀及注入示意图；4 is a schematic diagram of lithography, etching and implantation of the stop ring in the planar VDMOS manufacturing process;
图5是平面VDMOS制造工艺中截止环的光刻、刻蚀及注入俯视图；5 is a top view of photolithography, etching and implantation of the stop ring in the planar VDMOS manufacturing process;
图6是平面VDMOS制造工艺中去胶过程示意图；6 is a schematic diagram of the deglue process in the planar VDMOS manufacturing process;
图7是平面VDMOS制造工艺中终端环的光刻、刻蚀及注入示意图；7 is a schematic diagram of photolithography, etching and implantation of the terminal ring in the planar VDMOS manufacturing process;
图8是平面VDMOS制造工艺中现有技术的环区形貌俯视图；FIG. 8 is a top view of the topography of the ring area in the prior art in the planar VDMOS manufacturing process;
图9是平面VDMOS制造工艺中现有技术的环区形貌侧视图；FIG. 9 is a side view of the topography of the ring region in the prior art in the planar VDMOS manufacturing process;
图10是本发明实施例平面VDMOS环区制造方法的基本流程示意图；FIG. 10 is a schematic flowchart of a method for manufacturing a planar VDMOS ring region according to an embodiment of the present invention;
图11是本发明一个优选实施例平面VDMOS环区制造方法的流程示意图；FIG. 11 is a schematic flow chart of a method for manufacturing a planar VDMOS ring region in a preferred embodiment of the present invention;
图12是本发明一个优选实施例平面VDMOS环区制造方法所制造的环区形貌俯视图；Fig. 12 is a top view of the topography of the ring area manufactured by the planar VDMOS ring area manufacturing method in a preferred embodiment of the present invention;
图13是本发明一个优选实施例平面VDMOS环区制造方法所制造的环区形貌侧视图；Fig. 13 is a side view of the topography of the ring area manufactured by the planar VDMOS ring area manufacturing method in a preferred embodiment of the present invention;
图14是本发明实施例平面VDMOS环区制造系统的基本结构示意图。FIG. 14 is a schematic diagram of the basic structure of a planar VDMOS ring manufacturing system according to an embodiment of the present invention.
具体实施方式Detailed ways
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
本发明实施例首先提供一种平面VDMOS环区制造方法，参见图10，包括：Embodiments of the present invention firstly provide a method for manufacturing a planar VDMOS ring region, see FIG. 10 , including:
步骤1001：完成终端环区的光刻、刻蚀及第一导电类型离子注入。Step 1001: Complete photolithography, etching and ion implantation of the first conductivity type in the terminal ring region.
步骤1002：完成截止环区的光刻、刻蚀及第二导电类型离子注入，所述第二导电类型与平面VDMOS有源区导电类型相同，与第一导电类型相反。Step 1002: Complete photolithography, etching and second conductivity type ion implantation of the stop ring region, the second conductivity type is the same as the conductivity type of the planar VDMOS active region, and opposite to the first conductivity type.
可见，在本发明实施例提供的平面VDMOS环区制造方法中，通过优化环区制作流程，首先完成终端环区的刻蚀及注入，而后再完成截止环区的刻蚀及注入。有效地避免了终端环区侧壁形貌受到截止环区制备过程中去胶不净的影响，改善了终端环区侧壁形貌，解决了器件耐压降低和可靠性不高的技术问题。It can be seen that in the method for manufacturing the planar VDMOS ring region provided by the embodiment of the present invention, by optimizing the manufacturing process of the ring region, the etching and implantation of the terminal ring region are completed first, and then the etching and implantation of the stop ring region are completed. It effectively avoids the sidewall morphology of the terminal ring region from being affected by the unclean glue removal during the preparation process of the stop ring region, improves the sidewall morphology of the terminal ring region, and solves the technical problems of reduced withstand voltage and low reliability of the device.
在本发明的一个实施例中，优选地，第一导电类型可以为N型，相应地，第二导电类型可以为P型。In an embodiment of the present invention, preferably, the first conductivity type may be N type, and correspondingly, the second conductivity type may be P type.
在本发明的另一个实施例中，优选地，第一导电类型可以为P型，相应地，第二导电类型可以为N型。In another embodiment of the present invention, preferably, the first conductivity type may be P type, and correspondingly, the second conductivity type may be N type.
在本发明的一个实施例中，终端环区的终端环结构可以为一个终端环，或多个终端环并列的方式。In an embodiment of the present invention, the terminal ring structure of the terminal ring area may be one terminal ring, or a parallel arrangement of multiple terminal rings.
在本发明的另一个实施例中，为了能使等势线逐步平缓地终结于平面VDMOS器件表面，当终端环区包括多个终端环时，优选地，终端环间隙可以采用等差增加的方案，即由内而外的间隔等差增加。In another embodiment of the present invention, in order to enable the equipotential lines to gradually and gently terminate on the surface of the planar VDMOS device, when the terminal ring area includes multiple terminal rings, preferably, the terminal ring gap can adopt a scheme of increasing the difference between the terminal rings , that is, the interval increases from the inside to the outside.
下面以具体制备一种平面VDMOS的环区为例，来详细说明本发明实施例的实现过程，参见图11：The implementation process of the embodiment of the present invention will be described in detail below by taking the specific preparation of a planar VDMOS ring region as an example, see FIG. 11 :
步骤1101：完成终端环区的光刻、刻蚀及P+离子注入。Step 1101: Complete the photolithography, etching and P+ ion implantation of the terminal ring region.
在一个有源区为N型的平面VDMOS器件中，终端环的离子注入类型需要为P型。在本步骤中，首先进行终端环区的光刻、刻蚀和离子注入过程，其中终端环为5个，由内而外的间隔依次为：1um、2um、3um和4um。In a planar VDMOS device whose active region is N-type, the ion implantation type of the termination ring needs to be P-type. In this step, the photolithography, etching and ion implantation of the terminal ring area are firstly carried out, wherein there are 5 terminal rings, and the intervals from inside to outside are: 1um, 2um, 3um and 4um.
步骤1102：完成截止环区的光刻、刻蚀及N+离子注入。Step 1102: Complete the photolithography, etching and N+ ion implantation of the stop ring region.
本步骤中，在完成终端环区的制备过程后，再进行截止环区的制备过程，这样可以有效避免截止环区制备中去胶不净影响终端环区形貌的问题。制备完成后环区形貌如图12、图13所示。In this step, after the preparation process of the terminal ring region is completed, the preparation process of the cut-off ring region is carried out, which can effectively avoid the problem that the shape of the terminal ring region is affected by the unclean removal of glue in the preparation of the cut-off ring region. Figure 12 and Figure 13 show the morphology of the ring area after the preparation is completed.
至此，则完成了本发明实施例平面VDMOS环区的制备过程。So far, the preparation process of the planar VDMOS ring region of the embodiment of the present invention is completed.
本发明一个实施例还提供一种平面VDMOS环区制造系统，如图14，包括：An embodiment of the present invention also provides a planar VDMOS ring manufacturing system, as shown in Figure 14, including:
终端环制造单元1401，用于完成终端环区的光刻、刻蚀及第一导电类型离子注入；A terminal ring manufacturing unit 1401, configured to complete the photolithography, etching and first conductivity type ion implantation of the terminal ring region;
截止环制造单元1402，用于完成截止环区的光刻、刻蚀及第二导电类型离子注入，所述第二导电类型与平面VDMOS有源区导电类型相同，与第一导电类型相反。The stop ring manufacturing unit 1402 is used to complete photolithography, etching and second conductivity type ion implantation of the stop ring region. The second conductivity type is the same as the conductivity type of the planar VDMOS active region and opposite to the first conductivity type.
在本发明的一个实施例中，优选地，第一导电类型可以为N型，相应地，第二导电类型可以为P型。In an embodiment of the present invention, preferably, the first conductivity type may be N type, and correspondingly, the second conductivity type may be P type.
在本发明的另一个实施例中，优选地，第一导电类型可以为P型，相应地，第二导电类型可以为N型。In another embodiment of the present invention, preferably, the first conductivity type may be P type, and correspondingly, the second conductivity type may be N type.
在本发明的一个实施例中，终端环区的终端环结构可以为一个终端环，或多个终端环并列的方式。In an embodiment of the present invention, the terminal ring structure of the terminal ring area may be one terminal ring, or a parallel arrangement of multiple terminal rings.
在本发明的另一个实施例中，为了能使等势线逐步平缓地终结于平面VDMOS器件表面，当终端环区包括多个终端环时，优选地，终端环间隙可以采用等差增加的方案，即由内而外的间隔等差增加。In another embodiment of the present invention, in order to enable the equipotential lines to gradually and gently terminate on the surface of the planar VDMOS device, when the terminal ring area includes multiple terminal rings, preferably, the terminal ring gap can adopt a scheme of increasing the difference between the terminal rings , that is, the interval increases from the inside to the outside.
可见，本发明实施例具有如下有益效果：It can be seen that the embodiments of the present invention have the following beneficial effects:
在本发明实施例提供的平面VDMOS环区制造方法和系统中，通过优化环区制作流程，首先完成终端环区的刻蚀及注入，而后再完成截止环区的刻蚀及注入。有效地避免了终端环区侧壁形貌受到截止环区制备过程中去胶不净的影响，改善了终端环区侧壁形貌，解决了器件耐压降低和可靠性不高的技术问题。In the planar VDMOS ring region manufacturing method and system provided by the embodiments of the present invention, by optimizing the ring region manufacturing process, the etching and implantation of the terminal ring region are completed first, and then the etching and implantation of the stop ring region are completed. It effectively avoids the sidewall morphology of the terminal ring region from being affected by the unclean glue removal during the preparation process of the stop ring region, improves the sidewall morphology of the terminal ring region, and solves the technical problems of reduced withstand voltage and low reliability of the device.
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.
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