JP3557096B2 - Signal input circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a signal input circuit that outputs a binary signal serving as a basis for executing predetermined signal processing according to the level of an AC input signal.
[0002]
[Prior art]
FIG. 2 is a circuit block diagram showing a conventional signal processing circuit.
[0003]
In FIG. 2, resistors (1), (2), (3), (4), (5), and (6) are connected in series between a power supply VDD and a ground VSS, respectively, and the resistors (1), (2), ( 3) DC voltages V1, V2 and V3 are output from the connection points of (4), (5) and (6). The DC voltage has a relationship of V3 <V1 <V2. One end of the capacitive coupling capacitor (7) is connected to a connection point between the resistors (1) and (2). That is, the capacitive coupling capacitor (7) removes the DC component of the AC input signal Vin and passes only the AC component. Therefore, the AC input signal Vin changes while being superimposed on the DC voltage V1 at the connection point between the resistors (1) and (2). The comparator (8) has a negative terminal connected to a connection point of the resistors (3) and (4), and a positive terminal connected to a connection point of the resistors (1) and (2). That is, the comparator (8) relatively compares the magnitudes of the DC voltages V1 and V2, and outputs a high level when the DC voltage V1 becomes higher than the DC voltage V2. On the other hand, the comparator (9) has a negative terminal connected to a connection point of the resistors (1) and (2), and a positive terminal connected to a connection point of the resistors (5) and (6). That is, the comparator (9) relatively compares the magnitudes of the DC voltages V1 and V3, and outputs a high level when the DC voltage V1 becomes lower than the DC voltage V3. Therefore, the potential difference between the DC voltages V2 and V3 becomes a hysteresis with respect to the AC input signal Vin, and the comparator determines whether the level of the AC input signal Vin is DC voltage V2 or more, DC voltage V3 or more and less than DC voltage V2, or less than DC voltage V3. (8) Detected by (9). The S (set) terminal of the RS flip-flop (10) is connected to the output terminal of the comparator (8), and the R (reset) terminal is connected to the output terminal of the comparator (9). Therefore, when the level of the AC input signal Vin becomes equal to or higher than the DC voltage V2, the RS flip-flop (10) is set by the high level output of the comparator (8) and outputs a high level from the Q (output) terminal. When the level of the AC input signal Vin becomes lower than the DC voltage V3, the RS flip-flop (10) is reset by the high level output of the comparator (9) and outputs a low level from the Q terminal. When the level of the AC input signal Vin is equal to or higher than the DC voltage V3 and lower than the DC voltage V2, the RS flip-flop (10) is set and reset according to the low level output of the comparators (8) and (9). And the Q terminal output keeps the previous state. The hysteresis is used for detecting the amplitude of the AC input signal Vin.
[0004]
FIG. 3 is a time chart showing the operation of FIG. For example, when signal processing is performed by detecting the high level of the output Vout of the RS flip-flop (10), the signal processing is performed during a period from when the level of the AC input signal Vin becomes equal to or higher than the DC voltage V2 until it becomes lower than the DC voltage V3. , The signal processing is performed.
[0005]
[Problems to be solved by the invention]
However, the conventional signal processing circuit has a large number of components (the number of MOS transistors) of the comparators (8) and (9) and the RS flip-flop (10), so that the cost is high and the chip area becomes large even when integrated. There was a problem. It is desirable that the DC voltage V1 on which the AC input signal Vin is superimposed is intermediate between the DC voltages V2 and V3. However, since the characteristics of the resistors (1) and (2) and the characteristics of the MOS transistors vary on a chip, they vary. At present, it is difficult to set the DC voltage V1 to an intermediate value between the DC voltages V2 and V3 by adjusting the resistance ratio of the resistors (1) and (2). For example, it is difficult to set the DC voltage V1 to a certain level of the AC input signal Vin. When the noise is superimposed, there is a problem that the output signal Vout may change at a point where the output signal Vout should not change, and may malfunction against the user's intention. In addition, since the conventional signal processing circuit is constantly operating, there is a problem that current consumption is increased.
[0006]
Therefore, an object of the present invention is to provide a signal processing circuit capable of realizing a small chip area, stable operation, and low current consumption.
[0007]
[Means for Solving the Problems]
The present invention has been made to solve the above problems, and has a first threshold voltage and a second threshold voltage lower than the first threshold voltage, and according to the level of an AC input signal. An input circuit for setting one of the first and second threshold voltages, a conversion circuit for converting an output of the input circuit into a binary signal having a high level and a low level, and superimposing the AC input signal A bias circuit that generates a midpoint DC voltage of the first and second threshold voltages, a through current stop circuit that stops a through current of at least one of the input circuit and the bias circuit, the input circuit or A fixed circuit for fixing the output of the conversion circuit to one logical value when the through current of the bias circuit is stopped.
[0008]
A first bias circuit connected to a path of the AC input signal and configured to generate a midpoint DC voltage of the first and second threshold voltages for superimposing the AC input signal; And a second bias circuit that operates the first bias circuit independently of a signal path.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
The details of the present invention will be specifically described with reference to the drawings.
[0010]
FIG. 1 is a circuit diagram showing a signal processing circuit of the present invention.
[0011]
In FIG. 1, P-type MOSFETs (11) and (12) and N-type MOSFETs (13) and (14) constitute a first bias circuit, and drains of four MOSFETs (11), (12), (13) and (14). The source paths are connected in series, the source of the P-type MOSFET (11) therein is connected to the power supply VDD, and the gates of the four MOSFETs (11) (12) (13) (14) are connected in common. Has become. The P-type MOSFETs (15) and (16) and the N-type MOSFETs (17) and (18) constitute a second bias circuit, and the drain-source paths of the four MOSFETs (15), (16), (17) and (18) are connected in series. The source of the P-type MOSFET (15) connected thereto is connected to the power supply VDD, and the gates of the four MOSFETs (15) (16) (17) (18) are commonly connected and the P-type MOSFET (16) And the common drain of the N-type MOSFET (17). The common drain of the P-type MOSFET (16) and the N-type MOSFET (17) is connected to the common gate of the P-type MOSFETs (11) and (12) and the N-type MOSFETs (13) and (14). It operates with the output of the second bias circuit, and outputs a DC voltage V1 from the common drain of the P-type MOSFET (12) and the N-type MOSFET (13) constituting the first bias circuit. The capacitive coupling capacitor (19) removes the DC component of the AC input signal Vin and passes the AC component. That is, the AC input signal Vin is output from the common drain of the P-type MOSFET (12) and the N-type MOSFET (13) while being superimposed on the DC voltage V1.
[0012]
Since the first bias circuit operates with the output of the second bias circuit completely independent of the path of the AC input signal Vin and outputs the DC voltage V1, the first bias circuit is affected by the change of the AC input signal Vin. A stable DC voltage V1 is output without receiving.
[0013]
The P-type MOSFETs (20) and (21), the N-type MOSFETs (22) and (23), the NAND gate (24), the P-type MOSFET (25), and the N-type MOSFET (26) constitute an input circuit. As will be described later, when the signal input circuit of FIG. 1 operates, one input signal of the NAND gate (24) is at a high level. The drain-source paths of the four MOSFETs (20) (21) (22) (23) are connected in series and the source of the P-type MOSFET (20) therein is connected to the power supply VDD, and the four MOSFETs (20) (21) The gates of (22) and (23) are commonly connected and connected to the common drain of the preceding P-type MOSFET (12) and N-type MOSFET (13), and the P-type MOSFET (21) and the N-type MOSFET (22) ) Is connected to the other input terminal of the NAND gate (24). The P-type MOSFET (25) is connected in parallel with the P-type MOSFET (20) and provides a first threshold voltage. The N-type MOSFET (26) is connected in parallel with the N-type MOSFET (23), and provides a second threshold voltage. The output terminal of the NAND gate (24) is connected to the gates of the P-type MOSFET (25) and the N-type MOSFET (26).
[0014]
The inverter (27) inverts the logic of the preceding NAND gate (24). That is, when the AC input signal Vin is higher than the DC voltage V1, the output signal Vout is at a low level, and when the AC input signal Vin is lower than the DC voltage V1, the output signal Vout is at a high level.
[0015]
The N-type MOSFET (28) constitutes a through current stopping circuit for stopping a through current of the first bias circuit, the second bias circuit, and the input circuit, and the drains of the N-type MOSFETs (14) (18) (23) (26) ) And the source is grounded. The NAND gate (24) and the inverter (27) form a fixed circuit. A control signal is supplied to the gate of the N-type MOSFET (28) and one input terminal of the NAND gate (24). That is, when the control signal is at a high level, the signal processing circuit operates normally, but when the control signal is at a low level, the first bias circuit, the second bias circuit, The through current of the input circuit is stopped to reduce current consumption, and the NAND gate (24) is closed to fix the output of the inverter (27) to a low level regardless of the state of the AC input signal Vin.
[0016]
In recent integrated circuits, there is a high tendency to integrate a plurality of functions on one chip to form a system. Depending on the operation mode, some functions may be operated and the remaining functions may be stopped. In this case, if a means for interrupting the current path of the remaining functions is not provided, current consumption is unnecessarily increased, which is not preferable. Therefore, by using the control signal to control the N-type MOSFET (28) and the NAND gate (24), the current consumption of the signal input circuit can be reduced.
[0017]
Hereinafter, the operation when the control signal is at the high level will be described.
[0018]
First, when the AC input signal Vin changes to a side lower than the DC voltage V1, the P-type MOSFETs (20) and (21) are turned on, the input terminal of the inverter (24) is connected to the power supply VDD, and the P-type MOSFET (25) is connected. ) Is turned on in response to the low level output of the NAND gate (24). Therefore, the combined impedance of the P-type MOSFETs (20), (21) and (25) becomes smaller than the combined impedance of the P-type MOSFETs (20) and (21), and the input voltage of the NAND gate (24) increases. That is, the first threshold voltage is set in the input circuit. When the AC input signal Vin changes to a side higher than the DC voltage V1, the N-type MOSFETs (22) and (23) are turned on, the input terminal of the NAND gate (24) is connected to the ground VSS, and the N-type MOSFET ( 26) receives the high level output of the inverter (24) and turns on. Therefore, the combined impedance of the N-type MOSFETs (22) (23) and (26) becomes smaller than the combined impedance of the N-type MOSFETs (22) and (23), and the input voltage of the NAND gate (24) decreases. That is, the second threshold voltage is set in the input circuit.
[0019]
From the above,
(1) Since the first or second threshold voltage is set, the fluctuation of the AC input signal Vin can be absorbed by the hysteresis within the range of the first and second threshold voltages.
[0020]
{Circle around (2)} Since the number of elements is smaller than in the past, the chip area can be reduced when the signal input circuit is integrated.
[0021]
{Circle around (3)} Since the bias circuit is composed of only MOS transistors without using a resistor, the characteristics of the MOS transistors can be made uniform by setting the size of all the MOS transistors equal, and the reference voltage V1 is set to an intermediate value of the hysteresis width. Thus, malfunction of the signal input circuit can be prevented.
[0022]
(4) Since the reference voltage V1 which is not affected by the change of the AC input signal Vin can be output, the stable operation of the signal input circuit can be realized.
[0023]
{Circle around (5)} By using the control signal, the through current of the bias circuit and the input circuit is stopped according to the operation state, and the current consumption can be reduced.
This has the effect.
[0024]
【The invention's effect】
According to the present invention, since the first or second threshold voltage is set, the fluctuation of the AC input signal can be absorbed by the hysteresis within the range of the first and second threshold voltages. Further, since the number of elements is smaller than in the conventional case, the chip area can be reduced when the signal input circuit is integrated. Also, since the bias circuit is composed of only MOS transistors without using a resistor, the characteristics of the MOS transistors can be made uniform by setting the size of all the MOS transistors to be equal, and the superimposed voltage of the AC input signal is set to an intermediate value of the hysteresis width. To prevent malfunction of the signal input circuit. In addition, since a superimposed voltage that is not affected by a change in the AC input signal can be output, a stable operation of the signal input circuit can be realized. The current consumption can be reduced by stopping the through current of the bias circuit and the input circuit according to the operation state. Such advantages can be obtained.
[Brief description of the drawings]
FIG.
FIG. 2 is a circuit diagram illustrating a signal input circuit according to the present invention.
FIG. 2
FIG. 9 is a circuit diagram showing a conventional signal input circuit.
FIG. 3
3 is a time chart showing the operation of FIG.
[Explanation of symbols]
(11) (12) (13) (14) First bias circuit (15) (16) (17) (18) Second bias circuit (20) (21) (22) (23) (24) (25) (26) Input circuit (28) N-type MOSFET

Claims (2)

An input circuit having a first threshold voltage and a second threshold voltage lower than the first threshold voltage, wherein one of the first and second threshold voltages is set according to the level of an AC input signal When,
A conversion circuit for converting the output of the input circuit into a binary signal comprising a high level and a low level;
A bias circuit that generates a midpoint DC voltage between the first and second threshold voltages on which the AC input signal is superimposed;
A through current stop circuit for stopping at least one of the through current of the input circuit or the bias circuit;
When the through current of the input circuit or the bias circuit is stopped, a fixed circuit that fixes the output of the conversion circuit to one logical value,
A signal input circuit comprising: A first bias circuit that is connected to a path of the AC input signal and generates a midpoint DC voltage of the first and second threshold voltages that superimposes the AC input signal; 2. The signal input circuit according to claim 1, further comprising a second bias circuit that operates the first bias circuit independently of a path.

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