JP3540946B2 - Voltage detection circuit - Google Patents

Voltage detection circuit Download PDF

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Publication number
JP3540946B2
JP3540946B2 JP22167098A JP22167098A JP3540946B2 JP 3540946 B2 JP3540946 B2 JP 3540946B2 JP 22167098 A JP22167098 A JP 22167098A JP 22167098 A JP22167098 A JP 22167098A JP 3540946 B2 JP3540946 B2 JP 3540946B2
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Japan
Prior art keywords
voltage
circuit
power supply
channel mosfet
gate
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JP22167098A
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Japanese (ja)
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JP2000055946A (en
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聡 菅原
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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Description

【0001】
【発明の属する技術分野】
この発明は、主回路の電源電圧が低電圧となったことを検出する電圧検出回路に関する。
【0002】
【従来の技術】
電子回路を誤動作なく動作させるためには、その電源電圧の確保が必要である。また、電源電圧が電子回路の駆動に必要な値以下になった場合、電子回路を停止することが要求される。以上のことを実現するためには、常時、電源電圧を監視する必要がある。
【0003】
図5は従来の電圧検出回路である。主回路の電源電圧と同一の電圧検出回路の電源の高電位側VDD(端子または電圧を表す)に、定電流を流す回路を構成するpチャネルMOSFETであるM11とM12およびM17のソースが接続している。M11は定電流源12を介して接地側GND(端子または電圧を表す)に接続されている。基準電圧VREF を分圧抵抗R11およびR12で分圧し、分圧点の電圧である分圧電圧V13が発生する。M12のドレインがpチャネルMOSFETであるM13とM14のソースと接続し、それぞれのドレインはnチャネルMOSFETであるM15とM16のドレインに接続し、M15とM16のソースはGNDに接続する。VDDとGNDの間にVDDの電圧を分圧抵抗R13およびR14で分圧し、分圧点の電圧である分圧電圧V14が発生する。さらに、M17とnチャネルMOSFETであるM18がVDDとGNDの間に接続され、M17とM18の接続点が電圧検出回路の出力VOUT (端子または電圧を表す)となる。前記のV13は入力電圧VINで、M13のゲート電圧となり、V14はM14のゲート電圧となる。M14のドレインはM18のゲートと接続している。M11、M12およびM17のゲートがそれぞれ接続し、M11のゲートはM11のドレインに接続している。前記のVOUT は図示しない主回路に接続される。
【0004】
この図において、VDDは検出対象である電源電圧でもあり、VREF は基準電圧である。M13のゲート電圧V13(=VIN) は、基準電圧VREF を分圧抵抗R11とR12で分圧した値となり、V13=VREF ×R12/(R11+R12)となる。また、M14のゲート電圧V14は、電源電圧VDDを抵抗R13とR14で分圧した値となり、V14=VDD×R14/(R13+R14)となる。V13<V14の場合、つまり、VDD>VREF ×R12(R13+R14)/〔R14(R11+R12)〕の場合、出力電圧VOUT がVDDとなる。V13>V14の場合、つまり、VDD<VREF ×R12(R13+R14)/〔R14(R11+R12)〕の場合、出力電圧VOUT が0Vとなる。このように、電源電圧を基準電圧と比較することにより、電源電圧が低電圧になることを検出できる。
【0005】
【発明が解決しようとする課題】
しかし、図5に示す従来の電圧検出回路では、MOSFETの数が5個もある比較器を用いるため、回路構成が複雑である。主回路である電子回路の電源電圧が低下すると、主回路の電源が電圧検出回路に供給されているため、電圧検出回路の電源電圧も低下する。この従来回路の比較器は、定電流源を構成するM12と差動回路のM13とM14および能動負荷であるM15およびM16で構成され、電源の高電位側から接地側まで、3個のMOSFETが直列に接続されている。これら3個の直列に接続されるMOSFETは電流が一定となる飽和領域で動作させる。そのため、1個のMOSFETに対して、ソース・ドレイン間の電圧を0.6V程度の電圧が印加される必要があり、3個のMOSFETでは電源の高電位側と接地側の間の電圧としては低電圧となった場合でも、2V程度の電圧が必要となる。そのため、従来回路では、電圧検出回路の電圧は2V程度以上の電圧で、安定に動作するが、2V程度より低い電圧では誤動作する場合が生ずる。 また、従来回路では、電圧の比較はM13とM14のソース端子が電源の高電位側に接続されるpチャネルMOSFETで行うために、電源電圧が変動すると、M13とM14のソース電位およびM14のゲート電位が変動して、精度の高い比較が困難になる。そのために、精度の高い比較が要求される場合は、従来回路では、電圧検出回路の電源を主回路の電源とは切り離して別の安定した電源として、V14を検出するR13とR14の分圧抵抗の回路を主回路の電源に接続する必要がある。 また、電源電圧を高耐圧化するには、電圧検出回路を構成している多数の半導体素子の耐圧を高くする必要があり、回路が高価になる。
【0006】
この発明の目的は、前記の課題を解決して、消費電流が小さく、確実に低電圧を検出できる電圧検出回路を提供することにある。
【0007】
【課題を解決するための手段】
前記の目的を達成するために、主回路の電源電圧が低電圧になったことを検出する機能を備え、インバータ回路を2段接続し、前段のインバータ回路のしきい値電圧と電源電圧とを比較することで電源電圧が低電圧になったことを検出し、前段のインバータ回路の出力電圧を後段のインバータに入力し、低電圧を検出した時点で、後段のインバータ回路の出力電圧が接地電位となり、低電圧を検出しない範囲では後段のインバータ回路の出力電圧が電源電圧となる電圧検出回路において、前段のインバータへの入力が第1および第2の分圧抵抗によって分圧された前記主回路の電源電圧であり、前段のインバータ回路がゲートとドレインが接続された第1のpチャネルMOSFET,負荷抵抗およびゲートが前段のインバータの入力部となっている第1のnチャネルMOSFETが直列に接続されて構成され、後段のインバータ回路がゲートが前記第1のpチャネルMOSFETのゲートに接続されている第2のpチャネルMOSFETおよびゲートが前記負荷抵抗と前記第1のnチャネルMOSFETの接続点に接続されている第2のnチャネルMOSFETが直列に接続される構成とする
【0009】
前記の回路構成とすることで、回路が簡単で、誤動作のない、また、低電圧まで安定に動作し、消費電流の少な電圧検出回路を製作できる。
【0010】
【発明の実施の形態】
図1はこの発明の第1参考例の電圧検出回路である。この電圧検出回路は2段のインバータINV1、INV2から構成され、前段のインバータINV1には分圧抵抗R1 、R2 で電源電圧VDDを分圧した電圧が入力電圧VINとして入力されて、出力電圧VOUT1が出力される。このVOUT1が後段のインバータINV2の入力電圧となり、インバータINV2から出力電圧VOUT が出力される。
【0011】
INV1はVINを監視するためのものであり、その方法はINV1 のしきい値(インバータの出力電圧がHレベルからLレベル、LレベルからHレベルに切り替わる入力電圧のこと)とVINと比較することにより行う。VOUT1はVINがしきい値よりも高いとき0Vとなり、VINがしきい値よりも低い場合には、電源電圧VDDとなる。このVOUT1の信号を受けてINV2の出力電圧VOUT は、INV1の出力電圧VOUT1を反転させたレベルとなり、INV2の出力電圧VOUT はVINがしきい値よりも高いとき電源電圧VDDとなり、VINがしきい値よりも低い場合には、0V(GND)となる。このように、2段のインバータを用いることで、電圧検出回路は簡単化し、消費電流を抑え、低電圧になったとき、電圧検出回路の出力電圧であるVOUT を0Vとすることで、負荷回路に電源の供給を停止させることができる。
【0012】
図2はこの発明の第2参考例の電圧検出回路である。この回路は図1に示す回路のINV1を負荷抵抗1とnチャンルMOSFET2で構成したものである。入力電圧VINの監視はnチャネルMOSFET2のしきい値(Vth)とVINを比較することによって行う。また、INV2は1個あるいは2個のMOSFETで構成することが可能であり、この電圧検出回路は図5の従来回路と比較して構成が簡単である。
【0013】
図2の回路動作を説明する。まず、図示しない主回路の電源をオンすると、主回路の電源電圧と同一である電圧検出回路の電源電圧VDDが上昇し、VDDの分圧電圧で、nチャネルMOSFET2のゲート電圧でもあるVINも上昇する。VINがnチャネルMOSFET2のしきい値を超えると、nチャネルMOSFET2がオン状態となり、VOUT1が0Vとなる。このVOUT1がINV2の入力電圧となるため、INV2の入力電圧が0Vとなる。この0Vの信号がINV2によって反転され、INV2の出力電圧VOUT は電源電圧VDDとなる。つぎに、VDDが低下し、VINがnチャネルMOSFET2のしきい値を下回ると、このnチャネルMOSFET2がオフ状態となり、INV2の入力電圧が上昇し、VOUT が0Vとなる。さらにVDDが低下しても、nチャネルMOSFET2はオフ状態のままであるのでVOUT が0Vを維持し、従来回路のように、VDDが低下した場合に電圧検出回路が誤動作することはない。
【0014】
図3はこの発明の第実施例の電圧検出回路である。この回路は、2個のpチャネルMOSFETであるM1 、M2 と2個のnチャネルMOSFETであるM3 、M4 と2個の分圧抵抗R1 、R2 と1個の負荷抵抗R3 により構成されており、従来回路と比べて非常に簡単な回路構成となっている。この回路の入力電圧VINとして、電源電圧VDDを分圧抵抗R1 およびR2 で分圧した電圧を用いている。また、図2のnチャネルMOSFET2は、この回路ではM3 であり、図2の負荷抵抗1は、この回路では負荷3であり、この負荷3はM1 とR3 で構成されている。図2のINV2はM2 とM4 で構成されている。
【0015】
つぎに、回路動作を説明する。電源電圧VDDが上昇し、VDDをR1 とR2 によって分圧することで生じるM3 のゲート電圧V3 がM3 のしきい値を超えると、M3 がオン状態となり、M4 のゲート電圧V4 が0Vとなる。それによって、M4 がオフ状態となり、出力電圧VOUT がVDDとなる。つぎに、VDDが低下し、V3 がM3 のしきい値を下回ると、M3 がオフ状態となり、V4 が増加し、M4 がオン状態となり、VOUT が0Vとなる。電源電圧VDDの検出はVDDを分圧抵抗R1 、R2 で分圧した電圧である入力電圧VINと M3 のしきい値電圧を比較して行い、その検出電圧値の設定はR1 とR2 の比を調節することで可能となる。M3 のしきい値のばらつきによる誤差の影響はR2 /(R1 +R2 )の値を調節することで解消される。また、抵抗R3 はトランジスタM3 がオン状態の場合に、ドレイン電流を抑制するために設けている。
【0016】
図4は、本発明である電圧検出回路の電源電圧を変化させた場合の出力電圧を示す。ここで、図3に示すM1 、M2 のゲート幅は4μm、ゲート長さは8μm、M3 、M4 のゲート幅は12μm、ゲート長さは1. 6μmとした。また、R1 +R2 =1000kΩを一定とした。R2 /(R1 +R2 )=2/10の場合、検出電圧は3.15Vであり、R2 /(R1 +R2 )=3/10の場合は1.9Vであり、R2 /(R1 +R2 )=4/10の場合には検出電圧は1.35Vである。この1.35V以下のVDDの場合はVOUT は安定に0Vを維持できる。この1.35Vの検出電圧に対応する従来回路の検出電圧の最低値は1.9V程度であり、本発明の回路の方が検出電圧を小さくできて、主回路を安定に動作させる電圧範囲が広くなる。また、消費電流は分圧抵抗R1 、R2 を流れる電流を除くと、図5の従来回路では5μA程度であるのに対して、図3の回路では約1μAと大幅に小さくできる。
【0017】
尚、図2、図3の回路では、電圧の比較はソース端子が接地されているnチャネルMOSFET2やM3で行い、接地点(GND)を基準として動作するため、電源電圧VDDの変動に対して安定した動作を確保することができて、誤動作することもない。また、電源の高電位側端子VDDと接地側端子GNDの間に直列接続されるMOSFETの数を2個または1個にできるために、1V程度でも安定した動作が得られる。また、入力段から出力段までの段数が2段で、従来回路の4段に比べて少なく、消費電流も小さくできる。
【0018】
また回路を構成する素子数を従来回路に比べて減少させることができて、回路の誤動作要因を減少させることができる。さらに、回路の高耐圧化は、高耐圧化するMOSFETの数が少ないために、容易である。
【0019】
【発明の効果】
この発明により、電圧検出回路の構成が簡単となり、安定した動作を確保すると共に、高耐圧回路への拡張が容易となった。また、電源・接地間のトランジスタ数を2個以下としているので、1V前後の低電圧の時も安定した動作が可能となった。さらに、段数が少ないために、消費電流を大幅に低減できた。
【図面の簡単な説明】
【図1】この発明の第1参考例の電圧検出回路図
【図2】この発明の第2参考例の電圧検出回路図
【図3】この発明の第実施例の電圧検出回路図
【図4】本発明である電圧検出回路の電源電圧を変化させた場合の出力電圧を示す図
【図5】従来の電圧検出回路図
【符号の説明】
1 負荷抵抗
2 nチャネルMOSFET
3 負荷
11 比較器
12 定電流源
INV1、INV2 インバータ
R1 、R2 分圧抵抗
R3 負荷抵抗
VIN 入力電圧
VOUT1、VOUT 出力電圧
VDD 電源の高電位端子または電圧
GND 接地端子または電圧
M1 、M2 pチャネルMOSFET
M3 、M4 nチャネルMOSFET
V3 、V4 ゲート電圧10月2日付けで名称変更届けを提出済みです。
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a voltage detection circuit that detects that a power supply voltage of a main circuit has become low.
[0002]
[Prior art]
In order for an electronic circuit to operate without malfunction, it is necessary to secure its power supply voltage. In addition, when the power supply voltage falls below a value required for driving the electronic circuit, it is required to stop the electronic circuit. In order to realize the above, it is necessary to constantly monitor the power supply voltage.
[0003]
FIG. 5 shows a conventional voltage detection circuit. The sources of p-channel MOSFETs M11, M12 and M17, which constitute a circuit for passing a constant current, are connected to the high potential side VDD (representing a terminal or voltage) of the power supply of the voltage detection circuit which is the same as the power supply voltage of the main circuit ing. M11 is connected to ground GND (representing a terminal or voltage) via a constant current source 12. The reference voltage VREF is divided by the dividing resistors R11 and R12 to generate a divided voltage V13 which is a voltage at the dividing point. The drain of M12 is connected to the sources of p-channel MOSFETs M13 and M14, the respective drains are connected to the drains of n-channel MOSFETs M15 and M16, and the sources of M15 and M16 are connected to GND. The voltage of VDD is divided between VDD and GND by voltage dividing resistors R13 and R14 to generate a divided voltage V14 which is a voltage at a voltage dividing point. Further, M17 and an n-channel MOSFET M18 are connected between VDD and GND, and a connection point between M17 and M18 becomes an output VOUT (representing a terminal or voltage) of the voltage detection circuit. V13 is the input voltage VIN, which is the gate voltage of M13, and V14 is the gate voltage of M14. The drain of M14 is connected to the gate of M18. The gates of M11, M12 and M17 are respectively connected, and the gate of M11 is connected to the drain of M11. The aforementioned VOUT is connected to a main circuit (not shown).
[0004]
In this figure, VDD is also a power supply voltage to be detected, and VREF is a reference voltage. The gate voltage V13 (= VIN) of M13 is a value obtained by dividing the reference voltage VREF by the voltage dividing resistors R11 and R12, and becomes V13 = VREF × R12 / (R11 + R12). The gate voltage V14 of M14 is a value obtained by dividing the power supply voltage VDD by the resistors R13 and R14, and becomes V14 = VDD × R14 / (R13 + R14). When V13 <V14, that is, when VDD> VREF × R12 (R13 + R14) / [R14 (R11 + R12)], the output voltage VOUT becomes VDD. When V13> V14, that is, when VDD <VREF × R12 (R13 + R14) / [R14 (R11 + R12)], the output voltage VOUT becomes 0V. As described above, by comparing the power supply voltage with the reference voltage, it can be detected that the power supply voltage becomes low.
[0005]
[Problems to be solved by the invention]
However, the conventional voltage detection circuit shown in FIG. 5 uses a comparator having as many as five MOSFETs, so that the circuit configuration is complicated. When the power supply voltage of the electronic circuit as the main circuit decreases, the power supply voltage of the voltage detection circuit also decreases because the power supply of the main circuit is supplied to the voltage detection circuit. The comparator of this conventional circuit is composed of M12 forming a constant current source, M13 and M14 of a differential circuit, and M15 and M16 as active loads, and three MOSFETs from the high potential side of the power supply to the ground side. They are connected in series. These three MOSFETs connected in series are operated in a saturation region where the current is constant. Therefore, it is necessary to apply a voltage of about 0.6 V between the source and the drain to one MOSFET. With three MOSFETs, the voltage between the high potential side and the ground side of the power supply is Even when the voltage becomes low, a voltage of about 2 V is required. Therefore, in the conventional circuit, the voltage detection circuit operates stably at a voltage of about 2 V or more, but malfunctions at a voltage lower than about 2 V. Further, in the conventional circuit, the voltage comparison is performed by a p-channel MOSFET in which the source terminals of M13 and M14 are connected to the high potential side of the power supply. Therefore, when the power supply voltage fluctuates, the source potentials of M13 and M14 and the gate of M14 change. The potential fluctuates, making accurate comparison difficult. Therefore, when a highly accurate comparison is required, in the conventional circuit, the power supply of the voltage detection circuit is separated from the power supply of the main circuit as another stable power supply, and the voltage dividing resistors of R13 and R14 for detecting V14 are used. Must be connected to the power supply of the main circuit. Further, in order to increase the withstand voltage of the power supply voltage, it is necessary to increase the withstand voltage of a large number of semiconductor elements forming the voltage detection circuit, and the circuit becomes expensive.
[0006]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a voltage detection circuit which solves the above-mentioned problems and consumes less current and can reliably detect a low voltage.
[0007]
[Means for Solving the Problems]
In order to achieve the above-mentioned object, a function of detecting that the power supply voltage of the main circuit has become low voltage is provided, two stages of inverter circuits are connected, and the threshold voltage and the power supply voltage of the preceding inverter circuit are determined. comparison that is the supply voltage for the detected that becomes a low voltage, and inputs the output voltage of the preceding stage of the inverter circuit in the subsequent stage of the inverter, upon detecting a low voltage, ground and the output voltage of the subsequent stage of the inverter circuit In the voltage detection circuit in which the output voltage of the subsequent inverter circuit becomes the power supply voltage in a range where the low voltage is not detected in the voltage detection circuit, the input to the previous inverter is divided by the first and second voltage dividing resistors. The power supply voltage of the circuit, the preceding inverter circuit is a first p-channel MOSFET having a gate and a drain connected, a load resistor, and a gate are input parts of the preceding inverter. A first n-channel MOSFET is connected in series, and a second-stage inverter circuit has a second p-channel MOSFET whose gate is connected to the gate of the first p-channel MOSFET and a gate connected to the load resistor. The second n-channel MOSFET connected to the connection point of the first n-channel MOSFET is connected in series.
With the circuit configuration of the circuit is simple, no malfunction, also operates stably to a low voltage, can be manufactured with less has voltage detecting circuit current consumption.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Figure 1 is a voltage detection circuit of the first reference example of the present invention. This voltage detection circuit is composed of two stages of inverters INV1 and INV2, and a voltage obtained by dividing the power supply voltage VDD by the voltage dividing resistors R1 and R2 is input to the preceding stage inverter INV1 as an input voltage VIN, and an output voltage VOUT1 is obtained. Is output. This VOUT1 becomes the input voltage of the inverter INV2 at the subsequent stage, and the output voltage VOUT is output from the inverter INV2.
[0011]
INV1 is for monitoring VIN, and the method is to compare the threshold value of INV1 (the input voltage at which the output voltage of the inverter switches from H level to L level and from L level to H level) with VIN. Performed by VOUT1 becomes 0 V when VIN is higher than the threshold value, and becomes the power supply voltage VDD when VIN is lower than the threshold value. In response to the signal of VOUT1, the output voltage VOUT of INV2 becomes a level obtained by inverting the output voltage VOUT1 of INV1, and the output voltage VOUT of INV2 becomes the power supply voltage VDD when VIN is higher than the threshold value, and the threshold voltage is VIN. When it is lower than the value, the voltage becomes 0 V (GND). As described above, by using the two-stage inverter, the voltage detection circuit is simplified, the current consumption is suppressed, and when the voltage becomes low, the output voltage VOUT of the voltage detection circuit is set to 0 V, so that the load circuit is reduced. Power supply can be stopped.
[0012]
Figure 2 is a voltage detection circuit of the second reference example of the present invention. In this circuit, INV1 of the circuit shown in FIG. 1 is constituted by a load resistor 1 and an n-channel MOSFET 2. Monitoring of the input voltage VIN is performed by comparing the threshold value (Vth) of the n-channel MOSFET 2 with VIN. Further, INV2 can be constituted by one or two MOSFETs, and the configuration of this voltage detection circuit is simpler than that of the conventional circuit of FIG.
[0013]
The circuit operation of FIG. 2 will be described. First, when the power supply of the main circuit (not shown) is turned on, the power supply voltage VDD of the voltage detection circuit, which is the same as the power supply voltage of the main circuit, increases, and VIN, which is the divided voltage of VDD and the gate voltage of the n-channel MOSFET 2, also increases. I do. When VIN exceeds the threshold value of the n-channel MOSFET 2, the n-channel MOSFET 2 is turned on, and VOUT1 becomes 0V. Since VOUT1 becomes the input voltage of INV2, the input voltage of INV2 becomes 0V. This 0V signal is inverted by INV2, and the output voltage VOUT of INV2 becomes the power supply voltage VDD. Next, when VDD decreases and VIN falls below the threshold value of the n-channel MOSFET 2, the n-channel MOSFET 2 is turned off, the input voltage of INV2 increases, and VOUT becomes 0V. Even if VDD further decreases, VOUT is maintained at 0 V because the n-channel MOSFET 2 remains off, and the voltage detection circuit does not malfunction when VDD decreases as in the conventional circuit.
[0014]
FIG. 3 shows a voltage detection circuit according to a first embodiment of the present invention. This circuit comprises two p-channel MOSFETs M1 and M2, two n-channel MOSFETs M3 and M4, two voltage dividing resistors R1 and R2, and one load resistor R3. The circuit configuration is very simple as compared with the conventional circuit. As the input voltage VIN of this circuit, a voltage obtained by dividing the power supply voltage VDD by the voltage dividing resistors R1 and R2 is used. The n-channel MOSFET 2 in FIG. 2 is M3 in this circuit, and the load resistor 1 in FIG. 2 is a load 3 in this circuit, and the load 3 is composed of M1 and R3. INV2 in FIG. 2 is composed of M2 and M4.
[0015]
Next, the circuit operation will be described. When the power supply voltage VDD rises and the gate voltage V3 of M3 generated by dividing VDD by R1 and R2 exceeds the threshold value of M3, M3 is turned on and the gate voltage V4 of M4 becomes 0V. As a result, M4 is turned off, and the output voltage VOUT becomes VDD. Next, when VDD decreases and V3 falls below the threshold value of M3, M3 turns off, V4 increases, M4 turns on, and VOUT becomes 0V. The detection of the power supply voltage VDD is performed by comparing the input voltage VIN, which is the voltage obtained by dividing VDD with the voltage dividing resistors R1 and R2, with the threshold voltage of M3, and setting the detection voltage value by the ratio of R1 to R2. It becomes possible by adjusting. The influence of the error due to the variation of the threshold value of M3 can be eliminated by adjusting the value of R2 / (R1 + R2). The resistor R3 is provided to suppress the drain current when the transistor M3 is on.
[0016]
FIG. 4 shows an output voltage when the power supply voltage of the voltage detection circuit according to the present invention is changed. Here, the gate width of M1 and M2 shown in FIG. 3 was 4 μm, the gate length was 8 μm, the gate width of M3 and M4 was 12 μm, and the gate length was 1.6 μm. Further, R1 + R2 = 1000 kΩ was fixed. When R2 / (R1 + R2) = 2/10, the detection voltage is 3.15V, when R2 / (R1 + R2) = 3/10, the detection voltage is 1.9V, and R2 / (R1 + R2) = 4 / V. In the case of 10, the detection voltage is 1.35V. In the case of VDD of 1.35 V or less, VOUT can stably maintain 0 V. The minimum value of the detection voltage of the conventional circuit corresponding to the detection voltage of 1.35 V is about 1.9 V, and the voltage range in which the circuit of the present invention can reduce the detection voltage and stably operates the main circuit is smaller. Become wider. Excluding the current flowing through the voltage dividing resistors R1 and R2, the current consumption is about 5 .mu.A in the conventional circuit of FIG. 5, while it can be significantly reduced to about 1 .mu.A in the circuit of FIG.
[0017]
In the circuits of FIGS. 2 and 3, the voltage comparison is performed by the n-channel MOSFET 2 or M3 whose source terminal is grounded, and the operation is performed with reference to the ground point (GND). Stable operation can be ensured, and there is no malfunction. Further, since the number of MOSFETs connected in series between the high potential side terminal VDD and the ground side terminal GND of the power supply can be reduced to two or one, a stable operation can be obtained even at about 1V. Further, the number of stages from the input stage to the output stage is two, which is smaller than the four stages of the conventional circuit, and the current consumption can be reduced.
[0018]
Further, the number of elements constituting the circuit can be reduced as compared with the conventional circuit, and the cause of malfunction of the circuit can be reduced. Further, it is easy to increase the withstand voltage of the circuit because the number of MOSFETs to increase the withstand voltage is small.
[0019]
【The invention's effect】
According to the present invention, the configuration of the voltage detection circuit is simplified, stable operation is ensured, and extension to a high withstand voltage circuit is facilitated. In addition, since the number of transistors between the power supply and the ground is set to two or less, stable operation is possible even at a low voltage of about 1V. Further, since the number of stages is small, the current consumption can be significantly reduced.
[Brief description of the drawings]
[1] the first voltage detection circuit diagram of a reference example FIG. 2 voltage detecting circuit diagram of a second reference example of the present invention [3] Voltage detecting circuit diagram of a first embodiment of the present invention of the present invention FIG. 4 is a diagram showing an output voltage when the power supply voltage of the voltage detection circuit according to the present invention is changed. FIG. 5 is a diagram of a conventional voltage detection circuit.
1 load resistance 2 n-channel MOSFET
3 Load 11 Comparator 12 Constant current source INV1, INV2 Inverter R1, R2 Voltage dividing resistor R3 Load resistor VIN Input voltage VOUT1, VOUT Output voltage VDD High-potential terminal of power supply or voltage GND Ground terminal or voltage M1, M2 p-channel MOSFET
M3, M4 n-channel MOSFET
V3, V4 Gate voltage The name change notification has been submitted on October 2nd.

Claims (1)

主回路の電源電圧が低電圧になったことを検出する機能を備え、インバータ回路を2段接続し、前段のインバータ回路のしきい値電圧と電源電圧とを比較することで電源電圧が低電圧になったことを検出し、前段のインバータ回路の出力電圧を後段のインバータに入力し、低電圧を検出した時点で、後段のインバータ回路の出力電圧が接地電位となり、低電圧を検出しない範囲では後段のインバータ回路の出力電圧が電源電圧となる電圧検出回路において、前記前段のインバータへの入力が第1および第2の分圧抵抗によって分圧された前記主回路の電源電圧であり、前記前段のインバータ回路がゲートとドレインが接続された第1のpチャネルMOSFET,負荷抵抗およびゲートが前記前段のインバータの入力部となっている第1のnチャネルMOSFETが直列に接続されて構成され、前記後段のインバータ回路がゲートが前記第1のpチャネルMOSFETのゲートに接続されている第2のpチャネルMOSFETおよびゲートが前記負荷抵抗と前記第1のnチャネルMOSFETの接続点に接続されている第2のnチャネルMOSFETが直列に接続されて構成されていることを特徴とする電圧検出回路。 A function of detecting that the power supply voltage of the main circuit becomes low voltage, the inverter circuit is connected two stages, the threshold voltage and that the supply voltage for comparing the power supply voltage of the preceding stage of the inverter circuit is low Voltage is detected, the output voltage of the preceding inverter circuit is input to the succeeding inverter, and when the low voltage is detected, the output voltage of the succeeding inverter circuit becomes the ground potential and the low voltage is not detected. In the voltage detection circuit in which the output voltage of the subsequent inverter circuit becomes the power supply voltage , the input to the previous inverter is the power supply voltage of the main circuit divided by the first and second voltage dividing resistors, A first p-channel MOSFET having a gate and a drain connected to a preceding inverter circuit, a first n-channel MOSFET having a load resistor and a gate serving as an input section of the preceding inverter. And a second p-channel MOSFET having a gate connected to the gate of the first p-channel MOSFET and a gate connected to the load resistance and the first p-channel MOSFET. A voltage detection circuit, wherein a second n-channel MOSFET connected to a connection point of the n-channel MOSFET is connected in series .
JP22167098A 1998-08-05 1998-08-05 Voltage detection circuit Expired - Lifetime JP3540946B2 (en)

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KR100877882B1 (en) * 2002-06-22 2009-01-12 매그나칩 반도체 유한회사 Circuit for Detecting Low Voltage
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