JP3544863B2 - Semiconductor memory and semiconductor device having the same - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory having a configuration for temporarily changing a power supply voltage for a sense amplifier in order to speed up activation of a sense amplifier, and a semiconductor device including the same.
[0002]
[Prior art]
FIG. 8 shows a conventional sense amplifier 10 of an SDRAM and a circuit related thereto.
The sense amplifier 10 operates with a voltage between the power supply potentials VP and VN supplied from the sense amplifier driving circuit 11. In the sense amplifier drive circuit 11, a PMOS transistor 12 and NMOS transistors 13 to 15 are connected in series, and a gate of the NMOS transistor 15 is supplied with a sense amplifier control signal C0 from a control circuit (not shown). The gate is supplied with a signal * C0 complementary to this signal (hereinafter, * is also added to the sign of other complementary signals). When the sense amplifier control signals C0 and * C0 are low level and high level, respectively, the transistors 13 and 14 are turned on, the transistors 12 and 15 are turned off, and the potential Vii / 2 passes through the transistors 13 and 14 and becomes VP. And VN to the sense amplifier 10. At this time, the sense amplifier 10 is in a non-operation state. In this state, the transfer gates 16 and 17 are turned on, the precharge circuit 18 is turned on by the precharge signal PR, and the bit lines BL01, BL02, * BL01 and * BL02 are precharged to the potential Vii / 2. . The potential Vii / 2 is applied to the cell plate of the capacitor of the memory cell 19.
[0003]
For example, when data is read from the memory cell 19 in which “High” is stored, the word line WL0 rises, positive charges move from the memory cell 19 to the bit line BL01, and the bit lines BL01 and * BL01 Between about 100 and 200 mV. In order to operate the sense amplifier 10 at high speed, the power supply potential VH rises from the potential Vii to Vjj in response to a change in the row address, as shown in FIG. For example, the potentials Vii and Vjj are 1.5V and 2.0V, respectively.
[0004]
Next, the sense amplifier control signals C0 and * C0 transition to a high level and a low level, respectively, so that the transistors 15 and 12 are turned on, the transistors 13 and 14 are turned off, and the potentials VH and 0V turn the transistors 12 and 15 respectively. As described above, they are supplied to the sense amplifier 10 as VP and VN. As a result, the sense amplifier 10 is activated, and the potential difference between the bit lines BL01 and * BL01 is amplified. Due to this amplification, when bit lines BL01 and * BL01 almost fully swing between potentials Vii and 0V, potential VH decreases and returns to potential Vii.
[0005]
When reading is completed, the word line WL0 goes low, the sense amplifier control signals C0 and * C0 go low and high, respectively, and both VP and VN return to the potential Vii / 2, and the sense The amplifier 10 becomes inactive. Further, the precharge circuit 18 is turned on by the precharge signal PR, and the bit line potential is reset to the potential Vii / 2.
[0006]
In a conventional SDRAM having a plurality of banks, the potential VH is commonly supplied to the sense amplifier driving circuits of each bank. At the time of bank switching, processing of the bank after switching is performed in parallel while processing of the bank before switching is performed. Therefore, for example, when the banks 0 to 3 are sequentially switched as shown in FIG. 10, the power supply potential VH is maintained at the potential Vjj without dropping to the potential Vii.
[0007]
As a result, useless current is consumed, and the high-potential period becomes unnecessarily long, so that deterioration of transistor characteristics is accelerated.
The precharge by the precharge circuit 18 in FIG. 8 is rapidly performed mainly by short-circuiting between the bit lines BL02 and * BL02, and the precharge from the wiring of the potential Vii / 2 is gently performed in an auxiliary manner. For this reason, the read operation is performed again from the bank 0 after the bank 3, and the read operation is performed by connecting the bit line to which the potential difference amplification has been performed in the previous bank 0 and other than the memory cell selected last time and “High”. , The precharge potential Vpr2 becomes higher than the original precharge potential Vpr1 = Vii / 2, as shown in FIG. The potential difference ΔV between the pair of bit lines after reading from the memory cell and before amplification depends on the potential Vpr of the bit line precharged before reading and is expressed by the following equation.
[0008]
ΔV = (Vsn−Vpr) · Cs / (CBL + Cs)
Here, Cs is the capacitance of the memory cell, CBL is the parasitic capacitance of the bit line, and Vsn is the potential of the storage node 191 before reading.
As is apparent from this equation, when Vpr increases while Vsn is constant, ΔV decreases. That is, the potential difference ΔV2 between the bit line pair in FIG. 10 becomes smaller than ΔV1. If the potential difference ΔV between the bit line pairs becomes too small, the sense amplifier 10 may malfunction due to variations in element characteristics of the sense amplifier 10. Therefore, it is necessary to shorten the refresh cycle time and maintain the storage node potential Vsn high. As a result, the current consumption is greatly increased.
[0009]
[Problems to be solved by the invention]
An object of the present invention is to provide a semiconductor memory capable of reducing current consumption and preventing deterioration of element characteristics from being accelerated, and a semiconductor device including the same, in view of the above problems. is there.
[0011]
Means for Solving the Problems and Their Effects
A semiconductor memory according to claim 1, comprising a plurality of banks, and a sense amplifier for amplifying a voltage between a pair of bits in each bank.
In response to a selection control signal, a first power supply potential for activating the sense amplifier and a second power supply potential for activating the sense amplifier faster than when the first power supply potential is used. A selection circuit for selecting one of
A selection control circuit for selecting the second power supply potential for a predetermined time in response to activation of the bank activation signal, and thereafter generating the selection control signal for selecting the first power supply potential;
A sense amplifier driving circuit that supplies the power supply potential selected by the selection circuit to the sense amplifier in response to activation of a sense amplifier control signal;
The second power supply potential is provided for each of the plurality of banks, and the second power supply potential is higher than the first power supply potential.
The selection control circuit includes:
A circuit for generating a set pulse in response to activation of the bank activation signal;
A delay circuit for delaying the bank activation signal;
A circuit for generating a reset pulse in response to activation of an output of the delay circuit;
A flip-flop circuit for supplying the set pulse and the reset pulse to a set input terminal and a reset input terminal, respectively, and outputting the selection control signal;
Having.
[0012]
According to this semiconductor memory, the selection control circuits operate independently based on the bank activation signal, and the selection circuit for each bank is independently controlled by the output of the selection control circuit, so that the power supply potential is adjusted by the selection circuit and the sense amplifier drive. Since the power supply potential for the sense amplifier is supplied to the sense amplifier via the circuit, the power supply potential for the sense amplifier becomes the second power supply potential only during a period necessary for high-speed activation in accordance with the activation of the corresponding bank.
[0013]
Therefore, there is an effect that unnecessary consumption of the output current of the power supply circuit is omitted, and a period in which a high voltage is unnecessarily applied to the transistor is reduced, so that characteristic deterioration is reduced.
Further, since the potential difference between the bit line pair after the reading from the memory cell and before the amplification is prevented from decreasing, the refresh cycle time can be made longer and the current consumption can be reduced.
[0014]
According to a second aspect of the present invention, in the semiconductor memory according to the first aspect, when the sense amplifier control signal becomes inactive, the sense amplifier driving circuit switches the power supply potential to a bit line precharge potential and supplies the same to the sense amplifier. I do.
According to a third aspect of the present invention, in the semiconductor memory according to the first or second aspect, the selection circuit includes:
A first transistor switch element connected between the conductor of the first power supply potential and the output terminal of the selection circuit;
A second transistor switching element connected between the second power supply potential conductor and the output terminal.
[0015]
According to a fourth aspect of the present invention, the semiconductor memory according to the first or second aspect further includes a power supply circuit for generating the first and second power supply potentials based on an external power supply potential .
[0016]
According to a fifth aspect of the present invention, there is provided the semiconductor memory according to any one of the first to fourth aspects, further comprising a circuit for generating the bank activation signal which is activated for a predetermined period in response to the input of the activate command.
According to a sixth aspect of the present invention, in any one of the first to fourth aspects, the selection circuit and the selection control circuit are commonly used for a plurality of sense amplifier arrays.
[0017]
A semiconductor device according to a seventh aspect has the semiconductor memory according to any one of the first to sixth aspects.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a schematic block diagram showing a circuit related to a sense amplifier of the SDRAM 20 according to the first embodiment of the present invention.
[0019]
The SDRAM 20 includes banks BNK0 to BNK3, and a bank is selected by upper two bits of an address, for example, bits A17 and A16. Bank activation signal generation circuit 21 generates signals BA0 to BA3. Signals BA0 to BA3 are activated in response to an activation command input in a state where signals obtained by decoding bank address bits A17 and A16 are activated, and are inactivated at the end of access of the same row in the corresponding bank. You. At the time of bank switching, since the processing of the bank after switching is performed in parallel while the processing of the bank before switching is performed, for example, when the banks BNK0 to BNK3 are sequentially selected, the bank activating signals BA0 to BA3 are output. As shown in FIG. 6, the active periods partially overlap.
[0020]
The signals BA0 to BA3 are supplied to selection control circuits 22 to 25 having the same configuration. In response to the activation of signal BA0, selection control circuit 22 generates selection control signal SC0 that is activated for a predetermined time and selection control signal * SC0 that is complementary to selection control signal SC0. Supply to control input.
For example, in the selection circuit 28, as shown in FIG. 2, the source of the PMOS transistor 29 is connected to the wiring of the potential Vjj for activating the sense amplifier more quickly, and the drain of the PMOS transistor 29 is connected via the PMOS transistor 30. It is connected to the wiring of the potential Vii for activating the sense amplifier. The outputs SC0 and * SC0 of the selection control circuit 22 are supplied to the gates of the transistors 30 and 29, respectively. For example, a potential Vjj is applied to the N wells of the PMOS transistors 29 and 30.
[0021]
When the selection control signals * SC0 and SC0 are low and high, respectively, the transistors 29 and 30 are turned on and off, respectively, and the potential Vjj passes through the transistor 29 and is output as VH0. Conversely, when the selection control signals * SC0 and SC0 are high and low, respectively, the transistors 29 and 30 are turned off and on, respectively, and the potential Vii passes through the transistor 30 and is output as VH0. The potential VH0 is supplied as a power supply potential to the sense amplifier drive circuit 113 having the same configuration as the sense amplifier drive circuit 11 in FIG.
[0022]
2, the same components as those in FIG. 8 are denoted by the same reference numerals, and the description thereof will not be repeated.
FIG. 3 shows a configuration example of the selection control circuit 22, and FIG. 4 is a time chart showing the operation of this circuit.
In this circuit 22, the bank activation signal BA0 is supplied to one input terminal of the NAND gate 33 through the delay circuits 31 and 32, and the output TS of the delay circuit 31 is supplied to the other input terminal of the NAND gate 33. The signal TS is used by a control circuit (not shown) as a timing signal for starting the activation of the sense amplifier 10 by setting the sense amplifier control signals C0 and * C0 in FIG. The delay circuit 31 has a configuration in which a basic delay circuit in which an output of an inverter 34 is connected to a CR integrator circuit for delay is connected in even number stages, for example, in two stages. Similarly to the delay circuit 31, the delay circuit 32 has a configuration in which basic delay circuits are connected in even stages, for example, two stages in cascade.
[0023]
The output * RST of the NAND gate 33 becomes low during the period from the rise of the output of the delay circuit 32 to the fall of the signal TS, and is supplied to the reset input terminal * R of the RS flip-flop circuit 37. The reset signal * RST and the bank activating signal BA0 are supplied to the NAND gate 38, and the output * SET thereof becomes low level from the rising of the bank activating signal BA0 to the falling of the reset signal * RST. It is supplied to the set input terminal * S of the circuit 37.
[0024]
A PMOS transistor 39 is connected between the inverted output terminal * Q of the RS flip-flop circuit 37 and the wiring of the potential Vjj to set the output of the RS flip-flop circuit 37 to the initial state immediately after the power is turned on. Signal BA0 is supplied. When the bank activation signal BA0 is at a low level, the PMOS transistor 39 is turned on and the inverted output terminal * Q is at a high level. At this time, since the set input terminal * S is at a high level, the non-inverted output terminal Q is at a low level. Become a level. Thus, the initial state of the output of the RS flip-flop circuit 37 is determined.
[0025]
Inverting output terminals * Q of the RS flip-flop circuit 37 are connected to inverters 40 and 41 for amplifying driving capability, and non-inverting output terminals Q of the RS flip-flop circuit 37 are similarly connected to inverters 42 and 43. ing. Selection control signals SC0 and * SC0 are extracted from inverters 43 and 41, respectively.
With such a configuration, selection control circuit 22 generates selection control signals SC0 and * SC0 that are activated for a predetermined time in response to activation of bank activation signal BA0.
[0026]
Returning to FIG. 1, the selection circuits 26 to 28 are supplied with selection potentials Vii and Vjj from the power supply circuit 44. One of the potentials Vii and Vjj selected by the selection circuits 26 to 28 according to the output of the selection control circuit 22 is supplied to the sense amplifier driving circuits 111 to 113 having the same configuration. The potential Vii / 2 is further supplied from the power supply circuit 44 to the sense amplifier driving circuits 111 to 113.
[0027]
FIG. 5 shows a schematic configuration of the power supply circuit 44.
In the power supply circuit 44, a power supply potential VCC supplied from outside is applied to the drain of the NMOS transistor 45, the output potential VG of the constant potential generation circuit 46 is supplied to the gate of the transistor 45, and the potential Vjj is supplied from the source of the NMOS transistor 45. Is taken out. Since the NMOS transistor 45 is used instead of the PMOS transistor, the potential Vjj can be set to a substantially constant value (VG-Vth) without feedback of the potential Vjj to control the gate of the NMOS transistor 45. The configuration of the circuit 44 is simplified. Here, Vth is a threshold voltage of the NMOS transistor 45. A capacitor 47 is connected to the output terminal of the constant potential generation circuit 46 in order to reduce the output fluctuation of the constant potential generation circuit 46 and stabilize the potential Vjj.
[0028]
The circuit that generates the potential Vii is configured similarly to the circuit that generates the potential Vjj. The potential Vii / 2 is generated by the precharge potential generation circuit 48.
Returning to FIG. 1, the output potentials VP and VN of the sense amplifier drive circuits 111 to 113 are supplied to the first to third column sense amplifier groups of the bank BNK0, respectively. The configuration in which bit lines are connected to both sides of the sense amplifier has a symmetrical configuration on one side and the other side. For example, power supply wiring connections for supplying the potentials VP and VN from the sense amplifier drive circuit 113 to the sense amplifier 10 of the bank BNK0 are as shown in FIG.
[0029]
In FIG. 1, the configuration between the selection control circuit 23 and the bank BNK1, the configuration between the selection control circuit 24 and the bank BNK2, and the configuration between the selection control circuit 25 and the bank BNK3 are all the same as those of the selection control circuit 22 and the bank BNK0. Are the same as those described above. Power supply potentials VH1 to VH3 for banks BNK1 to BNK3 correspond to power supply potentials VH0 of bank BNK0.
[0030]
Next, the operation of the present embodiment configured as described above will be described with reference to FIG.
In the initial state immediately after the power is turned on, the selection control signals SC0 and * SC0 become low level and high level, respectively, so that the PMOS transistors 29 and 30 of the selection circuit 28 in FIG. 2 are turned off and on, respectively, and the potential Vii is selected. Is done.
FIG. 6 shows a case where the banks BNK0 to BNK3 of FIG. 1 are sequentially selected.
[0031]
When bank BNK0 is selected and bank activation signal BA0 transitions to a high level, outputs SC0 and * SC0 of selection control circuit 22 transition to a high level and a low level, respectively, in response to this, and PMOS transistor 29 of FIG. And 30 are turned on and off, respectively, and the potential VH0 rises from Vii to Vjj. At the timing when the signal TS in FIG. 4 transitions to the high level, the sense amplifier control signals C0 and * C0 in FIG. 2 transition to the high level and the low level, respectively, and the power supply potentials VP and VN change from Vii / 2 to Vjj and Vjj, respectively. It changes to 0V. As a result, the sense amplifier 10 is activated, and the potential difference between the bit lines BL01 and * BL01 is amplified. After a predetermined time has elapsed from the start of the activation of the sense amplifier 10, the outputs SC0 and * SC0 of the selection control circuit 22 return to the low level and the high level, respectively, and the PMOS transistors 30 and 29 in FIG. 2 are turned on and off, respectively. The potential VH0 drops to Vii.
[0032]
For each bank, adjacent sense amplifier rows and memory cell array areas (memory cell array areas including selected word lines) sandwiched between the sense amplifier rows are activated for each bank. For example, when the sense amplifier control signals C0 and * C0 supplied to the sense amplifier drive circuit 111 are at a low level and a high level, respectively, the sense amplifier control signals C0 and * C0 supplied to the sense amplifier drive circuits 112 and 113 are Transition to a high level and a low level, respectively. Therefore, the sense amplifier drive circuits 111 to 113 cannot be replaced with one sense amplifier drive circuit and commonly used.
[0033]
Next, the bank BNK1 is selected, the bank activation signal BS1 transitions to a high level, and the same operation as that of the bank BNK0 is performed for the bank BNK1. The same applies to the subsequent operations on the banks BNK2 and BNK3.
In the first embodiment, the selection control circuits 22 to 25 operate independently based on the bank activation signals BA0 to BA3, and the selection circuits for each bank are independently controlled by the outputs of the selection control circuits 22 to 25. Since the power supply potential from the power supply circuit 44 is supplied to the sense amplifier via the selection circuit and the sense amplifier drive circuit, the potentials VH0 to VH3 become the potential Vjj only during a necessary period according to the activation of the corresponding bank.
[0034]
For this reason, wasteful consumption of the output current of the power supply circuit 44 is omitted, and the period during which a high voltage is unnecessarily applied to the transistor is reduced, so that the characteristic deterioration is reduced.
Further, since a decrease in the potential difference ΔV between the bit line pair after reading from the memory cell and before amplification is prevented, the refresh cycle time can be made longer and the current consumption can be reduced.
[0035]
[Second embodiment]
FIG. 7 shows a circuit related to the sense amplifier of the SDRAM 20A according to the second embodiment of the present invention.
In this circuit, instead of the selection circuits 26 to 28 of FIG. 1, one selection circuit 26A having the same configuration as the selection circuit 26 and having a higher driving capability than the selection circuit 26 is used, and its output VH0 is output to the sense amplifier driving circuits 111 to 113. To supply in common. The configuration for banks BNK1 to BNK3 is the same as that for bank BNK0.
[0036]
The present invention also includes various modified examples.
For example, another type of switch element may be used instead of the PMOS transistor 29 or 30 in FIG.
Also, instead of driving one sense amplifier row by the sense amplifier drive circuit 111 of FIG. 1, this sense amplifier row is divided into a plurality of sense amplifier groups, and the drive capability of each sense amplifier group is set by the sense amplifier drive circuit 111. The configuration may be such that a small sense amplifier drive circuit is provided, the output of the selection circuit 26 is commonly supplied to each sense amplifier group, and each sense amplifier group is driven by the corresponding sense amplifier drive circuit. The same applies to the other sense amplifier drive circuits in FIG. 1 and the sense amplifier drive circuit in FIG.
[0037]
Of course, the configuration of the combination of FIG. 1 and FIG. 7 , specifically, the configuration of commonly supplying the output of the selection circuit 26A of FIG. 7 to the sense amplifier driving circuits 111 to 113 of FIG.
Further, the bit line precharge potential is not limited to the potential Vii / 2, and may be, for example, the potential Vii or the ground potential. In this case, in FIG. 2, the sense amplifier deactivation potential supplied to the sense amplifier drive circuit 113 is the same as the bit line precharge potential supplied to the precharge circuit 18.
[0038]
For example, when the bit line precharge potential is the potential Vii, the potential Vii is supplied to the sense amplifier driving circuit 113 instead of the potential Vii / 2. In this case, the potential VH0 is fixed to Vii, the source of the NMOS transistor 15, and the ground potential GND for the sense amplifier activation from one selection circuit with negative charge level for faster activation of the sense amplifier Supplied. Then, the selection circuit is controlled by the selection control signal SC0 and * SC0 in FIG 4, respectively when the signal SC0 is at high level and low level to select the negative charge level及 beauty ground potential GND.
[0039]
When the bit line precharge potential is the ground potential, the power supply potential VH0 supplied to the sense amplifier drive circuit 113 is switched and controlled in the same manner as in the above embodiment.
[Brief description of the drawings]
FIG. 1 is a diagram showing a circuit related to a sense amplifier of an SDRAM according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration example of a part of the circuit in FIG. 1;
FIG. 3 is a diagram illustrating a configuration example of a selection control circuit in FIG. 2;
FIG. 4 is a time chart illustrating the operation of the circuit of FIG. 3;
FIG. 5 is a schematic diagram showing a configuration example of a power supply circuit in FIG. 1;
FIG. 6 is a time chart showing the operation of the circuit of FIG. 1 when banks BNK0 to BNK3 are sequentially selected.
FIG. 7 is a diagram showing a circuit related to a sense amplifier of an SDRAM according to a second embodiment of the present invention.
FIG. 8 is a diagram showing a circuit related to a sense amplifier of a conventional SDRAM.
FIG. 9 is a voltage waveform diagram showing the operation of the circuit of FIG.
FIG. 10 is a waveform diagram of a sense amplifier power supply voltage and a bit line voltage in each bank when banks 0 to 3 are sequentially selected.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Sense amplifier 11, 11A, 111-113 Sense amplifier drive circuit 12, 29, 30, 39 PMOS transistor 13-15, 45 NMOS transistor 18 Precharge circuit 19 Memory cell 20, 20A SDRAM
21 bank activation signal generation circuits 22-25 selection control circuits 26-28 selection circuits 31, 32 delay circuit 37 RS flip-flop circuit 44 power supply circuit 46 constant potential generation circuits BNK0-BNK3 bank VCC external power supply potential C0, * C0 sense amplifier Control signal SC0, * SC0 Selection control signal BL01, * BL01, BL02, * BL02 Bit line

Claims (7)

In a semiconductor memory including a plurality of banks, and a sense amplifier for amplifying a voltage between a pair of bit lines in each bank,
In response to a selection control signal, a first power supply potential for activating the sense amplifier and a second power supply potential for activating the sense amplifier faster than when the first power supply potential is used. A selection circuit for selecting one of
A selection control circuit for selecting the second power supply potential for a predetermined time in response to activation of the bank activation signal, and thereafter generating the selection control signal for selecting the first power supply potential;
A sense amplifier driving circuit that supplies the power supply potential selected by the selection circuit to the sense amplifier in response to activation of a sense amplifier control signal;
Providing for each of the plurality of banks, wherein the second power supply potential is higher than the first power supply potential;
The selection control circuit includes:
A circuit for generating a set pulse in response to activation of the bank activation signal;
A delay circuit for delaying the bank activation signal;
A circuit for generating a reset pulse in response to activation of an output of the delay circuit;
A flip-flop circuit for supplying the set pulse and the reset pulse to a set input terminal and a reset input terminal, respectively, and outputting the selection control signal;
A semiconductor memory comprising: 2. The semiconductor memory according to claim 1, wherein the sense amplifier drive circuit switches the power supply potential to a bit line precharge potential and supplies the same to the sense amplifier when the sense amplifier control signal becomes inactive. . The selection circuit,
A first transistor switch element connected between the conductor of the first power supply potential and the output terminal of the selection circuit;
A second transistor switching element connected between the second power supply potential conductor and the output terminal;
The semiconductor memory according to claim 1, further comprising: 4. The semiconductor memory according to claim 1, further comprising a power supply circuit that generates the first and second power supply potentials based on an external power supply potential. The semiconductor memory according to in response to the input of the activate command, any one of claims 1 to 4, further comprising a circuit for generating the bank activation signal comprising a predetermined period activity. The selection circuit and the selection control circuit, a semiconductor memory according to any one of claims 1 to 4, characterized in that the plurality of sense amplifier arrays are used in common. Wherein a has a semiconductor memory according to any one of claims 1 to 6.

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