JP2000315389A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce dispersion of an amplifying time of a sense amplifier caused in accordance with kinds and arrangement patterns of data stored in each memory cell. SOLUTION: A delay circuit 20 is provided in an input system of an enable- signal lez for N channel out of two enable-signals lex, lez being in complementary relation, amplifying operation is performed slowly by a sense amplifier in a state in which only a sense amplifier activation signal psa is driven first by giving difference between first and second sense amplifier activation signals psa, nsa, current consumption by amplifying operation is reduced and voltage drop is suppressed, it is prevented that an amplifying time is delayed even in an sense amplifier 2 arranged at a position being remote from a sense amplifier driver 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a technique for driving a sense amplifier (S / A).

[0002]

2. Description of the Related Art In recent years, a chip area has been increased with an increase in capacity of a semiconductor memory device. As a countermeasure,
It is effective to increase the size of a repeated pattern component such as a word decoder or a sense amplifier for selecting a desired word line according to an address signal. Therefore, by increasing the number of sense amplifiers that are simultaneously activated in accordance with one address signal, that is, one activation block, an increase in chip area due to an increase in capacity is prevented.

FIG. 5 shows a configuration example of a semiconductor memory device having a large activation block. This FIG.
1 shows a configuration of a DRAM which is an example of a semiconductor memory device, and shows a configuration in a certain bank. In one bank, a plurality of memory cell arrays (cell blocks) 1 are provided in a matrix in a row (row) direction and a column (column) direction.

A plurality of sense amplifiers (S / Amp) 2 are provided above and below each memory cell array 1 (not shown in detail in the figure, but a plurality of sense amplifiers are provided in one S / Amp 2). Provided). In the last row in the bank, a main amplifier 3 is provided, and in the first row, a column decoder (C / dec) for selecting a desired bit line (not shown) wired in the column direction according to an address signal.
4 are provided.

In the row direction within the bank, a main word line 5 is wired through each memory cell array 1 in the row, and a sub word line 6 is wired for each memory cell array 1 (one representative in the figure). Only the row wiring is shown). The selection of the main word line 5 is as follows.
The input address signal is converted to a main word decoder (MW
/ Dec) 7 is selected based on the signal decoded, and the selection of the sub-word line 6 is performed based on the signal obtained by decoding the input address signal by the sub-word decoder (SW / dec) 8.

In the bank, a sense amplifier driver 9 is provided for every other cell block, and drives a plurality of sense amplifiers 2 arranged on both sides thereof as shown by arrows. A plurality of sense amplifiers 2 connected to one sense amplifier driver 9 are simultaneously activated according to a certain address signal, and constitute one activation block. Of the plurality of sense amplifiers 2 activated at the same time, the address signal is supplied to the column decoder (C / de).
c) Either one is selected according to the signal decoded in 4, and the data is amplified.

FIG. 6 is a diagram showing a partial configuration of one activation block. In FIG. 6, signals lex and lez input to the sense amplifier driver 9 are enable signals having a complementary relationship with each other, and each has a source connected to the power supply voltage Vii.
And the gates of P-channel transistor 11 and N-channel transistor 12 connected to ground level Vss. Rst is a precharge start signal, and Vpr is a voltage level at the time of precharging the bit line pair bl and / bl (/ indicates an inverted signal), and is set to 1/2 Vii.

Further, psa and nsa are sense amplifier activation signals for P channel and N channel, respectively, and enable signals lex and lez are supplied to the sense amplifier driver 9.
Is supplied to a plurality of sense amplifiers 2 which are cascaded and connected to the sense amplifier driver 9 when the signal is input. As shown in FIG. 7A, each sense amplifier 2 includes an inverter including two P-channel transistors Tr1 and Tr2 and two N-channel transistors T
It has a flip-flop configuration with an inverter composed of r3 and Tr4.

FIG. 7B is a diagram showing an activation timing of the sense amplifier 2 and an operation waveform of a voltage level appearing on the bit line pair bl and / bl. Before the word line is selected and the charge of the memory cell appears on the bit line pair bl, / bl,
The gate, source, and drain voltage levels of the transistors Tr1 to Tr4 in the sense amplifier 2 are all equal to Vpr. Here, for example, a case where amplification of “H” data is performed, that is, a case where one bit line bl is “H” and the other bit line / bl is “L” is considered.

In this case, when a difference potential ΔV is generated between the pair of bit lines bl and / bl due to charges from the memory cell, the gate voltages of the P-channel transistor Tr2 and the N-channel transistor Tr4 increase to (Vpr + ΔV).
Thereafter, when the sense amplifier activation signals psa and nsa are simultaneously input, the N-channel transistor Tr4 is turned off.
N, and the potential level of the node A falls.

As a result, the P-channel transistor Tr
1 is turned ON, the voltage of the bit line bl is charged to the voltage level (= Vii) of the P-channel sense amplifier activation signal psa by the P-channel transistor Tr1, and the voltage of the bit line / bl is changed to the N-channel sense. It falls to the level of the amplifier activation signal nsa (= Vss).

On the other hand, when amplifying "L" data,
Bit line pair bl, / bl due to the charge from the memory cell
Potential difference ΔV occurs in the P-channel transistor Tr
The gate voltages of the 2- and N-channel transistors Tr4 fall to (Vpr-ΔV). Thereafter, when the sense amplifier activation signals psa and nsa are simultaneously input, the N-channel transistor Tr2 is turned on, and the potential level of the node A increases.

Thus, the P-channel transistor Tr
3 is turned on, the voltage of the bit line bl is discharged to the voltage level (= Vss) of the sense amplifier activation signal nsa for N channel by the P channel transistor Tr3, and the voltage of the bit line / bl is sensed for P channel. It rises to the level of the amplifier activation signal psa (= Vii).

When "H" data is amplified by the sense amplifier 2, the N-channel transistor Tr4 starts operating first, and when "L" data is amplified, the P-channel transistor Tr2 starts operating first. That is, since the threshold voltage of the transistor is smaller in the N channel than in the P channel, if the difference potential ΔV is the same, the N channel transistor Tr
4 is ON earlier than the P-channel transistor Tr2
Becomes As a result, the gate voltage of the P-channel transistor Tr1 decreases quickly, so that the operation in the sense amplifier 2 is slightly faster in amplifying "H" data.

[0015]

However, according to the above-mentioned conventional technique, when the number of sense amplifiers 2 in an activation block is increased in order to prevent an increase in chip area,
Since the sense amplifier activating signals psa and nsa output from the sense amplifier driver 9 are sequentially supplied to the individual sense amplifiers 2 and consume current, the sense amplifier 2 located farther from the sense amplifier driver 9 has a higher drive voltage. Has been reduced, and the operating speed has been reduced.

For example, as shown in FIG. 8A, the last-stage sense amplifier 2 farthest from the sense amplifier driver 9 is provided.
"L" data is amplified by the other sense amplifiers 2
When the “H” data is all amplified (worst case), the bit line pair bl is charged through the P-channel transistor Tr1 by the amplification of the “H” data, and thus the sense amplifier activation signals psa and nsa are amplified here. Current is consumed.

Therefore, as shown in FIG. 8B, the voltage level of the P-channel sense amplifier activation signal psa gradually decreases as the distance from the sense amplifier driver 9 increases, and the N-channel sense amplifier activation occurs. The voltage level of the signal nsa gradually increases as the distance from the sense amplifier driver 9 increases. That is, a voltage drop occurs in which the difference between the voltage levels of the sense amplifier activation signals psa and nsa gradually decreases.

FIG. 9 is a diagram showing the activation timing of the sense amplifier 2 and the operation waveform of the voltage level appearing on the bit line pair bl and / bl. As shown in FIG. 9A, in the sense amplifier 2 closer to the sense amplifier driver 9, since the voltage drop of the sense amplifier activation signals psa and nsa does not occur so much, the voltage levels PSA and NSA are steep. stand up. Therefore, the voltage level difference between the sense amplifier activation signals psa and nsa increases in a short time,
Accordingly, the voltage level difference between the pair of bit lines bl and / bl also increases in a short time.

On the other hand, in the last stage sense amplifier 2 farthest from the sense amplifier driver 9, since the voltage drop of the sense amplifier activation signals psa and nsa is large, as shown in FIG. Voltage level PSA, NSA
Rises slowly. Therefore, the bit line pair bl,
/ Bl becomes slower than the sense amplifier 2 closer to the sense amplifier driver 9, and becomes “L”.
This results in a delay in the data sense time (amplification time).

As described above, in the conventional semiconductor memory device in which the number of sense amplifiers in one activation block is increased, the amplification time of the sense amplifier 2 depends on the type of data (“H”) stored in each memory cell. There is a problem that variation occurs depending on the data and the "L" data and the arrangement pattern (as described above, the amplification operation of the sense amplifier 2 is faster for "H" data than for "L" data). Since the current consumption is large, the worst case is when "L" data comes after "H" data continues).

The present invention has been made to solve such a problem, and it is possible to reduce the variation in the sensing time caused according to the type and arrangement pattern of data stored in each memory cell. The purpose is to be.

[0022]

A semiconductor memory device according to the present invention is a semiconductor memory device having a plurality of sense amplifiers operating in response to first and second sense amplifier activation signals. And the drive timing of the second sense amplifier activation signal is differentiated.
Also, an adjusting means for adjusting the difference between the drive timings of the first and second sense amplifier activating signals may be provided.

The present invention comprises the above technical means.
When only one of the second sense amplifier activation signal and the second sense amplifier activation signal is driven, the amplification operation by the sense amplifier is performed slowly, and the current consumption of the sense amplifier activation signal is increased by the amplification operation by the sense amplifier. , After the first and second sense amplifier activating signals are all driven. Therefore, the current consumption during the amplification operation can be reduced, the voltage drop of the sense amplifier activation signal can be suppressed, and the delay of the amplification time can be minimized.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a partial configuration of the semiconductor memory device according to the present embodiment, and the same components as those shown in FIG. 6 are denoted by the same reference numerals.

As shown in FIG. 1, the sense amplifier driver 10 of the present embodiment includes an N-channel enable signal le of two complementary enable signals lex and lez.
A delay circuit 20 is provided in the input system of z. The delay circuit 20 is configured by, for example, inverters connected in multiple stages. With this configuration, the rising timing of the sense amplifier activation signals psa and nsa (first and second sense amplifier activation signals) is differentiated. Note that the inverter 21 provided at the input stage of the sense amplifier driver 10 is for adjusting the phase of the signal.

FIG. 2 shows a sense amplifier in which the last sense amplifier 2 farthest from the sense amplifier driver 10 amplifies "L" data and the other sense amplifiers 2 amplify all "H" data. The activation signal psa,
5A and 5B are diagrams showing voltage levels of nsa, (a) shows a partial configuration of one activation block, and (b) shows fluctuations in voltage levels of sense amplifier activation signals psa and nsa. The configuration inside each sense amplifier 2 is shown in FIG.
This is the same as shown in FIG.

FIGS. 3A and 3B are diagrams showing the activation timing of the sense amplifier 2 and the operation waveform of the voltage level appearing on the bit line pair bl and / bl. FIG. 3A shows a position near the sense amplifier driver 10. FIG. 5 shows operation waveforms when "H" data is amplified by the sense amplifier 2;
(B) shows an operation waveform when the “L” data is amplified by the last stage sense amplifier 2.

In FIG. 3A, before the word line is selected and the charge of the memory cell appears on the pair of bit lines bl and / bl, each transistor Tr1 to Tr in the sense amplifier 2 is set.
The voltage levels of the gate, source, and drain of No. 4 are all the same potential at Vpr. When amplifying "H" data in this state, the bit line pair b
When a difference potential ΔV occurs between 1 and / bl, the gate voltages of the P-channel transistor Tr2 and the N-channel transistor Tr4 in the sense amplifier 2 increase to (Vpr + ΔV). Up to this point, it is the same as the conventional example shown in FIG.

After that, first, the P-channel sense amplifier activating signal psa for which the delay circuit is not provided in the input system is input, so that the P
The source potentials of the channel transistors Tr1 and Tr2 rise. As a result, the potential difference Vgs1 between the gate and the source of the P-channel transistor Tr1 gradually increases, and the supply of charges starts. At this time, the voltage at the node B of the bit line bl gradually increases due to the supply of charges from the P-channel transistor Tr1.

On the other hand, since the gate voltage of the P-channel transistor Tr2 has risen to (Vpr + ΔV), the difference potential Vgs2 of the P-channel transistor Tr2 does not increase as much as the difference potential Vgs1 of the P-channel transistor Tr1. Therefore, the supply of charge from the P-channel transistor Tr2 is small, and the voltage rise at the node A of the bit line / bl is smaller than the voltage rise at the node B.

At this time, since the N-channel sense amplifier activation signal nsa has not been input yet, the N-channel transistors Tr3 and Tr4 are in the OFF state.
The gate voltage of the P-channel transistor Tr1 remains at the Vpr level. Therefore, sense amplifier activation signal p
No charge is supplied from sa through the P-channel transistor Tr1.

That is, when only the P-channel sense amplifier activating signal psa is input and the N-channel sense amplifier activating signal nsa is not input, the N-channel transistor Tr4 remains OFF and the potential of the node A rises. The P-channel transistor Tr1 does not fall
It does not become N. Therefore, the sense amplifier activation signal psa
Is not supplied through the P-channel transistor Tr1, but the sense amplifier activation signal psa
Of the P-channel transistor T
The difference potential Vgs1 between the gate and the source of r1 gradually rises and approaches the threshold voltage.

Therefore, the P-channel transistor Tr1
, Charging is gradually performed, and the voltage level of the bit line bl gradually rises. Therefore, the rise of the voltage level on the bit line bl is slower than in the conventional case where the sense amplifier activation signals psa and nsa are simultaneously input.

Thereafter, by inputting an N-channel sense amplifier activation signal nsa provided with a delay circuit 20 to the input system, the N-channel sense amplifier activation signal ns
The voltage level of a is lowered. As a result, the source potentials of the N-channel transistors Tr3 and Tr4 decrease.

At this time, since the gate voltage of the N-channel transistor Tr4 has risen, the difference potential Vgs4 between its source and gate becomes sufficiently large, and the gate potential (voltage of the bit line / bl) of the P-channel transistor Tr1 is increased. Pull down. As a result, the sense amplifier activation signal psa
, Sufficient charge is supplied to the bit line pair bl through the P-channel transistor Tr1, and the voltage level rises sharply.

On the other hand, when amplifying "L" data,
Bit line pair bl, / bl due to the charge from the memory cell
Potential difference ΔV occurs in the P-channel transistor Tr
The gate voltages of the 2- and N-channel transistors Tr4 fall to (Vpr-ΔV). The operation up to this point is shown in FIG.
This is the same as the conventional example shown in FIG.

Thereafter, first, by increasing the voltage level of the P-channel sense amplifier activating signal psa,
The difference potential Vgs2 between the gate and the source of the P-channel transistor Tr2 gradually increases. Thereby, the P-channel transistor Tr is output from the sense amplifier activation signal psa.
2, the supply of charges starts, and the voltage of the node A of the bit line / bl gradually increases.

Next, by lowering the voltage level of the N-channel sense amplifier activation signal nsa, the gate-source difference potential Vgs3 of the N-channel transistor Tr3 gradually increases. As a result, the voltage of the bit line bl becomes P
It is discharged to the voltage level of the sense amplifier activation signal nsa through the channel transistor Tr3.

As described in detail above, by delaying the drive timing of the N-channel sense amplifier activation signal nsa from the drive timing of the P-channel sense amplifier activation signal psa, the P-channel sense amplifier activation signal psa is The current consumption increases after the voltage level of the N-channel sense amplifier activation signal nsa decreases. Therefore, the current consumption at the time of data amplification is reduced, and the sense amplifier activation signal psa, n
sa voltage drop can be suppressed.

As a result, as shown in FIG. 2B, even in the sense amplifier 2 located far from the sense amplifier driver 10, the sense amplifier activating signals psa, ns
The voltage drop of “a” does not occur so much, and the delay of the sense time (amplification time) hardly occurs. Therefore, even if the arrangement pattern of the data stored in each memory cell is different, the variation in the amplification time in each sense amplifier 2 can be reduced.

The time for amplifying "H" data and the time for amplifying "L" data due to the difference between the threshold voltages of P-channel transistors Tr1 and Tr2 and N-channel transistors Tr3 and Tr4 in sense amplifier 2 are reduced. Although a difference occurs, the difference in the amplification time can be reduced as compared with the conventional case (see FIG. 3). Further, the decrease in the voltage level of the sense amplifier activation signals psa and nsa is determined by the transistor capability (transistor width) of the sense amplifier driver 10.
And the layout area of the sense amplifier driver 10 can be reduced.

FIG. 4 is a diagram showing a configuration example of the delay circuit 20 in the sense amplifier driver 10. As shown in FIG. 4, the delay circuit 20 of the present embodiment is configured by cascade-connecting a plurality of inverters 22 and a plurality of fuse circuits 23. With this configuration, the delay amount of the delay circuit 20 can be adjusted arbitrarily.

That is, the difference between the threshold voltages of the P-channel transistors Tr1 and Tr2 in the sense amplifier 2 and the threshold voltages of the N-channel transistors Tr3 and Tr4 and the data mainly handled in the semiconductor memory device of the present embodiment. The optimum delay time for eliminating the variation in the amplification time of each sense amplifier 2 differs depending on the type of the amplifier.
Therefore, by providing a fuse circuit 23 in the delay circuit 20 and cutting it as necessary, the drive timing difference between the sense amplifier activation signals psa and nsa can be adjusted to a desired delay amount. I have.

It should be noted that the configurations, wirings, and the like of the respective parts shown in the above-described embodiments are merely examples of specific examples in practicing the present invention, and the technical scope of the present invention is limited thereby. It must not be interpreted in a way. That is, the present invention can be embodied in various forms without departing from the spirit or main features thereof.

For example, in the above embodiment, the delay circuit 20
Is provided on the input side of the N-channel transistor 12 in the sense amplifier driver 10, but may be provided on the output side. The delay circuit 20 does not necessarily need to be provided in the sense amplifier driver 10, and the sense amplifier activation signal p
Any configuration may be used as long as a difference can be made between the drive timings of sa and nsa.

[0046]

As described above, according to the present invention, the drive timings of the first and second sense amplifier activation signals are made different from each other. When only one of them is driven, the amplification operation by the sense amplifier is performed slowly, and the current consumption by the amplification operation can be reduced. Thus, a voltage drop of the sense amplifier activation signal can be suppressed, and a delay in amplification time can be prevented. Therefore, variation in the amplification time of each sense amplifier caused by the type of data stored in each memory cell, the arrangement pattern, and the like can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a partial configuration of an activation block of a semiconductor memory device according to an embodiment;

FIGS. 2A and 2B are diagrams showing a voltage level change of a sense amplifier activating signal according to the present embodiment, wherein FIG. 2A shows a partial configuration of an activating block, and FIG. It is a figure showing a change.

3A and 3B are diagrams showing activation timing and operation waveforms of a sense amplifier according to the present embodiment, and FIG. 3A shows an operation waveform when amplifying "H" data by a sense amplifier located near a sense amplifier driver; (B) is a diagram showing operation waveforms when "L" data is amplified by the last stage sense amplifier.

FIG. 4 is a diagram illustrating a configuration example of a delay circuit according to the present embodiment;

FIG. 5 is a diagram illustrating a configuration example of a DRAM.

FIG. 6 is a diagram showing a partial configuration of an activation block.

7A and 7B are diagrams showing a configuration and operation waveforms of a sense amplifier, FIG. 7A is a diagram showing a configuration of a sense amplifier, and FIG. 7B is a diagram showing an operation waveform thereof.

8A and 8B are diagrams showing a voltage level variation of a conventional sense amplifier activation signal, where FIG. 8A shows a partial configuration of an activation block, and FIG. 8B shows variation of the voltage level of the sense amplifier activation signal; FIG.

9A and 9B are diagrams showing an activation timing and an operation waveform of a conventional sense amplifier, and FIG. 9A shows an operation waveform when "H" data is amplified by a sense amplifier close to a sense amplifier driver. (B) is a diagram showing operation waveforms when "L" data is amplified by the last stage sense amplifier.

[Explanation of symbols]

 2 Sense amplifier 10 Sense amplifier driver 20 Delay circuit 22 Inverter 23 Fuse circuit

Claims (5)

[Claims] 1. A semiconductor memory device having a plurality of sense amplifiers that operate in response to first and second sense amplifier activating signals, wherein a drive timing of the first and second sense amplifier activating signals is provided. A semiconductor memory device characterized in that a difference is provided between the two. 2. A driving circuit for driving the first and second sense amplifier activation signals, wherein the driving timing of the first and second sense amplifier activation signals is differentiated. Item 2. The semiconductor memory device according to item 1. 3. The semiconductor memory device according to claim 1, further comprising adjusting means for adjusting a drive timing difference between said first and second sense amplifier activating signals. 4. The method according to claim 1, wherein the adjusting means is a fuse circuit provided in a delay circuit for delaying a drive timing of one of the first and second sense amplifier activation signals. 4. The semiconductor memory device according to claim 3, wherein: 5. A semiconductor memory device having a plurality of sense amplifiers operating in response to first and second sense amplifier activating signals, wherein the first and second sense amplifier activating signals include:
A semiconductor memory device comprising a delay circuit for delaying the drive timing of one of the sense amplifier activation signals compared to the other.