JP5630335B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device that performs a refresh operation.

  Conventionally, in a DRAM (Dynamic Random Access Memory), 1 or 0 is stored depending on whether or not electric charge is stored in a capacitor of a memory cell. Therefore, a refresh operation must be performed to maintain the storage. Specifically, the refresh operation means that a sense amplifier detects and amplifies a value held in a memory cell of a specified word line.

  Further, a plurality of memory banks are grouped so that the peak currents of the memory banks during the refresh operation do not overlap. A technique for shifting the start of the refresh operation for each group of memory banks (referred to as “conventional technique 1”) is known (for example, see Patent Documents 1 and 2 below). For example, the plurality of memory banks are divided into two groups, and the start of the refresh operation of the first group is made earlier than the start of the refresh operation of the second group. In this case, the refresh operation of the first group is referred to as a preceding REF, and the refresh operation of the second group is referred to as a subsequent REF.

  In addition, in order to speed up the operation of the PMOS (Positive Channel Metal Oxide Semiconductor) in the sense amplifier and speed up the opening of the bit line, a voltage value higher than a normal voltage value corresponding to 1 is sensed based on the threshold voltage. A technique called “overdrive” to be supplied to an amplifier (referred to as “conventional technique 2”) is known.

Japanese Patent Laid-Open No. 7-220469 JP 2008-299932 A JP 2003-68073 A

  However, in the prior art 1, the subsequent REF is affected by a voltage drop generated by the consumption current of the previous REF. Therefore, there is a problem in that the memory deterioration rate of the memory cell in the memory bank in which the subsequent REF is continuously performed becomes faster than the memory cell in the memory bank in which the subsequent REF is continuously performed. In the prior art 2, since a voltage value higher than the normal voltage value is supplied to the sense amplifier, if a voltage value higher than the normal voltage value is simultaneously supplied to a plurality of sense amplifiers, the current consumption increases. There is a problem.

  An object of the present invention is to provide a semiconductor memory device capable of reducing current consumption during a refresh operation in order to solve the above-described problems caused by the prior art.

  According to one aspect of the present invention, a plurality of memory banks each having a sense amplifier, and a sense amplifier of a part of the memory banks among the plurality of memory banks and the sense amplifier group activated by the same refresh operation. The voltage value supplied to the active period is set to a first voltage value that activates the sense amplifiers in the some memory banks in a first period within the active period of the sense amplifiers in the some memory banks. A second voltage value higher than the first voltage value is set in a second period different from the first period, and the sense amplifiers in the remaining memory banks are selected from the sense amplifier groups in the plurality of memory banks. A semiconductor memory device is proposed that includes a control circuit that sets a supplied voltage value to the first voltage value.

  According to one aspect of the present invention, it is possible to reduce current consumption during a refresh operation.

FIG. 1 is an explanatory diagram showing an example of the present invention. FIG. 2 is an explanatory diagram showing another example of the present invention. FIG. 3 is a block diagram illustrating an example of a DRAM. FIG. 4 is an explanatory diagram showing the MEMORY CORE CONTROLLER 307 and the memory bank 308-i. FIG. 5 is an explanatory diagram showing an example of the MEMORY CELL ARRAY 311-i. FIG. 6 is an explanatory diagram illustrating an example of a memory cell. FIG. 7 is an explanatory diagram illustrating an example of a sense amplifier. FIG. 8 is an explanatory diagram illustrating a signal example when the sense amplifier is overdriven in the period x and the period z. FIG. 9 is an explanatory diagram illustrating a signal example when the sense amplifier is overdriven during the period x. FIG. 10 is an explanatory diagram illustrating a signal example when the sense amplifier is overdriven during the period z. FIG. 11 is an explanatory diagram illustrating a signal example when the sense amplifier is not overdriven. FIG. 12 is an explanatory diagram showing a partial example of the COMMAND DECODER 303. FIG. 13 is an explanatory diagram illustrating a partial example of the MEMORY CORE CONTROLLER 307. FIG. 14 is an explanatory diagram illustrating an example of the Core control circuit 1310 to the Core control circuit 1313. FIG. 15 is an explanatory diagram of the first embodiment. FIG. 16 is an explanatory diagram of the second embodiment. FIG. 17 is an explanatory diagram of the third embodiment. FIG. 18 is an explanatory diagram of the fourth embodiment. FIG. 19 is an explanatory diagram of the fifth embodiment. FIG. 20 is an explanatory diagram of the sixth embodiment. FIG. 21 is an explanatory diagram showing signal values in each embodiment. FIG. 22 is an explanatory diagram of an example of switching the value of Status. FIG. 23 is an explanatory diagram illustrating another example of the Core control circuit 1310 to the Core control circuit 1313. FIG. 24 is an explanatory diagram of the seventh embodiment.

  Exemplary embodiments of a semiconductor memory device according to the present invention will be explained below in detail with reference to the accompanying drawings.

  FIG. 1 is an explanatory diagram showing an example of the present invention. For example, the semiconductor memory device includes memory banks 101 to 104 and a control circuit. The timing chart 100 shows changes in each BL (Bit Line) 0 of SA (Sense Amplifier) 00, SA10, SA20, and SA30 during the refresh operation. In the timing chart 100, since the value of each memory cell is BL0 when the value is 1, the voltage value of BL is equal to or higher than the first voltage value during the active period of the sense amplifier.

  In the timing chart 100, during the refresh operation of WL (Word Line) 0, SA00 of the memory bank 101 and SA10 of the memory bank 102 are overdriven, and SA20 of the memory bank 103 and SA30 of the memory bank 104 are not overdriven. .

  Specifically, for example, during the refresh operation of WL0, the control circuit supplies voltage values supplied to SA00 and SA10 during the first active period of SA00 of memory bank 101 and SA10 of memory bank 102, respectively. Set to the first voltage value. Specifically, for example, during the refresh operation of WL0, the control circuit supplies voltage values supplied to SA00 and SA10 in the second active period of SA00 of memory bank 101 and SA10 of memory bank 102, respectively. The second voltage value is higher than the first voltage value.

  Specifically, for example, during the refresh operation of WL0, the control circuit supplies the voltage value supplied to SA20 and SA30 during the activation period of SA20 of memory bank 103 and SA30 of memory bank 104 to the first voltage value. To.

  In the timing chart 100, during the refresh operation of WL1, SA00 of the memory bank 101 and SA20 of the memory bank 103 are overdriven, and SA10 of the memory bank 102 and SA30 of the memory bank 104 are not overdriven.

  Specifically, for example, during the refresh operation of WL1, the control circuit supplies voltage values supplied to SA00 and SA20 in the first period of the respective active periods of SA00 of memory bank 101 and SA20 of memory bank 103. Set to the first voltage value. Specifically, for example, during the refresh operation of WL1, the control circuit supplies voltage values supplied to SA00 and SA20 in the second active period of SA00 of memory bank 101 and SA20 of memory bank 103. The second voltage value is higher than the first voltage value.

  Specifically, for example, during the refresh operation of WL1, the control circuit supplies the voltage value supplied to SA10 and SA30 during the activation period of SA10 of memory bank 102 and SA30 of memory bank 104 to the first voltage value. To.

  In the timing chart 100, SA00 of the memory bank 101 and SA30 of the memory bank 104 are overdriven during the refresh operation of WL2, and SA10 of the memory bank 102 and SA20 of the memory bank 103 are not overdriven.

  Specifically, for example, during the refresh operation of WL2, the control circuit supplies voltage values to be supplied to SA00 and SA30 during the first active period of SA00 of memory bank 101 and SA30 of memory bank 104. Set to the first voltage value. Specifically, for example, the control circuit supplies voltage values to be supplied to SA00 and SA30 in the second period of the active period of SA00 of memory bank 101 and SA30 of memory bank 104 during the refresh operation of WL2. A second voltage value higher than the voltage value of 1 is set.

  FIG. 2 is an explanatory diagram showing another example of the present invention. In the timing chart 200, changes in BL0 of SA00 of the memory bank 101, SA10 of the memory bank 102, SA20 of the memory bank 103, and SA30 of the memory bank 104 during the refresh operation of WL0 to WLn are shown.

  In the timing chart 200, during the first refresh operation of WL0 to WLn, SA00 of the memory bank 101 and SA10 of the memory bank 102 are overdried in the second period. In the timing chart 200, the SA20 of the memory bank 103 and the SA30 of the memory bank 104 are not overdriven during the first refresh operation of WL0 to WLn.

  In the timing chart 200, during the second refresh operation of WL0 to WLn, SA20 of the memory bank 103 and SA30 of the memory bank 104 are overdried in the second period. In the timing chart 200, SA00 of the memory bank 101 and SA10 of the memory bank 102 are not overdriven during the second refresh operation of WL0 to WLn.

  Here, an active command, a precharge command, and a refresh command used in this embodiment will be described. The active command (hereinafter referred to as “ACTV command”) is a command for enabling the memory bank and the word line based on the input memory bank address and row address.

  The precharge command (hereinafter referred to as “PRE command”) is a command for closing a memory bank and a row address opened by an ACTV command (saving the row address in an invalid manner).

  The refresh command (hereinafter referred to as “REF command”) is a command for executing a refresh operation. For example, an ACTV command and a PRE command are input before the REF command. An interval of tREF must be provided between the input of the ACTV command and the input of the REF command. In addition, an interval of tREFC must be provided between the input of the REF command and the input of the next ACTV command or REF command.

  In the embodiment, the activation start of the sense amplifiers of some of the plurality of memory banks is different from the activation start of the sense amplifiers of the remaining memory banks of the plurality of memory banks. explain.

(Embodiment)
(DRAM block diagram)
FIG. 3 is a block diagram illustrating an example of a DRAM. In this embodiment, a DRAM 300 is described as an example of a semiconductor memory device that performs a refresh operation. The DRAM 300 includes a CLOCK BUFFER 301, an ADDRESS BUFFER 302, a COMMAND DECODER 303, and an I / O (Input / Output) BUFFER 304. The DRAM 300 includes a BURST CONTROLLER 305, an ADDRESS CONTROLLER 306, a MEMORY CORE CONTROLLER 307, and a memory bank 308-i (i = 0 to 3).

  The CLOCK BUFFER 301 supplies a clock to each block using the clock input from the CLK / CKE terminal 321. The ADDRESS BUFFER 302 holds a row address and a memory bank address input from the A terminal 322 and the BA terminal 323, respectively. Specifically, for example, the ADDRESS BUFFER 302 is a latch.

  The COMMAND DECODER 303 converts the command into a command that can be interpreted in the DRAM 300 according to a combination of values input from the CSB terminal 324, the RASB terminal 325, the CASB terminal 326, and the WEB terminal 327. Specifically, for example, the COMMAND DECODER 303 outputs signals of actpz, prepz, refpz, refpzd, and refz to the MEMORY CORE CONTROLLER 307.

  The I / O BUFFER 304 holds a value input from the MASK terminal 328 or the DQ terminal 329 or outputs data from the READ AMP 312-i to the DQ terminal 329. Specifically, for example, the I / O BUFFER 304 is a latch or an output Gate.

  The ADDRESS CONTROLLER 306 controls the address received from the ADDRESS BUFFER 302. BURST CONTROLLER 305 controls burst instructions.

  The MEMORY CORE CONTROLLER 307 determines an X address and a Y address according to data from the I / O BUFFER 304, the COMMAND DECODER 303, and the ADDRESS CONTROLLER 306. More specifically, for example, the MEMORY CORE CONTROLLER 307 passes signals of wlonz_i, saeodz_i, saeaz_i, and saez_i to the memory bank 308-i.

  The memory bank 308-i has a Y CONTROLLER 309-i, an X CONTROLLER 310-i, a MEMORY CELL ARRAY 311-i, a READ AMP 312-i, and a WRITE AMP 313-i.

  Y CONTROLLER 309-i controls reading and writing of the memory cell at the designated Y address. The X CONTROLLER 310-i controls reading and writing of the memory cell at the designated X address. MEMORY CELL ARRAY 311-i is a memory cell group arranged in an array.

  The READ AMP 312-i amplifies the voltage value of the data read from each MEMORY CELL ARRAY 311-i at the time of a read command. The READ AMP 312-i passes the amplified data to the I / O BUFFER 304. The WRITE AMP 313-i amplifies the voltage value of the write data transferred from the I / O BUFFER 304 at the time of the write command. The WRITE AMP 313-i delivers the amplified data to a designated memory cell in the MEMORY CELL ARRAY 311-i.

  FIG. 4 is an explanatory diagram showing the MEMORY CORE CONTROLLER 307 and the memory bank 308-i. FIG. 4 shows signals passed from the MEMORY CORE CONTROLLER 307 to the memory bank 308-i. In FIG. 4, READ AMP 312-i and WRITE AMP 313-i are omitted.

  The MEMORY CORE CONTROLLER 307 delivers wlonz_0, saeodz_0, saeaz_0, and saez_0 to the memory bank 308-0. The MEMORY CORE CONTROLLER 307 delivers wlonz_1, saeodz_1, saeaz_1, and saez_1 to the memory bank 308-1.

  The MEMORY CORE CONTROLLER 307 delivers wlonz_2, saeodz_2, saeaz_2, and saez_2 to the memory bank 308-2. The MEMORY CORE CONTROLLER 307 delivers wlonz_3, saeodz_3, saeaz_3, and saez_3 to the memory bank 308-3.

  FIG. 5 is an explanatory diagram showing an example of the MEMORY CELL ARRAY 311-i. The MEMORY CELL ARRAY 500 is an example of the MEMORY CELL ARRAY 311-i and is an open bit line system. In the MEMORY CELL ARRAY 500, memory cells are arranged through bit contacts at the intersections of WL and BL, / BL.

  Here, BL and / BL indicate any bit line. The sense amplifier outputs voltages corresponding to 1 and 0 to BL and / BL, respectively, based on the threshold voltage. Here, a voltage corresponding to 1 on the basis of the threshold voltage is referred to as a high voltage, and a high voltage value is referred to as a high voltage value. A voltage corresponding to 0 based on the threshold voltage is referred to as a Low voltage, and a value of the Low voltage is referred to as a Low voltage value. The overdrive voltage is referred to as an overdrive voltage, and the overdrive voltage value is referred to as an overdrive voltage value. The threshold voltage is referred to as a half voltage.

  Further, saeodz_n (n is any value from 0 to 3), saeaz_n, and saez_n are input to the sense amplifier. For example, in the case of a sense amplifier of MEMORY CELL ARRAY 311-0, saeodz_0, saeaz_0, and saez_0 are input.

  FIG. 6 is an explanatory diagram illustrating an example of a memory cell. The memory cell 600 is a detailed example of each memory cell of the MEMORY CELL ARRAY 500. The memory cell 600 has a MOS 601 and a capacitor 602. Memory cell 600 stores 1 or 0 depending on whether or not charge is stored in capacitor 602. The gate of the MOS 601 is connected to WL, the source of the MOS 601 is connected to BL, and the drain of the MOS 601 is connected to one end of the capacitor 602. The other end of the capacitor 602 is connected to a power source that supplies a plate potential.

  FIG. 7 is an explanatory diagram illustrating an example of a sense amplifier. The sense amplifier 700 is a detailed example of the sense amplifier indicated by the MEMORY CELL ARRAY 500. Sense amplifier 700 detects whether a memory cell on a designated word line stores 1 or 0. The sense amplifier 700 amplifies the data in the memory cell based on the detection result.

  A is a signal line for supplying a power supply voltage to the PMOS. B is a signal line for supplying a power supply voltage to the NMOS. C is a signal line for supplying a half voltage for precharging. D is a control signal for precharging.

  When the value of saez_n is High, the MOS 703 is turned on, and the Low voltage is supplied to the sense amplifier 700. For example, the voltage value of / BL becomes the Low voltage value. In the following description, description of the operation of the MOS 703 is omitted, and when the value of saez_n becomes High, a Low voltage is supplied to the sense amplifier.

  When the value of saeaz_n is High, the MOS 702 is turned on, and a High voltage is supplied to the sense amplifier 700. For example, the voltage value of BL becomes a High voltage value. In the following description, the description of the MOS 702 is omitted, and when it is saeaz_n, a high voltage is supplied to the sense amplifier.

  Since the MOS 701 is turned on and the overdrive voltage is supplied to the sense amplifier 700 while the value of saeodz_n is High, the voltage value of BL becomes the overdrive voltage value. In the following description, the description of the operation of the MOS 701 is omitted, and when it becomes saeodz_n, an overdrive voltage is supplied to the sense amplifier.

  Here, it is assumed that the active periods of the sense amplifiers of each MEMORY CELL ARRAY 311-i are the same time, and the description will be divided into the period x, the period y, and the period z. The period x is a period from the activation start time of the sense amplifier to the time after a predetermined time has elapsed in the active period of the sense amplifier. The predetermined time is determined by the designer of the DRAM 300. The period z is a period from the time before the activation end of the sense amplifier to the activation end time of the sense amplifier in the activation period of the sense amplifier. The predetermined time is determined by the designer of the DRAM 300. The period y is a period between the period x and the period z in the active period of the sense amplifier.

  FIG. 8 is an explanatory diagram illustrating a signal example when the sense amplifier is overdriven in the period x and the period z. A timing chart 800 shows a signal example when the sense amplifier is overdriven during the period x and the period z in the active period of the sense amplifier activated during the refresh operation. In the following description, an example in which H is output to the BL side will be described.

  In the timing chart 800, since the designated WL is activated during the period when the value of wlonz_n is High, the value of the designated WL becomes High. In the timing chart 800, when the value of saez_n becomes High during the active period of the sense amplifier, the Low voltage is supplied to the sense amplifier, and the voltage value of / BL decreases to the Low voltage value.

  In the timing chart 800, the value of saeodz_n becomes High and the value of saeaz_n becomes Low during the period x of the active period of the sense amplifier. Thus, the overdrive voltage is supplied to the sense amplifier during the period x in the active period of the sense amplifier, and the voltage value of BL becomes the overdrive voltage value.

  In the timing chart 800, the value of saeodz_n is Low and the value of saeaz_n is High during the period y of the active period of the sense amplifier. As a result, a high voltage is supplied to the sense amplifier during the period y of the active period of the sense amplifier, and the voltage value of BL becomes the high voltage.

  In the timing chart 800, the value of saeodz_n becomes High and the value of saeaz_n becomes Low during the period z of the active period of the sense amplifier. As a result, the overdrive voltage is supplied to the sense amplifier during the period z of the active period of the sense amplifier, and the voltage value for BL becomes the voltage value for overdrive.

  FIG. 9 is an explanatory diagram illustrating a signal example when the sense amplifier is overdriven during the period x. A timing chart 900 shows a signal example when the sense amplifier is overdriven during the period x of the active period of the sense amplifier activated during the refresh operation.

  In the timing chart 900, since the designated WL is activated during the period when the value of wlonz_n is High, the value of the designated WL becomes High. In the timing chart 900, when the value of saez_n becomes High during the active period of the sense amplifier, the Low voltage is supplied to the sense amplifier, and the voltage value of / BL decreases to the Low voltage value.

  In the timing chart 900, in the period x of the active period of the sense amplifier, the value of saeodz_n becomes High and the value of saeaz_n becomes Low. Thus, the overdrive voltage is supplied to the sense amplifier during the period x in the active period of the sense amplifier, and the voltage value of BL becomes the overdrive voltage value.

  In the timing chart 900, in the period y and the period z in the active period of the sense amplifier, the value of saeodz_n is Low and the value of saeaz_n is High. As a result, the High voltage is supplied to the sense amplifier during the period y and the period z in the active period of the sense amplifier, and the BL voltage value becomes the High voltage value.

  FIG. 10 is an explanatory diagram illustrating a signal example when the sense amplifier is overdriven during the period z. A timing chart 1000 shows a signal example when the sense amplifier is overdriven during the period z of the active period of the sense amplifier during the refresh operation.

  In the timing chart 1000, since the designated WL is activated during the period in which the value of wlonz_n is High, the value of the designated WL becomes High. In the timing chart 1000, during the period when the value of saez_n is High, the Low voltage is supplied to the sense amplifier, and the voltage value of / BL decreases to the Low voltage value.

  In the timing chart 1000, in the period x and the period y in the active period of the sense amplifier, the value of saeodz_n is Low and the value of saeaz_n is High. As a result, the high voltage is supplied to the sense amplifier during the period x and the period y in the active period of the sense amplifier, and the voltage value of BL becomes the high voltage value.

  In the timing chart 1000, the value of saeodz_n becomes High and the value of saeaz_n becomes Low during the period z of the active period of the sense amplifier. As a result, the overdrive voltage is supplied to the sense amplifier during the period z of the active period of the sense amplifier, and the voltage value of BL becomes the overdrive voltage value.

  FIG. 11 is an explanatory diagram illustrating a signal example when the sense amplifier is not overdriven. The timing chart 1100 shows an example in which the sense amplifier is not overdriven during the active period of the sense amplifier during the refresh operation.

  In the timing chart 1100, since the designated WL is activated during the period when the value of wlonz_n is High, the value of the designated WL becomes High. In the timing chart 1100, during a period in which the value of saez_n is High, the Low voltage is supplied to the sense amplifier, and the voltage value of / BL decreases to the Low voltage value.

  In the timing chart 1100, the value of saeodz_n is Low and the value of saeaz_n is High during the active period of the sense amplifier. As a result, the high voltage is supplied to the sense amplifier during the active period of the sense amplifier, and the voltage value of BL becomes the high voltage value.

  FIG. 12 is an explanatory diagram showing a partial example of the COMMAND DECODER 303. The COMMAND DECODER 300 includes a command generation unit 1201 and a delay 1202. The command generation unit 1201 determines a command according to a combination of values input from the CSB terminal 324, the RASB terminal 325, the CASB terminal 326, and the WEB terminal 327, and outputs an internal signal. In FIG. 12, the internal signals are actpz, prepz, refz, and refpz.

  When an ACTV command is input, the Command generator 1201 sets actpz to High for a certain time. When the PRE command is input, the Command generator 1201 sets prepz to High for a certain time. When the REF command is input, the Command generator 1201 sets refz and refpz to High for a certain time. Delay 1202 outputs refpzd obtained by delaying refpz.

  FIG. 13 is an explanatory diagram illustrating a partial example of the MEMORY CORE CONTROLLER 307. FIG. 13 shows a partial detailed example of the MEMORY CORE CONTROLLER 307. The MEMORY CORE CONTROLLER 307 outputs wlonz_i, saeaz_i, saeodz_i, and saez_i to the memory bank 308_i, respectively. The MEMORY CORE CONTROLLER 307 includes a selection circuit 1301, a selection circuit 1302, an inverter 1303, a Ref counter 1304, and a core control circuit 1310 to a core control circuit 1313.

  The Ref counter 1304 issues a signal (Status) for determining the operation order of the refresh operation. Specifically, for example, the Ref counter 1304 counts the number of refresh operations, and when the specified number is exceeded, the value of Status is inverted.

  The selection circuit 1301 selects one of refpz and refpzd in accordance with Status. For example, when the value of Status is 0, the selection circuit 1301 outputs the value of refpz, and when the value of Status is 1, the selection circuit 1301 outputs the value of refpzd.

  The selection circuit 1302 selects one of the signals refpz and refpzd according to the status. For example, when the value of Status is 0, the selection circuit 1302 outputs the value of refpzd, and when the value of Status is 1, the selection circuit 1302 outputs the value of refpz.

  That is, when the value of Status is 0, the activation of the bank activation of the memory bank 308-0 and the memory bank 308-1 is greater than the activation of the sense amplifier of the memory bank 308-2 and the activation of the bank of the memory bank 308-3 during the refresh operation. Get faster. If the value of Status is 1, the bank activation start of the memory bank 308-0 and the memory bank 308-1 is more active than the sense amplifier of the memory bank 308-2 and the bank activation start of the memory bank 308-3 during the refresh operation. Become slow.

  The inverter 1303 outputs the inverted value of the SEL value to the core control circuit 1312 and the core control circuit 1313. When the value of SEL is 0, the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 are not overdriven. When the value of SEL is 1, the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 are not overdriven.

  The Core control circuit 1310 to the Core control circuit 1313 output wlonz_0 to wlonz_3, saeaz_0 to saeaz_3, saeod_0 to saeodz_3, saez_0 to saez_3, respectively.

  FIG. 14 is an explanatory diagram illustrating an example of the Core control circuit 1310 to the Core control circuit 1313. The Core control circuit 1400 is a detailed example of each of the Core control circuit 1310 to the Core control circuit 1313.

  The Core control circuit 1400 outputs wlonz_n, saeaz_n, saeodz_n, and saez_n. The Core control circuit 1400 includes a NOR 1401, an inverter 1402, an RS latch 1403, a buffer 1404, a Delay 1405, a NAND 1406, a Delay 1407, and an AND 1408. The Core control circuit 1400 includes a NAND 1411, a NAND 1412, a combinational circuit 1413, a Delay 1414, an inverter 1415, an inverter 1416, a combinational circuit 1417, and a combinational circuit 1418.

  Here, one element of NAND, NOR, or inverter is one stage, and the odd stage in FIG. 14 indicates that an odd number of the elements are arranged, and the even stage in FIG. 14 indicates an even number of the elements. It shows that they are lined up.

  In the core control circuit 1400, wlonz_n and saez_n are output by the NORs 1401 to AND1408. In the core control circuit 1400, saeodz_n and saeaz_n are output by the NAND 1411 to the combination circuit 1418. saez_n becomes High for the active period of the sense amplifier. Specifically, Delay 1414 is, for example, a combination of NOR and an inverter.

  In the Core control circuit 1400, if the value of sel is Low, the value of saeodz_n remains Low. In the core control circuit 1400, when the value of sel is High and the value of Sta is High, when the value of refz is changed from Low to High, the value of saedz_n becomes High during the period x of the active period of the sense amplifier. , Saeaz_n becomes Low. In the core control circuit 1400, when the value of sel is High, the value of End is High, and the value of odz is High, when the value of refz is changed from Low to High, saodez_n in the period z of the active period of the sense amplifier. The value of becomes High. Then, in the Core control circuit 1400, the value of saeaz_n becomes Low.

  Next, Examples 1 to 6 are used in which sense amplifiers in some memory banks are overdriven and sense amplifiers in the remaining memory banks are not overdriven among the sense amplifier groups activated in the same refresh operation. I will explain.

  In the first, third, and fifth embodiments, the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 are not overdriven during the refresh operation. In the first, third, and fifth embodiments, the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 are overdriven during the refresh operation. In the second, fourth, and sixth embodiments, the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 are overdriven during the refresh operation. In the second, fourth, and sixth embodiments, the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 are not overdriven during the refresh operation.

Example 1
In the first embodiment, the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 are not overdriven during the refresh operation. In the first embodiment, in the refresh operation, the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 are overdriven during the period z of the active periods of the respective sense amplifiers.

The value of each signal in Example 1 is shown below.
・ Status = Low
SEL = Low (core control circuit 1310 sel = Low, Core control circuit 1311 sel = Low, Core control circuit 1312 sel = High, Core control circuit 1313 sel = High)
-Each core control circuit Sta = Low
-End = High of each Core control circuit
-Each core control circuit odz = High

  FIG. 15 is an explanatory diagram of the first embodiment. In FIG. 15, wlonz_0 to wlonz_3 and saez_0 to saez_3 are omitted. ACTV indicates input of the ACTV command, PRE indicates input of the PRE command, and REF indicates input of the REF command. In the timing chart 1500, the refresh operation start of the memory bank 308-0 and the memory bank 308-1 is earlier than the start of the refresh operation of the memory bank 308-2 and the memory bank 308-3. In the timing chart 1500, the sense amplifier of the memory bank 308-0 is not overdriven during the active operation.

  In the timing chart 1500, the value of saeodz_0 and the value of saeodz_1 are Low during the active periods of the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 by the refresh operation. In the timing chart 1500, the value of saeaz_0 and the value of saeaz_1 are High during the active period. Accordingly, during the active period, a high voltage is supplied to the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1, and the BL voltage value of the memory bank 308-0 and the memory bank 308-1 are supplied. The voltage value of BL becomes the voltage value for High.

  In the timing chart 1500, the value of saeodz_2 and the value of saeodz_3 are Low during the period x and the period y of the active periods of the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 by the refresh operation. is there. In the timing chart 1500, the value of saeaz_2 and the value of saeaz_3 are High in the period x and the period y. As a result, during the period x and the period y, a high voltage is supplied to the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3. Therefore, during the period x and the period y, the voltage value of BL in the memory bank 308-2 and the voltage value of BL in the memory bank 308-3 become high voltage values.

  In the timing chart 1500, the value of saeodz_2 and the value of saeodz_3 are High in the period z of the active periods of the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 by the refresh operation. In the timing chart 1500, the value of saeaz_2 and the value of saeaz_3 are Low during the period z. As a result, the overdrive voltage is supplied to the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 during the period z. Therefore, during the period z, the voltage value of BL in the memory bank 308-2 and the voltage value of BL in the memory bank 308-3 become the voltage values for overdrive.

(Example 2)
In the second embodiment, during the refresh operation, the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 are overdriven during the period z of the active period of each sense amplifier. In the second embodiment, the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 are not overdriven during the refresh operation.

The value of each signal in Example 2 is shown below.
・ Status = Low
SEL = High (core control circuit 1310 sel = High, Core control circuit 1311 sel = High, Core control circuit 1312 sel = Low, Core control circuit 1313 sel = Low)
-Each core control circuit Sta = Low
-End = High of each Core control circuit
-Each core control circuit odz = High

  FIG. 16 is an explanatory diagram of the second embodiment. In FIG. 16, wlonz_0 to wlonz_3 and saez_0 to saez_3 are omitted. In the timing chart 1600, the refresh operation of the memory bank 308-0 and the memory bank 308-1 starts earlier than the start of the refresh operation of the memory bank 308-2 and the memory bank 308-3. In the timing chart 1600, the sense amplifier of the memory bank 308-0 is not overdriven during the active operation.

  In the timing chart 1600, the value of saeodz_0 and the value of saeodz_1 are Low during the period x and the period y of the active periods of the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 by the refresh operation. is there. In the timing chart 1600, the value of saeaz_0 and the value of saeaz_1 are High in the period x and the period y. Accordingly, a high voltage is supplied to the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 in the period x and the period y. Therefore, during the period x and the period y, the BL voltage value of the memory bank 308-0 and the BL voltage value of the memory bank 308-1 become the high voltage value.

  In the timing chart 1600, the value of saeodz_0 and the value of saeodz_1 are High during the period z of the active periods of the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 by the refresh operation. In the timing chart 1600, the value of saeaz_0 and the value of saeaz_1 are Low during the period z. Thereby, in the period z, the overdrive voltage is supplied to the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1. Therefore, during the period z, the voltage value of BL of the memory bank 308-0 and the voltage value of BL of the memory bank 308-1 become voltage values for overdrive.

  In the timing chart 1600, the values of saeodz_2 and saeodz_2 are Low during the active periods of the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 by the refresh operation. In the timing chart 1600, the value of saeaz_2 and the value of saeaz_3 are High during the active period. Thus, a high voltage is supplied to the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 during the active period. Therefore, during the active period, the voltage value of BL in the memory bank 308-2 and the voltage value of BL in the memory bank 308-3 become the high voltage values. The first embodiment and the second embodiment can be switched depending on whether the value of SEL is Low or High.

Example 3
In the third embodiment, the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 are not overdriven during the refresh operation. In the third embodiment, during the refresh operation, the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 are overdriven during the period x of the active period of each sense amplifier.

The value of each signal in Example 3 is shown below.
・ Status = Low
SEL = Low (core control circuit 1310 sel = Low, Core control circuit 1311 sel = Low, Core control circuit 1312 sel = High, Core control circuit 1313 sel = High)
・ Sta = High of each Core control circuit
-End = Low of each Core control circuit
-Odz = Low of each Core control circuit

  FIG. 17 is an explanatory diagram of the third embodiment. In FIG. 17, wlonz_0 to wlonz_3 and saez_0 to saez_3 are omitted. In the timing chart 1700, the refresh operation start of the memory bank 308-0 and the memory bank 308-1 is earlier than the start of the refresh operation of the memory bank 308-2 and the memory bank 308-3. In the timing chart 1700, the sense amplifier of the memory bank 308-0 is not overdriven during the active operation.

  In the timing chart 1700, the value of saeodz_0 and the value of saeodz_1 are Low during the active period of the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 by the refresh operation. In the timing chart 1700, the value of saeodz_0 and the value of saeodz_1 are Low during the active period, and the value of saaez_0 and the value of saaez_1 are High. Accordingly, a high voltage is supplied to the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 during the active period. Therefore, during the active period, the voltage value of BL in the memory bank 308-0 and the voltage value of BL in the memory bank 308-1 become the high voltage value.

  In the timing chart 1700, the value of saeodz_2 and the value of saeodz_3 are High during the period x of the active period of the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 by the refresh operation. In the timing chart 1700, the value of saeaz_2 and the value of saeaz_3 are Low during the period x. As a result, the overdrive voltage is supplied to the sense amplifier in the memory bank 308-2 and the sense amplifier in the memory bank 308-3 during the period x. Therefore, during the period x, the voltage value of BL in the memory bank 308-2 and the voltage value of BL in the memory bank 308-3 become voltage values for overdrive.

  In the timing chart 1700, the value of saeodz_2 and the value of saeodz_3 are Low in the period y and the period z of the active periods of the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 by the refresh operation. . In the timing chart 1700, the value of saeaz_2 and the value of saeaz_3 are High in the period y and the period z. Accordingly, a high voltage is supplied to the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 during the period y and the period z. Therefore, during the period y and the period z, the voltage value of BL in the memory bank 308-2 and the voltage value of BL in the memory bank 308-3 become high voltage values.

Example 4
In the fourth embodiment, during the refresh operation, the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 are overdriven during the period x of the active period of each sense amplifier. In the fourth embodiment, the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 are not overdriven during the refresh operation.

The value of each signal in Example 4 is shown below.
・ Status = Low
SEL = High (core control circuit 1310 sel = High, Core control circuit 1311 sel = High, Core control circuit 1312 sel = Low, Core control circuit 1313 sel = Low)
・ Sta = High of each Core control circuit
-End = Low of each Core control circuit
-Odz = Low of each Core control circuit

  FIG. 18 is an explanatory diagram of the fourth embodiment. In FIG. 18, wlonz_0 to wlonz_3 and saez_0 to saez_3 are omitted. In the timing chart 1800, the refresh operation of the memory bank 308-0 and the memory bank 308-1 starts earlier than the start of the refresh operation of the memory bank 308-2 and the memory bank 308-3. In the timing chart 1800, the sense amplifier of the memory bank 308-0 is not overdriven during the active operation.

  In the timing chart 1800, the value of saeodz_0 and the value of saeodz_1 are High in the period x of the active periods of the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 by the refresh operation. In the timing chart 1800, the value of saeaz_0 and the value of saeaz_1 are low during the period x. Thereby, in the period x, the overdrive voltage is supplied to the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1. Therefore, during the period x, the voltage value of BL in the memory bank 308-0 and the voltage value of BL in the memory bank 308-1 become voltage values for overdrive.

  In the timing chart 1800, the value of saeodz_0 and the value of saeodz_1 are Low during the periods y and z of the active periods of the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 by the refresh operation. is there. In the timing chart 1800, the value of saeaz_0 and the value of saeaz_1 are High during the period y and the period z. Thus, a high voltage is supplied to the sense amplifier in the memory bank 308-0 and the sense amplifier in the memory bank 308-1 during the period y and the period z. Therefore, during the period y and the period z, the voltage value of BL in the memory bank 308-0 and the voltage value of BL in the memory bank 308-1 become high voltage values.

  In the timing chart 1800, the value of saeodz_2 and the value of saeodz_3 are Low during the active periods of the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 by the refresh operation. In the timing chart 1800, the value of saeaz_2 and the value of saeaz_3 are High during the active period. Thus, a high voltage is supplied to the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 during the active period. Therefore, the voltage value of BL in the memory bank 308-2 and the voltage value of BL in the memory bank 308-3 are the voltage values for High. The third embodiment and the fourth embodiment can be switched depending on whether SEL is 0 or 1.

(Example 5)
In the fifth embodiment, the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 are not overdriven during the refresh operation. In the fifth embodiment, during the refresh operation, the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 are overdriven in the period x and the period z of the active periods of the respective sense amplifiers.

The value of each signal in Example 5 is shown below.
・ Status = Low
SEL = Low (core control circuit 1310 sel = Low, Core control circuit 1311 sel = Low, Core control circuit 1312 sel = High, Core control circuit 1313 sel = High)
・ Sta = High of each Core control circuit
-End = High of each Core control circuit
-Each core control circuit odz = High

  FIG. 19 is an explanatory diagram of the fifth embodiment. In FIG. 19, wlonz_0 to wlonz_3 and saez_0 to saez_3 are omitted. In the timing chart 1900, the refresh operation start of the memory bank 308-0 and the memory bank 308-1 is earlier than the start of the refresh operation of the memory bank 308-2 and the memory bank 308-3. In the timing chart 1900, the sense amplifier of the memory bank 308-0 is not overdriven during the active operation.

  In the timing chart 1900, the value of saeodz_0 and the value of saeodz_1 are Low during the active period of the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 by the refresh operation. In the timing chart 1900, the value of saeaz_0 and the value of saeaz_1 are High during the active period. Accordingly, a high voltage is supplied to the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 during the active period. Accordingly, the BL voltage value of the memory bank 308-0 and the BL value of the memory bank 308-1 become the high voltage value during the active period.

  In the timing chart 1900, the value of saeodz_2 and the value of saeodz_3 are High during the period x of the active periods of the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 by the refresh operation. In the timing chart 1900, the value of saeaz_2 and the value of saeaz_3 are Low during the active period. As a result, the overdrive voltage is supplied to the sense amplifier in the memory bank 308-2 and the sense amplifier in the memory bank 308-3 during the period x. Therefore, the voltage value of BL in the memory bank 308-2 and the voltage value of BL in the memory bank 308-3 are the overdrive voltage values.

  In the timing chart 1900, the value of saeodz_2 and the value of saedz_3 are low during the period y of the active period of the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 by the refresh operation. In the timing chart 1900, the value of saeaz_2 and the value of saeaz_3 are high during the period y. Accordingly, a high voltage is supplied to the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 during the period y, and the BL voltage value of the memory bank 308-2 and the memory bank 308-3 are supplied. The voltage value of BL becomes the voltage value for High.

  In the timing chart 1900, the value of saeodz_2 and the value of saeodz_3 are High during the period z of the active periods of the sense amplifiers of the memory bank 308-2 and the memory bank 308-3. In the timing chart 1900, the value of saeaz_2 and the value of saeaz_3 are Low during the period z. As a result, the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 are transferred to the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 during the active period of the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3. A voltage for overdrive is supplied. Therefore, the voltage value of BL in the memory bank 308-2 and the voltage value of BL in the memory bank 308-3 are the overdrive voltage values.

(Example 6)
In the sixth embodiment, during the refresh operation, the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 are overdriven in the period x and the period z of the active periods of the respective sense amplifiers. In the sixth embodiment, the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 are not overdriven during the refresh operation.

The value of each signal in Example 6 is shown below.
・ Status = Low
SEL = High (core control circuit 1310 sel = High, Core control circuit 1311 sel = High, Core control circuit 1312 sel = Low, Core control circuit 1313 sel = Low)
・ Sta = High of each Core control circuit
-End = High of each Core control circuit
-Each core control circuit odz = High

  FIG. 20 is an explanatory diagram of the sixth embodiment. In FIG. 20, wlonz_0 to wlonz_3 and saez_0 to saez_3 are omitted. In the timing chart 2000, the refresh operation start of the memory bank 308-0 and the memory bank 308-1 is earlier than the start of the refresh operation of the memory bank 308-2 and the memory bank 308-3. In the timing chart 2000, the sense amplifier of the memory bank 308-0 is not overdriven during the active operation.

  In the timing chart 2000, the value of saeodz_0 and the value of saeodz_1 are High during the period x of the active periods of the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 by the refresh operation. In the timing chart 2000, the value of saeaz_0 and the value of saeaz_1 are low during the period x. Thereby, in the period x, the overdrive voltage is supplied to the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1. Therefore, the voltage value of BL in the memory bank 308-0 and the voltage value of BL in the memory bank 308-1 are the voltage values for overdrive.

  In the timing chart 2000, the value of saeodz_0 and the value of saeodz_1 are low during the period y of the active periods of the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 by the refresh operation. In the timing chart 2000, the value of saeaz_0 and the value of saeaz_1 are High during the period y. Accordingly, a high voltage is supplied to the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 during the period y. Therefore, during the period y, the BL voltage value of the memory bank 308-0 and the BL value of the memory bank 308-1 become the high voltage value.

  In the timing chart 2000, the value of saeodz_0 and the value of saeodz_1 are High during the period z of the active periods of the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 by the refresh operation. In the timing chart 2000, the value of saeaz_0 and the value of saeaz_1 are Low during the period z. Thereby, in the period z, the overdrive voltage is supplied to the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1. Therefore, during the period z, the voltage value of BL in the memory bank 308-0 and the voltage value of BL in the memory bank 308-1 become voltage values for overdrive.

  In the timing chart 2000, the value of saeodz_2 and the value of saeodz_3 are Low during the active periods of the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 by the refresh operation. In the timing chart 2000, the value of saeaz_2 and the value of saeaz_3 are High during the active period. As a result, a high voltage is supplied to the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3. Therefore, the BL voltage value of the memory bank 308-2 and the BL voltage value of the memory bank 308-3 are high voltage values during the active period of the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3. It becomes.

  FIG. 21 is an explanatory diagram showing signal values in each embodiment. In the table of FIG. 21, the value of each signal shown in Examples 1-6 is shown. The table 2100 includes an example item 2101, a Status item 2102, a SEL item 2103, a Sta item 2104, and an End item 2105.

  In the item 2101 of the example, the number of the example is registered. -Is registered in item 2101 of the example, it is an example not listed in examples 1-6. In the Status item 2102, the value of Status in the MEMORY CORE CONTROLLER 307 is registered. In the SEL item 2103, the value of SEL in the MEMORY CORE CONTROLLER 307 is registered. In an item 2104 of Sta, the value of Sta of each Core control circuit is registered. In an End item 2105, an End value of each Core control circuit is registered.

  For example, by setting the Status value to Low, the SEL value to Low, the Sta value to Low, and the End value to High, the memory banks 308-0 to 308-0 as shown in the timing chart 1500 shown in FIG. Each BL of the memory bank 308-3 changes.

  Further, when the Status value is High, the SEL value is Low, the Sta value is Low, and the End value is High, the presence or absence of overdrive is the same as that in the first embodiment. In the first embodiment, the refresh operation of the memory bank 308-0 and the refresh operation of the memory bank 308-1 are started from the start of the refresh operation of the memory bank 308-2 and the refresh operation of the memory bank 308-3. Too early. When the value of Status is High, the refresh operation of the memory bank 308-0 and the refresh operation of the memory bank 308-1 are started, the refresh operation of the memory bank 308-2 and the refresh operation of the memory bank 308-3 are started. Will be slower. The Ref counter 1304 described above counts the number of refresh operations, and inverts the value of Status when the number of refresh operations exceeds a specified number.

  FIG. 22 is an explanatory diagram of an example of switching the value of Status. For example, it is assumed that each memory bank of DRAM 300 has word lines WL0 to WL4095. The specific number is 4096, and the Ref counter 1304 inverts the value of Status for each count from 0 to 4096.

  In FIG. 22, for example, during the first refresh operation from WL0 to WL4095, the memory bank 308-0 and the memory bank 308-1 perform the A operation. The memory bank 308-2 and the memory bank 308-3 perform the B operation. In the second refresh operation from WL0 to WL4095, the value of Status becomes High, so that the memory bank 308-0 and the memory bank 308-1 perform the B operation, and the memory bank 308-2 and the memory bank 308 -3 performs the A operation. For example, the A operation and the B operation are refresh operations, the A operation is an operation in which overdrive is performed, and the B operation is an operation in which overdrive is not performed. Not limited to this, the A operation may be an operation in which overdrive is not performed, and the B operation may be an operation in which overdrive is performed.

(Example 7)
The seventh embodiment shows an example in which the sense amplifier activated during the active operation by the ACTV command is always overdriven, and only the sense amplifiers of some memory banks are overdriven during the refresh operation.

  FIG. 23 is an explanatory diagram illustrating another example of the Core control circuit 1310 to the Core control circuit 1313. The Core control circuit 2300 is a detailed example of each of the Core control circuit 1310 to the Core control circuit 1313 in the case of the seventh embodiment.

  The Core control circuit 2300 outputs wlonz_n, saeaz_n, saeodz_n, and saez_n. The Core control circuit 2300 includes a NOR 2301, an inverter 2302, an RS latch 2303, a buffer 2304, a Delay 2305, a NAND 2306, a Delay 2307, and an AND 2308. The Core control circuit 2300 includes a combinational circuit 2311, a combinational circuit 2312, a combinational circuit 2313, a Delay 2314, an inverter 2315, an inverter 2316, a combinational circuit 2317, and a combinational circuit 2318.

  The NOR 2301, the inverter 2302, the RS latch 2303, and the buffer 2304 shown in FIG. 23 are the same as the NOR 1401, the inverter 1402, the RS latch 1403, and the buffer 1404 shown in FIG. The Delay 2305, the NAND 2306, the Delay 2307, and the AND 2308 shown in FIG. 23 are the same as the Delay 1405, the NAND 1406, the Delay 1407, and the AND 1408, respectively.

  The combinational circuit 2313 and Delay 2314 shown in FIG. 23 are the same as the combinational circuit 1413 and Delay 1414 shown in FIG. The inverter 2315, the inverter 1416, the combination circuit 2317, and the combination circuit 2318 illustrated in FIG. 23 are the same as the inverter 1415, the inverter 1416, the combination circuit 1417, and the combination circuit 1418 illustrated in FIG. The connection relationship between each element is also the same.

  The Core control circuit 1400 illustrated in FIG. 14 is different from the Core control circuit 2300 illustrated in FIG. 23 in a NAND 1411 and a NAND 1412, and a combinational circuit 2311 and a combinational circuit 2312.

  When the value of saez_n becomes High except when the value of refz changes from Low to High, saeodz_n and saeaz_n change according to Sta and End. That is, when the sense amplifier is active other than during the refresh operation, the sense amplifier is overdriven in accordance with Sta and End.

  In the Core control circuit 2300, when the value of refz changes from Low to High, if the value of sel is Low, the value of saezz_n remains Low and the value of saeaz_n becomes High when the value of saez_n is High. . That is, during the refresh operation, if the value of sel is Low, the sense amplifier is not overdriven.

  In the seventh embodiment, the sense amplifier of the memory bank 308-0 is overdriven during the active operation, and the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 are not overdriven during the refresh operation. Then, during the refresh operation, the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 are overdriven in the period x and the period z of the active periods of the respective sense amplifiers.

The value of each signal in Example 7 is shown below.
・ Status = Low
SEL = Low (core control circuit 1310 sel = Low, Core control circuit 1311 sel = Low, Core control circuit 1312 sel = High, Core control circuit 1313 sel = High)
・ Sta = High of each Core control circuit
-End = High of each Core control circuit
-Each core control circuit odz = High

  FIG. 24 is an explanatory diagram of the seventh embodiment. In FIG. 24, wlonz_0 to wlonz_3 and saez_0 to saez_3 are not described. In the timing chart 2400, the refresh operation start of the memory bank 308-0 and the memory bank 308-1 is earlier than the start of the refresh operation of the memory bank 308-2 and the memory bank 308-3.

  In the timing chart 2400, a case where the memory bank 308-0 is designated by the ACTV command is taken as an example. In the timing chart 2400, in the period x of the active period of the sense amplifier of the memory bank 308-0 during the active operation, the value of saeod_0 is High and saeaz_0 is Low. As a result, the overdrive voltage is supplied to the sense amplifier of the memory bank 308-0 during the period x. Therefore, the voltage value of BL in the memory bank 308-0 becomes the voltage value for overdrive during the period x.

  In the timing chart 2400, the value of saeod_0 is low and the value of saeaz_0 is high during the period y in the active period of the sense amplifier of the memory bank 308-0 during the active operation. Accordingly, a high voltage is supplied to the sense amplifier of the memory bank 308-0 during the period y. Therefore, during the period y, the voltage value of BL in the memory bank 308-0 becomes the voltage value for High.

  In the timing chart 2400, in the period z in the active period of the sense amplifier of the memory bank 308-0 in the active operation, the value of saeodz_0 is High and the value of saeaz_0 is Low. As a result, the overdrive voltage is supplied to the sense amplifier of the memory bank 308-0 during the period z of the active period of the sense amplifier of the memory bank 308-0. Therefore, BL of the memory bank 308-0 becomes the overdrive voltage value in the period z.

  In the timing chart 2400, the value of saeodz_0 and the value of saeodz_1 are Low during the active period of the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 during the refresh operation. In the timing chart 2400, the value of saeaz_0 and the value of saeaz_1 are High during the active period. Thus, a high voltage is supplied to the sense amplifier of the memory bank 308-0 and the sense amplifier of the memory bank 308-1 during the active period. Therefore, the BL voltage value of the memory bank 308-0 and the BL voltage value of the memory bank 308-1 become High voltage values during the active period.

  In the timing chart 2400, the value of saeodz_2 and the value of saeodz_3 are High in the period x of the active periods of the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 during the refresh operation. In the timing chart 2400, the value of saeaz_2 and the value of saeaz_3 are Low during the period x. As a result, the overdrive voltage is supplied to the sense amplifier in the memory bank 308-2 and the sense amplifier in the memory bank 308-3 during the period x. Therefore, the voltage value of BL in the memory bank 308-2 and the voltage value of BL in the memory bank 308-3 become voltage values for overdrive in the period x.

  In the timing chart 2400, the value of saeodz_2 and the value of saedz_3 are low during the period y of the active period of the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 during the refresh operation. In the timing chart 2400, the value of saeaz_2 and the value of saeaz_3 are High during the period y. Accordingly, a high voltage is supplied to the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 during the period y. Therefore, during the period y, the voltage value of BL in the memory bank 308-2 and the voltage value of BL in the memory bank 308-3 become high voltage values during the period y.

  In the timing chart 2400, the value of saeodz_2 and the value of saeodz_3 are High during the period z of the active periods of the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 during the refresh operation. In the timing chart 2400, the value of saeaz_2 and the value of saeaz_3 are Low during the period z. As a result, the overdrive voltage is supplied to the sense amplifier of the memory bank 308-2 and the sense amplifier of the memory bank 308-3 during the period z. Accordingly, the BL voltage value of the memory bank 308-2 and the BL voltage value of the memory bank 308-3 become the overdrive voltage value during the period z.

  Although not shown, all sense amplifiers activated during the operation other than the refresh operation are overdriven. Then, only the sense amplifiers of some memory banks may be overdriven only during the refresh operation, and the sense amplifiers of the remaining memory banks may not be overdriven.

  In the above-mentioned MEMORY CORE CONTROLER 307, the memory bank 308-0, the memory bank 308-1, the memory bank 308-2, and the memory bank 308-3 are grouped. For example, the memory bank 308-0 and the memory bank 308-2 may be grouped with the memory bank 308-1 and the memory bank 308-3. For example, the memory bank 308-0 and the memory bank 308-3 may be grouped with the memory bank 308-1 and the memory bank 308-2. For example, as in the memory bank 308-0 and the memory bank 308-1 to the memory bank 308-3, the number of memory banks belonging to the group may be different for each group.

  As described above in the embodiment, according to the semiconductor memory device, in a plurality of memory banks, among the sense amplifier groups activated during the same refresh operation, the sense amplifiers in some memory banks are overdriven. . In the sense amplifier group, the sense amplifiers in the remaining memory banks are not overdriven. That is, overdrive is not performed by the sense amplifiers of all memory banks. As a result, current consumption caused by overdrive during the refresh operation can be reduced.

  In addition, the activation start of the sense amplifiers of some memory banks is made later than the activation start of the sense amplifiers of the remaining memory banks. That is, the refresh operation start of some memory banks is later than the refresh operation start of the remaining memory banks. Therefore, the influence of the refresh operation of the remaining memory banks on some memory banks can be reduced by overdriving the sense amplifiers of some memory banks.

  Also, during different refresh operations, the activation start of the sense amplifiers in some memory banks is made earlier than the activation start of the sense amplifiers in the remaining memory banks. That is, the order of the operation start of some memory banks and the operation start of the remaining memory banks is switched. As a result, it is possible to prevent a state in which the refresh operation of some of the memory banks continues and the subsequent REF, and the refresh operation of some of the memory banks and the refresh operation of the remaining memory banks are performed as the subsequent REF. The case can be dispersed. Therefore, it is possible to prevent a bias from occurring in the storage characteristics of the memory cells of some memory banks and the storage characteristics of the memory cells of the remaining memory banks. The memory characteristic of a memory cell is the amount of change in charge stored in the capacitor of the memory cell.

  In addition, the activation of the sense amplifiers in some memory banks is made earlier than the activation of the sense amplifiers in the remaining memory banks. In other words, the refresh operation of some memory banks starts earlier than the refresh operation of the remaining memory banks. Therefore, when the sense amplifier is overdriven when there is no influence from other refresh operations, it is possible to prevent deterioration of storage in the overdriven memory bank.

  In addition, the activation start of the sense amplifiers of some memory banks is delayed from the activation start of the sense amplifiers of the remaining memory banks during different refresh operations. That is, the operation start of some memory banks and the operation start of the remaining memory banks are switched. As a result, the state in which the refresh operation of the remaining memory banks continues and the subsequent REF can be prevented, and the refresh operation of some memory banks and the refresh operation of the remaining memory banks are performed as the subsequent REF. Can be dispersed. Therefore, it is possible to prevent a bias from occurring in the storage characteristics of the memory cells of some memory banks and the storage characteristics of the memory cells of the remaining memory banks.

  Further, the sense amplifiers in some memory banks are overdriven in a period from the start of activation of the sense amplifiers in some memory banks until a predetermined time elapses. As a result, the bit line of the sense amplifiers in some memory banks can be opened quickly, so that the write operation to the memory cell can be accelerated.

  Further, the sense amplifiers in some memory banks are overdriven in a period from a predetermined time before the end of activation of the sense amplifiers in some of the memory banks until the end of activation of the sense amplifiers in some of the memory banks. Thereby, when the bit lines of the sense amplifiers of some memory banks are closed, the charge amount of writing to the memory cell can be increased, and the writing to the memory cell can be strengthened.

  Further, the sense amplifiers in some memory banks are overdriven in a period from the start of activation of the sense amplifiers in some memory banks until a predetermined time elapses. Further, the sense amplifiers of some memory banks are overdriven in a period from a predetermined time before the activation end of the sense amplifiers of some memory banks until the activation end of the sense amplifiers of some memory banks. As a result, the opening of the bit lines of the sense amplifiers in some memory banks can be accelerated, and the writing to the memory cells can be strengthened when the bit lines of the sense amplifiers in some memory banks are closed. .

  During different refresh operations, the sense amplifiers of some memory banks are not overdriven, and the sense amplifiers of the remaining memory banks are overdriven. By switching the presence / absence of overdrive, it is possible to prevent the occurrence of bias in the storage characteristics of the memory cells of some memory banks and the storage characteristics of the memory cells of the remaining memory banks.

  The following additional notes are disclosed with respect to the embodiment described above.

(Appendix 1) A plurality of memory banks each having a sense amplifier;
Among the sense amplifier groups activated by the refresh operation of the plurality of memory banks, a voltage value supplied to the sense amplifiers of some memory banks is set to a first value within an active period of the sense amplifiers of the some memory banks. The first voltage value that activates the sense amplifiers of the part of the memory banks in the period is higher than the first voltage value in the second period different from the first period in the active period. A control circuit which sets the voltage value to be supplied to the sense amplifiers of the remaining memory banks out of the sense amplifier groups of the plurality of memory banks to the first voltage value;
A semiconductor memory device comprising:

(Supplementary Note 2) The control circuit includes:
2. The semiconductor memory device according to appendix 1, wherein the activation start of the sense amplifiers of the some memory banks is made later than the activation start of the sense amplifiers of the remaining memory banks.

(Supplementary Note 3) The control circuit includes:
3. The semiconductor memory device according to claim 2, wherein, during a refresh operation different from the refresh operation, the activation start of the sense amplifiers of the some memory banks is made earlier than the activation start of the sense amplifiers of the remaining memory banks. .

(Supplementary Note 4) The control circuit includes:
2. The semiconductor memory device according to appendix 1, wherein the activation start of the sense amplifiers of the remaining memory banks is made later than the activation start of the sense amplifiers of the partial memory banks.

(Supplementary Note 5) The control circuit includes:
The semiconductor memory device according to appendix 4, wherein the activation start of the sense amplifiers of the remaining memory banks is made earlier than the activation start of the sense amplifiers of the partial memory banks during a refresh operation different from the refresh operation. .

(Supplementary note 6) The semiconductor according to any one of supplementary notes 1 to 5, wherein the second period is a period from the start of activation of the sense amplifiers of the partial memory banks to a lapse of a predetermined time. Storage device.

(Supplementary note 7) The second period is a period from a predetermined time before the end of activation of the sense amplifiers of the partial memory banks to the end of activation of the sense amplifiers of the partial memory banks. The semiconductor memory device according to any one of appendices 1 to 5.

(Supplementary Note 8) The second period includes a period from the start of activation of the sense amplifiers in the partial memory banks to a lapse of a predetermined time, and a predetermined period before the end of activation of the sense amplifiers in the partial memory banks. 6. The semiconductor memory device according to any one of appendices 1 to 5, wherein the period is a period until the activation of the sense amplifiers of the partial memory banks.

(Supplementary note 9) The control circuit includes:
During a refresh operation different from the refresh operation, the voltage value supplied to the sense amplifiers of the some memory banks is set to the first voltage value, and the voltage value supplied to the sense amplifiers of the remaining memory banks is set to the first voltage value. 9. The semiconductor memory device according to any one of appendices 1 to 8, wherein the first voltage value is set to the first voltage value during the period and the second voltage value is set to the second period.

300 DRAM
307 MEMORY CORE CONTROLLER
308-0, 308-1, 308-2, 308-3 Memory bank

Claims (6)

A plurality of memory banks each having a sense amplifier;
Among the sense amplifier groups activated by the refresh operation of the plurality of memory banks, a voltage value supplied to the sense amplifiers of some memory banks is set to a first value within an active period of the sense amplifiers of the some memory banks. The first voltage value that activates the sense amplifiers of the some memory banks during the period is a second period different from the first period within the active period , and the some memory banks A second voltage value higher than the first voltage value in a second period from a predetermined time before the end of activation of the sense amplifier to the end of activation , which is different from some of the plurality of memory banks. Sense periods of the remaining memory banks that are active periods of the remaining memory banks that overlap at least partially with the active periods of the sense amplifiers of the partial memory banks. In all periods within the active period of the pump, and a control circuit for a voltage value to be supplied to the sense amplifier of the remaining memory banks to said first voltage value,
A semiconductor memory device comprising: The control circuit includes:
2. The semiconductor memory device according to claim 1, wherein the activation start of the sense amplifiers of the some memory banks is made later than the activation start of the sense amplifiers of the remaining memory banks. The control circuit includes:
3. The semiconductor memory according to claim 2, wherein, during a refresh operation different from the refresh operation, the activation start of the sense amplifiers of the some memory banks is made earlier than the activation start of the sense amplifiers of the remaining memory banks. apparatus. The control circuit includes:
2. The semiconductor memory device according to claim 1, wherein the activation start of the sense amplifiers of the remaining memory banks is made later than the activation start of the sense amplifiers of the partial memory banks. The control circuit includes:
5. The semiconductor memory according to claim 4, wherein, during a refresh operation different from the refresh operation, the activation start of the sense amplifiers of the remaining memory banks is made earlier than the activation start of the sense amplifiers of the partial memory banks. apparatus. The control circuit includes:
During a refresh operation different from the refresh operation, the voltage value supplied to the sense amplifiers of the some memory banks is set to the first voltage value, and the voltage value supplied to the sense amplifiers of the remaining memory banks is set to the first voltage value. 6. The semiconductor memory device according to claim 1, wherein the first voltage value is set to the first voltage value during the period and the second voltage value is set to the second period.

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