JP3534079B2 - Data processing device and data processing method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device and a data processing method for performing data transfer between devices such as an image input unit, an image output unit, a compression / decompression device, and a page memory through a data bus. Is.

[0002]

2. Description of the Related Art In an image processing apparatus such as a digital copying machine, an image input unit (hereinafter abbreviated as "IIT") for inputting image data from an image scanner or the like, or an image data is output to a recording device such as a printer. Data transfer between an image output unit (hereinafter abbreviated as “IOT”), a compression / expansion device, and the like is performed by DMA transfer (DMA ... Direct memory access) through an image data bus.

FIG. 6 is a block diagram of such a conventional image processing apparatus. In FIG. 6, 1 is DMAC
(Direct memory access controller), 2
Is a compressed data storage memory, 3 is a local DMA bus, 4
Is IIT, 4-1 is a buffer, 5 is an IOT, 5-1 is a buffer, 6 is a compression / expansion device, 7 is a page memory, 8 is an image data bus, 9 is a CPU (Central Processing Unit), 1
Reference numeral 0 is a DMAC, and 11 is a system bus.

The image data input to the image processing device is
The data is temporarily stored in the buffer 4-1 of the IIT 4 and is DMA-transferred to the page memory 7 via the image data bus 8 in units of a predetermined amount. Also, page memory 7
When outputting the image data expanded in to a printer or the like, from the page memory 7 via the image data bus 8,
Once DMA transfer to the buffer 5-1 of IOT5,
Is output. The DMAC 10 controls these transfers. The DMAC 10 is activated by a command sent from the CPU 9 via the system bus 11.

When it is necessary to encode the input image data, it is transferred to the compression / expansion device 6, where it is compressed (encoded) and DMA transferred to the compressed data storage memory 2. When outputting the compressed data stored in the compressed data storage memory 2 as image data, the compression / expansion unit 6
Is stretched. Compressor / expander 6 and compressed data storage memory 2
DMA transfer between and is controlled by the DMAC1.

The main components of the image processing apparatus are connected to the image data bus 8 and transfer data through the image data bus 8. However, in the conventional image processing apparatus, DMA transfer between certain components is performed. Only after the completion, DMA transfer can be performed between other components. For example, I
When the DMA transfer from the IT4 to the page memory 7 is completed, the page memory 7 must be started after the DMA transfer.
To DMA transfer from IOT to IOT5 cannot be performed.

As a conventional document relating to the image processing apparatus as described above, for example, Japanese Patent Laid-Open No. 62-17637.
4 and JP-A-62-266922.

[0008]

(Problem) In the above-mentioned conventional image processing apparatus, a plurality of types of processing, which involves the operation of DMA transfer of image data through the image data bus, are performed in parallel at the same time. There was a problem that I could not do it. Along with this, there has been a problem that the image data bus is not used for a long time and rests, which is an obstacle to improving the processing speed.

(Explanation of Problems) FIG. 7 is a diagram for explaining the usage status of the image data bus in the conventional image processing apparatus. Conventionally, DMA transfer through the image data bus, such as DMA transfer when inputting image data from IIT and DMA transfer when compression processing, can be performed for other types of transfer unless one type of transfer is completed. There wasn't. Therefore, the occupancy of the image data bus is shown in FIG.
It becomes as shown in (a). Therefore, for example, two types of processing, that is, processing for inputting image data from the IIT 4 to the page memory 7 and processing for outputting already input image data from the page memory 7 to the IOT 5 cannot be performed simultaneously in parallel. It was

If the image data bus is occupied by one type of transfer, the image data bus may be idle and unused depending on the image size, which hinders improvement in the processing speed of the image processing apparatus. It was the cause. FIG. 7B is an enlarged view showing a situation where the image data bus is actually used during the time when the image data bus is occupied due to “IIT input”. The shaded area represents the time actually used, and the blank area represents the unused time.

Next, the reason why such unused time occurs will be described. FIG. 8 is a diagram for explaining the document size and the usage time of the image data bus in the conventional image processing apparatus. In FIG. 8, 50 is the maximum size, 51
Is the document size, 52 and 53 are line synchronization signals, and 54 and 5
Reference numeral 5 is a page sync signal, 56 is an image data bus occupation time within one scan time, S ₁ and S ₂ are scan lines, W is an extra width, and L is an extra length.

The maximum size 50 is the maximum size of an original that can be processed by the image processing apparatus, and this is determined at the time of design. The document size 51 is the size of the document that is about to be input. Therefore, although the document size 51 may coincide with the maximum size 50, it is often smaller than that. The extra width W is the difference between the length of the document size 51 and the maximum size 50 in the horizontal direction (scan line direction). Similarly, the extra length L is the difference in length between the document size 51 and the maximum size 50 in the vertical direction (direction perpendicular to the scan line).

Scanning at the time of image input is performed on the maximum size 50 regardless of the size of the original. Therefore, in the case of a document of the document size 51, there is no document to be read in the portion with the excess width W and the portion with the excess length L, but scanning is also performed for these portions.

In the conventional image processing apparatus, when an image is input from the IIT 4, the image data bus 8 is occupied for image input over the entire period of one scan. That is, the image data bus occupation time 56 (the shaded area is occupied by the scan line S ₁ or the scan line S ₂ is scanned regardless of whether the scan is performed on the original or the scan line S _2. The image data bus 8 is always occupied as shown in FIG.

Although the image data bus 8 is occupied for the entire period, the image data bus 8 is not used during the time for scanning the portion having the extra width W and the time for scanning the portion having the extra length L. Therefore, as shown in FIG. 7B, only part of the occupied time is actually used, and the use efficiency of the image data bus 8 is poor. As a result, the above-mentioned problems occur, which hinders the improvement of the processing speed. An object of the present invention is to solve the above problems.

[0016]

In order to solve the above-mentioned problems, according to the present invention, in a data processing device and a data processing method for transferring data through a data bus, a group of one or more devices having a constant data transfer rate. During the request period from the device of the first device group, the device of the second device group, which is a group of one or more devices having a variable data transfer rate, is periodically transmitted to the device of the first device group. The data bus usage right is assigned prior to the device, and the data bus usage right is also assigned to the devices of the second device group during the request period, and arbitration means for performing such arbitration is provided. I decided to provide it.

Further, in the data processing device for transferring data through the data bus, the data transfer rate is fixed to 1
During the request period from the devices in the first device group, which is the above group of devices, the first
The data bus usage right is preferentially assigned to the device of the device group of No. 2 and the device of the second device group, which is a group of one or more devices having a variable data transfer rate during the same request period, The right to use the data bus is assigned only when the device of the first device group is not used, and the arbitration means for performing such arbitration is provided.

When assigning the right to use the data bus to the device in the first device group or the device in the second device group, the right to use the data bus can be assigned in units of a predetermined time. Data transfer can be performed by DMA transfer. Furthermore, when receiving a request from a plurality of devices of the first device group, the right to use the data bus can be alternately assigned to each device.

[0019]

According to the present invention, the right to use the data bus is assigned to a group of one or more devices having a constant data transfer rate.
During the request period from the device of the device group, the data of the device of the first device group is assigned with priority over the device of the second device group having a variable data transfer rate. The second transfer during the request period.
The right to use the data bus is also assigned to the devices in the device group. Alternatively, the right to use the data bus
Periodically during the request period from the device of the first device group, which is a group of one or more devices having a constant data transfer rate, the device of the first device group is preferentially assigned and the same request period. Even if the data transfer speed is indefinite, the data transfer is performed by assigning the right to use the data bus even when the device in the first device group is not using the data bus. I do. The devices of the first device group having a constant data transfer speed have a speed restriction that the data transfer must be performed in accordance with the data transfer speed. In the present invention,
During the request period from the device of the first device group, by periodically assigning the data bus use right to the device of the first device group and transferring the data, this restriction Are satisfied. Alternatively, for the devices of the second device group whose data transfer speed is variable, when the devices of the first device group are not using the data bus, the right to use the data bus is assigned to transfer the data. By doing so, the speed constraint on the devices of the first device group is satisfied. In addition, it becomes possible to concurrently perform processing involving the operation of transferring data through the data bus.

Furthermore, since the data bus usage right is assigned with a predetermined time as one unit,
Since the data bus is distributed and used in a predetermined time unit, the unused time is reduced and the usage efficiency is improved.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a block configuration of an image processing apparatus of the present invention. The reference numerals correspond to those in FIG. 6,
A and B are compression / expansion devices, 12 is an image data bus arbiter, and 13 is an oscillator. The configuration is different from the conventional image processing apparatus in that the image data bus arbiter 12 that adjusts the usage allocation time of the image data bus 8 is used.
The point is that an oscillator 13 for providing a clock is provided. The clock can also be generated by using a clock generation circuit (not shown) which the image processing apparatus originally has.

Although FIG. 1 shows a device having two compression / expansion units, one image is divided into two parts, and each divided part is assigned to another compression / expansion part for parallel processing. As a result, an example in which the present invention is applied to a device that improves the processing speed is shown, and of course, it can be applied to a device in which only one is mounted.

In the present invention, the time is divided into a fixed short time, which is an allocation unit time, and the right of use of the image data bus 8 is allocated in units of this. Then, the allocation is performed according to the following criteria. That is, the first priority allocation ... The IIT and the IOT whose operation speed is fixed to a certain fixed value are alternately allocated. Second priority allocation ... Assigned time to IIT and IO
Only assign to the decompressor when T is unused. When a plurality of compression / expansion devices are provided, priorities are set among the compression / expansion devices and assigned according to the priorities. Use permission only at request ... In any case, in order to actually use the image data bus, a request signal (REQ) for using the image data bus is issued and an acknowledge signal (ACK) is received and used.

The reason why the IIT4 and IOT5 are assigned with the first priority is that they are made to operate at a constant speed, and there is a speed restriction that the DMA transfer must be performed in accordance with the speed. Because there is. That is, the operating speeds of IIT4 and IOT5 are constant and are determined by the mechanical design conditions.

For example, when the IIT4 operates, it corresponds to the operating speed of the image reading mechanism such as the image scanner,
Image data comes in at a constant speed without a break.
Although it enters the buffer 4-1 once, it cannot store more than a predetermined amount. Therefore, before the predetermined amount of image data is stored in the buffer 4-1, the transfer destination (eg, page memory 7)
I have to send it to. Therefore, it is necessary to preferentially allocate the use of the image data bus 8.

On the other hand, the compression / expansion devices A and B are provided with II
There is no speed restriction as in T4 and IOT5, and compression processing and decompression processing can be stopped or restarted arbitrarily. Therefore, the DMA in which the decompressors A and B are involved
The transfer can be performed after waiting for the image data bus 8 to become free. Therefore, the priority order of allocation of the image data bus 8 is the second priority. When there are a plurality of compression / expansion units as in the example of FIG. 1, priority is given to them (for example, A and B in this order).

FIG. 9 is a diagram for explaining the document size and the usage time of the image data bus in the image processing apparatus of the present invention. The reference numerals correspond to those in FIG. This is an example of a case where a document of document size 51 is read by an image scanner and the image data is input via IIT4.

The difference from FIG. 8 lies in the image data bus occupation time 56. This shows the state at the time of scanning the scan line S ₁ that passes across the document. The time is divided into allocation unit times, which are constant short times, and the allocation unit times are alternately allocated to IIT4 and IOT5. Of the allocation unit times allocated to IIT4, the time when the line synchronization signal 53 is output. The IIT 4 occupies the image data bus 8 only in the allocation unit time belonging to (indicated by the shaded area).

As the scan progresses, the original size 51
Scan line S below the bottom of the manuscript ₂To scan in
Then, the line synchronization signal 53 becomes 0, so II
Do not allow T4 to occupy image data bus 8
Yes. And even during the scan
Of the allocation unit time allocated to IIT4, II
Part of the excess width W and excess length L in which T4 is not substantially operating
In the allocation unit time belonging to the time to scan the minutes
Connects the image data bus 8 to the compressor / decompressor A or B.
Transfer the right to use.

By doing so, it is possible to improve the use efficiency of the image data bus 8 and increase the processing speed, and at the same time, it is possible to simultaneously perform a plurality of types of DMA transfers in parallel. As a result, image input,
It is possible to perform compression processing, decompression processing, image output, etc. simultaneously in parallel.

(Structure of Image Data Bus Arbiter)
The purpose of allocating and using the right to use the image data bus 8 in accordance with the above criteria is
The image data bus arbiter 12 is shown in FIG.
The concrete structure is shown. In FIG. 3, 20 to 25 are signal lines, 26 to 30 are D flip-flops, 31 to 35.
Is an AND circuit, 36-41 are inverter circuits, 42, 4
3 is an OR circuit and 44 to 47 are signal lines.

The clock from the oscillator 13 of FIG. 1 is input to the signal line 24, and is supplied to the clock input terminals of the D flip-flops 26 to 30. D flip-flop 2
6 outputs from its output terminals Q to I based on this clock.
Issue an IT enable signal. Figure 4 shows the clock and IIT
The waveform diagram of an enable signal is shown. The IIT enable signal is a rectangular wave whose half cycle is the time between clocks (for example, 170 nS).

The D flip-flops 27 to 30 are for receiving a request signal from the IIT4 or the like which issues a request to use the image data bus 8 and outputs it in synchronization with a clock. The D flip-flop 27 has an IIT
The request signal from the IOT 5 is input, and the request signal from the IOT 5 is input to the D flip-flop 28.

The outputs from these are AND of two input terminals.
It is input to one input terminal of each of the circuits 31 and 32. The other input terminal of the AND circuit 31 has an IIT
The enable signal is input, and the IIT enable signal inverted by the inverter circuit 36 is input to the other input terminal of the AND circuit 32.

Therefore, the AND circuits 31 and 32 have the IIT
The gates are alternately turned on by the enable signal, and if the outputs from the D flip-flops 26, 27 come in in that state, they are output as an acknowledge signal via the signal lines 44, 45.

The requests from the compression / expansion units A and B are output from the D flip-flops 29 and 30 in synchronism with the clock, and they are ANDed with three input terminals, respectively.
It is input to one input terminal of each of the circuits 34 and 35. The other one of the three input terminals has an AND circuit 33 of two input terminals.
The output of is input. The two input terminals of the AND circuit 33 pass through inverter circuits 37 and 38, respectively, and AND
It is connected to the output terminals of the circuits 31 and 32. Therefore,
The AND circuit 33 outputs high only when neither acknowledge signal to IIT4 nor IOT5 is output.
As a result, the acknowledge signal to the IIT4 and IOT5 can be output with priority over the acknowledge signal to the compression / expansion devices A and B (first priority).

The priority order between the compression / expansion devices A and B is determined by the priority signal input from the signal line 25. When the value of the priority signal is high, the compression / expansion device A has priority, and when it is low, the compression / expansion device B has priority. That is, when the priority signal is high, the OR circuit 42 outputs high and AND
The signal is input to the third input terminal of the circuit 34, and the gate is turned on. At this time, if the request from the compression / expansion device A is output from the D flip-flop 29, it is processed by the AND circuit 3.
4 and is output to the compression / expansion device A as an acknowledge signal.

On the other hand, a high priority signal is made low by the inverter circuit 41 and input to one input terminal of the two-input terminal OR circuit 43. When the request from the compression / expansion device A is output from the D flip-flop 29, what is made low by the inverter circuit 40 is input to the other input terminal. Therefore, a high output is not output from the OR circuit 43. Therefore, the AND circuit 35 is not in the gate-on state, and even if the compression / expansion device B makes a request, the acknowledge signal to the compression / expansion device B is not output. In this way, preference is given to the compressor / expander A. When it is desired to give priority to the compression / expansion device B over the compression / expansion device A, the value of the priority signal input from the signal line 25 may be set to low.

(Operation of Image Data Bus Arbiter)
FIG. 5 is a time chart explaining the operation of the image data bus arbiter. FIG. 5A shows the same IIT enable signal as in FIG. 4B. In FIG. 5B, the IIT 4 in which time is divided into allocation unit times based on the IIT enable signal and the allocation order is the first priority order.
And IOT5, the situation where the usage rights of the image data bus 8 are alternately assigned is shown. The allocation unit time in which "I" is entered indicates that the usage right is allocated to the IIT4, and the allocation unit time in which "O" is entered indicates that the usage right is allocated to the IOT5. Shows. This allocation is performed by the AND circuit 3 in FIG.
One of the two input terminals 1 and 32 has I
This is performed by alternately inputting a high value by the IT enable signal.

FIG. 5D shows the request signal from the IIT 4 (the output of the D flip-flop 27 in FIG. 3), which corresponds to the line synchronization signal (53 in FIG. 9) when scanning the original. Will be issued. Figure 5 (e) is II
The acknowledge signal to T4, which is shown in FIG.
It is issued only during the allocation unit time in which the request signal of (d) is issued and the "I" of FIG. 5 (b) is written (signal line 44 of FIG. 3). The IIT 4 actually uses the image data bus 8 in the allocated unit time. This is indicated by the allocation unit time in which "I" is written in FIG.

The allocation unit time in which the IOT 5 actually uses the image data bus 8 is similarly obtained, and is the allocation unit time in which "O" is written in FIG. That is, within the time when the request signal (the output of the D flip-flop 28 of FIG. 3) from the IOT 5 of FIG. 5F is issued, the allocation unit in which “O” is written in FIG. 5B. At the time, an acknowledge signal (signal on the signal line 45 of FIG. 3) to the IOT 5 of FIG. 5 (g) is issued.

When the request signals for using the image data bus 8 are issued from the compression / expansion units A and B, these request signals are issued because they have lower priority than IIT4 and IOT5. The right to use the image data bus 8 is given only in the allocated unit time during which the acknowledge signal is not output to the IIT4 or the IOT5 within the existing time.

Now, it is assumed that it is decided that the compression / expansion device A should be prioritized between the compression / expansion devices A and B. This priority is determined by giving a "high" priority signal to the signal line 25 in FIG. Then, the acknowledge signal to the compression / expansion device A of FIG.
Fig. 5 (e) during the time when the request signal from
No acknowledge signal of FIG. 5 and the acknowledge signal of FIG. 5 (g) are issued only during the allocation unit time in which none is issued. The assigned unit time is the time written as “A” in FIG. 5C, and the compression / expansion device A can use the image data bus 8 at this time.

The compressing / expanding device B is within the time when the request signal of FIG.
Of course, the acknowledge signal is also issued to the compression / expansion device A only during the allocation unit time in which the acknowledge signal is not issued (FIG. 5 (l)). The allocation unit time is shown in Fig. 5 (c).
It is the time when "B" is written in, and at this time,
The compression / expansion device B can use the image data bus 8.

By the way, when two compression / expansion devices are provided, the problem arises that the processing of the compression / expansion device having a lower priority is delayed. FIG. 2 shows two compression / expansion units.
It is a figure explaining the image data bus usage condition when it is equipped. This is the output to IOT5,
The case where the processing by the compression / expansion devices A and B is performed in parallel is taken as an example.

FIG. 2A shows the usage status of the image data bus. One partition represents the above-mentioned allocation unit time, and "O" written therein is used by the IOT5. "A" and "B" indicate that the compressors / expanders A and B are used, respectively. The solid line drawn in the horizontal direction in FIG. 2B represents the time until the image data sufficient for DMA transfer is obtained after the processing in the compression / expansion device A is performed, and is directed toward FIG. The arrow line written with indicates the allocation unit time for DMA transfer of the image data obtained by the processing. After the transfer, the process is restarted. Similarly, FIG. 2C shows the processing in the compression / expansion device B.

Since it is assumed that the compression / expansion device A has priority over the compression / expansion device B, when the processing of the compression / expansion device A is completed, the IOT 5 does not use the image data bus 8 in the allocated unit time. , The compression / expansion device A uses. However, in the case of the allocation unit time A-1, the processing B-1 of the compression / expansion device A has not been completed by the start of the allocation unit time B-1, so the compression / expansion device A should use it. I can't.

In this case, the processing unit -1 until the image data sufficient for the DMA transfer is obtained has already been completed, and the compression / expansion unit B waiting for the allocation unit time to become available is assigned to the allocation unit time I. The use of the image data bus 8 at -1 is permitted. Even in the allocation unit time B-2, the compression / expansion device B is similarly permitted to use.

If the priority of the compression / expansion device B is always lower than that of the compression / expansion device A, as described above, the compression / expansion device B cannot use the image data bus 8 for a short time. The processing of the image area in charge of is significantly delayed from the processing of the image area in charge of the compression / expansion device A.

In order to avoid this, the priority order between the compression / expansion devices may be changed in the middle of processing one image. For example, the CPU 9 of FIG. 1 finds a compression / expansion device whose processing is delayed by monitoring the address counter (not shown) of the DMAC 10 at regular time intervals (eg, once every 100 mS), and Raise the priority of the compression / expansion device. To reverse the priority order, change the value of the priority signal input from the signal line 25 in FIG.
Just flip it.

[0051]

As described above, according to the present invention, the right to use the data bus is periodically assigned to the first right during the request period from the device of the first device group having a constant data transfer rate. A second device group having a variable data transfer rate is assigned to a device of the device group in preference to a device of the second device group to transfer data, or a second device group having a further variable data transfer rate. The right to use the data bus is assigned to the above device when the device of the first device group having a constant data transfer rate is not using the data bus. As a result, it is possible to concurrently perform the processing accompanied by the operation of transferring the data through the data bus while satisfying the speed constraint in the devices of the first device group having the constant data transfer speed. Become.

Further, since the data bus is distributed and used in a predetermined time unit, the unused time is reduced and the efficiency of use is improved. Therefore, the time until the whole processing is completed is shortened.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an image processing apparatus of the present invention.

FIG. 2 is a diagram for explaining the usage status of an image data bus when two compression / expansion devices are provided.

FIG. 3 is a diagram showing a configuration of an image data bus arbiter.

FIG. 4 is a waveform diagram of a clock and an IIT enable signal.

FIG. 5 is a time chart explaining the operation of the image data bus arbiter.

FIG. 6 is a block configuration diagram of a conventional image processing apparatus.

FIG. 7 is a diagram for explaining the usage status of an image data bus in a conventional image processing apparatus.

FIG. 8 is a diagram illustrating a document size and a usage time of an image data bus in a conventional image processing apparatus.

FIG. 9 is a diagram for explaining the document size and the usage time of the image data bus in the image processing apparatus of the present invention.

[Explanation of symbols]

1 ... DMAC, 2 ... compressed data storage memory, 3 ... local
DMA bus, 4 ... IIT, 4-1 ... buffer, 5 ... I
OT, 5-1 ... buffer, 6 ... compression / decompressor, 7 ... page
Memory, 8 ... Image data bus, 9 ... CPU, 10 ...
DMAC, 11 ... System bus, 12 ... Image data
Bus arbiter, 13 ... Oscillator, 20-25 ... Signal line,
26-30 ... D flip-flops, 31-35 ... AND
Circuits, 36 to 41 ... Inverter circuits, 42, 43 ... OR
Circuits, 44 to 47 ... Signal lines, 50 ... Maximum size, 51 ...
Original size, 52, 53 ... Line synchronization signal, 54, 55
… Page sync signal, 56… When the image data bus is occupied
Between A, B ... Compressor / Expander, S ₁, S₂… Scanray
N, W ... surplus width, L ... surplus length.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-58-223833 (JP, A) JP-A-3-149627 (JP, A) JP-A-6-205223 (JP, A) JP-A-58- 97726 (JP, A) JP-A-57-29127 (JP, A) JP-A-56-161740 (JP, A) Fukukaihei 4-74352 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 13/20-13/378

Claims (10)

(57) [Claims] 1. A data processing device for transferring data through a data bus, wherein a first device group, which is a group of one or more devices connected to the data bus and having a constant data transfer rate, is connected to the data bus. And a second device group, which is a group of one or more devices having variable data transfer rates, and an arbitration unit for allocating the right to use the data bus, wherein the arbitration unit includes the devices of the first device group. During the request period from the first device group, the device in the first device group is regularly assigned the right to use the data bus in preference to the second device group, and the device is assigned the right to use the data bus during the request period. The data bus usage right is also assigned to the devices of the second device group. Data processing equipment. 2. A data processing device for transferring data through a data bus, the first device group being a group of one or more devices connected to the data bus and having a constant data transfer speed, and connected to the data bus. And a second device group, which is a group of one or more devices having variable data transfer rates, and an arbitration unit for allocating the right to use the data bus, wherein the arbitration unit includes the devices of the first device group. The data bus usage right to the devices of the first device group on a regular basis during the request period from the device, and the device of the first device group uses the data bus during the request period. The data bus usage right to the device group of the second device group. Data processing apparatus and allocating the scan. 3. The arbitration means assigns a right to use the data bus to a device of the first device group or a device of the second device group in units of a predetermined time. The data processing device according to claim 1 or claim 2. 4. The data processing device according to claim 1, wherein the data transfer is a DMA transfer. 5. The arbitration means, when receiving requests from a plurality of devices in the first device group, alternately allocates the right to use the data bus to each device. The data processing device according to any one of claims 1 to 4. 6. A data processing method for transferring data through a data bus, wherein the data transfer rate is constant.
Use of the data bus at regular intervals during a request from a device of another device group, over a device of a second device group having a variable data transfer rate with respect to a device of the first device group. A data processing method, wherein a right is assigned to transfer data, and a right to use the data bus is also assigned to a device in the second device group during the request period. 7. A data processing method for transferring data through a data bus, wherein the first device is in a request period from a device of a first device group, which is a group of one or more devices having a constant data transfer rate. A device of the second device group, which is a group of one or more devices whose data transfer rate is variable during the request period, is assigned to the devices of the group on a regular basis and the usage right of the data bus is assigned. On the other hand, when the device of the first device group is not using the data bus, the right to use the data bus is assigned to transfer data. 8. When assigning the right to use the data bus to the device in the first device group or the device in the second device group, the right to use the data bus is set in units of a predetermined time. 8. The data processing method according to claim 6 or 7, wherein: 9. The data processing method according to claim 6, wherein the data transfer is a DMA transfer. 10. The data bus use right is alternately assigned to each device when receiving requests from a plurality of devices of the first device group. Item 10. The data processing method according to any one of items 9.