JP3532398B2 - Semiconductor integrated circuit device and semiconductor integrated circuit memory device - Google Patents
Semiconductor integrated circuit device and semiconductor integrated circuit memory deviceInfo
- Publication number
- JP3532398B2 JP3532398B2 JP30239797A JP30239797A JP3532398B2 JP 3532398 B2 JP3532398 B2 JP 3532398B2 JP 30239797 A JP30239797 A JP 30239797A JP 30239797 A JP30239797 A JP 30239797A JP 3532398 B2 JP3532398 B2 JP 3532398B2
- Authority
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- Japan
- Prior art keywords
- film
- capacitance
- electrode
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 62
- 239000000758 substrate Substances 0.000 claims description 32
- 239000010410 layer Substances 0.000 claims description 21
- 239000011229 interlayer Substances 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 22
- 229910052751 metal Inorganic materials 0.000 description 22
- 239000002184 metal Substances 0.000 description 22
- 229910052814 silicon oxide Inorganic materials 0.000 description 22
- 230000001360 synchronised effect Effects 0.000 description 10
- 238000005530 etching Methods 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 230000002093 peripheral effect Effects 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 244000228957 Ferula foetida Species 0.000 description 1
- -1 Phospho Chemical class 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体チップのピ
ン容量の調整を必要とする半導体集積回路装置に関し、
特に、シンクロナスＤＲＡＭ（Synchronous Dynamic Ra
ndom Access Memory）を有する半導体集積回路装置に適
用して有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device requiring adjustment of pin capacitance of a semiconductor chip,
Especially, synchronous DRAM (Synchronous Dynamic Ra
The present invention relates to a technique effectively applied to a semiconductor integrated circuit device having an ndom access memory).
【０００２】[0002]
【従来の技術】シンクロナスＤＲＡＭは、システムクロ
ックと同期させて、すべての入出力情報を半導体チップ
の入出力部のラッチでとり込み動作させる同期動作方式
であり、すべての動作モードをシステムクロック幅に等
しいコマンド信号の組み合わせで指定できるので、従来
の高速ページモード以上の高スループット機能をもつ。2. Description of the Related Art Synchronous DRAM is a synchronous operation system in which all input / output information is taken in by a latch of an input / output unit of a semiconductor chip in synchronization with a system clock, and all operation modes are set to system clock width. Since it can be specified by a combination of command signals equal to, it has high throughput function over the conventional high speed page mode.
【０００３】すなわち、クロックパルス幅に等しい外部
信号の組み合わせでチップの動作モードが決まり、この
モードがチップ内のコマンドデコーダで解読され、これ
をもとにチップ内部の動作が始まる。ここで、列アドレ
スやバースト長などをクロックサイクル数という形でア
ドレスピンから初期入力すると、バンクを切り換えても
連続データが絶え間無く得られる。これらの動作は、バ
ーストモードのアドレスをアドレスカウンタによって発
生して、順次列デコーダに送ることによって実現されて
いる。That is, the operation mode of the chip is determined by the combination of external signals having the same clock pulse width, this mode is decoded by the command decoder in the chip, and the operation inside the chip is started based on this. Here, if the column address, burst length, etc. are initially input from the address pins in the form of the number of clock cycles, continuous data can be obtained continuously even if the banks are switched. These operations are realized by generating a burst mode address by an address counter and sending it to a sequential column decoder.
【０００４】従って、このシンクロナスＤＲＡＭでは、
高速動作を実現するために、半導体チップのピン容量の
最大値が規定されており、例えば、Ｉ／Ｏ部（入出力
部）のピン容量は４〜５ｐＦ、他のピン容量は２. ５ｐ
Ｆ以下に設定される。ここでピン容量とは、半導体チッ
プの外部、すなわち、リードフレームから見た半導体集
積回路装置の内部回路、ボンディングパッド、ワイヤー
などの全容量である。Therefore, in this synchronous DRAM,
In order to realize high-speed operation, the maximum value of the pin capacitance of the semiconductor chip is specified. For example, the pin capacitance of the I / O unit (input / output unit) is 4 to 5 pF, and the other pin capacitance is 2.5 pF.
It is set to F or less. Here, the pin capacitance is the total capacitance of the external circuit of the semiconductor chip, that is, the internal circuit of the semiconductor integrated circuit device viewed from the lead frame, the bonding pad, the wire and the like.
【０００５】なお、シンクロナスＤＲＡＭについては、
例えば、培風館発行「超ＬＳＩメモリ」 １９９４年１１
月５日発行、伊藤清男著、Ｐ３４６に記載されている。Regarding the synchronous DRAM,
For example, published by Baifukan "Ultra LSI Memory", 1994 11
Published on May 5, published by Kiyoo Ito, P346.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、シンク
ロナスＤＲＡＭにおいては、ノイズの発生を抑え、ま
た、発生したノイズの反射を抑えるために、インピーダ
ンスの整合をとらなくてはならず、このため、ピン容量
の最大値に加えてピン容量の最小値を規定する必要が生
じた。However, in the synchronous DRAM, impedance matching must be taken in order to suppress the generation of noise and the reflection of the generated noise. It became necessary to specify the minimum value of pin capacitance in addition to the maximum value of capacitance.
【０００７】ところが、本発明者が検討したところによ
ると、ピン容量の最小値を設定するために、単に、ボン
ディングパッドと内部回路との間に容量素子を接続する
と、ピン容量が規格の最大値よりも増加して回路動作に
影響を及ぼすという問題が生ずる。However, according to a study made by the present inventor, if a capacitance element is simply connected between the bonding pad and the internal circuit in order to set the minimum value of the pin capacitance, the pin capacitance is the maximum value of the standard. However, there is a problem that it increases more than that and affects the circuit operation.
【０００８】本発明の目的は、半導体集積回路装置の回
路動作に影響を及ぼすことなくピン容量を制御すること
ができる技術を提供することにある。An object of the present invention is to provide a technique capable of controlling the pin capacitance without affecting the circuit operation of the semiconductor integrated circuit device.
【０００９】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【００１０】[0010]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
次のとおりである。Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.
【００１１】すなわち、本発明の半導体集積回路装置
は、半導体チップのピン容量を調整するための容量素子
を有しており、上記容量素子がボンディングパッドと内
部回路との間以外の領域でボンディングパッドに直付け
されているものである。That is, the semiconductor integrated circuit device of the present invention has a capacitance element for adjusting the pin capacitance of the semiconductor chip, and the capacitance element has a bonding pad in a region other than between the bonding pad and the internal circuit. It is directly attached to.
【００１２】上記した手段によれば、ボンディングパッ
ドに容量素子を直付けすることによってピン容量の最小
値が確保され、また、ボンディングパッドと内部回路と
の間に上記容量素子は形成されないので、容量素子の容
量成分は信号パス上には現れず、回路動作には影響を及
ぼさない。According to the above-mentioned means, the minimum value of the pin capacitance is secured by directly attaching the capacitance element to the bonding pad, and the capacitance element is not formed between the bonding pad and the internal circuit. The capacitive component of the element does not appear on the signal path and does not affect the circuit operation.
【００１３】[0013]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.
【００１４】なお、実施の形態を説明するための全図に
おいて同一機能を有するものは同一の符号を付し、その
繰り返しの説明は省略する。In all the drawings for explaining the embodiments, parts having the same functions are designated by the same reference numerals, and the repeated description thereof will be omitted.
【００１５】図１は、本発明の一実施の形態であるピン
容量調整用の容量素子を説明するための入力端子部の回
路図を示す。FIG. 1 is a circuit diagram of an input terminal portion for explaining a capacitance element for adjusting a pin capacitance according to an embodiment of the present invention.
【００１６】半導体集積回路装置の内部回路とボンディ
ングパッドとの間には、静電気放電（Electrostatic Di
scharge ；ＥＳＤ）入力保護素子が設けられている。Electrostatic discharge (Electrostatic Dielectric) is provided between the internal circuit of the semiconductor integrated circuit device and the bonding pad.
scharge (ESD) input protection element is provided.
【００１７】接地していない導電体や人間は、誘電によ
り、あるいは電荷を帯びた絶縁物に触れることによって
静電気を蓄える。このような導電体や人間が半導体チッ
プに触れて回路中の放電向きのパスを通じて静電気が放
電されると、瞬間的に大電流が流れ回路が破壊されるこ
とがある。そこで、信頼性を確保するために、内部回路
をＥＳＤから保護する頑丈な入力デバイス、すなわちＥ
ＳＤ保護素子が設けられている。Non-grounded conductors and humans store static electricity by dielectrics or by touching electrically charged insulators. When such a conductor or a person touches the semiconductor chip and static electricity is discharged through a path for discharging in the circuit, a large current may momentarily flow to destroy the circuit. Therefore, in order to ensure reliability, a robust input device that protects the internal circuit from ESD, that is, E
An SD protection element is provided.
【００１８】さらに、ボンディングパッドには、例え
ば、約１ｐＦの容量を有するピン容量調整用の容量素子
Ｃが直付けされている。信号のアクセス時間は信号パス
の遅延時間（抵抗×容量）によって決まるが、ピン容量
調整用の容量素子Ｃはボンディングパッドと内部回路と
の間には形成されずに、ボンディングパッドに直付けさ
れているので、容量素子Ｃの容量成分は信号パス上には
現れない。Further, a capacitance element C for adjusting the pin capacitance having a capacitance of, for example, about 1 pF is directly attached to the bonding pad. The signal access time is determined by the delay time (resistance × capacitance) of the signal path, but the capacitance element C for adjusting the pin capacitance is not formed between the bonding pad and the internal circuit, but is directly attached to the bonding pad. Therefore, the capacitive component of the capacitive element C does not appear on the signal path.
【００１９】次に、シンクロナスＤＲＡＭに適用された
本実施の形態のピン容量調整用の容量素子Ｃの製造方法
を図２および図３を用いて説明する。図２はピン容量調
整用の容量素子Ｃの要部平面図、図３は図２のＡ−Ａ’
線の要部断面図である。なお、シンクロナスＤＲＡＭを
構成するメモリセルのメモリセル選択用ＭＩＳＦＥＴと
情報蓄積用容量素子および周辺回路は図には示さず、ピ
ン容量調整用の容量素子Ｃのみを示す。Next, a method of manufacturing the capacitance element C for adjusting the pin capacitance according to the present embodiment applied to the synchronous DRAM will be described with reference to FIGS. 2 is a plan view of a main part of the capacitance element C for adjusting the pin capacitance, and FIG. 3 is AA ′ of FIG.
It is an important section sectional view of a line. It should be noted that the memory cell selecting MISFET, the information storage capacitive element, and the peripheral circuit of the memory cells that form the synchronous DRAM are not shown in the figure, and only the pin capacitance adjusting capacitive element C is shown.
【００２０】まず、ｐ- 型シリコン単結晶からなる半導
体基板１の主面上に周知の方法で、ｐ型ウエルおよびｎ
型ウエルを形成し、次いで、素子間分離用のフィールド
絶縁膜を形成する。ここで、上記フィールド絶縁膜と同
一層の絶縁膜２によってピン容量調整用の容量素子Ｃの
容量絶縁膜が形成される。First, the p-type well and the n-type well are formed on the main surface of the semiconductor substrate 1 made of p - type silicon single crystal by a known method.
A mold well is formed, and then a field insulating film for element isolation is formed. Here, the capacitance insulating film of the capacitance element C for adjusting the pin capacitance is formed by the insulating film 2 in the same layer as the field insulating film.
【００２１】次に、半導体基板１上にメモリセルのメモ
リセル選択用ＭＩＳＦＥＴ（MetalInsulator Semicondu
ctor Field Effect Transistor ）および周辺回路のＭ
ＩＳＦＥＴのゲート絶縁膜を形成する。この後、半導体
基板１上に堆積された第１の窒化シリコン膜、第１のタ
ングステンシリサイド（ＷＳｉx ）膜および第１の多結
晶シリコン膜からなる積層膜を順次エッチングすること
により、第１のＷＳｉx 膜および第１の多結晶シリコン
膜からなるメモリセルのメモリセル選択用ＭＩＳＦＥＴ
および周辺回路のＭＩＳＦＥＴのゲート電極を形成す
る。Next, a memory cell selecting MISFET (Metal Insulator Semiconductor) is formed on the semiconductor substrate 1.
ctor Field Effect Transistor) and peripheral circuit M
A gate insulating film of ISFET is formed. Thereafter, the first silicon nitride film deposited on the semiconductor substrate 1, by sequentially etching the laminated film made of the first tungsten silicide (WSi x) film and the first polycrystalline silicon film, a first MISFET for memory cell selection of memory cell composed of WSi x film and first polycrystalline silicon film
And the gate electrode of the MISFET of the peripheral circuit is formed.
【００２２】ここで、上記ゲート電極と同一層の導電膜
３を一方の電極とし、半導体基板１を他方の電極とした
ピン容量調整用の容量素子Ｃが形成される。ピン容量調
整用の容量素子Ｃの一方の電極を構成する導電膜３の面
積は、ピン容量の規格値０.５〜１. ５ｐＦを満たすよ
うに最適設計される。Here, the capacitance element C for adjusting the pin capacitance is formed using the conductive film 3 in the same layer as the gate electrode as one electrode and the semiconductor substrate 1 as the other electrode. The area of the conductive film 3 forming one electrode of the capacitance element C for adjusting the pin capacitance is optimally designed so as to satisfy the standard value of the pin capacitance of 0.5 to 1.5 pF.
【００２３】なお、上記ゲート電極を構成するメタルシ
リサイド膜にＷＳｉx 膜を用いたが、その他のメタルシ
リサイド膜、例えばモリブデンシリサイド（ＭｏＳ
ｉx ）膜、チタンシリサイド（ＴｉＳｉx ）膜、タンタ
ルシリサイド（ＴａＳｉx ）膜などを用いてもよい。Although the WSi x film is used as the metal silicide film forming the gate electrode, other metal silicide films such as molybdenum silicide (MoS) are used.
i x) film, a titanium silicide (TiSi x) film, a tantalum silicide (or the like may be used TaSi x) film.
【００２４】次に、周辺回路のｎチャネル型ＭＩＳＦＥ
Ｔのｎ型半導体領域およびｐチャネル型ＭＩＳＦＥＴの
ｐ型半導体領域を形成した後、半導体基板１上に堆積さ
れた第２の窒化シリコン膜をＲＩＥ（Reactive Ion Etc
hing）法などの異方性エッチングで加工することによっ
て、上記ゲート電極の側壁にサイドウォールスペーサを
形成し、ゲート電極を第１の窒化シリコン膜および第２
の窒化シリコン膜からなる絶縁膜４で覆う。この際、ピ
ン容量調整用の容量素子Ｃの一方の電極を構成する導電
膜３も上記絶縁膜４によって覆われる。Next, the n-channel type MISFE of the peripheral circuit
After forming the n-type semiconductor region of T and the p-type semiconductor region of the p-channel type MISFET, the second silicon nitride film deposited on the semiconductor substrate 1 is subjected to RIE (Reactive Ion Etc).
Hing) method or the like to form a side wall spacer on the side wall of the gate electrode by processing the gate electrode with the first silicon nitride film and the second silicon film.
Covered with an insulating film 4 made of a silicon nitride film. At this time, the conductive film 3 forming one electrode of the capacitance element C for adjusting the pin capacitance is also covered with the insulating film 4.
【００２５】次に、半導体基板１上に第１の酸化シリコ
ン膜５および第１のＢＰＳＧ（Boron-doped Phospho Si
licate Glass）膜６をＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａ
ｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法によって順次堆積し
た後、９００〜９５０℃のリフロー処理により上記第１
のＢＰＳＧ膜６の表面を平坦化する。Next, the first silicon oxide film 5 and the first BPSG (Boron-doped Phospho Si) are formed on the semiconductor substrate 1.
The licate glass film 6 is formed by CVD (Chemical Va
por deposition method and then sequentially depositing it, and then performing a reflow treatment at 900 to 950 ° C.
The surface of the BPSG film 6 is flattened.
【００２６】次に、図には示さないが、メモリセルのメ
モリセル選択用ＭＩＳＦＥＴと情報蓄積用容量素子を形
成する。まず、レジストパターンをマスクにして第１の
ＢＰＳＧ膜６、酸化シリコン膜５およびゲート絶縁膜と
同一層の絶縁膜を順次エッチングすることにより、メモ
リセル選択用ＭＩＳＦＥＴの一方の後に形成されるｎ型
半導体領域上に第１のコンタクトホールを形成する。Next, although not shown in the figure, a memory cell selecting MISFET and an information storing capacitive element of the memory cell are formed. First, the first BPSG film 6, the silicon oxide film 5, and the insulating film in the same layer as the gate insulating film are sequentially etched using the resist pattern as a mask to form an n-type formed after one of the memory cell selecting MISFETs. A first contact hole is formed on the semiconductor region.
【００２７】次いで、上記第１のコンタクトホール内に
Ｐが導入された第２の多結晶シリコン膜からなる第１の
プラグ電極を形成する。なお、この第２の多結晶シリコ
ン膜に導入されたＰの拡散によってメモリセル選択用Ｍ
ＩＳＦＥＴの一方のｎ型半導体領域が形成される。Next, a first plug electrode made of a second polycrystalline silicon film having P introduced therein is formed in the first contact hole. It should be noted that the M for memory cell selection is diffused by diffusion of P introduced into the second polycrystalline silicon film.
One n-type semiconductor region of the ISFET is formed.
【００２８】次に、半導体基板１上に第２の酸化シリコ
ン膜７をＣＶＤ法によって堆積する。次いで、レジスト
パターンをマスクにして第２の酸化シリコン膜７、第１
のＢＰＳＧ膜６、第１の酸化シリコン膜５およびゲート
絶縁膜と同一層の絶縁膜を順次エッチングすることによ
り、メモリセル選択用ＭＩＳＦＥＴの他方の後に形成さ
れるｎ型半導体領域上に第２のコンタクトホールを形成
する。Next, a second silicon oxide film 7 is deposited on the semiconductor substrate 1 by the CVD method. Then, using the resist pattern as a mask, the second silicon oxide film 7 and the first silicon oxide film 7 are formed.
By sequentially etching the BPSG film 6, the first silicon oxide film 5, and the insulating film in the same layer as the gate insulating film, thereby forming a second film on the n-type semiconductor region formed after the other of the memory cell selecting MISFETs. Form a contact hole.
【００２９】次いで、半導体基板１上にＰが導入された
第３の多結晶シリコン膜および第２のＷＳｉｘ 膜をＣ
ＶＤ法によって順次堆積した後、レジストパターンをマ
スクにして第２のＷＳｉx 膜および第３の多結晶シリコ
ン膜を順次エッチングすることにより、第２のＷＳｉx
膜および第３の多結晶シリコン膜からなるビット線を形
成する。Next, the third polycrystalline silicon film having P introduced thereinto and the second WSi x film on the semiconductor substrate 1 are replaced with C
After sequentially deposited by VD method, by sequentially etching the second WSi x film and the third polycrystalline silicon film using the resist pattern as a mask, the second WSi x
A bit line composed of the film and the third polycrystalline silicon film is formed.
【００３０】また、上記第３の多結晶シリコン膜に導入
されたＰの拡散によってメモリセル選択用ＭＩＳＦＥＴ
の他方のｎ型半導体領域は形成され、ビット線は第２の
コンタクトホールを通して、このメモリセル選択用ＭＩ
ＳＦＥＴの他方のｎ型半導体領域に接続される。In addition, by diffusion of P introduced in the third polycrystalline silicon film, a MISFET for memory cell selection.
The other n-type semiconductor region is formed, and the bit line passes through the second contact hole to allow the memory cell selection MI.
It is connected to the other n-type semiconductor region of the SFET.
【００３１】次に、半導体基板１上に第３の酸化シリコ
ン膜８、第３の窒化シリコン膜および第２のＢＰＳＧ膜
をＣＶＤ法によって順次堆積した後、９００〜９５０℃
のリフロー処理により上記第２のＢＰＳＧ膜の表面を平
坦化する。Next, a third silicon oxide film 8, a third silicon nitride film and a second BPSG film are sequentially deposited on the semiconductor substrate 1 by the CVD method, and then 900 to 950 ° C.
The surface of the second BPSG film is flattened by the reflow treatment of.
【００３２】次に、半導体基板１上にＰが導入された第
４の多結晶シリコン膜をＣＶＤ法によって堆積した後、
レジストパターンをマスクにしてこの第４の多結晶シリ
コン膜をエッチングする。次いで、半導体基板１上にＣ
ＶＤ法によって堆積されたＰが導入された第５の多結晶
シリコン膜をＲＩＥ法などの異方性エッチングによって
加工し、第４の多結晶シリコン膜の側壁に第５の多結晶
シリコン膜からなるサイドウォールスペーサを形成す
る。Next, after a fourth polycrystalline silicon film having P introduced therein is deposited on the semiconductor substrate 1 by the CVD method,
This fourth polycrystalline silicon film is etched using the resist pattern as a mask. Then, C on the semiconductor substrate 1
The fifth polycrystalline silicon film having P introduced therein, which is deposited by the VD method, is processed by anisotropic etching such as the RIE method to form the fifth polycrystalline silicon film on the side wall of the fourth polycrystalline silicon film. Form sidewall spacers.
【００３３】次いで、レジストパターンをマスクにして
メモリセルの第２のＢＰＳＧ膜、第３の窒化シリコン
膜、第３の酸化シリコン膜８および第２の酸化シリコン
膜７を順次エッチングすることにより、第１のコンタク
トホール内に設けられた第１のプラブ電極上に第３のコ
ンタクトホールを形成した後、半導体基板１上にＰが導
入された第６の多結晶シリコン膜および第３のＢＰＳＧ
膜をＣＶＤ法によって順次堆積する。Next, by using the resist pattern as a mask, the second BPSG film, the third silicon nitride film, the third silicon oxide film 8 and the second silicon oxide film 7 of the memory cell are sequentially etched, thereby After forming the third contact hole on the first plug electrode provided in the first contact hole, the sixth polycrystalline silicon film in which P is introduced on the semiconductor substrate 1 and the third BPSG.
The films are sequentially deposited by the CVD method.
【００３４】次に、レジストパターンをマスクにして上
記第３のＢＰＳＧ膜、第６多結晶シリコン膜および第４
の多結晶シリコン膜を順次エッチングした後、半導体基
板１上にＰが導入された第７の多結晶シリコン膜をＣＶ
Ｄ法によって堆積する。次いで、この第７の多結晶シリ
コン膜をＲＩＥ法などの異方性エッチングによって加工
し、メモリセルの第３のＢＰＳＧ膜、第６の多結晶シリ
コン膜および第４の多結晶シリコン膜の側壁に第７の多
結晶シリコン膜を残す。Next, using the resist pattern as a mask, the third BPSG film, the sixth polycrystalline silicon film and the fourth film are formed.
After sequentially etching the polycrystalline silicon films of C, the seventh polycrystalline silicon film having P introduced therein is CV-doped on the semiconductor substrate 1.
It is deposited by the D method. Then, the seventh polycrystalline silicon film is processed by anisotropic etching such as RIE to form sidewalls of the third BPSG film, the sixth polycrystalline silicon film and the fourth polycrystalline silicon film of the memory cell. The seventh polycrystalline silicon film is left.
【００３５】次に、例えば、フッ酸溶液を用いたウエッ
トエッチングによって、第３のＢＰＳＧ膜および第２の
ＢＰＳＧ膜を除去し、メモリセルに第４の多結晶シリコ
ン膜から第７の多結晶シリコン膜によって構成される円
筒型の蓄積電極を形成する。Next, the third BPSG film and the second BPSG film are removed by, for example, wet etching using a hydrofluoric acid solution, and the fourth polycrystalline silicon film to the seventh polycrystalline silicon are formed in the memory cell. A cylindrical storage electrode composed of a film is formed.
【００３６】次に、半導体基板１上に厚さ約２ｎｍの第
４の窒化シリコン膜をＣＶＤ法によって堆積し、続い
て、厚さ約３０ｎｍの非晶質の酸化タンタル（Ｔａ2 Ｏ
5 ）膜をＣＶＤ法によって堆積した後、半導体基板１に
熱酸化処理を施すことによって、上記Ｔａ2 Ｏ5 膜を結
晶化する。その後、半導体基板１上に窒化チタン（Ｔｉ
Ｎ）膜をＣＶＤ法によって堆積し、次いで、レジストパ
ターンをマスクにしてこのＴｉＮ膜をエッチングするこ
とにより、ＴｉＮ膜からなるプレート電極を形成する。Next, a fourth silicon nitride film having a thickness of about 2 nm is deposited on the semiconductor substrate 1 by the CVD method, and subsequently, an amorphous tantalum oxide (Ta 2 O) having a thickness of about 30 nm is deposited.
5 ) After the film is deposited by the CVD method, the semiconductor substrate 1 is subjected to thermal oxidation treatment to crystallize the Ta 2 O 5 film. After that, titanium nitride (Ti
A N) film is deposited by the CVD method, and then the TiN film is etched using the resist pattern as a mask to form a plate electrode made of the TiN film.
【００３７】なお、容量絶縁膜にＴａ2 Ｏ5 膜を用いた
が、その他の酸化メタル膜（例えば、（Ｂａ，Ｓｒ）Ｔ
ｉＯ膜またはＰｂ（Ｚｒ，Ｔｉ）Ｏ3 膜）などを用いて
もよく、また、上記プレート電極にＴｉＮ膜を用いた
が、その他のメタルナイトライド膜（例えば、ＷＮ膜）
またはメタル膜（例えば、Ｗ膜）などを用いてもよい。Although the Ta 2 O 5 film is used as the capacitance insulating film, other metal oxide films (for example, (Ba, Sr) T) are used.
For example, an iO film or a Pb (Zr, Ti) O 3 film) may be used, and a TiN film is used as the plate electrode, but other metal nitride films (for example, WN film) are used.
Alternatively, a metal film (for example, a W film) or the like may be used.
【００３８】以上の製造工程により、メモリセルのメモ
リセル選択用ＭＩＳＦＥＴと情報蓄積用容量素子が完成
する。Through the above manufacturing steps, the memory cell selecting MISFET and the information storing capacitive element of the memory cell are completed.
【００３９】次に、半導体基板１上に第４の酸化シリコ
ン膜９および第４のＢＰＳＧ膜１０をＣＶＤ法によって
順次堆積した後、９００〜９５０℃のリフロー処理によ
り上記第４のＢＰＳＧ膜１０の表面を平坦化する。Next, after the fourth silicon oxide film 9 and the fourth BPSG film 10 are sequentially deposited on the semiconductor substrate 1 by the CVD method, the fourth BPSG film 10 is reflowed at 900 to 950 ° C. Flatten the surface.
【００４０】次いで、プレート電極上、ビット線上、お
よび周辺回路のＭＩＳＦＥＴの半導体領域上とゲート電
極上に第４のコンタクトホールを形成する。この際、レ
ジストパターンをマスクにして第４のＢＰＳＧ膜１０、
第４の酸化シリコン膜９、第３の酸化シリコン膜８、第
２の酸化シリコン膜７、第１のＢＰＳＧ膜６、第１の酸
化シリコン膜５および絶縁膜４を順次エッチングするこ
とにより、ピン容量調整用の容量素子Ｃの一方の電極で
ある導電膜３上にも第４のコンタクトホール１１を形成
する。Next, a fourth contact hole is formed on the plate electrode, the bit line, and the semiconductor region of the MISFET of the peripheral circuit and the gate electrode. At this time, the fourth BPSG film 10 is formed by using the resist pattern as a mask,
By sequentially etching the fourth silicon oxide film 9, the third silicon oxide film 8, the second silicon oxide film 7, the first BPSG film 6, the first silicon oxide film 5 and the insulating film 4, The fourth contact hole 11 is also formed on the conductive film 3 which is one electrode of the capacitance element C for capacitance adjustment.
【００４１】次に、半導体基板１上に金属膜（図示せ
ず）を堆積した後、レジストパターンをマスクにして上
記金属膜をエッチングすることにより、第１層目のメタ
ル配線Ｍ1 が形成される。次いで、半導体基板１上にＥ
ＣＲ（Electron Cyclotron Resonance：電子サイクロト
ロン共鳴）プラズマＣＶＤ法によって第５の酸化シリコ
ン膜を堆積し、この第５の酸化シリコン膜によって構成
される第１の層間絶縁膜１２を設ける。Next, after depositing a metal film (not shown) on the semiconductor substrate 1, the metal film M 1 of the first layer is formed by etching the metal film using the resist pattern as a mask. It Then, E on the semiconductor substrate 1
A fifth silicon oxide film is deposited by a CR (Electron Cyclotron Resonance) plasma CVD method, and a first interlayer insulating film 12 constituted by the fifth silicon oxide film is provided.
【００４２】次に、レジストパターンをマスクにして上
記第１の層間絶縁膜１２をエッチングすることにより、
第１層目のメタル配線Ｍ1 に達するスルーホール１３を
形成した後、半導体基板１上に金属膜を堆積し、次い
で、この金属膜をレジストパターンをマスクにしてエッ
チングすることにより、第２層目のメタル配線Ｍ2 を形
成する。Next, by etching the first interlayer insulating film 12 using the resist pattern as a mask,
After forming the through hole 13 reaching the metal wiring M 1 of the first layer, a metal film is deposited on the semiconductor substrate 1 and then the metal film is etched using the resist pattern as a mask to form the second layer. An eye metal wiring M 2 is formed.
【００４３】さらに、半導体基板１上にＥＣＲプラズマ
ＣＶＤ法によって第６の酸化シリコン膜を堆積し、この
第６の酸化シリコン膜によって構成される第２の層間絶
縁膜１４を設ける。Further, a sixth silicon oxide film is deposited on the semiconductor substrate 1 by the ECR plasma CVD method, and a second interlayer insulating film 14 composed of the sixth silicon oxide film is provided.
【００４４】次に、レジストパターンをマスクにして上
記第２の層間絶縁膜１４をエッチングすることにより、
第２層目のメタル配線Ｍ2 に達するスルーホール１５を
形成した後、半導体基板１上に金属膜を堆積し、次い
で、この金属膜をレジストパターンをマスクにしてエッ
チングすることにより、第３層目のメタル配線Ｍ3 を形
成する。Next, the second interlayer insulating film 14 is etched by using the resist pattern as a mask,
After forming the through hole 15 reaching the second-layer metal wiring M 2 , a metal film is deposited on the semiconductor substrate 1 and then the metal film is etched using the resist pattern as a mask to form the third layer. The eye metal wiring M 3 is formed.
【００４５】最後に、半導体基板１の表面をパッシベー
ション膜１６で被覆し、次いで、レジストパターンをマ
スクにして上記パッシベーション膜１６をエッチングす
ることにより、ボンディングパッドを構成する第３層目
のメタル配線Ｍ3 上にホール１７を形成する。Finally, the surface of the semiconductor substrate 1 is covered with the passivation film 16, and then the passivation film 16 is etched by using the resist pattern as a mask to form the metal wiring M of the third layer constituting the bonding pad. A hole 17 is formed on the top surface 3 .
【００４６】以上の製造方法によって、本実施の形態の
ピン容量調整用の容量素子Ｃを有するシンクロナスＤＲ
ＡＭが完成する。By the above manufacturing method, the synchronous DR having the capacitance element C for adjusting the pin capacitance of this embodiment is provided.
AM is completed.
【００４７】このように、本実施の形態によれば、メモ
リセルのメモリセル選択用ＭＩＳＦＥＴおよび周辺回路
のＭＩＳＦＥＴのゲート電極と同一層の導電膜３を一方
の電極とし、半導体基板１を他方の電極とし、フィール
ド絶縁膜と同一層の絶縁膜２を容量絶縁膜とする容量素
子Ｃをボンディングパッドに直付けして容量成分を形成
し、この容量素子Ｃを最適設計することによってピン容
量の最小値を設定することができる。さらに、上記容量
素子Ｃはボンディングパッドと内部回路との間には設け
られていないので、容量素子Ｃの容量成分は信号パス上
には現れず、容量素子Ｃを設けても回路動作には影響を
及ぼさない。As described above, according to the present embodiment, the conductive film 3 in the same layer as the gate electrodes of the memory cell selecting MISFET of the memory cell and the peripheral circuit MISFET is used as one electrode, and the semiconductor substrate 1 is used as the other electrode. Capacitance element C having an insulating film 2 of the same layer as the field insulation film as a capacitance insulation film is directly attached to the bonding pad to form a capacitance component, and this capacitance element C is optimally designed to minimize the pin capacitance. You can set the value. Furthermore, since the capacitive element C is not provided between the bonding pad and the internal circuit, the capacitive component of the capacitive element C does not appear on the signal path, and providing the capacitive element C does not affect the circuit operation. Does not reach.
【００４８】以上、本発明者によってなされた発明を発
明の実施の形態に基づき具体的に説明したが、本発明は
前記実施の形態に限定されるものではなく、その要旨を
逸脱しない範囲で種々変更可能であることはいうまでも
ない。Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.
【００４９】例えば、前記実施の形態では、ピン容量調
整用の容量素子は、メモリセルのメモリセル選択用ＭＩ
ＳＦＥＴおよび周辺回路のＭＩＳＦＥＴのゲート電極と
同一層の導電膜を一方の電極とし、半導体基板を他方の
電極とし、フィールド絶縁膜を容量絶縁膜としたが、上
記他方の電極を半導体基板に設けられたウエル領域とし
てもよい。また、層間絶縁膜を介して上下に位置するメ
タル配線の上層のメタル配線を一方の電極とし、下層の
メタル配線を他方の電極とし、上記層間絶縁膜を容量絶
縁膜としてピン容量調整用の容量素子を構成してもよ
い。For example, in the above embodiment, the capacitance element for adjusting the pin capacitance is the memory cell selection MI of the memory cell.
Although the conductive film in the same layer as the gate electrode of the SFET and the MISFET of the peripheral circuit was used as one electrode, the semiconductor substrate was used as the other electrode, and the field insulating film was used as the capacitive insulating film, the other electrode was provided on the semiconductor substrate. Well region. In addition, the metal wiring in the upper layer above and below the inter-layer insulating film is used as one electrode, the metal wiring in the lower layer is used as the other electrode, and the inter-layer insulating film is used as a capacitance insulating film to adjust the capacitance for pin capacitance adjustment. The element may be configured.
【００５０】[0050]
【発明の効果】本願によって開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.
【００５１】本発明によれば、回路動作に影響を及ぼす
ことなくボンディングパッドに直付けされた容量素子に
よってピン容量を調整することができる。According to the present invention, the pin capacitance can be adjusted by the capacitance element directly attached to the bonding pad without affecting the circuit operation.
【図１】本発明の一実施の形態であるピン容量調整用の
容量素子を説明するための入力端子部の回路図を示す。FIG. 1 is a circuit diagram of an input terminal portion for explaining a capacitance element for adjusting a pin capacitance according to an embodiment of the present invention.
【図２】本発明の一実施の形態であるピン容量調整用の
容量素子の製造方法を説明するための半導体基板の要部
平面図である。FIG. 2 is a plan view of a principal part of a semiconductor substrate for explaining a method of manufacturing a capacitive element for adjusting pin capacitance according to an embodiment of the present invention.
【図３】図２のＡ−Ａ’線における半導体基板の要部断
面図である。3 is a cross-sectional view of the main part of the semiconductor substrate taken along the line AA ′ in FIG.
１ 半導体基板 ２ 絶縁膜 ３ 導電膜 ４ 絶縁膜 ５ 第１の酸化シリコン膜 ６ 第１のＢＰＳＧ膜 ７ 第２の酸化シリコン膜 ８ 第３の酸化シリコン膜 ９ 第４の酸化シリコン膜 １０ 第４のＢＰＳＧ膜 １１ 第４のコンタクトホール １２ 第１の層間絶縁膜 １３ スルーホール １４ 第２の層間絶縁膜 １５ スルーホール １６ パッシベーション １７ ホール Ｃ 容量素子 Ｍ1 第１層目のメタル配線 Ｍ2 第２層目のメタル配線 Ｍ3 第３層目のメタル配線1 semiconductor substrate 2 insulating film 3 conductive film 4 insulating film 5 first silicon oxide film 6 first BPSG film 7 second silicon oxide film 8 third silicon oxide film 9 fourth silicon oxide film 10 fourth BPSG film 11 Fourth contact hole 12 First interlayer insulating film 13 Through hole 14 Second interlayer insulating film 15 Through hole 16 Passivation 17 Hole C Capacitive element M 1 First layer metal wiring M 2 Second layer Metal wiring M 3 Third layer metal wiring
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 H01L 21/822 H01L 21/82 H01L 27/04 ─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 21/60 H01L 21/822 H01L 21/82 H01L 27/04
Claims (3)
の容量素子が、前記半導体チップ内に半導体基板または
ウエル領域を一方の電極とし、ＭＩＳＦＥＴのゲート電
極と同一層の導電膜を他方の電極とし、素子間分離用の
フィールド絶縁膜を容量絶縁膜として形成され、かつボ
ンディングパッドにスルーホールおよび層間配線層を介
して接続され、前記容量素子は、前記ボンディングパッ
ドから内部回路もしくは入力保護素子へつながる配線よ
りも前記ボンディングパッドに近接した近傍領域に形成
されていることを特徴とする半導体集積回路装置。1. A capacitive element for adjusting the pin capacitance of a semiconductor chip is a semiconductor substrate or a semiconductor substrate in the semiconductor chip.
The well region is used as one electrode, and the gate voltage of the MISFET is
The conductive film of the same layer as the electrode is used as the other electrode to separate the elements.
The field insulating film is formed as a capacitive insulating film , and the bonding pad is provided with a through hole and an interlayer wiring layer.
And the capacitive element is connected to the bonding pad.
From the internal circuit to the input protection element.
Formed in the vicinity of the bonding pad
A semiconductor integrated circuit device characterized by being provided .
って、前記容量素子の容量値は、０.５〜１.５ｐＦであ
ることを特徴とする半導体集積回路装置。2. The semiconductor integrated circuit device according to claim 1, wherein the capacitance value of the capacitive element is 0.5 to 1.5 pF.
るための容量素子が、前記ＤＲＡＭの半導体チップ内に
形成され、かつ前記容量素子は一方の電極を前記半導体
チップの基板もしくは基板内に形成されたウエルとし、
他方の電極はゲート電極を形成する導電膜とし、容量絶
縁膜は素子分離用のフィールド絶縁膜とした構造からな
り、前記容量素子はボンディングパッドから内部回路も
しくは入力保護素子へつながる前に前記ボンディングパ
ッドにスルーホールおよび層間配線層を介して接続され
ていることを特徴とする半導体集積回路メモリ装置。3. A capacitive element for adjusting the pin capacitance of the I / O portion of the DRAM is formed in the semiconductor chip of the DRAM, and one electrode of the capacitive element is the substrate of the semiconductor chip or in the substrate. And the well formed in
The other electrode is a conductive film that forms a gate electrode, and the capacitive insulating film is a field insulating film for element isolation, and the capacitive element has the bonding pad before connecting to the internal circuit or the input protection element. A semiconductor integrated circuit memory device, wherein the semiconductor integrated circuit memory device is connected to the semiconductor device through a through hole and an interlayer wiring layer .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30239797A JP3532398B2 (en) | 1997-11-05 | 1997-11-05 | Semiconductor integrated circuit device and semiconductor integrated circuit memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30239797A JP3532398B2 (en) | 1997-11-05 | 1997-11-05 | Semiconductor integrated circuit device and semiconductor integrated circuit memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11145394A JPH11145394A (en) | 1999-05-28 |
| JP3532398B2 true JP3532398B2 (en) | 2004-05-31 |
Family
ID=17908431
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30239797A Expired - Fee Related JP3532398B2 (en) | 1997-11-05 | 1997-11-05 | Semiconductor integrated circuit device and semiconductor integrated circuit memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3532398B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10131940B4 (en) | 2001-07-02 | 2006-01-19 | Infineon Technologies Ag | Semiconductor chip and method for forming contacts on a semiconductor device |
| JP4240983B2 (en) | 2002-10-07 | 2009-03-18 | 沖電気工業株式会社 | How to set the input pin capacitance |
-
1997
- 1997-11-05 JP JP30239797A patent/JP3532398B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11145394A (en) | 1999-05-28 |
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