JP3520392B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a multilayer structure.

[0002]

2. Description of the Related Art Several patterns are formed in the course of manufacturing a semiconductor device, but a pattern forming film such as a resist is used in the pattern formation, and wet etching is performed in the subsequent etching process. May be implemented. In particular, it has been generalized to be used for etching a shape having a high aspect ratio such as HOLE. That is, H
The wiring is formed immediately after the formation of the OLE, but it is necessary to make the shape of the upper portion of the HOLE inclined so that the wiring can be well distributed in the HOLE. Wet etching is mainly used as a means of grading. For example, when forming a HOLE by a conventional technique, a resist is applied on the interlayer film to form a HOLE pattern. After that, wet etching is performed with an anisotropic etchant, the upper portion of the HOLE is inclined, and then the HOLE portion is formed by dry etching. Finally,
The resist film is peeled off to complete the process.

Further, the interlayer film of the semiconductor device is formed for the purpose of separating the layers into layers of the semiconductor device having a multi-layer structure.
It is generally formed by a multi-layer structure using a seed oxide film. A conventional method for forming an interlayer film is, for example, in the case of an interlayer film having a three-layer structure, the first layer is formed by CVD (Chemical).
S by the Al Vapor Deposition method
An io2 film is formed and a liquid SOG (Spin) is formed on the second layer.
An On Glass) film is spin-coated to flatten the recess. Next, there is a method in which an extra SOG film thickly attached to the baked and solidified SOG film is etched by dry etching, and then a SiO2 film is formed as the third layer by the above-described CVD as in the first layer.

[0004]

However, the conventional HOL
In the method of forming E, the etchant permeates the interface between the interlayer film and the resist film more than necessary during the wet etching, and the interlayer film other than the HOLE forming portion is also etched. In particular, if the penetration spreads to a step,
The etchant accumulates in the step portion and is locally etched, and a deep groove or hole is formed in the interlayer film. for that reason,
When the wiring film is formed on the interlayer film and the wiring is etched to form the wiring, the AL film enters the groove or the hole and remains unetched when the wiring is etched, and the wiring is short-circuited. However, there is a problem that the wiring film does not enter the groove or the hole and is hollowed, which causes a disconnection of the wiring formed thereon.

Further, in the case of a correlation film having a multilayer structure during the wet etching, an etchant permeates between the films forming one interlayer film and the interlayer film is peeled off or a void is formed in the interlayer film. For example, in the case of the three-layered interlayer film of the above example, when the etchant soaks between the first and third CVD films, the SOG film accumulated in the concave portion at the soaked point has a high etching rate and is rapidly etched. It If that happens, the CVD of the first and third layers
The adhesion of the film is significantly deteriorated, and there is a problem that the semiconductor device is defective due to the division of the interlayer film.

Therefore, the present invention solves the above-mentioned problems, and its problem is to control the penetration of etchant at the interface between the resist film and the interlayer film by enhancing the adhesion between the resist and the correlation film, and the film for forming the interlayer film. It is to prevent the penetration of an etchant by strengthening the adhesion at the interface between the film and the film, and to obtain a method that can be performed without adversely affecting the semiconductor device by a method for solving the problem.

[0007]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first wiring layer above a substrate and a second wiring layer formed apart from the first wiring layer, Forming a first oxide film covering the first wiring layer and the second wiring layer and having a recess between the first wiring layer and the second wiring layer; and forming an SOG film in the recess. Forming process,
Irradiating the first oxide film and the SOG film with inert ions to change the surface condition of the first oxide film and the surface condition of the SOG film, and the steps of forming the first oxide film and the SOG film. Forming a second oxide film on the surface whose surface state has changed; irradiating the second oxide film with inert ions;
Forming a resist film on the second oxide film irradiated with the inert ions, and forming a first hole in the resist film above the first wiring layer and the second wiring layer. A step of performing wet etching using the resist film and a step of performing dry etching using the resist film to form a second oxide film on the first oxide film and the second oxide film.
And a step of forming a hole, and a step of forming a third wiring layer on the second hole and the second oxide film.

The method of manufacturing a semiconductor device according to the present invention is
The method for manufacturing a semiconductor device includes a cleaning step of cleaning the second oxide film irradiated with the inert ions after the step of irradiating the second oxide film with the inert ions.

Further, in the method of manufacturing a semiconductor device of the present invention, in the method of manufacturing a semiconductor device, the inert ions are Ar ions.

According to the above-mentioned means , the surface condition of the contact surface changes, it is possible to control the intrusion of the etchant during wet etching, and it is possible to enhance the adhesiveness of the bonding surface and make it difficult to peel it off. Therefore, during wet etching, the etchant spreads more than necessary and the surface of the layer forming the wiring becomes uneven, so that it is possible to prevent the occurrence of defects such as short-circuiting or disconnection of the wiring above it. In addition, it is possible to prevent the interlayer film from being peeled off due to an insufficient bonding state and causing a defect in the semiconductor device.

[0011]

[0012]

[0013]

[0014]

[0015]

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Next, with reference to the drawings, an embodiment of a method for changing the bonding property with a film or a pattern and a method for controlling penetration and spread during wet etching according to the present invention will be described. In this embodiment, a first wiring, an interlayer film, and a second wiring are formed in this order on a silicon wafer, and the first wiring and the second wiring are connected by HOLE.

(First Embodiment) FIG. 1 is a sectional view showing a case where the structure is normally formed. The first wiring 6 and the second wiring 7 formed on the field 2 on the substrate 1 are
It is separated by an interlayer film having a multi-layered structure composed of the oxide film 3, the SOG film 4 and the second oxide film 5. The shape of the second wiring is substantially flat without any severe irregularities on the surface state of the second oxide film 5 in the lower layer, and therefore has a good shape with no breaks. Further, the adhesion between the interfaces of the first oxide film 3, the SOG film 4, and the second oxide film 5 forming the interlayer film is good, and there are no places where they are likely to peel off or no voids are formed.

However, as shown in the sectional view of FIG. 2, a resist film 8 is formed on the second oxide film 5 of the interlayer film, and HO
When forming the LE 11, it is necessary to make an inclination so that the wiring film can satisfactorily penetrate into the HOLE 11. HOLE
Since wet etching is used to form the inclined shape of 11, the etchant may permeate the contact interface between the second oxide film 5 of the interlayer film and the resist film 8 at that time to form the groove 10. When the groove 10 is formed, the wire is broken at the groove 10 like the second wiring 7 in the cross-sectional view of FIG. Further, when the adhesion at the contact interface between the first oxide film 3 and the second oxide film 5 in FIG. 2 is low, the etchant penetrates into the inside of the correlation film from the interface and reaches the SOG film 4 formed in the recess. I will end up. Then, since the SOG film has a high etching rate, the void 9 is formed, and the second oxide film 5 above the void 9 is in a floating state, and peels off when the resist film 8 in the next step is removed.

Therefore, as shown in FIG. 4A, after the second oxide film 5 is formed, an inert ion 1 such as Ar ion is formed.
2 is applied to the surface of the second oxide film 5 to change the surface condition. By changing it, the contact interface state with the resist film formed next on the second oxide film 5 also changes, and the penetration of the etchant during the wet etching of HOLE is also controlled. Further, as shown in FIG. 4B, after forming the SOG film 4, inert ions 12 such as Ar ions are struck on the surfaces of the SOG film 4 and the first oxide film 1 to change the surface condition.
By changing it, the contact interface state between the SOG film 4 and the second oxide film formed on the first oxide film 3 also changes, and HOL
It is possible to prevent the etchant from entering during the wet etching of E.

(Second Embodiment) Next, an embodiment of a method for removing deposits generated on the surface of a film hit with inert ions such as Ar ions will be described. Although the removal method is briefly shown in FIG. 5, the silicon wafer 13 is seen from the lateral direction, and the deposits 16 on the surface of the silicon wafer 13 after being hit with inert ions such as Ar ions are thin and soft. Remove using a brush 14 with hair. In addition,
Brushing is performed while rotating the brush 14 and the silicon wafer 13 while contacting the entire surface of the silicon wafer 13. In addition, the brushing is pure water blowing nozzle 1
It is effective to carry out with deionized water from 5.

[0021]

As described above, the present invention has the following effects.

According to the present invention , the bonding state between layers in a semiconductor device having a multilayer structure or the bonding state between a resist film and each layer is determined by Ar ions on the surface of the layer to be contacted or the surface of the pattern forming film. The bonding state at the contact interface can be controlled by hitting an inert ion such as. Therefore, HOL
It is possible to prevent the occurrence of irregularities on the surface of the interlayer film due to the excessive spread of the etchant in the wet etching during the formation of E, and to reduce the fatal defects of the semiconductor device such as the disconnection of the wiring formed on the interlayer film and the short circuit. You can Also, when the layers are weakly peeled off from each other, the damage may spread not only to the peeled wafer but also to other wafers. The present invention, which can enhance the strength, is very effective in improving the yield and reducing the cost.

Further , by hitting inert ions such as Ar ions , the deposits generated on the surface of the hit film are diffused to other wafers in the processing device in the subsequent processing step, causing a defect. However, almost all the deposits can be removed by a removal method using a contact brush and pure water in combination.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a normal structure and shape of an interlayer film and HOLE according to the present invention.

[FIG. 2] H at the interface between the interlayer film and the resist film and in the interlayer film
It is sectional drawing which shows the shape and the path | route which penetrates when an etchant permeates at the time of OLE wet etching.

FIG. 3 is a cross-sectional view showing that an etchant permeates an interface between an interlayer film and a resist film during HOLE wet etching, and a wiring is short-circuited on the interlayer film having an uneven surface.

FIG. 4 is a view showing the interface between the interlayer film and the resist film (a) and the layers of the interlayer film and the layer (b), in order to strengthen the respective bonding states,
It is sectional drawing which shows the process of implanting an inert ion.

FIG. 5 is a side view showing a method of removing deposits generated by implanting inert ions.

[Explanation of symbols]

1 substrate 2 fields 3 First oxide film 4 SOG film 5 Second oxide film 6 First wiring 7 Second wiring 8 Resist film 9 porosity 10 grooves 11 HOLE section 12 inert ions 13 Silicon wafer 14 brushes 15 Pure water blowing nozzle

─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hiroo Sato 3-3-5 Yamato, Suwa-shi, Nagano Seiko Epson Co., Ltd. (72) Masanori Yasuhara 3-3-5 Yamato, Suwa-shi, Nagano Sei (56) References JP-A-5-33163 (JP, A) JP-A-5-82502 (JP, A) JP-A-10-242028 (JP, A) JP-A-52-50690 ( (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/306-21/308

Claims (3)

(57) [Claims] 1. A step of forming a first wiring layer and a second wiring layer formed apart from the first wiring layer above a substrate, and covering the first wiring layer and the second wiring layer, And a step of forming a first oxide film having a recess between the first wiring layer and the second wiring layer, a step of forming an SOG film in the recess, the first oxide film and the SOG film A step of irradiating the surface of the first oxide film and the surface of the SOG film with inert ions, and a second surface on which the surface conditions of the first oxide film and the SOG film are changed. Forming an oxide film; irradiating the second oxide film with inert ions; forming a resist film on the second oxide film irradiated with the inert ions; Forming a first hole located above the first wiring layer and the second wiring layer; A step of performing wet etching using the resist film, a step of performing dry etching using the resist film to form a second hole in the first oxide film and the second oxide film, and the second hole And a step of forming a third wiring layer on the second oxide film, a method of manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a cleaning step of cleaning the second oxide film irradiated with the inert ions after the step of irradiating the second oxide film with the inert ions. . 3. The method for manufacturing a semiconductor device according to claim 1, wherein the inactive ions are Ar ions.