JP3520392B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3520392B2 JP3520392B2 JP05784697A JP5784697A JP3520392B2 JP 3520392 B2 JP3520392 B2 JP 3520392B2 JP 05784697 A JP05784697 A JP 05784697A JP 5784697 A JP5784697 A JP 5784697A JP 3520392 B2 JP3520392 B2 JP 3520392B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- forming
- wiring layer
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は、多層構造を有する
半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a multilayer structure.
【0002】[0002]
【従来の技術】半導体装置を製造する課程には幾つかの
パターンを形成するが、そのパターン形成の際はレジス
ト等のパターン形成用膜を用いており、また、その後の
エッチング工程ではウエットエッチングを実施する場合
がある。特に、HOLE等のアスペクト比の高い形状の
エッチングへの使用は一般化しおりている。つまり、H
OLEを形成した直後に配線を形成するが、その配線が
HOLE内に良好に付き廻るように、HOLE上部の形
状に傾斜を付けることが必要となる。ウエットエッチン
グはその傾斜付けの手段として主に利用されている。例
えば、従来技術でHOLEを形成する場合、層間膜上に
レジストを塗布し、HOLEパターンを形成する。その
後、異方性のエッチャントによってウエットエッチング
を行い、前記HOLE上部の傾斜付けを行った後、ドラ
イエッチングによってHOLE部を形成する。最後に、
レジスト膜を剥離し終了となる。2. Description of the Related Art Several patterns are formed in the course of manufacturing a semiconductor device, but a pattern forming film such as a resist is used in the pattern formation, and wet etching is performed in the subsequent etching process. May be implemented. In particular, it has been generalized to be used for etching a shape having a high aspect ratio such as HOLE. That is, H
The wiring is formed immediately after the formation of the OLE, but it is necessary to make the shape of the upper portion of the HOLE inclined so that the wiring can be well distributed in the HOLE. Wet etching is mainly used as a means of grading. For example, when forming a HOLE by a conventional technique, a resist is applied on the interlayer film to form a HOLE pattern. After that, wet etching is performed with an anisotropic etchant, the upper portion of the HOLE is inclined, and then the HOLE portion is formed by dry etching. Finally,
The resist film is peeled off to complete the process.
【0003】また、半導体装置の層間膜は多層構造を有
する半導体装置の、層と層との分別化のために形成する
が、バリア性と平坦性の両立から1つの層間膜は2〜3
種の酸化膜を用いた多層構造によって形成することが一
般的となっている。従来の層間膜の形成方法は、例えば
3層構造の層間膜では、1層目にCVD(Chemic
al Vapor Deposition)法によりS
iO2膜を形成し、2層目に液状のSOG(Spin
On Grass)膜をスピンコーティングし、凹部を
平坦化する。次にベークし固化したSOG膜の厚く付い
た余分なSOG膜をドライエッチングによってエッチン
グした後、3層目に1層目と同様の前述したCVDによ
りSiO2膜を形成する方法がある。Further, the interlayer film of the semiconductor device is formed for the purpose of separating the layers into layers of the semiconductor device having a multi-layer structure.
It is generally formed by a multi-layer structure using a seed oxide film. A conventional method for forming an interlayer film is, for example, in the case of an interlayer film having a three-layer structure, the first layer is formed by CVD (Chemical).
S by the Al Vapor Deposition method
An io2 film is formed and a liquid SOG (Spin) is formed on the second layer.
An On Glass) film is spin-coated to flatten the recess. Next, there is a method in which an extra SOG film thickly attached to the baked and solidified SOG film is etched by dry etching, and then a SiO2 film is formed as the third layer by the above-described CVD as in the first layer.
【0004】[0004]
【発明が解決しようとする課題】しかし、従来のHOL
Eの形成方法では、ウエットエッチング時に層間膜とレ
ジスト膜との界面にエッチャントが必要以上に染み込
み、HOLE形成部以外の層間膜までエッチングされて
しまう。特に、段差のある所まで染み込みが広がると、
その段差部にエッチャントが溜まり局所的にエッチング
され、層間膜に深い溝や穴が出来てしまう。そのため、
層間膜上に配線膜を形成し、配線パターンにエッチング
して配線を形成する際、前記溝や前記穴に前記AL膜が
入り込み、前記配線のエッチングの際にエッチングしき
れずに残り、配線のショートとなってしまったり、また
は、前記溝や前記穴に前記配線膜が入り込まずに空洞化
し、その上に形成された配線の断線の原因となる問題が
ある。However, the conventional HOL
In the method of forming E, the etchant permeates the interface between the interlayer film and the resist film more than necessary during the wet etching, and the interlayer film other than the HOLE forming portion is also etched. In particular, if the penetration spreads to a step,
The etchant accumulates in the step portion and is locally etched, and a deep groove or hole is formed in the interlayer film. for that reason,
When the wiring film is formed on the interlayer film and the wiring is etched to form the wiring, the AL film enters the groove or the hole and remains unetched when the wiring is etched, and the wiring is short-circuited. However, there is a problem that the wiring film does not enter the groove or the hole and is hollowed, which causes a disconnection of the wiring formed thereon.
【0005】更に、前記ウエットエッチング時に多層構
造の相関膜の場合は、1つの層間膜を形成する膜と膜の
間にエッチャントが染み込み層間膜の剥がれや、層間膜
中に鬆ができてしまう。例えば、前記例の3層構造の層
間膜では1層目と3層目のCVD膜間にエッチャントが
染み込むと、染み込んだ先にある凹に溜まったSOG膜
はエッチングレートが高いため急激にエッチングされ
る。そうなってしまうと、前記1層目と3層目のCVD
膜の密着性は著しく悪化し、層間膜の分裂による半導体
装置の不良原因となる問題がある。Further, in the case of a correlation film having a multilayer structure during the wet etching, an etchant permeates between the films forming one interlayer film and the interlayer film is peeled off or a void is formed in the interlayer film. For example, in the case of the three-layered interlayer film of the above example, when the etchant soaks between the first and third CVD films, the SOG film accumulated in the concave portion at the soaked point has a high etching rate and is rapidly etched. It If that happens, the CVD of the first and third layers
The adhesion of the film is significantly deteriorated, and there is a problem that the semiconductor device is defective due to the division of the interlayer film.
【0006】そこで本発明は上記問題点を解決するもの
であり、その課題は、レジストと相関膜の密着性強化に
よるレジスト膜と層間膜界面でのエッチャントの染み込
み制御、及び、層間膜形成の膜と膜の界面での密着性強
化によるエッチャントの染み込み防止であり、更にはそ
の課題解決方法によって半導体装置に悪影響を与えるこ
となく行える方法を得ることにある。Therefore, the present invention solves the above-mentioned problems, and its problem is to control the penetration of etchant at the interface between the resist film and the interlayer film by enhancing the adhesion between the resist and the correlation film, and the film for forming the interlayer film. It is to prevent the penetration of an etchant by strengthening the adhesion at the interface between the film and the film, and to obtain a method that can be performed without adversely affecting the semiconductor device by a method for solving the problem.
【0007】[0007]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、基板上方に第1配線層及び該第1配線層と離
間して形成された第2配線層を形成する工程と、前記第
1配線層と前記第2配線層とを覆い、且つ、該第1配線
層と該第2配線層との間に凹部を備える第1酸化膜を形
成する工程と、前記凹部にSOG膜を形成する工程と、
前記第1酸化膜と前記SOG膜とに不活性イオンを照射
し、該第1酸化膜の表面状態と該SOG膜の表面状態と
を変化させる工程と、前記第1酸化膜及び前記SOG膜
の表面状態が変化した表面に第2酸化膜を形成する工程
と、前記第2酸化膜に不活性イオンを照射する工程と、
不活性イオンが照射された前記第2酸化膜上にレジスト
膜を形成する工程と、前記レジスト膜に、前記第1配線
層及び前記第2配線層上方に位置する第1ホールを形成
する工程と、前記レジスト膜を用いてウエットエッチン
グを行う工程と、前記レジスト膜を用いてドライエッチ
ングを行い、前記第1酸化膜及び前記第2酸化膜に第2
ホールを形成する工程と、前記第2ホールと前記第2酸
化膜上とに第3配線層を形成する工程と、を備える。A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first wiring layer above a substrate and a second wiring layer formed apart from the first wiring layer, Forming a first oxide film covering the first wiring layer and the second wiring layer and having a recess between the first wiring layer and the second wiring layer; and forming an SOG film in the recess. Forming process,
Irradiating the first oxide film and the SOG film with inert ions to change the surface condition of the first oxide film and the surface condition of the SOG film, and the steps of forming the first oxide film and the SOG film. Forming a second oxide film on the surface whose surface state has changed; irradiating the second oxide film with inert ions;
Forming a resist film on the second oxide film irradiated with the inert ions, and forming a first hole in the resist film above the first wiring layer and the second wiring layer. A step of performing wet etching using the resist film and a step of performing dry etching using the resist film to form a second oxide film on the first oxide film and the second oxide film.
And a step of forming a hole, and a step of forming a third wiring layer on the second hole and the second oxide film.
【0008】また、本発明の半導体装置の製造方法は、
前記半導体装置の製造方法において、前記第2酸化膜に
不活性イオンを照射する工程後に、不活性イオンが照射
された前記第2酸化膜を洗浄する洗浄工程を備える。The method of manufacturing a semiconductor device according to the present invention is
The method for manufacturing a semiconductor device includes a cleaning step of cleaning the second oxide film irradiated with the inert ions after the step of irradiating the second oxide film with the inert ions.
【0009】さらに、本発明の半導体装置の製造方法
は、前記半導体装置の製造方法において、前記不活性イ
オンは、Arイオンである。Further, in the method of manufacturing a semiconductor device of the present invention, in the method of manufacturing a semiconductor device, the inert ions are Ar ions.
【0010】上記手段によれば、接触面の表面状態が変
化し、ウエットエッチング時のエッチャントの浸入を制
御することや、接合面の密着性を高め剥がれ難くするこ
とができる。そのため、ウエットエッチング時にエッチ
ャントが必要以上に広がり配線を形成する層の表面が凸
凹になり、その上層の配線がショートや断線するといっ
た不良発生を防止できる。また、層間膜の接合状態が不
十分なために剥がれ、半導体装置の不良原因となること
も防止できる。According to the above-mentioned means , the surface condition of the contact surface changes, it is possible to control the intrusion of the etchant during wet etching, and it is possible to enhance the adhesiveness of the bonding surface and make it difficult to peel it off. Therefore, during wet etching, the etchant spreads more than necessary and the surface of the layer forming the wiring becomes uneven, so that it is possible to prevent the occurrence of defects such as short-circuiting or disconnection of the wiring above it. In addition, it is possible to prevent the interlayer film from being peeled off due to an insufficient bonding state and causing a defect in the semiconductor device.
【0011】[0011]
【0012】[0012]
【0013】[0013]
【0014】[0014]
【0015】[0015]
【0016】[0016]
【発明の実施の形態】次に、図面を参照して本発明に係
る、膜やパターンと接合性を変化させる方法及び、ウエ
ットエッチング時の染み込みや広がりを制御する方法の
実施例を説明する。本実施例はシリコンウエハー上に第
1配線、層間膜、第2配線の順で形成し、第1配線と第
2配線をHOLEによって接続するものである。BEST MODE FOR CARRYING OUT THE INVENTION Next, with reference to the drawings, an embodiment of a method for changing the bonding property with a film or a pattern and a method for controlling penetration and spread during wet etching according to the present invention will be described. In this embodiment, a first wiring, an interlayer film, and a second wiring are formed in this order on a silicon wafer, and the first wiring and the second wiring are connected by HOLE.
【0017】(第1実施例)その構造での正常に形成さ
れた場合の断面図を図1に示す。基板1上のフィールド
2の上に形成された、第1配線6と第2配線7は、第1
酸化膜3とSOG膜4と第2酸化膜5から成る多層構造
を有する層間膜によって分別化されている。第2配線の
形状は、下層の第2酸化膜5の表面状態に激しい凸凹も
無くほぼ平坦となっているため断線個所も無い良い形状
となっている。また、層間膜を形成している第1酸化膜
3、SOG膜4、第2酸化膜5の界面の密着性も良好
で、剥がれそうな所や鬆ができているところもない。(First Embodiment) FIG. 1 is a sectional view showing a case where the structure is normally formed. The first wiring 6 and the second wiring 7 formed on the field 2 on the substrate 1 are
It is separated by an interlayer film having a multi-layered structure composed of the oxide film 3, the SOG film 4 and the second oxide film 5. The shape of the second wiring is substantially flat without any severe irregularities on the surface state of the second oxide film 5 in the lower layer, and therefore has a good shape with no breaks. Further, the adhesion between the interfaces of the first oxide film 3, the SOG film 4, and the second oxide film 5 forming the interlayer film is good, and there are no places where they are likely to peel off or no voids are formed.
【0018】しかし、図2の断面図に示すように、層間
膜の第2酸化膜5の上層にレジスト膜8を形成し、HO
LE11を形成する場合、HOLE11内に配線膜が良
好に突き廻るように傾斜を付ける必要がある。HOLE
11の傾斜形状の形成にはウエットエッチングを用いる
ため、その際層間膜の第2酸化膜5とレジスト膜8との
接触界面をエッチャントが染み込んでいき溝10が形成
される場合がある。溝10が形成されると、図3の断面
図の第2配線7のように溝10のところで断線してしま
う。更に、図2の第1酸化膜3と第2酸化膜5の接触界
面の密着性が低いと、その界面からエッチャントが相関
膜内部に浸入していき凹部に形成されたSOG膜4まで
達してしまう。すると、SOG膜はエッチングレートが
高いため鬆9が形成され、鬆9の上部の第2酸化膜5が
浮いた状態となり、次工程のレジスト膜8を除去する際
に剥がれてしまう。However, as shown in the sectional view of FIG. 2, a resist film 8 is formed on the second oxide film 5 of the interlayer film, and HO
When forming the LE 11, it is necessary to make an inclination so that the wiring film can satisfactorily penetrate into the HOLE 11. HOLE
Since wet etching is used to form the inclined shape of 11, the etchant may permeate the contact interface between the second oxide film 5 of the interlayer film and the resist film 8 at that time to form the groove 10. When the groove 10 is formed, the wire is broken at the groove 10 like the second wiring 7 in the cross-sectional view of FIG. Further, when the adhesion at the contact interface between the first oxide film 3 and the second oxide film 5 in FIG. 2 is low, the etchant penetrates into the inside of the correlation film from the interface and reaches the SOG film 4 formed in the recess. I will end up. Then, since the SOG film has a high etching rate, the void 9 is formed, and the second oxide film 5 above the void 9 is in a floating state, and peels off when the resist film 8 in the next step is removed.
【0019】そこで、図4(a)に示すように、第2酸
化膜5を形成した後に、Arイオン等の不活性イオン1
2を第2酸化膜5表面に打ち当て表面状態を変化させ
る。変化させることで、次に第2酸化膜5上に形成され
るレジスト膜との接触界面状態も変化し、HOLEのウ
エットエッチング時のエッチャントの染み込みも制御さ
れる。また、図4(b)に示すようにSOG膜4を形成
後にArイオン等の不活性イオン12をSOG膜4と第
1酸化膜1の表面上に打ち当て表面状態を変化させる。
変化させることで、次にSOG膜4と第1酸化膜3上に
形成する第2酸化膜との接触界面状態も変化し、HOL
Eのウエットエッチング時のエッチャントの浸入を防ぐ
ことができる。Therefore, as shown in FIG. 4A, after the second oxide film 5 is formed, an inert ion 1 such as Ar ion is formed.
2 is applied to the surface of the second oxide film 5 to change the surface condition. By changing it, the contact interface state with the resist film formed next on the second oxide film 5 also changes, and the penetration of the etchant during the wet etching of HOLE is also controlled. Further, as shown in FIG. 4B, after forming the SOG film 4, inert ions 12 such as Ar ions are struck on the surfaces of the SOG film 4 and the first oxide film 1 to change the surface condition.
By changing it, the contact interface state between the SOG film 4 and the second oxide film formed on the first oxide film 3 also changes, and HOL
It is possible to prevent the etchant from entering during the wet etching of E.
【0020】(第2実施例)次に、Arイオン等の不活
性イオンを打ち当てた膜の表面に発生した付着物の除去
方法についての実施例を説明する。図5に除去方法を簡
単に示すが、シリコンウエハー13は横方向から見たも
のであり、Arイオン等の不活性イオンを打ち当てた後
のシリコンウエハー13の表面の付着物16は、細く柔
らかい毛の付いたブラシ14を用いて除去する。なお、
ブラシ14やシリコンウエハー13を回転させながらシ
リコンウエハー13の表面全域を接触しながらブラッシ
ングする。また、ブラッシングは純水吹き出しノズル1
5から純水を出しながら行うと効果的である。(Second Embodiment) Next, an embodiment of a method for removing deposits generated on the surface of a film hit with inert ions such as Ar ions will be described. Although the removal method is briefly shown in FIG. 5, the silicon wafer 13 is seen from the lateral direction, and the deposits 16 on the surface of the silicon wafer 13 after being hit with inert ions such as Ar ions are thin and soft. Remove using a brush 14 with hair. In addition,
Brushing is performed while rotating the brush 14 and the silicon wafer 13 while contacting the entire surface of the silicon wafer 13. In addition, the brushing is pure water blowing nozzle 1
It is effective to carry out with deionized water from 5.
【0021】[0021]
【発明の効果】以上説明したように本発明によれば以下
の効果を有する。As described above, the present invention has the following effects.
【0022】本願発明によれば、多層構造を有する半導
体装置での層と層との接合状態や、レジスト膜と各層の
接合状態は、接触させる層の膜表面や、パターン形成膜
表面にArイオン等の不活性イオンを打ち当てることで
接触界面での接合状態を制御できる。このため、HOL
E形成時のウエットエッチングでのエッチャントの必要
以上の広がりにより層間膜表面にできる凸凹の発生を防
止でき、層間膜上に形成する配線の断線や、ショートと
いった半導体装置の致命的な不良を減らすことができ
る。また、層と層の接合状態が弱く剥がれてしまう場合
は、剥がれたウエハーだけではなく、その剥がれた物が
他のウエハーに付着することで被害が拡大する場合もあ
り、層と層の接合状態を強く出来る本発明はとても歩留
まり向上、コスト低減に効果がある。According to the present invention , the bonding state between layers in a semiconductor device having a multilayer structure or the bonding state between a resist film and each layer is determined by Ar ions on the surface of the layer to be contacted or the surface of the pattern forming film. The bonding state at the contact interface can be controlled by hitting an inert ion such as. Therefore, HOL
It is possible to prevent the occurrence of irregularities on the surface of the interlayer film due to the excessive spread of the etchant in the wet etching during the formation of E, and to reduce the fatal defects of the semiconductor device such as the disconnection of the wiring formed on the interlayer film and the short circuit. You can Also, when the layers are weakly peeled off from each other, the damage may spread not only to the peeled wafer but also to other wafers. The present invention, which can enhance the strength, is very effective in improving the yield and reducing the cost.
【0023】さらに、Arイオン等の不活性イオンを打
ち当てることで、打ち当てた膜の表面発生するに付着物
は、その後の処理工程での処理装置内で他のウエハーに
拡散し不良の原因となることが考えられるが、接触形の
ブラシと純水を併用する除去方法によってほぼ全ての付
着物を除去できる。Further , by hitting inert ions such as Ar ions , the deposits generated on the surface of the hit film are diffused to other wafers in the processing device in the subsequent processing step, causing a defect. However, almost all the deposits can be removed by a removal method using a contact brush and pure water in combination.
【図1】本発明に係る層間膜とHOLEの正常な構造と
形状を示す断面図である。FIG. 1 is a cross-sectional view showing a normal structure and shape of an interlayer film and HOLE according to the present invention.
【図2】層間膜とレジスト膜の界面及び、層間膜内へH
OLEウエットエッチング時にエッチャントが染み込ん
だ場合の、形状と染み込む経路を示す断面図である。[FIG. 2] H at the interface between the interlayer film and the resist film and in the interlayer film
It is sectional drawing which shows the shape and the path | route which penetrates when an etchant permeates at the time of OLE wet etching.
【図3】層間膜とレジスト膜の界面にHOLEウエット
エッチング時にエッチャントが染み込み、表面が凸凹し
た層間膜上で配線がショートすることを示す断面図であ
る。FIG. 3 is a cross-sectional view showing that an etchant permeates an interface between an interlayer film and a resist film during HOLE wet etching, and a wiring is short-circuited on the interlayer film having an uneven surface.
【図4】層間膜とレジスト膜の界面(a)及び、層間膜
の層と層(b)、それぞれの接合状態を強めるために、
不活性イオンの打ち込みを行う工程を示す断面図であ
る。FIG. 4 is a view showing the interface between the interlayer film and the resist film (a) and the layers of the interlayer film and the layer (b), in order to strengthen the respective bonding states,
It is sectional drawing which shows the process of implanting an inert ion.
【図5】不活性イオンの打ち込みにより発生した付着物
を除去する方法を示す側面図である。FIG. 5 is a side view showing a method of removing deposits generated by implanting inert ions.
1 基板 2 フィールド 3 第1酸化膜 4 SOG膜 5 第2酸化膜 6 第1配線 7 第2配線 8 レジスト膜 9 鬆 10 溝 11 HOLE部 12 不活性イオン 13 シリコンウエハー 14 ブラシ 15 純水吹き出しノズル 1 substrate 2 fields 3 First oxide film 4 SOG film 5 Second oxide film 6 First wiring 7 Second wiring 8 Resist film 9 porosity 10 grooves 11 HOLE section 12 inert ions 13 Silicon wafer 14 brushes 15 Pure water blowing nozzle
───────────────────────────────────────────────────── フロントページの続き (72)発明者 佐藤 浩男 長野県諏訪市大和3丁目3番5号 セイ コーエプソン株式会社内 (72)発明者 安原 正典 長野県諏訪市大和3丁目3番5号 セイ コーエプソン株式会社内 (56)参考文献 特開 平5−33163(JP,A) 特開 平5−82502(JP,A) 特開 平10−242028(JP,A) 特開 昭52−50690(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/306 - 21/308 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hiroo Sato 3-3-5 Yamato, Suwa-shi, Nagano Seiko Epson Co., Ltd. (72) Masanori Yasuhara 3-3-5 Yamato, Suwa-shi, Nagano Sei (56) References JP-A-5-33163 (JP, A) JP-A-5-82502 (JP, A) JP-A-10-242028 (JP, A) JP-A-52-50690 ( (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/306-21/308
Claims (3)
離間して形成された第2配線層を形成する工程と、 前記第1配線層と前記第2配線層とを覆い、且つ、該第
1配線層と該第2配線層との間に凹部を備える第1酸化
膜を形成する工程と、 前記凹部にSOG膜を形成する工程と、 前記第1酸化膜と前記SOG膜とに不活性イオンを照射
し、該第1酸化膜の表面状態と該SOG膜の表面状態と
を変化させる工程と、 前記第1酸化膜及び前記SOG膜の表面状態が変化した
表面に第2酸化膜を形成する工程と、 前記第2酸化膜に不活性イオンを照射する工程と、 不活性イオンが照射された前記第2酸化膜上にレジスト
膜を形成する工程と、 前記レジスト膜に、前記第1配線層及び前記第2配線層
上方に位置する第1ホールを形成する工程と、 前記レジスト膜を用いてウエットエッチングを行う工程
と、 前記レジスト膜を用いてドライエッチングを行い、前記
第1酸化膜及び前記第2酸化膜に第2ホールを形成する
工程と、 前記第2ホールと前記第2酸化膜上とに第3配線層を形
成する工程と、を備える、半導体装置の製造方法。1. A step of forming a first wiring layer and a second wiring layer formed apart from the first wiring layer above a substrate, and covering the first wiring layer and the second wiring layer, And a step of forming a first oxide film having a recess between the first wiring layer and the second wiring layer, a step of forming an SOG film in the recess, the first oxide film and the SOG film A step of irradiating the surface of the first oxide film and the surface of the SOG film with inert ions, and a second surface on which the surface conditions of the first oxide film and the SOG film are changed. Forming an oxide film; irradiating the second oxide film with inert ions; forming a resist film on the second oxide film irradiated with the inert ions; Forming a first hole located above the first wiring layer and the second wiring layer; A step of performing wet etching using the resist film, a step of performing dry etching using the resist film to form a second hole in the first oxide film and the second oxide film, and the second hole And a step of forming a third wiring layer on the second oxide film, a method of manufacturing a semiconductor device.
性イオンを照射する工程後に、不活性イオンが照射され
た前記第2酸化膜を洗浄する洗浄工程を備える、半導体
装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, further comprising a cleaning step of cleaning the second oxide film irradiated with the inert ions after the step of irradiating the second oxide film with the inert ions. .
ンは、Arイオンである、半導体装置の製造方法。3. The method for manufacturing a semiconductor device according to claim 1, wherein the inactive ions are Ar ions.
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JP05784697A JP3520392B2 (en) | 1997-03-12 | 1997-03-12 | Method for manufacturing semiconductor device |
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JP05784697A JP3520392B2 (en) | 1997-03-12 | 1997-03-12 | Method for manufacturing semiconductor device |
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JPH10256224A JPH10256224A (en) | 1998-09-25 |
JP3520392B2 true JP3520392B2 (en) | 2004-04-19 |
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JP05784697A Expired - Fee Related JP3520392B2 (en) | 1997-03-12 | 1997-03-12 | Method for manufacturing semiconductor device |
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JP4759117B2 (en) * | 2000-06-22 | 2011-08-31 | 日本特殊陶業株式会社 | SUBSTRATE WITH METAL OXIDE FILM AND METHOD FOR PRODUCING SUBSTRATE WITH METAL OXIDE FILM |
JP2011243657A (en) | 2010-05-14 | 2011-12-01 | Mitsumi Electric Co Ltd | Semiconductor device manufacturing method |
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