JP3515947B2 - Display element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving thin film
Transistor and a thin film transistor for driving.
Body display element and projection type equipped with such display element
The present invention relates to a display device and a method for manufacturing such a display element.
You. [0002] 2. Description of the Related Art Liquid crystal display devices and organic EL display devices include:
A driving circuit (also referred to as a “driver”) serves as a display panel.
So-called driver-integrated display device integrally formed with
There is. For example, a driver-integrated liquid crystal display device
Is a thin film transistor using polycrystalline silicon
It is called "TFT". Active matrix with
TFT for driving is formed integrally with the liquid crystal display element
I have. [0004] Referring to FIG.
The structure of the body type liquid crystal display device will be described. FIG.
4 schematically shows the structure of the driver-integrated liquid crystal display element 300.
FIG. The liquid crystal display element 300 includes a gate drive circuit 3
2, the source drive circuit 33, and the TFT array unit (display
Part) 34. The gate drive circuit 32 includes a shift
A register 32a and a buffer 32b,
A scanning signal (ge signal) is supplied to the pixel TFT 35 of the TFT array unit 34.
Signal). The source drive circuit 33 is less
, The shift register 33a, the buffer 33b, and the video
Sampling of video signal supplied from offline 38
And an analog switch 39 for performing the following. Source drive
The driving circuit 34 supplies a display signal (source signal) to the pixel TFT 35.
No.). In the TFT array section 34, a plurality of pixels 36
Electrically connected in parallel to each of the plurality of pixels 36.
And the additional capacitors 37 arranged in a matrix.
Each pixel (liquid crystal capacity) 37 and additional capacity 37
Is electrically connected to the drain electrode D of the TFT 35
I have. The pixel 36 includes a pixel electrode, a counter electrode,
And a liquid crystal layer provided therebetween. TFT3
The fifth gate electrode G extends from the gate drive circuit 32
The gate bus wiring 42 is connected and the TFT 35
The source electrode S has a source extending from the source driving circuit 33.
The bus wiring 41 is connected. One of the additional capacity 37
The additional capacitance common wiring 43 functioning as an electrode is
It is formed parallel to the source wiring 42. Additional capacitance common wiring
Reference numeral 43 is connected to an electrode having the same potential as the counter electrode. Constituting the pixel 36 of the liquid crystal display element 300
The counter electrode is a TFT array 3 on a TFT substrate (not shown).
4 so as to face each other via a liquid crystal layer (not shown).
Formed on the liquid crystal layer side of a counter substrate (not shown)
The components are formed on a TFT substrate. Next, referring to FIG. 11 and FIG.
Describes the structure of one pixel portion of the conventional liquid crystal display element 300.
I do. FIG. 11 is a plan view of one pixel portion of the liquid crystal display element 300.
It is a figure which shows a structure typically, omits a counter substrate, and shows TFT
2 shows a planar structure of a substrate. FIG. 12 is similar to FIG.
Corresponds to a cross-sectional view taken along line A-A ′ of FIG. As schematically shown in FIG.
T near the intersection of the source wiring 16 and the source bus wiring 20.
FT35 is formed. The pixel electrode 25 is a TFT3
5 is electrically connected to the drain electrode D of
35 source electrodes S are formed integrally with the source bus wiring 20
Have been. The gate electrode G of the TFT 35 is a gate bus.
It is formed integrally with the wiring 16. The TFT 35 is formed on the insulating substrate 30.
On the light shielding layer 32 with the insulating layer 10 interposed.
You. The light shielding layer 32 prevents light from entering the TFT 35.
Is provided. In particular, it is used for projection type liquid crystal display devices.
The liquid crystal display element has more powerful light than a direct-view display device.
Irradiation is required, and particularly excellent light resistance is required. The TFT 35 is formed on the insulating layer 10.
Polycrystalline silicon layer 11 and covering polycrystalline silicon layer 11
Insulating layer 13 formed as described above and gate insulating layer 1
3 and an additional capacitor common electrode formed on
The pole 14, the gate electrode 16 and the additional capacitance common electrode 14
And a first interlayer insulating layer 16 formed so as to cover
I have. The source electrode formed on the first interlayer insulating layer 16
The pole (source bus wiring) 41 is connected to the first interlayer insulating layer 16 and
Contact hole 1 penetrating through gate insulating layer 13
8 and is electrically connected to the source region of the semiconductor layer 11.
Have been. Similarly, formed on the first interlayer insulating layer 16
Drain electrode 21 is formed between the first interlayer insulating layer 16 and the gate.
A second contact hole 19 penetrating through the heat insulating layer 13 is formed.
Electrically connected to the drain region of the semiconductor layer 11 through the
ing. The source electrode 41 and the drain of the TFT 35
Second interlayer insulating layer 2 formed so as to cover
4, a pixel electrode 25 is formed. Pixel electrode 25
Is the third contact formed on the second interlayer insulating layer 24.
Electrically connected to the drain electrode 21 through the through hole 23
Have been. The pixel electrode 25 includes a counter electrode (not shown),
A liquid crystal layer (non-conductive) provided between the pixel electrode 25 and the counter electrode.
(Shown) together form a pixel (liquid crystal capacitor) 36. In this specification, the minimum unit of display is
The configuration of the liquid crystal display element corresponding to the pixel
Therefore, it is referred to as a “pixel”. This pixel is
In general, a liquid crystal capacitor (composed of pixel electrode / liquid crystal layer / counter electrode)
Corresponding). Also, it is electrically parallel to the liquid crystal capacitor 36.
The additional capacitor 37 connected to the column and the liquid crystal capacitor 36 are combined.
This is also referred to as “pixel capacitance”. According to the scanning signal applied to the gate electrode, T
During the period when the FT 35 is turned on, the voltage according to the display signal
Is applied to the pixel capacitance via the TFT 35, and the pixel capacitance is
Period until TFT 35 is turned on by the next scanning signal
This voltage over a period (one field or one frame)
Hold. Liquid constituting the liquid crystal capacitance 36 of this pixel capacitance
The liquid crystal molecules in the crystal layer change their orientation according to the applied voltage.
By modulating the light passing through the liquid crystal layer,
The display state according to the indication signal is presented. The additional capacity 37 is
It is provided to improve the voltage holding characteristic of the elementary capacitor. The additional capacitance 37 is connected to the additional capacitance common electrode 14.
And a gate insulating layer 13, and
Region 11 of semiconductor layer 11 opposed to added capacitance common electrode 14
A. Region 11 of semiconductor layer 11
A functions as an additional capacitance electrode. Below, additional capacity
The electrodes are also designated by reference numeral 11A. In addition,
The quantity common electrode 14 extends in parallel with the gate bus wiring 16
Of the wiring (common wiring for additional capacitance), additional capacitance electrode 11A
This is a region facing. The pixel electrode is connected to the additional capacitance electrode 11A.
The same voltage as that of the pole 25 is applied to the additional capacitance common electrode 14.
Is applied with the same voltage as the counter voltage. For the gate electrode 16
Other than the corresponding semiconductor layer 11 region (channel region) 12
Regions (source region, drain region and additional electrodes)
In the region 11A) functioning as a
Have been The above-described TFT 35 is, for example, as follows.
Manufactured. First, the pixel TFT 3 is placed on the insulating substrate 30.
5 is a light-shielding layer (for example,
A crystalline silicon layer 32 is formed. I will cover the light shielding layer 32
Thus, for example, a silicon oxide having a thickness of about 300 n
m of the insulating layer 10 is formed. Next, a polycrystalline silicon layer having a thickness of about 40
The semiconductor layer 11 having a thickness of about 10 nm to about 80 nm is formed. afterwards,
The semiconductor layer 1 is formed by sputtering or CVD.
1, silicon oxide (SiO 2)_Two)
A gate insulating layer having a thickness of about 80 nm to about 150 nm
13 is formed. Next, it becomes an additional capacitance electrode of the semiconductor layer 11.
For example, in the region 11A (corresponding to the hatched portion in FIG. 11)
If phosphorus ion (P⁺) Is about 1 × 10¹⁵/ Cm^TwoAt the concentration of
inject. This is common to the gate electrode 16 and the additional capacitance.
When ion implantation is performed after the electrode 14 is formed,
This is because ions are not implanted below the electrode. Next, the gate electrode 16 and the additional capacitance are shared.
The electrode 14 is made of metal or low-resistance polycrystalline silicon.
Form. Next, the conductivity type of the TFT 35 to be manufactured is determined.
For this purpose, 1 × phosphorus ions are applied from above the gate electrode 16.
10¹⁵/ Cm^TwoIon implantation at a concentration of
A channel region 12 is formed below 16. Next,
The first interlayer using silicon oxide or silicon nitride
After the insulating layer 15 is formed on the entire surface, the contact holes 18 and
And 19 are formed. Thereafter, the source bus wiring 41 and
The drain electrode 21 is formed using a low-resistance metal such as Al.
To achieve. This drain electrode 21 is connected to an additional capacitance electrode (additional capacitance electrode).
Region 1 of semiconductor layer 11 functioning as lower electrode of capacitor)
1A. Next, silicon oxide or silicon nitride
The second interlayer insulating layer 24 is formed on the entire surface by using a material. This
After that, a contact hole 23 is formed, and then I
Uses transparent conductive materials such as TO (indium tin oxide)
Then, a pixel electrode 25 is formed. Japanese Patent No. 2859785 discloses in FIG.
It has the same structure as the pixel TFT 35 shown in FIG.
With DD (Lightly Doped Drain),
Discloses TFTs with improved off characteristics (for example,
See FIG. 2 of the above publication). Also, the above publication discloses the above L.
The following method is disclosed as a method of forming a DD structure.
I have. First, the gate electrode and the resist layer are masked.
In this case, phosphorus ions are implanted into the semiconductor layer at a low concentration. So
After that, an opening is formed in a region 1.5 to 2 μm away from the gate electrode.
A resist layer having a portion is formed, and a gate electrode and this resist are formed.
High concentration of phosphorus ions in the semiconductor layer using the
Inject in degrees. As a result, the channel is located below the gate electrode.
The region (intrinsic semiconductor region) is 1.5 μm from the channel region.
LDD region (low concentration)
Impurity region), the source region and the
A rain region (high concentration impurity region) is formed. [0024] SUMMARY OF THE INVENTION
In a conventional TFT structure, for example, a small
Used for projection display devices (projectors), etc.
To obtain a small, high-definition driver-integrated liquid crystal display device
Sufficient driving capability (particularly, a sufficiently large on-current and
It is difficult to achieve a sufficiently high source / drain breakdown voltage).
It is difficult. For example, when the pixel pitch is 30 μm or less,
Realize a liquid crystal display device with a narrow pitch of 20 μm or less
Attempts to obtain sufficient driving capability with the conventional TFT structure
Therefore, the transistor width required for
It is difficult to increase the driving capability of T, and as a result
It is difficult to make a driver that operates at
Problem. As a result, conventionally, high definition and high quality
Realizes display element and projection display device that can display position
It was difficult to do. Further, Japanese Patent No. 2859785 discloses the above.
The disclosed method of manufacturing a TFT includes the steps of:
And high concentration impurity regions
It is necessary to form a resist pattern corresponding to the area
Therefore, the exposure process for forming the resist pattern
Due to the effect of mask alignment error
Problem that it is difficult to form a pattern with high positional accuracy
There is. As a result, miniaturization is limited and TF
The dispersion of the T characteristic is large, which causes a decrease in yield. Sa
In addition, the production process is complicated, resulting in low production efficiency
There is also a problem. On the other hand, a technique for increasing the driving capability of the TFT
Gate electrodes on the upper and lower surfaces of the semiconductor layer in the channel region.
The so-called double gate structure TFT with a pole
(For example, Japanese Patent No. 2589877). This
By adopting the structure described above, it is possible to increase the ON current of the TFT.
However, there is a problem that the withstand voltage is low. The present invention has been made in view of the above problems.
Its main purpose is to have excellent light resistance and large size.
High ON current and sufficiently high source / drain breakdown voltage
Thin film transistorPrepare,High definition and high quality display
It is to provide a possible display element. [0028] The display element of the present invention is a drive element.
A driving circuit including a driving transistor; and
With multiple pixels driven by the supplied voltage
Display device, wherein the driving transistor comprises a first transistor.
Gate electrode, first gate insulating layer, semiconductor layer, second gate
An insulating layer and a second gate electrode are formed on the substrate in this order
Wherein the semiconductor layer is a thin film transistor.
Channel region, low concentration impurity region and high concentration impurity region
And the first gate electrode has a light-shielding property.
Made of a material, at least the channel region
And formed in a region facing the low concentration impurity region.
handAnd each of the plurality of pixels is a display medium.
Layer, an electrode for applying a voltage to the display medium layer,
A pixel transistor provided between the electrode and the driving circuit.
Transistor and the semiconductor layer of the pixel transistor.
A light-shielding layer provided on the substrate side, wherein the light-shielding layer is
The same material as the first gate electrode of the driving transistor
And the semiconductor of the pixel transistor
A lower insulating layer between the body layer and the light-shielding layer;
The thickness of the insulating layer is larger than the thickness of the first gate insulating layer.
IThereby, the above object is achieved. [0029] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment will be described. In addition, the present invention relates to the following embodiments.
Not limited to (Embodiment 1) The cross-sectional structure of the TFT 100A according to the first embodiment of the present invention will be described.
FIG. 1 schematically shows this. The TFT 100A is mounted on the insulating substrate 101.
First gate electrode 102 and first gate insulating layer 104
, The semiconductor layer 106, the second gate insulating layer 108,
And two gate electrodes 110A in this order. Semiconductor layer (for example, polycrystalline silicon layer) 10
6 is a channel region 114, a low concentration impurity region 112 and
And a high concentration impurity region 113, and a first gate
The electrode 102 is made of a material having a light-shielding property (eg, a metal silicide).
And the channel region 114 and
It is formed in a region facing the low concentration impurity region 112 and
Is formed in a region facing the high-concentration impurity region 113.
Not. In addition, the second gate electrode 110A is
Is formed in a region facing the storage region 114, and
Formed in a region facing the low concentration impurity region 112;
Not in. The TFT 100A includes a second gate electrode 110
A further having an insulating layer 116 formed so as to cover A.
The insulating layer 116 and the second gate insulating layer 108
, Each of which has a high impurity concentration in the semiconductor layer 106.
Area (source region and drain region) 113
It has contact holes 118 and 120. Insulation
A source electrode 122 and a drain electrode
120 are formed and these are contact holes
118 and 120, respectively.
It is electrically connected to the area 113. The TFT 100A is located above and below the semiconductor layer 106.
Are formed with gate electrodes 102 and 110A,
With a double gate structure, relatively large ON
Indicates the current value. Further, the channel region of the semiconductor layer 106
114 and the high-concentration impurity regions 113 on both sides thereof.
Since it has the concentration impurity region 112, a relatively high
Source / drain breakdown voltage. Further, in the TFT 100A, light is shielded.
The first gate electrode 102 made of a conductive material is semiconductive.
Lightly doped region 112 and channel region of body layer 106
The substrate 1 is formed so as to correspond to the region 114.
Light incident from the 01 side is a low concentration impurity of the TFT 100A.
Irradiating region 112 and channel region 114
It is suppressed and prevented, and as a result, leakage current due to light irradiation
Is suppressed or prevented from increasing. Also, the first gate
The electrode 102 and the high concentration impurity region (the source region and the drain region)
Overlap with the in-region 113
Thus, a TFT having a relatively small parasitic capacitance is realized. As a material of the first gate electrode 102,
Uses metal silicide (for example, WSi)
preferable. Metal silicide is a conductive material with excellent light-shielding properties
As well as excellent heat resistance,
Has the advantage of being less susceptible to
You. Further, the thickness of the first gate insulating layer 104 is about 50
nm to about 200 nm.
Sufficiently large on-current while ensuring sufficient insulation
Can be obtained. The TFT 100A according to the present embodiment is
As described above, the source / drain withstand voltage is high and
Since the current is large, the drive of display
It is suitably used as a working TFT. TF of the present embodiment
By using T100A as a driver for display elements,
The driver becomes highly functional and realizes a high-definition display element
Is done. As the display element, for example, FIG. 10 and FIG.
To the conventional liquid crystal display element 300 described with reference to FIG.
Not limited, well-known TFT-type liquid crystal display devices and organic EL devices
(See, for example, Japanese Patent Application Laid-Open No.
2000-163014).
You. Furthermore, this high-definition display element has excellent light resistance.
Use one to three of these,
A fine projection display device can be realized. In addition,
Widely applicable to projection type display devices with known structures
Wear. Of course, the TFT 100A of the present embodiment is
Although it can be used as a TFT for
Since the required characteristics of the TFT are lower than those of the driving TFT,
Driving TFT rather than applying the present invention to pixel TFT
The effect obtained by applying the present invention to the present invention is greater. Next, referring to FIGS. 2 (a) to 2 (c),
A method of manufacturing the TFT 100A will be described. FIG.
FIG. 4 schematically shows a cross-sectional structure in a manufacturing process of the FT100A.
are doing. First, as shown in FIG.
A first gate electrode 102 is formed on a substrate 101 by metal silicide.
(For example, WSi). Metal silicide
Is less susceptible to heat damage in later processes.
Excellent light-shielding properties. This first gate electrode 102 is
To cover, for example, silicon oxide (SiO_Two)
To form the first gate insulating layer (thickness: about 150 nm) 104
To achieve. Next, as shown in FIG.
For example, using polycrystalline silicon, a semiconductor layer serving as an active layer
(Thickness: about 40 nm to about 80 nm) 106 is formed.
Then, for example, by sputtering or CVD,
The second gate insulating layer (thickness: about 80
(from about 150 nm to about 150 nm). After this,
2 A resist layer 108 is formed so as to cover the gate insulating layer 108.
And then irradiate light from the back side (substrate 101 side).
Therefore, the resist pattern corresponding to the first gate electrode 102
The pattern 109A is formed in a self-aligned manner. Such a backside
In order to perform exposure, a semiconductor layer (polycrystalline silicon layer) 1
06 should be in the range of about 10 to about 100 nm.
Is preferable, and considering semiconductor characteristics, about 40 nm to about 40 nm.
More preferably, it is within the range of 80 nm. Subsequently, the resist pattern 109A is
As a mask, use phosphorous or boron ions, for example.
About 1 × 10¹⁵/ Cm^TwoHigh concentration of the semiconductor layer 106
Region 106 not covered with resist pattern 109A
b. This region 106b is formed by the TFT 100A.
It becomes a source region and a drain region. Meanwhile, the semiconductor layer
The region located below the resist pattern 109A of 106
No ions are implanted into the region 106a. Next, the resist pattern 109A is peeled off.
After that, as shown in FIG.
The second gate using crystalline silicon or metal silicide
An electrode (thickness: about 300 nm) 110A is formed. That
Then, in order to determine the conductivity type of the TFT to be manufactured, the second gate
Using the gate electrode 110A as a mask, the second gate electrode 11
Phosphorus ion or boron ion from above 0A
About 1 × 10¹³/ Cm^TwoInject at low concentration, low concentration impurity
Object region 112 and the second gate electrode 11
Undoped channel region below 0A
(Intrinsic semiconductor region) 114 is formed. Note that the channel
The region 114 includes 1 × 1 to control the threshold voltage.
0¹²/ Cm^TwoOf ultra-low concentration of impurities
There is also. The second gate electrode 110 has a low concentration impurity region.
A structure that is not formed in a region facing 112
The gate length of the second gate electrode 110A is
If a configuration shorter than the gate length of the pole 102 is adopted,
As described above, using the first gate electrode 102 as a mask,
The pure region 112 can be formed. 1st gate power
Difference in gate length between pole 102 and second gate electrode 110A
Is preferably, for example, about 3 μm to about 4 μm.
No. The width of the low concentration impurity region 112 becomes wider than this
And the on-current decreases due to the electrical resistance.
Not good. Subsequently, an insulating layer 116 is formed on the entire surface.
Contact holes 118 and 120 in insulating layer 116
To form Next, the contact holes 118 and
The source electrode 122 and the drain electrode 12
4 is obtained, and the TFT 100A shown in FIG. 1 is obtained. As described above, the TFT of the present embodiment is manufactured.
According to the fabrication method, the first gate electrode 10 of the TFT 100A is formed.
2 is used as a mask to form high concentration impurity region 113.
Resist pattern 109A can be formed for
A mask for forming the low concentration impurity region 112;
Thus, the second gate electrode 110A can be used.
The TFT 100A is manufactured by a relatively simple manufacturing process.
Can be built. In addition, the high-concentration impurity regions 113 and
And the low-concentration impurity region 112 are respectively connected to the first gate electrode.
Self-aligned with 102 and second gate electrode 110A
These can be formed in a highly accurate
Can be formed. Therefore, the characteristics of the TFT 100A are
Characteristics variation and mask misalignment
Since there is no need to consider differences, it is smaller than conventional manufacturing methods.
Type TFT can be manufactured. (Embodiment 2) The sectional structure of the TFT 100B according to the second embodiment of the present invention will be described.
Figure3Is shown schematically in FIG. The TFT 100B includes a second gate electrode 110
B has substantially the same gate length as the first gate electrode 102.
This is different from the TFT 100 </ b> A of the first embodiment.
ThatotherThe configuration is substantially the same as the TFT 100A of the first embodiment.
Since they are the same, they are denoted by the same reference numerals, and the description is
Omitted. First gate electrode 102 and second gate electrode 1
10B has the same gate length as each other and has a channel region
114 and a region opposed to the low concentration impurity region 112
And is opposed to the high concentration impurity region 113.
It is not formed in the area. The TFT 100B is also the TF of the first embodiment.
Like the T100A, it has a double gate structure
Indicates a relatively high on-current value. Further, the semiconductor layer 1
06 channel region 114 and high concentration impurity regions on both sides thereof
A low-concentration impurity region 112 between the region 113
Therefore, it has a relatively high source / drain breakdown voltage. Also, in the TFT 100B, the TFT
Similar to 100A, a first light-shielding material
The gate electrode 102 is a low-concentration impurity region of the semiconductor layer 106
Formed to correspond to 112 and channel region 114
Light from the substrate 101 side
100B low concentration impurity region 112 and channel region
114 is suppressed or prevented from being irradiated,
Increased leakage current due to irradiation is suppressed and prevented.
It is. Further, the TFT 100B has a light shielding property.
The second gate electrode 110B formed of a material
Low concentration impurity region 112 together with channel region 1114
, So that the second gate electrode
Light incident from the 110B side passes through the low-concentration impurity region 112.
Irradiation is suppressed / prevented. Therefore, the TFT 100
The light resistance of B is even better than that of TFT 100A. Also, like the TFT 100A, the first game
Electrode 102 and the high concentration impurity region (the source region and the
There is virtually no overlap with the rain area 113
Thus, a TFT having a relatively small parasitic capacitance is realized. Further
In addition, metal silicide is used as a material of the first gate electrode 102.
(For example, WSi), the TFT 10
Of course, the same advantages as described above for 0A can be obtained.
That is. Further, the thickness of the first gate insulating layer 104
To a range of about 50 nm to about 200 nm.
As in the case of the TFT 100A, sufficient insulation is ensured.
At the same time, a sufficiently large on-current can be obtained. The TFT 100B according to the present embodiment is also
Similar to the TFT 100A of Embodiment 1, the source / drain resistance
High pressure and high on-current, especially for drivers
Suitable for use as a TFT for driving an integrated display element
You. Further, the TFT 100B is more
Further excellent light resistance makes it suitable for high-definition projection display devices.
It can be suitably used. Hereinafter, referring to FIGS. 4 (a) to 4 (c),
A method of manufacturing the TFT 100B will be described. FIG.
FIG. 4 schematically shows a cross-sectional structure in a manufacturing process of FT100B.
are doing. First, as shown in FIG.
A first gate electrode 102 is formed on a substrate 101 by metal silicide.
(For example, WSi). Metal silicide
Is less susceptible to heat damage in later processes.
Excellent light-shielding properties. This first gate electrode 102 is
To cover, for example, silicon oxide (SiO_Two)
To form the first gate insulating layer (thickness: about 150 nm) 104
To achieve. Next, as shown in FIG.
For example, using polycrystalline silicon, a semiconductor layer serving as an active layer
(Thickness: about 40 nm to about 80 nm) 106 is formed.
Then, for example, by sputtering or CVD,
The second gate insulating layer (thickness: about 80
(from about 150 nm to about 150 nm). After this,
2 A resist layer 109 is formed so as to cover the gate insulating layer 108.
Formed and light through a mask (not shown) with a predetermined pattern
By irradiation of the first gate electrode 102
A resist pattern 109B having a narrow width (in the gate length direction)
Form. Subsequently, the resist pattern 109B is
As a mask, use phosphorous or boron ions, for example.
About 1 × 10¹³/ Cm^TwoOf the semiconductor layer 106
Region 106 not covered with resist pattern 109B
Inject into c. On the other hand, the resist pattern of the semiconductor layer 106
In the region 106a located below the ion 109B,
Is not implanted and the channel region (intrinsic semiconductor region) 114
Becomes Next, the resist pattern 109A is peeled off.
After that, as shown in FIG.
The second gate using crystalline silicon or metal silicide
An electrode (thickness: about 300 nm) 110B is formed. Shading
From the viewpoint of performance, the metal
It is preferable to use side (for example, WSi).
New The formation of the second gate electrode 110B is based on the first gate electrode.
Substantially the same process using the mask used to form the pole 102
Can be formed. Thereafter, the conductivity type of the TFT to be manufactured is determined.
Therefore, using the second gate electrode 110B as a mask,
2 From above the gate electrode 110B,
About 1 × 10¹⁵/ Cm^TwoNote at high concentration of
And the high concentration impurity region 113 is formed. 2nd gate
The ions formed under the electrode 110A are doped.
The region that is not filled becomes the channel region 114 as it is.
You. The second gate electrode 110 is connected to the high-concentration impurity region 113.
If a configuration that is not formed in the facing area is adopted,
High concentration using the second gate electrode 110B as a mask.
The impurity regions 113 can be formed. Subsequently, an insulating layer 116 is formed on the entire surface.
Contact holes 118 and 120 in insulating layer 116
To form Next, the contact holes 118 and
The source electrode 122 and the drain electrode 12
4 is obtained, and the TFT 100B shown in FIG. 3 is obtained. As described above, the fabrication of the TFT of this embodiment
According to the fabrication method, the high concentration impurity region 113 is formed.
The second gate electrode 11 of the TFT 100B as a mask
0B can be used, making it a relatively simple manufacturing process.
In the process, the TFT 100B can be manufactured. Ma
Further, the high concentration impurity region 113 is formed in the second gate electrode 110B.
Can be formed in a self-aligned
Impurity region 113 with high positional accuracy.
Wear. Therefore, variation in characteristics of the TFT 100B is small.
And it is necessary to consider the mask alignment error
Since there is no TFT, it is possible to manufacture a TFT smaller than the conventional manufacturing method.
Can be (Embodiment 3) The structure of the display element according to Embodiment 3 of the present invention is shown in FIGS.
This will be described with reference to FIG. 6, and FIGS. 7 and 8.
The display element according to the present invention comprises a driving TFT and / or
It is characterized by the structure of the pixel TFT and its manufacturing method,
For example, the slave described with reference to FIGS.
Not limited to the conventional liquid crystal display element 300, but a well-known TFT-type liquid
It can be applied to crystal display devices and organic EL devices
Here, only the TFT will be described. FIG. 5 shows the driving T of the display element of the third embodiment.
FIG. 6 schematically shows a cross-sectional structure of the FT 200, and FIG.
The cross-sectional structure of the pixel TFT 200C of the display element of the third embodiment is schematically illustrated.
It is shown in a formula. FIGS. 7A to 7C show the driving TFT 20.
8 schematically shows a cross-sectional structure in the manufacturing process of FIG.
(A) to (c) show the manufacturing process of the pixel TFT 200C.
1 schematically shows a cross-sectional structure in the present embodiment. First, referring to FIG. 5, the driving TFT
200 will be described. The driving TFT 200 is a CMOS transistor.
(CMOS TFT), n-channel transistor
(N-channel TFT) 200A and p-channel transistor
(N-channel TFT) 200B.
You. As shown in FIG. 5, the n-channel TFT 2
00A is the first gate electrode 20 on the insulating substrate 201.
6, a first gate insulating layer 210, a semiconductor layer 214,
The second gate insulating layer 219 and the second gate electrode 224 are
It has in this order. The n-channel TFT 200A has a double gate
And has substantially the same structure as the TFT 100A of the first embodiment.
It has the same characteristics. That is, the first gate electrode 20
6 is a light-shielding material (for example, metal silicide)
And the channel region 2 of the semiconductor layer 214
11 and the low concentration impurity region 217
And a region opposed to the high-concentration impurity region 215
Is not formed. Also, the second gate electrode 224
Is formed in a region facing the channel region 211.
And a region facing the low concentration impurity region 217
Not formed. Therefore, the n-channel TFT 200A
Has the same advantages as the TFT 100A of the first embodiment.
You. On the other hand, the p-channel TFT 200B
A first gate electrode 208 and a first gate electrode
Insulation layer 210, semiconductor layer 216, and second gate insulation
Having a layer 219 and a second gate electrode 226 in this order.
I have. The p-channel TFT 200B also has the semiconductor layer 2
16th channel region 211B
Including a first gate electrode 208 and a second gate electrode 226;
It has a double gate structure. However, the semiconductor layer 216
Indicates the channel region 211B and the high concentration formed on both sides thereof.
Channel region 211B having only impurity region 225
And high-concentration impurity regions 225 formed on both sides thereof
And a low-concentration impurity region. Also, the first gate
The electrode 208 and the second gate electrode 226 are
Formed at positions corresponding to the 16 channel regions 211B.
And a region corresponding to the high-concentration impurity region 225 has a shape.
Not done. The CMOS TFT 200 has an n-channel TF
T200A second gate electrode 224 and p-channel T
Formed to cover the second gate electrode 226 of the FT 200B
Insulating layer 232, and the insulating layer 232 and
The second gate insulating layer 219 penetrates these,
This is a high concentration impurity region of the semiconductor layers 214 and 216.
(Source region and drain region) 215 and 225
Contact holes 236, 238, 240 leading to
242. The electrode 24 is formed on the insulating layer 232.
6, 250 and 252 are formed,
Contact holes 236, 238, 240 and 242
Through the high-concentration impurity regions 215 and 22 respectively.
5 is electrically connected. n-channel TFT200
The A electrode 246 is a low-potential electrode and has a p-channel T
The electrode 248 of the FT 200B is a high potential electrode. Ma
The output electrode 250 of the CMOS TFT 200 is
High concentration impurity region 215 of the p-channel TFT 200A.
And the high-concentration impurity region 225 of the
Is electrically connected to To cover these,
In addition, a second interlayer insulating layer 252 is formed. As described above, the CMOS TFT 200 is
The n-channel TFT 200A to be configured is the same as the TFT of the first embodiment.
Has substantially the same structural features as FT100A
Therefore, the source / drain breakdown voltage is high and the on-current is
It has the feature of being large. In general, n channel T
The FT has a lower withstand voltage than the p-channel TFT, and
Characteristics are likely to be degraded due to carrier generation.
It is preferable to form a low concentration impurity region in the channel TFT.
New Although the number of manufacturing processes increases, low concentration
Impurity regions may be formed. Next, referring to FIG.
The structure of 200C will be described. The TFT 200C is mounted on the insulating substrate 201.
A light-shielding layer 202, an insulating layer 204, and a first gate insulating layer.
Layer 210, semiconductor layer 218, and second gate insulating layer 21
9 and the gate electrode 220 in this order. The semiconductor layer 218 includes the channel region 211
C, low concentration impurity region 212 and high concentration impurity region 2
13 and the gate electrode 220 has a channel region
It is formed in the area opposite to 211C and has a low impurity concentration.
Object region 212 and high-concentration impurity region 213
It is not formed in the area. The semiconductor layer 218 has an additional volume.
Extended high-concentration impurity region 2 functioning as a charge electrode
13A. Extended high concentration impurity area
In the region (additional capacitance electrode) 213A, the second gate insulating layer 21 is formed.
9, an additional capacitance common electrode 222 is formed
Has been established. The TFT 200C has a gate electrode 220 and
And an additional capacitor common electrode 222 formed to cover the
Further comprising an edge layer 232, wherein the insulating layer 232 and the second gate
The insulating layer 219 penetrates these, and the semiconductor layer 218
To the high concentration impurity region (source region) 213 of FIG.
The hole 234 is provided. Formed on insulating layer 232
The source electrode 244 that is
4 electrically connected to the high-concentration impurity region 213
ing. In order to cover them, a second interlayer insulating
A layer 252 is formed and is formed on the second interlayer insulating layer.
The pixel electrode 256, which is connected to the second interlayer insulating layer 252,
Penetrates the edge layer 232 and the second gate insulating layer 219
High-concentration impurity region through contact hole 254
(Drain region) 213. The TFT 200C has a channel region 211C.
Between the high-concentration impurity regions 213 on both sides thereof.
Since it has the pure region 212, a relatively high source
It has a drain breakdown voltage. Next, referring to FIG. 7 and FIG.
TFT 2 in manufacturing method of display element of embodiment
00 and a method of manufacturing the pixel TFT 200C.
You. Other components of the display element are manufactured by known methods.
Therefore, the description is omitted here. First, FIG. 7A and FIG.
As described above, a light-shielding conductive
Using a material (for example, metal silicide), a pixel TF
Light shielding layer 20 for blocking light emitted to T200C
2 is formed in a predetermined pattern. Here, the TFT 20
In order to shield almost the entirety of the semiconductor layer 218 of O.C.
Although the optical layer 202 is formed, at least the channel region 21 is formed.
1C, preferably the channel region 211C and low concentration impurities
What is necessary is just to form so that the object area | region 212 and light may be shielded. Of course
Of course, it is necessary to shield the entire semiconductor layer 218 from light in terms of light resistance.
Is most preferred. The same process as the formation of this light shielding layer 202
And the n-channel constituting the driving CMOS TFT 200
First gate electrode 206 of TFT 200A and p-channel T
The first gate electrode 208 of the FT 200B is formed. You
That is, for example, the metal is almost entirely over the insulating substrate 201.
A silicide film (for example, WSi) is formed and
The light shielding layer 202, the first gate
Electrodes 206 and 208 are formed simultaneously. Next, the light shielding layer 202 and the n-channel TFT
200A first gate electrode 206 and p-channel TFT
Insulating substrate 2 so as to cover first gate electrode 208.
01, a thickness of, for example, silicon oxide
An insulating layer 204 of about 300 nm is formed. After this, drive
Layer 20 formed in the region of the CMOS TFT 200 for use
4 is removed by etching, and the first gate of the n-channel TFT is removed.
Electrode 206 and the first gate electrode 20 of the p-channel TFT.
And 8 are exposed. Thereafter, almost the entire surface of the insulating substrate 201 is covered.
For example, using silicon oxide, the thickness is about 50 nm to about 2 nm.
A first gate insulating layer 210 having a thickness of 00 nm is formed.
As a result, the first gate voltage of the driving CMOS TFT 200 is increased.
The poles 206 and 208 are only the first gate insulating layer 210
And the light-shielding layer 202 of the pixel TFT 200C.
Is covered with the insulating layer 204 and the first gate insulating layer 210.
Is As described above, the driving CMOS TFT 200
First gate electrodes 206 and 208 and their respective semiconductors
Gate insulation formed between body layers 214 and 216
The insulating layer functioning as a layer corresponds to the first gate insulating layer 210.
The thickness is easy to control.
And have a relatively large on-current.
(For example, about 50 nm to about 200 nm).
Wear. On the other hand, between the light shielding layer 202 and the semiconductor layer 218
The first gate insulating layer 210 and the insulating layer 204 are formed.
As a result, the light-shielding layer 202 and the semiconductor layer 218 are compared.
And separated by a thick insulating layer.
An increase in the parasitic capacitance of the elementary TFT 200C is suppressed. Next, FIG. 7B and FIG.
As described above, on the first gate insulating layer 210, for example,
Each silicon TFT 200A, 200
B and a semiconductor layer to be an active layer of 200C (thickness: about 1
0 nm to about 100 nm) 214, 216 and 218
It is formed in a predetermined pattern. Subsequently, almost the entire surface of the insulating substrate 201
The second gate insulating layer using, for example, silicon oxide
(Thickness: about 100 nm to about 200 nm) 219 is formed
You. This second gate insulating layer219On top of, for example, metal (eg
For example, using Al) or low-resistance polycrystalline silicon,
Gate electrode 220 and additional capacitance of element TFT 200C
Common electrode (upper electrode of additional capacitance) 222 and n-channel
A second gate electrode 224 of the TFT 200A and a p-channel
A predetermined pattern is applied to the second gate electrode 226 of the TFT 200B.
Formed. First gate electrodes 206 and 208;
CMOST is used for the second gate electrodes 224 and 226.
An input voltage to the FT 200 is applied. Next, the second gate of the n-channel TFT 200A
Gate electrode 224 and the gate electrode of the pixel TFT 200C
220 and the semiconductor layers 214 and 218
Then, about 1 × 10¹³/
cm^TwoInject at a low concentration. At this time, p channel
Resist pattern covering the semiconductor layer 216 of the TFT 200B.
Turns are formed, and ions are injected into the semiconductor layer 216.
Not to be entered. By this ion implantation,
The first gate voltage of each of the semiconductor layers 214 and 218
Low concentration near the bottom of the pole 224 and the gate electrode 220
Pure regions 217 and 212 are formed, respectively. Semiconduct
First gate electrode 2 of each of body layers 214 and 218
24 and the gate electrode 220
Flannel regions 211A and 211C are formed. Subsequently, the low density of the n-channel TFT 200A is
Impurity region 217 and low concentration impurities of TFT 200C
Forming a resist pattern covering the object region 212,
Phosphorous ions from above substrate 201¹⁵/ Cm^Two
Inject at high concentration. At this time, the p-channel TF
Resist pattern covering semiconductor layer 216 of T200B
Are formed, and ions are implanted into the semiconductor layer 216.
Keep away. By this ion implantation, the first gate
A channel under the gate electrode 224 and the gate electrode 220.
Areas 211A and 211C, and low density
Impurity regions 217 and 212 and further outside
Concentration impurity regions 215 and 213 are formed, and n channel
A tunnel type TFT 200A and TFT 200C are obtained.
You. Subsequently, the n-channel type TFT 200A and the
And a resist pattern covering the TFT 200C,
The second gate electrode 226 of the p-channel TFT 200B is
As a mask, on the semiconductor layer 216, on the insulating substrate 201.
From boron ion 1 × 10¹⁵/ Cm^TwoAt a high concentration of
inject. In this manner, the lower part of the second gate electrode 226
Channel region 211B, and a high concentration non-
A pure region 225 is formed, and a p-channel TFT is obtained.
You. Almost all over the insulating substrate 201 so as to cover these
A first interlayer insulating layer using, for example, silicon oxide
232 are formed. Next, the first interlayer insulating layer 232 is patterned
And contact holes 234 (FIG. 6), 23
6, 238, 240 and 242 (FIG.5) Is formed.
Thereafter, as shown in FIG.
Is formed integrally with the source bus wiring so as to cover
Electrode 244, n-channel T to which the lower voltage is applied
246 of FT200A, higher voltage is applied
Electrode 248 of p-channel TFT 200B, n-channel T
FT200A and p-channel TFT200B
To which the output voltage from the CMOS TFT 200 is applied.
Each of the poles 250 is formed using a metal (for example, Al).
In a pattern of Subsequently, over almost the entire surface of the insulating substrate 201,
After forming the second interlayer insulating layer 252, the pixel TFT 20
Gate insulating layer 219 and first interlayer insulating layer 23 at 0C
2. Contact holes penetrating the second interlayer insulating layer 252
254 are formed by etching. Next, the second layer
A transparent conductive film (eg, ITO) is formed on almost the entire surface of the insulating layer 252.
Film), and by patterning it,
The pixel electrode 256 is formed. The pixel electrode 256 has a contour
And the pixel portion of the TFT 200C through the connection hole 254.
The pixel electrode 25 is connected to the drain of the transistor.
6 is formed. Hereinafter, as described above, the driving CMOST
Actuator with FT200 and pixel TFT 200C formed
Matrix substrate and opposing substrate on which opposing electrodes are formed
And sealing the liquid crystal material between the two substrates.
Therefore, the liquid crystal display device of the present embodiment is obtained. Above
Of components other than the driving TFT and pixel TFT
Known methods can be widely used for fabrication. The above-described driver-integrated liquid of the present embodiment
In the crystal display element, the lower part of the pixel TFT 200C
Is incident on the TFT 200C from the insulating substrate 201 side.
A light-blocking layer 202 for blocking light is formed. Ma
The driving CMOSTF is formed from the same film as the light shielding layer 202.
First gate electrodes 206 and 208 of T200 are formed.
Have been. The first gate electrodes 206 and 208
At least a channel of each of the semiconductor layers 214 and 216
Formed in a region facing the cell regions 211A and 211B.
Channel region 2 from the insulating substrate 201 side.
The light incident on 11A and 211B is blocked. Follow
Pixel TFT 200C and driving CMOS TFT
All 200 have excellent light resistance. The n-ch of the driving CMOS TFT 200
The channel TFT 200A is the TFT 100A of the first embodiment.
Has the same structural features as practical
High drain-drain breakdown voltage and large on-current. Therefore, the liquid crystal display device of the present embodiment has a high durability.
Driving CMO with excellent optical properties and operating at high frequency
Extremely high definition and high quality due to the provision of STFT200
The display of the order can be realized. In addition, this LCD table
Since the display element has excellent light resistance, it is suitable for projection type display devices.
Used for The above-described pixel TFT 200C of the display element
Instead of using the TFT 200D shown in FIG.
Wear. The TFT 200D has an insulating layer (for example, a thickness
The additional capacitance of silicon oxide film 204
In that the region to be formed has an opening 204a.
Therefore, it is different from the TFT 200C. Other components are T
Since they are substantially the same as the FT200C, they are denoted by the same reference numerals.
The description is omitted here. The first gate formed on the insulating layer 204
Region of the insulating layer 210 and the semiconductor layer 218 (additional capacitance
Electrode) 213A, second gate insulating layer 219, and additional capacitor
The common electrode 22 is formed so as to cover the opening 204a.
Have been. That is, the additional capacitance electrode 213A and the second game
The insulating layer 219 and the additional capacitance common electrode 222 have openings.
204a as well.
The effective area of the additional capacitance constituted by
Larger than the projected area to Therefore, the structure of the TFT 200D shown in FIG.
When the structure is adopted, a capacitance value larger than that of the TFT 200C is obtained.
The additional capacitance can be formed. Conversely, the same
When forming an additional capacitor having a quantity value, the TFT 20
Area (projection plane)
Product), reducing the area of the light-impermeable area.
To improve the aperture ratio of the display element
Can be. The display device including the TFT 200D is described above.
It is manufactured using substantially the same method as the manufacturing method described above.
The opening 204a of the insulating layer 204 of the TFT 200D is an example.
For example, in the manufacturing method described above, the driving CMOSTF
Etching the insulating layer 204 formed in the region of T200
At the same time in the removing step. This manufacturing
If the method is adopted, a table having the above-described TFT 200C is obtained.
The TFT 2 can be manufactured without increasing the number of steps in the method of manufacturing the display element.
A display element having 00D can be manufactured. [0099] According to the present invention,Driving transistor and
do it,Excellent light resistance, large on-current and sufficient
Thin film transistor with high source / drain breakdown voltage
Since it hasHigh-definition, high-quality display
An element can be realized. In addition, the thin film transistor
Stars have excellent light resistance, making them suitable for projection display devices.
High-definition and high-quality display
You.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram schematically showing a cross-sectional structure of a TFT 100A according to a first embodiment of the present invention. FIGS. 2A to 2C are diagrams schematically showing a cross-sectional structure in a manufacturing process of the TFT 100A. FIG. 3 is a diagram schematically showing a cross-sectional structure of a TFT 100B according to a second embodiment of the present invention. FIGS. 4A to 4C are diagrams schematically showing a cross-sectional structure in a manufacturing process of the TFT 100B. FIG. 5 shows a driving element T for a display element according to a third embodiment of the present invention.
It is a figure which shows the cross-section of FT200 typically. FIG. 6 shows a pixel T of a display device according to a third embodiment of the present invention.
It is a figure which shows the cross-section of FT200C typically. FIGS. 7A to 7C are diagrams schematically showing a cross-sectional structure in a manufacturing process of a display element driving TFT 200 according to a third embodiment of the present invention. FIGS. 8A to 8C are diagrams schematically showing a cross-sectional structure in a manufacturing process of a pixel TFT 200C of a display element according to a third embodiment of the present invention. FIG. 9 is a diagram schematically showing a cross-sectional structure of another pixel TFT 200D of the display element according to the third embodiment of the present invention. FIG. 10 is a plan view schematically showing the structure of a conventional driver-integrated liquid crystal display element 300. FIG. 11 is a diagram schematically showing a planar structure of one pixel portion of a conventional liquid crystal display element 300. 12 is a diagram schematically showing a cross-sectional structure of one pixel portion of a conventional liquid crystal display element 300, and corresponds to a cross-sectional view taken along line AA ′ of FIG. [Description of Reference Numerals] 100A TFT 101 Insulating substrate 102 First gate electrode 104 First gate insulating layer 106 Semiconductor layer 108 Second gate insulating layer 110A Second gate electrode 112 Low concentration impurity region 113 High concentration impurity region 114 Channel region 116 Insulating layers 118, 120 Contact hole 120 Drain electrode 122 Source electrode

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 21/336 H01L 29/78 616A 21/8238 612B 27/092 619B 27/08 321D

Claims (1)

(57) [Claim 1] A driving circuit including a driving transistor,
A display element having a plurality of pixels driven by a voltage supplied from the driving circuit, wherein the driving transistor includes a first gate electrode, a first gate insulating layer, a semiconductor layer, a second gate insulating layer, And a second gate electrode formed on the substrate in this order, wherein the semiconductor layer has a channel region, a low-concentration impurity region and a high-concentration impurity region, and the first gate electrode is light-shielded. is formed of a material having a gender, with formed in a region facing at least the channel region and the low concentration impurity regions, each of the plurality of pixels, and the display medium layer, wherein the display
An electrode for applying a voltage to the medium layer;
A pixel transistor provided between the driving circuit and
Provided on the substrate side of the semiconductor layer of the pixel transistor.
A light shielding layer, wherein the light shielding layer is
The first gate electrode of the transistor is formed of the same material as the first gate electrode.
The semiconductor layer and the light shielding layer of the pixel transistor
A lower insulating layer between them, the thickness of the lower insulating layer being
A display element having a thickness greater than the thickness of the first gate insulating layer.