CN113571002A

CN113571002A - Pixel circuit, display panel and electronic equipment

Info

Publication number: CN113571002A
Application number: CN202010358194.8A
Authority: CN
Inventors: 胡晓宇; 张玉婷; 金志河; 袁泽
Original assignee: Shenzhen Royole Technologies Co Ltd
Current assignee: Shenzhen Royole Technologies Co Ltd
Priority date: 2020-04-29
Filing date: 2020-04-29
Publication date: 2021-10-29

Abstract

The application provides a pixel circuit, pixel circuit includes first switch element, and first switch element includes first source electrode, first drain electrode, first channel, first grid and first shielding piece, and first source electrode and first drain electrode are connected first channel respectively, first shielding piece set up in first channel deviates from one side of first grid. The first gate and the first shielding piece have a shielding protection effect on the first channel layer, so that the characteristics of the first switch unit can be improved, and the stability of the first switch unit, the circuit design of the pixel circuit and the performance of the pixel circuit are improved. The application also provides a display panel, the display panel comprises a plurality of light-emitting units distributed in an array manner and a plurality of pixel circuits corresponding to the light-emitting units, and the light-emitting units are electrically connected with anodes of the pixel circuits. The application also provides an electronic device, which comprises a body and a display panel, wherein the body is used for bearing the display panel.

Description

Pixel circuit, display panel and electronic equipment

Technical Field

The present application relates to the field of display technologies, and in particular, to a pixel circuit, a display panel, and an electronic device.

Background

Display technology of electronic devices has been one of the major research directions, and pixel circuits are the core of display technology. In a conventional pixel circuit, the stability of the thin film transistor is easily affected by illumination and electron current, which causes poor display and errors.

Disclosure of Invention

The application discloses a pixel circuit, which can solve the technical problem that the stability of a thin film transistor is easily influenced by illumination and electron current.

In a first aspect, the present application provides a pixel circuit, the pixel circuit includes a first switch unit, the first switch unit includes a first source electrode, a first drain electrode, a first channel, a first gate and a first shielding member, the first source electrode is connected with the first drain electrode respectively and is connected with the first channel, the first shielding member is disposed on one side of the first channel deviating from the first gate.

The first gate and the first shielding piece have a shielding protection effect on the first channel layer, so that the characteristics of the first switch unit can be improved, and the stability of the first switch unit, the circuit design of the pixel circuit and the performance of the pixel circuit are improved.

In a second aspect, the present application further provides a display panel, where the display panel includes a plurality of light emitting units distributed in an array, and a plurality of pixel circuits corresponding to the light emitting units as described in the first aspect, and the light emitting units are electrically connected to the anodes of the pixel circuits.

In a third aspect, the present application further provides an electronic device, where the electronic device includes a body and the display panel of the second aspect, and the body is used for bearing the display panel.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for a person skilled in the art to obtain other drawings based on the drawings without any inventive exercise.

Fig. 1 is a schematic cross-sectional view of a first switch unit according to a first embodiment of the present application.

Fig. 2 is a schematic cross-sectional view of a first switch unit according to an embodiment of the present application.

Fig. 3 is a schematic cross-sectional view of a first switch unit according to an embodiment of the present application.

Fig. 4 is a schematic cross-sectional view of a first switch unit and a second switch unit according to an embodiment of the present application.

Fig. 5 is a schematic cross-sectional view of a first switch unit and a second switch unit according to an embodiment of the present application.

Fig. 6 is a schematic cross-sectional view of a first switch unit and a second switch unit according to an embodiment of the present application.

Fig. 7 is a schematic cross-sectional view of a first switch unit and a second switch unit according to an embodiment of the present application.

Fig. 8 is a schematic diagram of a pixel circuit according to an embodiment of the present application.

Fig. 9 is a schematic diagram of a pixel circuit according to an embodiment of the present application.

Fig. 10 is a schematic diagram of a signal timing sequence according to an embodiment of the present application.

Fig. 11 is a schematic circuit diagram of a display panel according to an embodiment of the present application.

Fig. 12 is a schematic circuit diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.

Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a first switch unit according to a first embodiment of the present disclosure. The pixel circuit 1 includes a first switching unit T1, the first switching unit T1 including a first source s1, a first drain d1, a first channel sd1, a first gate g1, and a first shutter ls 1. The first source s1 and the first drain d1 are respectively connected to a first channel sd1, and the first shade ls1 is disposed on a side of the first channel sd1 away from the first gate g 1.

In one possible embodiment, referring to fig. 1 again, the pixel circuit 1 further includes a blocking layer LS, a channel layer a, a gate layer G, a source/drain layer SD, and an anode layer P. The first shielding LS1 is disposed on the shielding layer LS, the first channel SD1 is disposed on the channel layer a, the first gate G1 is disposed on the gate layer G, and the first source s1 and the first drain d1 are disposed on the source drain layer SD. The anode layer P is provided with an anode a, and the first source s1 is electrically connected to the anode a.

Specifically, the pixel circuit 1 further includes a substrate B, the first shielding LS1 is disposed on a side of the shielding layer LS adjacent to the substrate B, and the substrate B is used for carrying the shielding layer LS and the first shielding LS 1.

Specifically, the first source s1 and the first drain d1 extend from the source/drain layer SD to the channel layer a through a conductor and are respectively connected to the first channel SD1 through a conductor. The first shutter ls1 can block light and electron current entering the first channel sd1 from the side of the first shutter ls1 away from the first channel sd1, so as to prevent the stability of the first switch unit T1 from being affected by the light and electron current.

Specifically, the first gate g1 and the first shielding member ls1 are respectively disposed at two sides of the first channel sd1, and shield the first channel sd1, so that the variation of the turn-on voltage of the first switch unit T1 can be reduced, that is, the drift amount of the first switch unit T1 is reduced. As the operation time of the first switch unit T1 increases, the turn-on voltage of the first switch unit T1 may change due to temperature and the like, and the decrease in the drift amount of the first switch unit T1 means that the change value before and after the turn-on voltage of the first switch unit T1 decreases, so that the stability of the first switch unit T1 is improved. Further, the first shield ls1 covers the orthographic projection area of the first channel sd1 on the channel layer a, so that the first shield ls1 has a better shielding effect.

It can be understood that, in an embodiment, the first gate g1 and the first shielding member ls1 are connected to different voltage points, and the first gate g1 and the first shielding member ls1 have shielding protection effect on the first channel sd1 layer, so that the characteristics of the first switch unit T1 can be improved, which is beneficial to the stability of the first switch unit T1, the circuit design of the pixel circuit 1, and the performance of the pixel circuit 1.

In a possible embodiment, the shielding layer LS, the channel layer a, the gate layer G, the source drain layer SD, and the anode layer P are stacked from bottom to top at a projection overlapping portion.

In one possible embodiment, first shade ls1 is a conductive material and is electrically connected to a predetermined voltage point.

Specifically, the predetermined voltage point refers to an output point having a voltage, and may be, for example, an output point outputting a fixed voltage, or the first gate g1, the first source s1, the first drain d1, and the like. The preset voltage point at which the first shutter ls1 is electrically connected is not limited by this application.

Specifically, according to the difference between the voltage points at which the first gate g1 and the first shade ls1 are electrically connected, the capacitance values of the coupling capacitors respectively formed by the first gate g1 and the anode a and the first source s1 can be adjusted, so that the light emitting unit in the pixel circuit 1 can operate more stably.

The operation of the first switching unit T1 when the first shade ls1 has different electrical connection voltage points will be described in detail.

In one possible embodiment, the first shutter ls1 is electrically connected to a fixed potential Vint. In this embodiment, the fixed potential Vint is disposed on the source/drain layer SD.

Specifically, when the fixed potential Vint is a dc negative voltage, the turn-on voltage of the first switching unit T1 drifts in a positive direction. When the fixed potential Vint is a positive dc voltage, the turn-on voltage of the first switching unit T1 drifts in the reverse direction.

Specifically, since the voltage of the first gate g1 controlling the first switch unit T1 to be turned on or off is a positive voltage, the voltage between the first gate g1 and the first source s1 of the first switch unit T1 is greater than the turn-on voltage. When the fixed potential Vint is a dc negative voltage, the voltage of the first gate g1 controlling the first switch unit T1 to be turned on and off is increased, and the turn-on voltage of the first switch unit T1 is shifted in a forward direction. Similarly, when the fixed potential Vint is a positive dc voltage, the voltage of the first gate g1 controlling the first switch unit T1 to be turned on or off decreases, and the turn-on voltage of the first switch unit T1 shifts in the opposite direction.

Specifically, the on-voltage of the first switch unit T1 drifts in the forward direction or in the reverse direction, which is adaptive to the circuit design of the pixel circuit 1. For example, the initial turn-on voltage of the first switch unit T1 is 1V, and the turn-on voltage of the first switch unit T1 required by the pixel circuit 1 is 1.2V, so that when the fixed potential Vint is a dc negative voltage, the turn-on voltage of the first switch unit T1 can be adjusted to drift forward from 1V to 1.2V. Vice versa, the initial turn-on voltage of the first switch unit T1 is 1V, and the turn-on voltage of the first switch unit T1 required by the pixel circuit 1 is 0.8V, so that when the fixed potential Vint is a positive dc voltage, the turn-on voltage of the first switch unit T1 can be adjusted to drift reversely from 1V to 0.8V.

It can be understood that, in the present embodiment, the first shutter ls1 is electrically connected to the fixed potential Vint, which improves the adaptability and circuit design of the pixel circuit 1.

It should be noted that the difference between the forward drift or the reverse drift of the turn-on voltage of the first switch unit T1 and the characteristic drift of the first switch unit T1 described above is that the characteristic drift of the first switch unit T1 is passive, and the reduction of the characteristic drift of the first switch unit T1 can make the first switch unit T1 more stable. The forward drift or the reverse drift of the turn-on voltage of the first switch unit T1 is actively adjusted, which improves the adaptability and the design of the pixel circuit 1. That is to say, the two are independent technical solutions, and the achieved beneficial effects are different.

It is understood that, in the present embodiment, the turn-on voltage of the first switching unit T1 may be controlled according to the positive and negative of the voltage to which the first shutter ls1 is electrically connected.

In a possible embodiment, please refer to fig. 2, and fig. 2 is a schematic cross-sectional view of a first switch unit according to an embodiment of the present application. The first shutter ls1 is electrically connected to the first gate g1 by a conductor. The first shutter ls1 and the first gate g1 are used to simultaneously apply a voltage to the first channel sd 1.

Specifically, in the present embodiment, the first shutter ls1 and the first gate g1 in the first switch unit T1 form a double-gate structure, that is, the first shutter ls1 and the first gate g1 are electrically connected, and the first shutter ls1 and the first gate g1 apply a voltage to the first channel sd1 at the same time. This arrangement enhances the current stability of the first channel sd1, and increases the turn-on of the first channel sd1, resulting in a larger current. Meanwhile, the characteristic drift of the first switching unit T1 is reduced, thereby reducing the device power consumption of the first switching unit T1.

In one possible embodiment, the first shutter ls1 is electrically connected to the first source s1 by a conductor.

It is understood that the first shield ls1 electrically connected to the first source s1 by a conductor is an embodiment included in the present application. The first shutter ls1 has a shielding protection effect on the first channel sd1 layer, so that the characteristics of the first switch unit T1 can be improved, which is beneficial to the stability of the first switch unit T1.

In the embodiments included herein, the first gate g1 forms coupling capacitances with the anode a and the first source s1, respectively.

Specifically, as shown in fig. 2, since the first gate g1 is electrically connected to the first shutter ls1, the coupling capacitance is equivalent to the coupling capacitance formed between the first shutter ls1 and the anode a. In general, the pixel circuit 1 further includes a coupling capacitor formed between an electrode of the anode layer P and an electrode of the gate layer G, or formed between an electrode of the source/drain layer SD and an electrode of the gate layer G. The coupling capacitor is used for storing the driving voltage value of the first switch unit T1, so that the light emitting unit in the pixel circuit 1 can be kept working normally.

Specifically, the shielding layer LS, the channel layer a, the gate layer G, the source drain layer SD, and the anode layer P are stacked from bottom to top at a projection overlapping portion, which is beneficial to formation of the coupling capacitor. It is understood that the order of disposing the shielding layer LS, the channel layer a, the gate layer G, the source/drain layer SD and the anode layer P is not limited as long as the formation of the coupling capacitor is not affected.

In a possible embodiment, please refer to fig. 3, and fig. 3 is a schematic cross-sectional view of a first switch unit according to an embodiment of the present application. The pixel circuit 1 further includes a capacity expansion electrode G11, and the capacity expansion electrode G11 is disposed between the gate layer G and the source drain layer SD. The capacity electrode g11 is electrically connected to the first source s1, and the first shield ls1 is electrically connected to the capacity electrode g 11.

Specifically, in this embodiment, the coupling capacitance is a coupling capacitance formed between the expansion electrode g11 and the first gate g 1. The first shutter ls1 is electrically connected to the first source s1 through the capacity expansion electrode g11, and may change an overlapping area formed between the first gate g1 and the first source s 1. According to the capacitance formula:

wherein epsilon is the dielectric constant of the medium between the polar plates, S is the overlapping area of the polar plates, k is the constant of the electrostatic force, and d is the distance between the polar plates. It can be concluded that the larger the overlap area between the plates, the larger the capacitance. That is, the first shield ls1 is electrically connected to the first source s1 through a conductor, and the capacitance of the coupling capacitor can be increased without changing the layout size.

Specifically, as shown in fig. 3, a projection of the first gate g1 falls within a projection of the anode a and the capacity expansion electrode g 11.

It is understood that the projection of the first gate g1 falls within the projection of the anode a and the capacity expansion electrode g11 to ensure that the overlapping area of the first gate g1 with the anode a and the capacity expansion electrode g11 is maximized, thereby increasing the capacitance value of the coupling capacitor.

In a possible embodiment, please refer to fig. 4, in which fig. 4 is a schematic cross-sectional view of a first switch unit and a second switch unit according to an embodiment of the present disclosure. The pixel circuit 1 further includes a second switching unit T2, the second switching unit T2 including a second source s2, a second drain d2, a second channel sd2, a second shutter ls2, and a second gate g 2. The second source s2 and the second drain d2 are respectively connected to the second channel sd 2. The second shutter ls2 is electrically connected to a predetermined voltage point and is used for shielding the second channel sd 2. The second shielding LS2 is disposed on the shielding layer LS, the second channel SD2 is disposed on the channel layer a, the second gate G2 is disposed on the gate layer G, and the second source s2 and the second drain d2 are disposed on the source drain layer SD.

Specifically, the second shield LS2 is disposed on a side of the shield layer LS adjacent to the substrate B, and the substrate B is also used for carrying the shield layer LS and the second shield LS 2.

Specifically, as shown in fig. 4, the first shutter ls1 is electrically connected to the second source s2, and the coupling capacitance is a coupling capacitance formed between the first shutter ls1 and the anode a. The second shade ls2 and the first gate g1 are electrically connected to a fixed potential Vint; the second source s2 is connected to the first conductive shield by a conductor.

Specifically, the first switching unit T1 has a bottom gate structure due to the introduction of the first shutter ls 1. When the first switch unit T1 operates, the first gate g1 is electrically connected to a fixed potential Vint, so that the characteristics of the first switch unit T1 drift and the offset of the turn-on voltage of the first switch unit T1 decreases. The first shutter ls1 can block the electron current entering the first channel sd1 from the side of the first channel sd1 departing from the first shutter ls1, and the first gate g1 can block the light entering the first channel sd1 from the side of the first channel sd1 departing from the first gate g1, so that the stability of the first switch unit T1 is improved. Similarly, the second shutter ls2 is electrically connected to a fixed potential Vint, so that the characteristics of the second switch unit T2 drift, and the offset of the turn-on voltage of the second switch unit T2 decreases. The second shutter ls2 can block the electron current entering the second channel sd2 from the side of the second channel sd2 departing from the second shutter ls2, and the second gate g2 can block the light entering the first channel sd1 from the side of the second channel sd2 departing from the second gate g2, so as to improve the stability of the first switch unit T1.

In a possible embodiment, please refer to fig. 5, and fig. 5 is a schematic cross-sectional view of a first switch unit and a second switch unit according to an embodiment of the present disclosure. The second shield ls2 is electrically connected to the second gate g2 by a conductor, and the first shield ls1 is electrically connected to the second source s2 and the first gate g1, respectively.

Specifically, as shown in fig. 5, the coupling capacitance is a coupling capacitance formed between the first shutter ls1 and the anode a. The present embodiment is different from the above embodiments in that the first switching cell T1 has a dual gate structure, and the second shutter ls2 is electrically connected to the second gate g2 through a conductor, and the second switching cell T2 has a dual gate structure. The second shutter ls2 applies a voltage to the second channel sd2 simultaneously with the second gate g 2. This arrangement enhances the current stability of the second channel sd2, and increases the on-state of the second channel sd2, resulting in a larger current. Meanwhile, the characteristic drift of the second switching unit T2 is reduced, thereby reducing the device power consumption of the second switching unit T2.

In a possible embodiment, please refer to fig. 6, and fig. 6 is a schematic cross-sectional view of a first switch unit and a second switch unit according to an embodiment of the present disclosure. The second shutter ls2 is electrically connected to a fixed potential Vint, and the first gate g1 is electrically connected to the first shutter ls1 and the second source s 2.

Specifically, as shown in fig. 6, the coupling capacitance is a coupling capacitance formed between the first gate g1 and the first source s1 and the anode a. The present embodiment is different from the above embodiments in that the first switching unit T1 has a double gate structure, and the second shutter ls2 is electrically connected to a fixed potential Vint. For the explanation of the dual gate structure and the electrically connected fixed potential Vint, please refer to the above description, which is not repeated herein.

In a possible embodiment, please refer to fig. 7, and fig. 7 is a schematic cross-sectional view of a first switch unit and a second switch unit according to an embodiment of the present disclosure. The pixel circuit 1 further includes a capacity expansion electrode G11, the capacity expansion electrode G11 is disposed between the gate layer G and the source drain layer SD, and the capacity expansion electrode G11 is electrically connected to the first source s 1. The first shade is 1 is electrically connected to the capacity expansion electrode g11, the second shade is 2 is electrically connected to a fixed potential Vint, and the second source s2 is conductively connected to the first gate g 1.

Specifically, as shown in fig. 7, the coupling capacitance is a coupling capacitance formed between the expansion electrode g11 and the first gate g 1. The present embodiment is different from the above embodiments in that the first shutter ls1 is electrically connected to the capacity expansion electrode g11 and the first source s1 through a conductor, and the second shutter ls2 is electrically connected to a fixed potential Vint.

Specifically, the projection of the first gate g1 falls within the projection of the anode a and the capacity expansion electrode g 11.

It can be understood that, since the first shutter ls1 is electrically connected to the capacity expansion electrode g11, the overlapping area of the capacity expansion electrode g11 with the anode a and the first gate g1 is increased, and the capacitance value of the coupling capacitor is increased. For the explanation of the electrical connection of the second shielding member ls2 to the fixed potential Vint, please refer to the above description, and further description is omitted here.

In a possible embodiment, please refer to fig. 8, in which fig. 8 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure. The pixel circuit 1 further includes a third switching unit T3 and a fourth switching unit T4, the third switching unit T3 includes a third gate g3, a third source s3 and a third drain d 3. The fourth switching unit T4 includes a fourth gate g4, a fourth source s4 and a fourth drain d 4. The first gate g1 is electrically connected to the second source s2, the first source s1 is electrically connected to the fourth source s4, and the first drain d1 is electrically connected to the third source s 3. The second gate g2 is electrically connected to a first Scan signal Scan (n), the second drain d2 is electrically connected to a data signal Vref/Vdata, the third gate g3 is electrically connected to a control signal En, the third drain d3 is electrically connected to a high potential VDD, the fourth gate g4 is electrically connected to a second Scan signal Scan (n-1), and the fourth drain d4 is electrically connected to a fixed potential Vint.

Specifically, the pixel circuit 1 further includes a storage capacitor C2, one end of the storage capacitor C2 is electrically connected to the high potential VDD, and the other end of the storage capacitor C2 is electrically connected to the anode a. The storage capacitor C2 is used to store the voltage value between the high potential VDD and the anode a, so that the charging current when the high potential VDD charges the anode a is more stable.

Specifically, the first scan signal scan (n) is used to control the on/off of the second switch unit T2, so that the data signal Vref/Vdata is transmitted to the first switch unit T1 through the second switch unit T2. The control signal En is used to control the on/off of the third switching unit T3, and is used to transmit the high potential VDD to the anode a through the third switching unit T3. The second Scan signal Scan (n-1) is used to control the on/off of the fourth switching unit T4, and is used to transmit a fixed potential Vint to the anode a through the fourth switching unit T4, so as to perform voltage reset. The pixel circuit 1 drives the light emitting unit to emit light by the data signal Vref/Vdata.

In a possible embodiment, please refer to fig. 9 together, and fig. 9 is a schematic diagram of a pixel circuit according to an embodiment of the present application. The third switching unit T3 includes a third channel sd3, the third source s3 and the third drain d3 are respectively connected to the third channel sd3, the fourth switching unit T4 includes a fourth channel sd4, the fourth source s4 and the fourth drain d4 are respectively connected to the fourth channel sd4, a third channel sd3 is formed between the third source s3 and the third drain d3, and a fourth channel sd4 is formed between the fourth source s4 and the fourth drain d 4. The third switching unit T3 further includes a third shade ls3 electrically connected to a preset voltage point and used for shading the third channel sd 3. The fourth switching unit T4 further includes a fourth shade ls4 electrically connected to a predetermined voltage point and for shielding the fourth channel sd 4.

It can be understood that, in the present embodiment, the third shutter ls3 shutters the third channel sd3, increasing the stability of the third switching unit T3. The fourth shutter ls4 shutters the fourth channel sd4, increasing the stability of the fourth switching unit T4.

Specifically, the third shutter ls3 is electrically connected to at least one of the third gate g3, the third source s3, the digital potential, and the fixed potential Vint. The fourth shutter ls4 is electrically connected to at least one of the fourth gate g4, the fourth source s4, the digital potential, and the fixed potential Vint.

The advantageous effects are different according to the voltage point to which the third shade ls3 is electrically connected. Since the third shielding member ls3 and the first shielding member ls1 have similar structures and principles, when the voltage points of the third shielding member ls3 are different, please refer to the explanation of the voltage points of the first shielding member ls1, which is not described herein again. Similarly, when the voltage points of the fourth shielding member ls4 are different, please refer to the explanation of the voltage points of the first shielding member ls1, which is not described herein again.

It should be noted that, as long as the normal operation of the pixel circuit 1 is not affected, the connection relationships between the first source s1 and the first drain d1, the second source s2 and the second drain d2, the third source s3 and the third drain d3, and the fourth source s4 and the fourth drain d4 in the above embodiments may be replaced correspondingly, and the present application does not limit this.

In a possible embodiment, please refer to fig. 9 and fig. 10 together, and fig. 10 is a schematic timing diagram of signals provided by an embodiment of the present application. In the initialization phase M1 of the pixel circuit 1, the control signal En outputs a low level to turn off the third switching unit T3.

Specifically, the process of driving the light emitting unit to emit light by the pixel circuit 1 can be divided into four stages, and the first stage is the initialization stage M1. As shown in fig. 9 and 10, in the initialization phase M1, the second Scan signal Scan (n-1) outputs a high level to turn on the fourth switching unit T4, and a fixed potential Vint is input to the anode a to be reset. At this time, the control signal En outputs a low level such that the third switching unit T3 is turned off to prevent the high potential VDD from being transmitted to the anode a through the third switching unit T3. Generally, the voltage value of the anode a is greater than the voltage value of the fixed potential Vint. If the third switching unit T3 is turned on, a current will be transmitted from the high voltage VDD to the fixed voltage Vint through the third switching unit T3, the first switching unit T1 and the fourth switching unit T4, thereby increasing the power consumption of the pixel circuit 1. It is understood that, in the present embodiment, in the initialization phase M1, the control signal En outputs a low level to turn off the third switching unit T3, so that the power consumption of the pixel circuit 1 is reduced.

Specifically, as shown in fig. 10, the data signal Vref/Vdata includes a reference voltage signal Vref and a data voltage signal Vdata; the first scan signal scan (n) outputs a high level when the data signal Vref/Vdata is the reference voltage signal Vref; when the first scan signal scan (n) is a data voltage signal Vdata, a low level is output.

Specifically, the reference voltage signal Vref is used to initialize the voltage point of the second source s2, and the data voltage signal Vdata is transmitted to the anode a for driving the light emitting unit to emit light.

Specifically, in the present embodiment, in the first time of the initialization stage M1 of the pixel circuit 1, the first scan signal scan (n) outputs a high level, and the data signal Vref/Vdata outputs a reference voltage; during the second time of the initialization phase M1 of the pixel circuit 1, the first scan signal scan (n) outputs a low level, and the data signal Vref/Vdata outputs a data voltage.

Specifically, in the initialization stage M1, when the first scan signal scan (n) outputs a high level, the second switch unit T2 is turned on, and the reference voltage signal Vref is transmitted to the second source s 2. When the first scan signal scan (n) outputs a low level, the second switching unit T2 is turned off. Since the voltage values of the data voltage signals Vdata may be different, the setting method can make the voltage values transmitted to the second source s2 consistent in each initialization period M1, so that the next initialization period M1 is not affected, and the stability of the pixel circuit 1 is improved.

The second process of the pixel circuit 1 driving the light emitting unit to emit light is the compensation phase M2. Specifically, as shown in fig. 10 and 10, in the compensation phase M2, the second Scan signal Scan (n-1) outputs a low level, the fourth switching unit T4 is controlled to be turned off, and the fixed potential Vint stops being transmitted to the anode a through the fourth switching unit T4. The first scan signal scan (n) outputs a high level, controls the second switch unit T2 to turn on, and transmits the reference voltage signal Vref to the second source s2 again. The control signal En outputs a high level to control the third switching unit T3 to be turned on, and the high level VDD is charged to the anode a through the third switching unit T3 and the first switching unit T1 until the first switching unit T1 is turned off when the voltage value between the first gate g1 and the first source s1 is equal to the turn-on voltage of the first switching unit T1. At this time, the voltage value of the anode a is a difference between the voltage value of the reference voltage signal Vref and the voltage value of the turn-on voltage of the first switching unit T1, that is:

Vanode＝Vref-Vth

wherein Vanode is a voltage value of the anode a, Vref is a voltage value of the reference voltage signal Vref, and Vth is a turn-on voltage value of the first switch unit T1. By properly setting the voltage values of the reference voltage signal Vref and the fixed potential Vint, it can be ensured that the voltage value of the anode a is smaller than the turn-on voltage of the light emitting unit at the end of the compensation phase M2, in other words, the light emitting unit does not emit light during the compensation phase M2.

The third process of the pixel circuit 1 driving the light emitting unit to emit light is the writing phase M3. In other words, the voltage value of the data voltage signal Vdata may be greater than, equal to, or less than the voltage value of the reference voltage signal Vref. In the write phase M3, as shown in fig. 9 and 10, the second Scan signal Scan (n-1) output is still low, and the fourth switching unit T4 is turned off. The control signal En outputs a low level, the high potential VDD stops the charging of the anode a through the third switching unit T3, and the voltage value of the anode a is maintained at the voltage value of the anode a of the compensation period M2. The first scan signal scan (n) outputs a high level, controls the second switching unit T2 to turn on, and the data voltage signal Vdata is transmitted to the second source s2 through the second switching unit T2, at which time, the voltage of the second source s2 changes, and the voltage of the anode a is changed through the coupling capacitor Cst. The voltage change value formula of the anode a is as follows:

Δ Anode is a voltage variation value of the Anode a, Δ Nst is a voltage variation value of the second source s2, Cst is a capacitance value of the coupling capacitor Cst, C2 is a capacitance value of the storage capacitor C2, Coled is a voltage value of the light emitting unit, and Vdata is a voltage value of the data voltage signal Vdata.

The third process of the pixel circuit 1 driving the light emitting unit to emit light is the light emitting period M4. As shown in fig. 9 and 10, the second Scan signal Scan (n-1) is still low, and the fourth switching unit T4 is turned off. The first scan signal scan (n) outputs a low level, and controls the second switching unit T2 to turn off, and the coupling capacitor Cst maintains the voltage value of the second source s2 at the voltage value of the data voltage signal Vdata. The control signal En outputs a high level to control the third switching unit T3 to be turned on, and the high potential VDD is charged to the anode a through the third switching unit T3, at this time, the current value of the first switching unit T1 is:

it can be understood that the current value passing through the first switching unit T1 is equal to the current value passing through the light emitting unit, that is, the current value of the first switching unit T1 cancels the influence of the turn-on voltage, so that the light emitting unit emits light without being influenced by the turn-on voltage, thereby emitting light more stably.

Fig. 11 is a schematic diagram of a display panel 2, and fig. 11 is a schematic diagram of a display panel circuit according to an embodiment of the present disclosure. The display panel 2 includes a plurality of light emitting units 21 distributed in an array, and a plurality of pixel circuits 1 corresponding to the light emitting units 21 as described above, and the light emitting units 21 are electrically connected to the anodes a of the pixel circuits 1.

Specifically, the light emitting units 21 and the pixel circuits 1 are disposed on the substrate B. The pixel circuit 1 refers to the above description, and is not described herein again. In general, the light emitting unit 21 is electrically connected to a low potential, and the pixel circuit 1 is configured to transmit the voltage of the data voltage signal Vdata output according to the data signal Vref/Vdata to the anode a and drive the light emitting unit to emit light in combination with the low potential, so as to achieve the purpose of displaying the image.

Fig. 12 is a schematic circuit diagram of an electronic device 3 according to an embodiment of the present application, and fig. 12 is a block diagram of the electronic device 3. The electronic device 3 includes a body 31 and the display panel 2, where the body 31 is used for carrying the display panel 2.

The principle and the implementation of the present application are explained herein by applying specific examples, and the above description of the embodiments is only used to help understand the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. The pixel circuit is characterized by comprising a first switch unit, wherein the first switch unit comprises a first source electrode, a first drain electrode, a first channel, a first grid electrode and a first shielding piece, the first source electrode and the first drain electrode are respectively connected with the first channel, and the first shielding piece is arranged on one side of the first channel, which is deviated from the first grid electrode.

2. The pixel circuit according to claim 1, further comprising a barrier layer, a channel layer, a gate layer, a source drain layer, and an anode layer; the first shielding piece is arranged on the shielding layer, the first channel is arranged on the channel layer, the first grid is arranged on the grid layer, the first source electrode and the first drain electrode are arranged on the source drain electrode layer, and the anode layer is provided with an anode; the first source is electrically connected to the anode.

3. The pixel circuit according to claim 2, wherein the barrier layer, the channel layer, the gate layer, the source and drain layers, and the anode layer are stacked from bottom to top at a projection overlapping portion.

4. The pixel circuit according to claim 1, wherein the first shielding member is a conductive material and is electrically connected to a predetermined voltage point.

5. The pixel circuit according to any one of claims 1 to 4, wherein the first shutter is electrically connected to a fixed potential.

6. The pixel circuit according to claim 5, wherein when the fixed potential is a dc negative voltage, an on voltage of the first switching unit drifts in a forward direction; when the fixed potential is a direct-current positive voltage, the starting voltage of the first switch unit drifts reversely.

7. The pixel circuit according to any one of claims 1 to 4, wherein the first shutter is electrically connected to the first gate electrode through a conductor; the first shade and the first gate are used to apply a voltage to the first channel simultaneously.

8. The pixel circuit according to any of claims 1-4, wherein the first shutter is electrically connected to the first source electrode by a conductor.

9. The pixel circuit according to claim 2, wherein the first gate forms a coupling capacitance with the anode and the first source, respectively.

10. The pixel circuit according to claim 9, further comprising a flash electrode disposed between the gate layer and the source and drain layers; the capacity expansion electrode is electrically connected with the first source electrode; the first shielding member is electrically connected to the capacity expansion electrode.

11. The pixel circuit according to claim 10, wherein a projection of the first gate falls within a projection of the anode and the flash electrode.

12. The pixel circuit according to claim 2, further comprising a second switching unit, wherein the second switching unit comprises a second source, a second drain, a second channel, a second barrier, and a second gate, and wherein the second source and the second drain are respectively connected to the second channel; the second shielding piece is electrically connected to a preset voltage point position and used for shielding the second channel; the second shielding piece is arranged on the shielding layer, the second channel is arranged on the channel layer, the second grid is arranged on the grid layer, and the second source electrode and the second drain electrode are arranged on the source drain electrode layer.

13. The pixel circuit according to claim 12, wherein the second shutter and the first gate are electrically connected to a fixed potential; the second source electrode is connected to the first conductive shield by a conductor.

14. The pixel circuit according to claim 12, wherein the second shutter is electrically connected to the second gate electrode through a conductor; the first blocking member is electrically connected to the second source electrode and the first gate electrode, respectively.

15. The pixel circuit according to claim 12, wherein the second shutter is electrically connected to a fixed potential; the first gate is electrically connected to the first shield and the second source.

16. The pixel circuit according to claim 12, further comprising a flash electrode disposed between the gate layer and the source drain layer, the flash electrode electrically connected to the first source; the first shielding piece is electrically connected to the capacity expansion electrode; the second shielding member is electrically connected to a fixed potential; the second source conductor is connected to the first gate.

17. The pixel circuit according to claim 16, wherein a projection of the first gate falls within a projection of the anode and the flash electrode.

18. The pixel circuit according to claim 12, further comprising a third switching unit and a fourth switching unit, the third switching unit including a third gate, a third source, and a third drain; the fourth switch unit comprises a fourth grid, a fourth source and a fourth drain;

the first grid is electrically connected with the second source; the first source electrode is electrically connected with the fourth source electrode; the first drain electrode is electrically connected with the third source electrode; the second grid is electrically connected with a first scanning signal; the second drain electrode is electrically connected with a data signal; the third grid is electrically connected with a control signal; the third drain electrode is electrically connected with a high potential; the fourth grid is electrically connected with a second scanning signal; the fourth drain is electrically connected to a fixed potential.

19. The pixel circuit according to claim 18, wherein the third switching unit comprises a third channel, the third source and the third drain are respectively connected to the third channel, the fourth switching unit comprises a fourth channel, the fourth source and the fourth drain are respectively connected to the fourth channel, and the third switching unit further comprises a third shielding member electrically connected to a predetermined voltage point and used for shielding the third channel; the fourth switch unit further comprises a fourth shielding piece which is electrically connected with the preset voltage point and used for shielding the fourth channel.

20. The pixel circuit according to claim 19, wherein the third shield is electrically connected to at least one of a third gate, a third source, a digital potential, and a fixed potential; the fourth shielding member is electrically connected to at least one of a fourth gate, a fourth source, a digital potential, and a fixed potential.

21. The pixel circuit according to claim 18, wherein the control signal outputs a low level to turn off the third switching unit in an initialization stage of the pixel circuit.

22. The pixel circuit according to claim 21, wherein the data signal comprises a reference voltage signal and a data voltage signal; the first scanning signal outputs a high level when the data signal is a reference voltage signal; and outputting a low level when the first scanning signal is a data voltage signal.

23. The pixel circuit according to claim 22, wherein in a first time of an initialization phase of the pixel circuit, the first scan signal outputs a high level, and the data signal outputs a reference voltage; in a second time of the initialization stage of the pixel circuit, the first scan signal outputs a low level and the data signal outputs a data voltage.

24. A display panel comprising a plurality of light emitting units arranged in an array, and a plurality of pixel circuits according to any one of claims 2 to 23 corresponding to the light emitting units, wherein the light emitting units are electrically connected to the anodes of the pixel circuits.

25. An electronic device, comprising a body and the display panel of claim 24, wherein the body is used for carrying the display panel.