JP3493525B2 - Programmable controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller (hereinafter, referred to as a "PC") for simultaneously and separately processing programs managed separately. 2. Description of the Related Art A general PC program has a main program which is repeatedly scanned and operated by a timer interrupt or an external interrupt. It has a program added. When creating such a PC sequence program, each output condition must be incorporated into a series of programs, which complicates the program, and changes in the program that are not related to the output condition require changes. Even if it did, the program was affected, so it took time to change the program, and it was easy to make a mistake. In addition, when the created sequence program is complex and huge, as described above, the program is unified, so that one scan requires time and high speed cannot be achieved. Was. In a general programmable controller, there is only one storage area for storing on / off states of bit signals, and an area referred to in a conditional operation is affected by writing of an operation result. Since the execution result of the program is affected by the order, the program must be created in consideration of that. Further, for example, as shown in FIG. 5 (a), when outputs such as forward and reverse rotations of a motor are programmed in a continuous stage, the output is overlapped by one scan, so that the output is like a ladder. It was avoided by adding a conditional instruction, but the program was complicated. Also, when programming the same figure (b), when the stage S5 is turned on and its input I5 is already on, a trouble often occurs when an external stage condition is used.
In some cases, the condition of input I5 used at 0 did not turn on even one scan. SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. The present invention has been made so that conditions necessary for safe operation of an apparatus and its processing program can be separately managed from a normal program. , A PC that enables the management level to be subdivided, such as a change of a program, and that can separately process a separately managed program at high speed, and a PC in which the execution order of the program is not affected by the writing order of the program The purpose is to obtain. A programmable controller according to the present invention is provided with a first storage unit for storing a main program, two input / output terminals, and an input signal, an output signal, and an internal signal. And a second storage unit having a read storage area in which the input / output signal and the internal signal stored in the write storage area are stored. A third storage unit to be stored and a main program are executed and operated by referring to input / output signals and internal signals in a read storage area of the second storage unit, and an output signal and an internal signal of the operation result are output to the third storage unit. A first CPU stored in a write storage area of a second storage unit, and an input / output determination processing program stored in a second CPU while the first CPU is executing a main program.
Execute while referring to the input / output signals and internal signals in the read storage area of the storage unit, and by executing the program,
When transferring the output signal written in the read storage area of the second storage unit to the outside, it is determined whether or not the output signal satisfies a predetermined condition. When the above condition is not satisfied, a predetermined arithmetic processing is performed to generate a signal corresponding to the abnormality and the signal is transferred to the outside, and when an external input signal is read, a second memory is stored. And a second CPU that stores the output signal and the internal signal stored in the write storage area of the second storage unit each time the first CPU finishes the arithmetic processing of the main program. The input signal stored in the write storage area by the 2CPU is copied to the read storage area of the second storage unit. In the present invention, each time the first CPU terminates the arithmetic processing of the main program, the first CPU outputs the output signal and the internal signal stored in the write storage area of the second storage section, and outputs the second signal.
The input signal stored by the CPU is copied to the read storage area of the second storage unit, and the second CPU
While U is executing the main program, the input / output determination processing program is executed while referring to the input / output signals and the internal signals in the read storage area of the second storage unit. FIG. 1 shows a CPU of a PC according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a hardware configuration of the module, FIG. 2 is a configuration diagram of a bidirectional RAM, FIG. 3 is a timing chart showing timings at which two CPUs access the bidirectional RAM, and FIG.
9 is a flowchart for explaining the operation of the present embodiment. In the figure, 1 is a CPU module of a PC, 2 is a RAM of a first storage unit of the present invention in which a main program is stored, and 3 is a bidirectional RAM showing an example of a second storage unit. As shown, an external input signal written by the CPU 6, an output signal by execution and calculation of the main program of the CPU 4, and an internal signal are stored in the write storage area, and the input / output signal and the internal signal stored in the write storage area are stored. A read storage area to which signals are written. The CPU 4 has the function of the first CPU of the present invention, and executes and calculates the main program of the RAM 2 based on the system program stored in the ROM 5. At the time of the main program operation, as shown in FIG. 3, related input / output signals and internal signals are read out from the read storage area of the bidirectional RAM 3 and referred to, and output signals and internal signals of the operation result are written into the bidirectional RAM 3. In the storage area for When one scan of the main program is completed, the output signal and the internal signal stored in the write storage area of the bidirectional RAM 3 are copied to the read storage area. At this time, the external input signal stored by the CPU 6 is also copied to the read storage area. When this transfer processing is completed, the main program is executed and operated again with reference to the input / output signals and internal signals copied to the read storage area, and the resulting output signals and internal signals are stored in the write storage area. . In this way, each time the main program completes one scan, the signals stored in the write storage area are copied to the read storage area. The CPU 6 has the function of the second CPU of the present invention, and while the CPU 4 is executing the main program,
R based on the system program stored in the ROM 7
The input / output determination processing program of AM8 (third storage unit) is executed. When the output signal written to the read storage area is transferred to the outside, as shown in FIG. 3, input / output signals and internal signals necessary to determine whether the output signal satisfies a predetermined condition are determined. Read from the read storage area. When the condition is satisfied, the data is transferred to the output module 21 via the input / output IF (interface) 10 as it is. When the condition is not satisfied, a predetermined arithmetic processing is performed to generate a signal corresponding to the abnormality,
The data is transferred to the output module 21 via the input / output IF 10. When a signal is input to the input / output IF 10 via the input module 20, the CPU 6 reads the input signal as an item related to the output signal. At this time, when it is determined that the input signal is abnormal, the input signal is stored in the write storage area of the bidirectional RAM 3, for example, in a pause state for temporarily stopping the PC or performing a stop process. The above-mentioned input / output determination processing program is a program for determining whether each input / output signal satisfies a condition, and a program for performing processing corresponding to the abnormality when the condition is not satisfied. And the following contents are programmed. (A) Conditions for controlling the operating state of the PC, the whole or part of the program execution, or the whole or part of the output operation, and the control contents in that case. (B) Normal / abnormal judgment condition of output ON (or OFF) operation. Operation check signal and operation monitoring time. Interlock condition (operating condition / prohibiting condition). (C) Processing details at the time of output operation abnormality determination. Reference numeral 9 denotes a RAM for storing data such as numerical values and characters to be read / written by a user in an application, and 11 denotes an IF connected to a display device 22.
The display device 22 sequentially displays each signal written to the read storage area of the bidirectional RAM 3. In the PC constructed as described above, FIG.
The operation will be described based on the flowchart of FIG. Here, for convenience of explanation, the RUN start processing (initial setting) ends,
It is also assumed that the CPU 4 has completed one scan of the main program in the RAM 2 (S1 to S6). At this time, CP
U4 writes the output signal and the internal signal stored in the write storage area of the bidirectional RAM 3 and the external input signal stored by the CPU 6 to the read storage area, respectively (S7). Then, execution of the main program is started again (S1). When the instruction of the program is a bit processing instruction (S2), the operation is performed according to the instruction and the result is stored in the write storage area of the bidirectional RAM 3 (S1).
3) If the instruction is a conditional instruction (S2), the input / output signal and the internal signal related thereto are read from the read storage area and referenced (S4). Then, it is determined whether the program instruction is an END instruction (S5). END
When the instruction is an instruction, the process proceeds to step 6, and when the instruction is not the END instruction, the process returns to step 2 and follows the instruction. This series of actions
The operation is sequentially performed according to the instruction of the main program, and the output of the operation result and the internal signal are stored in the write storage area (S2 to S5). At this time, the CPU 6 processes the output signal stored in the read storage area of the bidirectional RAM 3 and the signal input from the outside based on the input / output determination processing program stored in the RAM 8. Bidirectional RAM
3, when the output signal stored in the read storage area is transferred to the outside, the output signal satisfies a predetermined condition while referring to the related input / output signal and the internal signal written in the read storage area. (S1)
1). If the condition is satisfied, the signal is transferred to the output module 21 via the input / output I / F 10 as it is (S12). If the condition is not satisfied, a predetermined arithmetic processing is performed to output a signal corresponding to the abnormality. Is generated, and the signal is transferred to the output module 21 via the input / output I / F 10 (S12). When a response signal to the output signal is input to the input module 20, the CPU 6 fetches the input signal (S13) and determines whether or not a predetermined condition is satisfied. The determination is made with reference to the signal and the internal signal (S14). When the condition is satisfied, the state is stored as it is in the write storage area of the bidirectional RAM 3, and when the condition is not satisfied, for example, a pause state for temporarily stopping the PC is stored in the write storage area. At this time, the contents of the input / output signal and the internal signal stored in the read storage area are displayed on the display device 22 via the I / F 11. On the other hand, when the CPU 4 confirms the END instruction during the execution of the main program (S5), the execution of the program is terminated (S6), and the output of the operation result written in the write storage area of the bidirectional RAM 3 and the internal Signal and C
The input signal written by PU6 and the bidirectional RAM
3 is copied to the read storage area (S7), and the CPU 6
At the same time, the same operation as described above is repeated. In the above embodiment, the bidirectional RAM 3
Is provided with a storage area for writing and a storage area for reading,
Although the example of copying each signal written to the write storage area to the read storage area has been described above, an index register for writing and an index register for reading are prepared, and an index for writing and an index for reading are prepared every main program scan. The address data may be replaced. Further, the CPU 6 may have a function of copying each signal written in the write storage area to the read storage area. In this case, when the CPU 4 finishes executing the main program, a signal notifying the end is output to the CPU 6 so as to give a timing of signal copying. As described above, according to the present invention, the main program and the input / output determination processing program are separately managed independently of each other, so that it is necessary to change the operation order and the like. The input / output judgment processing program that does not change even if the program is changed can be separately managed, and the management level can be divided, such as a change in the program, and a safety circuit such as an interlock and monitoring time can be included in the main program. Since the necessity is eliminated, the effect of facilitating the work of changing the program by changing the sequence is obtained. Further, since the write storage area and the read storage area are provided in the bidirectional RAM of the second storage section, the following effects are obtained. (1) Two CPUs can process each program simultaneously in parallel, and high-speed scanning is possible. (2) Since various signals in the read storage area do not change during execution of the main program, there is no difference in operation due to the writing order of the program, and a program such as an alternate operation can be easily created. Further, the display unit can display an actual situation. (3) Even when outputs such as normal rotation and reverse rotation are programmed in successive stages, the previous output (OFF) is stored in the read storage area, and the subsequent output (ON) is stored in the write storage area. Therefore, there is no need for a complicated program for attaching an output condition instruction as in the related art. In addition, if the stage transition conditions were met from the beginning,
The trouble that often occurs when the stage condition is used externally, that is, that the stage condition does not turn on even one scan after passing through the stage is eliminated.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a hardware configuration of a CPU module of a PC according to one embodiment of the present invention. FIG. 2 is a configuration diagram of a bidirectional RAM. FIG. 3 is a timing chart showing the timing at which the two CPUs access the bidirectional RAM. FIG. 4 is a flowchart for explaining the operation of the present embodiment. FIG. 5 is an explanatory diagram for explaining a conventional problem.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G05B 19/05

Claims (1)

(57) [Claim 1] A first storage section in which a main program is stored, and two input / output terminals are provided, and an input signal and an output signal are stored.
And a write storage area in which an internal signal is stored , and the input / output signal stored in the write storage area and
A second storage unit having a read storage area in which an internal signal is written , a third storage unit storing an input / output determination processing program, and the main program stored in the read storage area of the second storage unit . the 1CPU the input and output signals and executing, calculated with reference to the internal signal, stores the output signal and an internal signal of the operation result to the write memory area of the <br/> second storage unit
While the first CPU is executing the main program.
The input / output determination processing program is stored in the second storage unit.
Refer to the input / output signals and internal signals in the read storage area.
While executing the program, and by executing the program,
2 The output copied to the read storage area of the storage unit
When transferring a signal to the outside, the output signal
Judge whether the condition is satisfied and satisfy the above conditions
Transfer to the outside as it is, satisfying the above conditions
If not, perform the specified calculation to deal with the abnormality
Generated signals are transferred to the outside, and input from outside
When the force signal is read, it is used for writing in the second storage unit.
A second CPU for storing the data in a storage area , wherein the first CPU performs arithmetic processing of the main program.
Every time is completed, the write storage area of the second storage unit
Output signal and internal signal stored in the second CPU
Input signal stored in the write storage area
A programmable controller for writing data to a read storage area of the second storage unit .